A four-tube Buck-Boost PFC converter control method and control circuit

Abstract

This invention discloses a control method and circuit for a four-tube Buck-Boost PFC converter. By adjusting the duty cycle of switch Q1, flexible output voltage selection is achieved. By replacing diodes with switches, reverse inductor current flow is enabled, achieving zero-voltage switching (ZVS) for all switches. PWM plus phase-shift control minimizes inductor current ripple and RMS value. This invention fully accounts for the wide range of input voltage and current variations in the converter, enabling power factor correction and achieving optimal PCRM and PDCM operating modes.

Description

Technical Field

[0001] The present invention belongs to the technical field of power converters, and in particular relates to a control method and a control circuit for a four-tube Buck-Boost PFC converter. Background Art

[0002] In daily life and industry, electrical energy is typically drawn from the AC power grid, while many electrical devices require DC power. Therefore, AC-DC converters are widely used in applications such as LED lighting power supplies, communication power supplies, battery chargers, and DC motor power supplies. Traditional AC-DC converters typically utilize a rectifier bridge plus filter capacitor circuit structure. This circuit structure offers advantages such as simplicity and low cost, but it also suffers from severe input current distortion and a significant phase difference with the input voltage, resulting in a low power factor. A low power factor can adversely impact the power grid by: 1) reducing the utilization of generators and transformers, increasing power supply costs; 2) increasing the effective value of the grid current and, consequently, increasing line transmission losses; and 3) causing voltage drops across the line impedance caused by input current harmonics, leading to grid voltage distortion, a so-called "secondary effect."

[0003] To improve the power factor of electrical equipment, power factor correction (PFC) technology is required. PFC technology can be categorized as either passive or active PFC, depending on whether active components such as switching transistors are used. Passive PFC circuits use a passive network composed of inductors, capacitors, and diodes to correct the input current waveform. While this circuit offers a simple structure, high reliability, and low cost, it offers limited improvement in power factor, and the output voltage cannot be adjusted, fluctuating significantly with input voltage and load, resulting in poor power quality. Among active PFC converters, the buck PFC converter has an input current dead zone, resulting in a low power factor. The boost PFC converter has no input current dead zone and can achieve unity power factor, but is only applicable in high-voltage output applications. Compared to the buck-boost PFC converter, the buck-boost PFC converter has no input current dead zone and offers flexible output voltage selection. However, its output voltage has a negative polarity and the voltage stress on the power transistor is high, being the sum of the input voltage peak and the output voltage. Adding a pair of switching transistors and a diode to a buck-boost PFC converter creates a two-transistor buck-boost PFC converter. This converter retains the advantages of the buck-boost PFC converter while reducing the voltage stress on the power transistors. However, due to the unidirectional conductivity of the diodes, the inductor current in the two-transistor buck-boost PFC converter can only flow in one direction, making zero voltage switching (ZVS) of the switches impossible. Replacing the two diodes in the two-transistor buck-boost PFC converter with synchronous rectifiers creates a four-transistor buck-boost PFC converter. In a four-transistor buck-boost PFC converter, the inductor current can flow in both directions, thereby achieving zero voltage switching (ZVS) for all switches. For a four-transistor buck-boost converter, PWM plus phase-shift control can be used to achieve zero voltage switching for all switches and minimize inductor current ripple.

[0004] When a four-switch Buck-Boost converter is used in a PFC converter, its input voltage and current are both rectified sinusoidal waves with a wide range of variation, which differs from the operating mode and design methods of DC-DC converters. Therefore, for a four-switch Buck-Boost PFC converter, finding a simple and feasible control scheme based on the wide range of input voltage and input current, combined with the control principles of a four-switch Buck-Boost converter, is an urgent problem for researchers in this field. Summary of the Invention

[0005] The technical problem to be solved by the present invention is to address the deficiencies of the above-mentioned prior art and provide a control method and control circuit for a four-tube Buck-Boost PFC converter. The control method and control circuit fully take into account the characteristics of wide-range variation of the converter input voltage and input current, and can realize power factor correction and achieve the optimal operating modes of PCRM and PDCM.

[0006] In order to achieve the above technical objectives, the technical solution adopted by the present invention is:

[0007] A four-tube Buck-Boost PFC converter control method, wherein the four-tube Buck-Boost PFC converter includes four switch tubes Q1, Q2, Q3, Q4, a filter inductor L c , an output filter capacitor C o , a rectifier bridge capacitor C g and an input voltage source v in The connected diode rectifier bridge; Q1 and Q2 are complementary turned on to form a bridge arm unit, Q3 and Q4 are complementary turned on to form a bridge arm unit; L c The two ends of C are connected to the midpoints of the bridge arm units of Q1 and Q2 and the midpoints of the bridge arm units of Q3 and Q4 respectively. o In parallel with the bridge arm units of Q3 and Q4, the diode rectifier bridge, C g Both are connected in parallel with the bridge arm units of Q1 and Q2; C o 、C g The voltages at both ends are the output voltage v o and input voltage v g , the control method includes:

[0008] Step 1: Sample v o and v g , get the output voltage sampling signal v o_s With the input voltage sampling signal v g_s , v o_s and the reference signal V o_ref The error is amplified by the output voltage regulator to obtain the signal v c , and v g_s After multiplication, the input current reference signal i is obtained g_ref ;

[0009] Step 2: Sample input current i g Get the input current sampling signal i g_s ,i g_s and i g_ref In comparison, the input current is adjusted by closed loop through the input current regulator to make the input current follow the reference, and the duty cycle D of Q1 is obtained. y1 , to control the switching action of the switch tube Q1, and its inverse signal is used to control the switching action of the switch tube Q2;

[0010] Step 3: Sampling L c The inductor current i Lc , with the negative current reference required for soft switching -I ZVS For comparison, when i Lc Linearly decrease to -I ZVS When the switch Q3 is turned off, the duty cycle of Q3 is 1-D y2 , to control the switching action of the switch tube Q3, and its inverse signal is used to control the switching action of the switch tube Q4;

[0011] Step 4: Under PDCM, according to v g 、i g_ref Approximately calculate the phase shift angle D between the phase difference between Q1 and Q3 when they are turned on θ_PCRM , according to v o and v g 、D y1 Approximately calculate the phase shift angle D between the phase difference between the switch tubes Q1 and Q3 when they are turned on θ_PDCM ; D θ_PCRM and D θ_PDCM The larger value of the two is sent to the diode gating circuit and used as the phase shift duty cycle D θ , to control the phase difference between the turn-on moments of the switch tubes Q1 and Q3.

[0012] To optimize the above technical solutions, specific measures taken also include:

[0013] Step 4 above D θ_PCRM for:

[0014] D θ_PCRM =K vg v g +K ig i g_ref +D θ_PCRM_dc

[0015] Among them, K vg , K ig and D θ_PCRM_dc are all constants.

[0016] Step 4 above D θ_PDCM for:

[0017]

[0018] Among them, D c_max The expression is:

[0019] D c_max =2L c I ZVS / (Vo T s )

[0020] Among them, L c is the filter inductor L c Inductance value;

[0021] T s is the switching cycle length of the switch tube;

[0022] I ZVS To achieve the minimum current value for soft switching;

[0023] D c_max The inductor current is from –I ZVS Rise to I ZVS Or from I ZVS Descend to –I ZVS The maximum value of the duty cycle corresponding to the time.

[0024] I ZVS This is to achieve soft switching of the switch tubes Q2 and Q3, to ensure that the inductor current is positive before the switch tube is turned on, and to discharge the junction capacitance of the switch tube to zero so that its reverse-parallel diode can naturally turn on.

[0025] A four-tube Buck-Boost PFC converter control circuit includes an input current reference signal generating circuit, a Q1 and Q2 drive signal generating circuit, a Q3 and Q4 drive signal generating circuit, and a phase shift signal generating circuit;

[0026] Input current reference signal generating circuit, used to generate input current reference signal i using output voltage regulator and multiplier g_ref ; Q1 and Q2 drive signal generating circuit, used to use input current regulator, comparator, clock signal CLK1, 1# RS trigger to generate Q1 and Q2 drive signals; Q3 and Q4 drive signal generating circuit, used to use hysteresis comparator, OR gate, CLK1, clock signal CLK2, 2# RS trigger to generate Q3 and Q4 drive signals; phase shift signal generating circuit, used to use subtractor, multiplier Mult2, adder, diode gating circuit, comparator and monostable circuit to generate clock signal CLK2, whose phase difference with CLK1 corresponds to phase shift duty ratio D θ .

[0027] The output voltage regulator includes an operational amplifier EA1 and its peripheral circuits, which are used to sample the output voltage signal v o_s and the reference signal V o_ref The error is amplified, and the output signal of EA1 v c With the input voltage sampling signal v g_s After multiplication by the multiplier, the input current reference signal i is obtainedg_ref ,i g_ref With v g The waveform is the same.

[0028] The above-mentioned input current regulator includes an operational amplifier EA2 and its peripheral circuits, which samples the input current signal i g_s and reference signal i g_ref The error is amplified, and the output signal of EA2 v error and sawtooth wave v saw After comparison by the comparator, it is sent to the 1#RS trigger together with CLK1 to generate the driving signal of Q1 and Q2; the sawtooth wave v saw Synchronous with CLK1, v saw The amplitude is recorded as V M , then the duty cycle of Q1 is D y1 for:

[0029] In the above Q3 and Q4 drive signal generating circuit, i Lc with -I ZVS The output signal v of the hysteresis comparator is sent to the hysteresis comparator Comp2, or the gate is connected to the hysteresis comparator comp OR operation is performed with CLK1. When i Lc Descend to -I ZVS When v comp is high, the Q generated by the OR gate 3off Also high level, Q 3off Send it to the reset terminal of 2#RS trigger to turn off Q3. If i Lc Failure to drop to -I at the end of the switching cycle ZVS When CLK1 is high, Q2 and Q3 are turned off at the same time, and the turn-on time of Q3 is determined by CLK2.

[0030] In the above phase shift signal generating circuit, the subtractor includes EA3 and its peripheral circuits, and the adder includes EA4 and its peripheral circuits. Under PDCM, the sampling signal v g_s and v o_s It is sent to the subtractor and then clamped by the diode to generate the y input signal y of Mult2 Mult2 ,y Mult2 With v error Multiply and divide by v o_s , and then through the adder and D c_max V M Add them together to get D θ_PDCM The modulation signal v θ_PDCM ,for:

[0031]

[0032] The proportional adder includes the operational amplifier EA5 and its peripheral circuits. Under PCRM, the input voltage sampling signal v g_s The current reference signal i is sent to the reverse input terminal of EA5. g_ref and DC signal V M It is sent to the non-inverting input of EA5, and finally generates D θ_PCRM The modulation signal v θ_PCRM ;

[0033] v θ_PCRM and v θ_PDCM Get v through the diode gating circuit θ , and then through the comparator and sawtooth wave v saw After comparison, a phase-shifted PWM signal Q is generated. θ , its rising edge corresponds to CLK1, and the duty cycle is D θ ; where v θ for:

[0034] v θ =min[max(v θ_PCRM ,v θ_PDCM ),v error ]

[0035] Q θ The falling edge of the monostable circuit generates CLK2, which lags behind CLK1 by a time of D θ T s .

[0036] The present invention has the following beneficial effects:

[0037] This invention achieves power factor correction, zero voltage switching (ZVS) for all switching transistors, and minimized inductor current RMS in a four-transistor Buck-Boost PFC converter. Compared to a boost PFC converter, this invention allows flexible output voltage selection by adjusting the duty cycle of switch Q1. Compared to a two-transistor Buck-Boost PFC converter, this invention replaces diodes with switching transistors, allowing reverse inductor current flow and achieving zero voltage switching (ZVS) for all switching transistors. This invention uses PWM plus phase-shift control to minimize inductor current ripple and RMS. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] Figure 1 This is the circuit structure diagram of the four-tube Buck-Boost PFC converter.

[0039] Figure 2 FIG. 4 is an overall block diagram of a four-tube Buck-Boost PFC converter control circuit according to an embodiment of the present invention.

[0040] Figure 3This is the working waveform of the converter in the present invention.

[0041] Figure 4a This is an experimental waveform diagram of the PCRM mode under full load when the effective value of the input voltage is 220V in the present invention.

[0042] Figure 4b This is an experimental waveform diagram of the PDCM mode under full load when the effective value of the input voltage is 220V in the present invention.

[0043] Figure 5a This is an experimental waveform diagram of the present invention when the effective value of the input voltage jumps between 176V and 264V at full load.

[0044] Figure 5b This is an experimental waveform diagram of the load jumping between 10% and 90% when the effective value of the input voltage is 220V in the present invention. DETAILED DESCRIPTION

[0045] The embodiments of the present invention are described in further detail below with reference to the accompanying drawings.

[0046] The present invention proposes a four-tube Buck-Boost PFC converter control method. Figure 1 The circuit structure diagram of the four-tube Buck-Boost PFC converter is shown in Figure 2. The four-tube Buck-Boost PFC converter mainly consists of four switching tubes Q1, Q2, Q3, and Q4, a filter inductor L c , an output filter capacitor C o , a rectifier bridge capacitor C g and an input voltage source v in The connected diode rectifier bridge is composed of the following components. The switch tube Q1 and the switch tube Q2 are complementary and conduction, forming a bridge arm unit, and the switch tube Q3 and the switch tube Q4 are complementary and conduction, forming a bridge arm unit. Inductor L c The two ends of the capacitor are connected to the midpoints of the bridge arms of the switch tubes Q1 and Q2 and the midpoints of the bridge arms of the switch tubes Q3 and Q4 respectively. The output filter capacitor C o The two ends of the rectifier bridge capacitor C are connected to the drain of the switch tube Q3 and the source of the switch tube Q4 to filter out the ripple of the switching frequency. g The two ends of the switch are connected to the drain of the switch tube Q1 and the source of the switch tube Q2 to absorb i g Short-term negative current to ensure v g In T s The interior remains basically unchanged.

[0047] The control method includes three control variables: the duty cycle D of the switch tube Q1 y1 , the duty cycle D of the switch tube Q4 y2, and the phase shift duty cycle D corresponding to the phase difference between the turn-on moments of Q1 and Q3 θ Among them, the control degree of freedom D y1 It is used to control the switching action of the switch tube Q1, and its inverse signal is used to control the switching action of the switch tube Q2; the control degree of freedom D y2 It is used to control the switching action of the switch tube Q4, and its inverse signal is used to control the switching action of the switch tube Q3; the control degree of freedom D θ It is used to control the phase difference between the turn-on time of switch tubes Q1 and Q3. To achieve soft switching of switch tubes Q1 and Q4, it is necessary to ensure that the inductor current is too negative before the switch tube is turned on, so that the junction capacitance of the switch tube is discharged to zero and the reverse parallel diode is naturally turned on. The magnitude of the negative current required is defined as –I ZVS To achieve soft switching of the switches Q2 and Q3, it is necessary to ensure that the inductor current is positive before the switch is turned on, discharge the junction capacitance of the switch to zero, and make its reverse-parallel diode naturally conduct. The magnitude of the positive current required is defined as I ZVS .

[0048] The control methods specifically include:

[0049] Step 1: Sample the output voltage v o and input voltage v g , output voltage sampling signal v o_s and the reference signal V o_ref The error is amplified by the output voltage regulator, and the output signal v c With the input voltage sampling signal v g_s After multiplication, the input current reference signal i is obtained g_ref ;

[0050] Step 2: Sample input current i g , input current sampling signal i g_s and the input current reference signal i g_ref In comparison, the input current is closed-loop regulated by the input current regulator to follow the reference, and the duty cycle D of the switch tube Q1 is obtained. y1 ;

[0051] Step 3: Sample the inductor current i Lc , with the negative current reference required for soft switching -I ZVS For comparison, when i Lc Linearly decrease to -I ZVS When the switch tube Q3 is turned off, the duty cycle of the switch tube Q3 is 1-D y2 ;

[0052] Step 4: Under PRCM, the phase shift duty cycle D θ The theoretical calculated value is actually the input voltage v g and input current ig The function of phase shift duty cycle is approximated by a plane, thereby achieving the goal of simplifying control. The simplified phase shift duty cycle is a linear combination of the input voltage sampling value and the input current reference signal. g , the phase shift angle D between the phase difference of the switch tubes Q1 and Q3 at the time of opening is approximately calculated θ_PCRM ,Right now:

[0053] D θ_PCRM =K vg v g +K ig i g_ref +D θ_PCRM_dc

[0054] Among them, K vg , K ig and D θ_PCRM_dc are all constants.

[0055] In PDCM, the sampling input voltage v g and the output voltage v o , the phase shift angle D between the phase difference of the switch tubes Q1 and Q3 at the time of opening is approximately calculated θ_PDCM ,Right now:

[0056]

[0057] Among them, D c_max The expression is:

[0058] D c_max =2L c I ZVS / (V o T s )

[0059] In order to ensure that Lc There is enough pulsation to achieve ZVS of the switch tube, and D θ_PCRM and D θ_PDCM The larger value of the two is sent to the diode gating circuit, which is the phase shift duty cycle D θ .

[0060] In addition, the present invention also proposes a four-tube Buck-Boost PFC converter control circuit. The embodiment of the present invention takes an analog control circuit as an example, and its principle diagram is shown as follows: Figure 2 As shown, the control circuit mainly includes four components: input current reference signal generating circuit, Q1 and Q2 drive signal generating circuit, Q3 and Q4 drive signal generating circuit, and phase shift signal generating circuit.

[0061] (A) Input current reference signal generation circuit

[0062] The input current reference signal generating circuit is used to obtain the input current reference signal i g_ref The operational amplifier EA1 and its peripheral circuits form an output voltage regulator, which samples the output voltage signal v o_s and the reference signal V o_ref The error is amplified. The output signal of EA1 is v c With the input voltage sampling signal v g_s After multiplication, the input current reference signal i is obtained g_ref In steady state, v c remains essentially unchanged, so i g_ref With v g The waveform is the same.

[0063] (B) Q1 and Q2 drive signal generation circuit

[0064] The Q1 and Q2 drive signal generating circuit is used to obtain the drive signals of Q1 and Q2. The operational amplifier EA2 and its peripheral circuits constitute the input current regulator, which samples the input current signal i g_s and reference signal i g_ref The error is amplified. The output signal of EA2 is v error and sawtooth wave v saw After comparison, it is sent to RS trigger 1 together with CLK1 to generate the driving signal of Q1 and Q2. saw Synchronous with CLK1, v saw The amplitude is recorded as V M , then the duty cycle of Q1 is D y1 for:

[0065]

[0066] (C) Q3 and Q4 drive signal generation circuit

[0067] The Q3 and Q4 drive signal generating circuit is used to obtain the drive signals of Q3 and Q4. Lc Descend to -I ZVS It must be turned off at the same time as Q1, and must not be turned off later than Q2 to ensure the optimal switching timing. Lc with -I ZVS Sent to the hysteresis comparator Comp2, when i Lc Descend to -I ZVS When the comparator output signal v comp is high, the Q generated by the OR gate 3off Also high level. 3off Send it to the reset terminal of 2#RS flip-flop to turn off Q3. In order to ensure the optimal switching timing, CLK1 and v comp Perform an OR operation. If i LcFailure to drop to -I at the end of the switching cycle ZVS When CLK1 is high, Q2 and Q3 are turned off at the same time. The turn-on time of Q3 is determined by CLK2.

[0068] (D) Phase-shift signal generation circuit

[0069] The phase shift signal generating circuit is used to obtain the clock signal CLK2, whose phase difference with CLK1 corresponds to the phase shift duty ratio D θ In different modes, D θ There are different expressions, which are analyzed below.

[0070] Under PCRM, the operational amplifier EA5 and its peripheral circuits form a proportional adder. The input voltage sampling signal v g_s The current reference signal i is sent to the reverse input terminal of EA5. g_ref and DC signal V M It is sent to the non-inverting input of EA5, and finally generates D θ_PCRM The modulation signal v θ_PCRM .

[0071] Under PDCM, v θ_PDCM The calculation circuit consists of a subtractor (EA3 and its peripheral circuits), a multiplier Mult2 and an adder (EA4 and its peripheral circuits). The sampling signal v g_s and v o_s It is sent to the subtractor and then clamped by the diode to generate the y input signal of Mult2, y Mult2 With v error Multiply and divide by v o_s , and then with D c_max V M Add them together to get D θ_PDCM The modulation signal v θ_PDCM ,for:

[0072]

[0073] In order to ensure that Lc There is enough pulsation to achieve ZVS of the switch tube, v θ Should take v θ_PCRM and v θ_PDCM The larger value of , but not more than v error , to ensure the optimal switching timing, that is:

[0074] v θ =min[max(v θ_PCRM ,v θ_PDCM ),v error ]

[0075] Use diode gating circuit to get vθ , and then with sawtooth wave v saw After comparison, a phase-shifted PWM signal Q is generated. θ , its rising edge corresponds to CLK1, and the duty cycle is D θ .Q θ The falling edge of the monostable circuit generates CLK2, so the time lag of CLK2 behind CLK1 is D θ T s .

[0076] Through the above control circuit, the following can be achieved: Figure 3 The working waveform is shown.

[0077] In order to further illustrate the advantages of this control method, an experimental example of the present invention is given below.

[0078] According to the parameters of the 500W four-tube Buck-Boost PFC converter given in Table 1, a prototype was built in the laboratory. Figure 4a 、 Figure 4b The experimental waveform diagram of the input voltage RMS value under full load is given, where: Figure 4a This is the experimental waveform of the PCRM mode; Figure 4b The experimental waveform diagram of PDCM mode shows that all switches can achieve ZVS and the inductor current pulsation is small. Figure 5a 、 Figure 5b The experimental waveforms of load jump and input voltage jump are given, among which, Figure 5a The middle one is the experimental waveform when the input voltage RMS value jumps between 176V and 264V at full load; Figure 5b The experimental waveform is shown when the load jumps between 10% and 90% when the effective value of the input voltage is 220V. It can be seen that the output voltage can be stabilized at 300V and has a fast dynamic response speed.

[0079] Table 1 Main parameters of the four-tube Buck-Boost PFC converter

[0080] parameter symbol Numerical parameter symbol Numerical Input voltage RMS <![CDATA[V in ]]> 220V±20％ filter inductors <![CDATA[L c ]]> 16μH Input voltage frequency <![CDATA[f in ]]> 50Hz Output filter capacitor <![CDATA[C o ]]> 360μF Output voltage <![CDATA[V o ]]> 300V Input filter inductor <![CDATA[L in ]]> 12μH Output power <![CDATA[P o ]]> 500W Input filter capacitor <![CDATA[C in ]]> 510nF Switching frequency <![CDATA[f s ]]> 500kHz Rectifier bridge capacitor <![CDATA[C g ]]> 270nF

[0081] The above are merely preferred embodiments of the present invention. The scope of protection of the present invention is not limited to the above embodiments. All technical solutions based on the principles of the present invention are within the scope of protection of the present invention. It should be noted that for those skilled in the art, various improvements and modifications that do not depart from the principles of the present invention should be considered within the scope of protection of the present invention.

Claims

1. A control method for a four-tube Buck-Boost PFC converter, wherein the four-tube Buck-Boost PFC converter includes four switch tubes Q1, Q2, Q3, and Q4, a filter inductor L c , an output filter capacitor C o , a rectifier bridge capacitor C g and an input voltage source v in The connected diode rectifier bridge; Q1 and Q2 are complementary turned on to form a bridge arm unit, Q3 and Q4 are complementary turned on to form a bridge arm unit; L c The two ends of C are connected to the midpoints of the bridge arm units of Q1 and Q2 and the midpoints of the bridge arm units of Q3 and Q4 respectively. o In parallel with the bridge arm units of Q3 and Q4, the diode rectifier bridge, C g Both are connected in parallel with the bridge arm units of Q1 and Q2; C o 、C g The voltages at both ends are the output voltage v o and input voltage v g , characterized in that, The control method includes: Step 1: Sample v o and v g , get the output voltage sampling signal v o_s With the input voltage sampling signal v g_s , v o_s and the reference signal V o_ref The error is amplified by the output voltage regulator to obtain the signal v c , and v g_s After multiplication, the input current reference signal i is obtained g_ref ; Step 2: Sample input current i g Get the input current sampling signal i g_s ,i g_s and i g_ref In comparison, the input current is adjusted by closed loop through the input current regulator to make the input current follow the reference, and the duty cycle D of Q1 is obtained. y1 , to control the switching action of the switch tube Q1, and its inverse signal is used to control the switching action of the switch tube Q2; Step 3: Sampling L c The inductor current i Lc , with the negative current reference required for soft switching -I ZVS For comparison, when i Lc Linearly decrease to -I ZVS The switch Q3 is turned off at this time, and the duty cycle of Q3 is obtained according to the turn-off and turn-on time of Q3. y2 , to control the switching action of the switch tube Q3, and its inverse signal is used to control the switching action of the switch tube Q4, where the opening time of Q3 is determined by CLK2, D y2 is the duty cycle of the switch tube Q4; Step 4: Under PCRM, according to v g 、i g_ref Approximately calculate the phase shift angle D between the phase difference between Q1 and Q3 when they are turned on θ_PCRM ; Under PDCM, according to v o and v g 、D y1 Approximately calculate the phase shift angle D between the phase difference between the switch tubes Q1 and Q3 when they are turned on θ_PDCM ; D θ_PCRM and D θ_PDCM The larger value of the two is sent to the diode gating circuit and used as the phase shift duty cycle D θ , to control the phase difference between the turn-on moments of the switch tubes Q1 and Q3; The D θ_PCRM for: D θ_PCRM =K vg v g +K ig i g_ref +D θ_PCRM_dc Among them, K vg , K ig and D θ_PCRM_dc are all constants; The D θ_PDCM for: Among them, D c_max The expression is: D c_max =2L c I ZVS / (V o T s ) Among them, L c is the filter inductor L c Inductance value; T s is the switching cycle length of the switch tube; I ZVS To achieve the minimum current value for soft switching; D c_max The inductor current is from –I ZVS Rise to I ZVS Or from I ZVS Descend to –I ZVS The maximum value of the duty cycle corresponding to the time.

2. A four-transistor Buck-Boost PFC converter control circuit implementing the method of claim 1, characterized in that: It includes an input current reference signal generating circuit, a Q1 and Q2 drive signal generating circuit, a Q3 and Q4 drive signal generating circuit, and a phase shift signal generating circuit; Input current reference signal generating circuit, used to generate input current reference signal i using output voltage regulator and multiplier g_ref ; Q1 and Q2 drive signal generating circuit, used to use the input current regulator, comparator, clock signal CLK1, 1# RS trigger to generate Q1 and Q2 drive signals; Q3 and Q4 drive signal generating circuit, used to use the hysteresis comparator, OR gate, CLK1, clock signal CLK2, 2# RS trigger to generate Q3 and Q4 drive signals; Phase shift signal generating circuit, used to generate clock signal CLK2 by using subtractor, multiplier Mult2, adder, diode gating circuit, comparator and monostable circuit, whose phase difference with CLK1 corresponds to phase shift duty ratio D θ .

3. A four-tube Buck-Boost PFC converter control circuit according to claim 2, characterized in that: The output voltage regulator includes an operational amplifier EA1 and its peripheral circuits, which are used to sample the output voltage signal v o_s and the reference signal V o_ref The error is amplified, and the output signal of EA1 v c With the input voltage sampling signal v g_s After multiplication by the multiplier, the input current reference signal i is obtained g_ref ,i g_ref With v g The waveform is the same.

4. A four-tube Buck-Boost PFC converter control circuit according to claim 2, characterized in that: The input current regulator includes an operational amplifier EA2 and its peripheral circuits, and samples the input current signal i g_s and reference signal i g_ref The error is amplified, and the output signal of EA2 v error and sawtooth wave v saw After comparison by the comparator, it is sent to the 1#RS trigger together with CLK1 to generate the driving signal of Q1 and Q2; the sawtooth wave v saw Synchronous with CLK1, v saw The amplitude is recorded as V M , then the duty cycle of Q1 is D y1 for:

5. The four-tube Buck-Boost PFC converter control circuit according to claim 2, characterized in that: In the Q3 and Q4 drive signal generating circuit, i Lc with -I ZVS The output signal v of the hysteresis comparator is sent to the hysteresis comparator Comp2, or the gate is connected to the hysteresis comparator comp OR operation is performed with CLK1. When i Lc Descend to -I ZVS When v comp is high, the Q generated by the OR gate 3off Also high level, Q 3off Send it to the reset terminal of 2#RS trigger to turn off Q3. If i Lc Failure to drop to -I at the end of the switching cycle ZVS When CLK1 is high, Q2 and Q3 are turned off at the same time, and the turn-on time of Q3 is determined by CLK2.

6. The four-transistor Buck-Boost PFC converter control circuit according to claim 2, characterized in that: In the phase shift signal generating circuit, the subtractor includes EA3 and its peripheral circuits, the adder includes EA4 and its peripheral circuits, and under PDCM, the sampling signal v g_s and v o_s It is sent to the subtractor and then clamped by the diode to generate the y input signal y of Mult2 Mult2 ,y Mult2 With v error Multiply and divide by v o_s , and then through the adder and D c_max V M Add them together to get D θ_PDCM The modulation signal v θ_PDCM ,for: The proportional adder includes the operational amplifier EA5 and its peripheral circuits. Under PCRM, the input voltage sampling signal v g_s The current reference signal i is sent to the reverse input terminal of EA5. g_ref and DC signal V M It is sent to the non-inverting input of EA5, and finally generates D θ_PCRM The modulation signal v θ_PCRM ; v θ_PCRM and v θ_PDCM Get v through the diode gating circuit θ , and then through the comparator and sawtooth wave v saw After comparison, a phase-shifted PWM signal Q is generated. θ , its rising edge corresponds to CLK1, and the duty cycle is D θ ; where v θ for: v θ =min[max(v θ_PCRM ,v θ_PDCM ),v error ] Q θ The falling edge of the monostable circuit generates CLK2, which lags behind CLK1 by a time of D θ T s .

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