A method and circuit for CTLE adaptive equalization convergence

Abstract

The present invention provides a method and circuit for CTLE adaptive equalization convergence, the circuit is composed of a continuous time linear equalizer CTLE, a variable gain amplifier VGA, a high-pass filter, a low-pass filter, a power detection circuit, a comparator and a digital control unit. The present invention adopts a spectrum balance structure to compare with the traditional spectrum comparison equalization structure, which greatly saves power consumption and area. Compared with the traditional spectrum balance equalization structure, digital control is used to perform adaptive equalization convergence, which is more controllable than using analog units for convergence, and the digital circuit is less affected by PVT, has good robustness, and has higher convergence accuracy; at the same time, the cutoff frequency of the filter significantly affected by PVT is calibrated by the digital control unit, which further improves the convergence accuracy of adaptive equalization and has a wider range of application scenarios.

Description

Technical Field

[0001] The invention belongs to the technical field of optical communication and high-speed interface, and in particular relates to a method and circuit for CTLE adaptive equalization convergence. Background Art

[0002] In high-speed signal transmission systems, the signal transmission rate is getting higher and higher. The parasitic distribution parameters of the signal transmission medium (package bonding wire, PCB transmission line, etc.) will cause serious insertion loss (Insert loss) to the high-frequency signal, causing the signal to be seriously affected by inter-symbol interference (ISI), the eye diagram quality deteriorates, and the bit error rate increases. In order to compensate for the insertion loss caused by the channel, a continuous time linear equalizer (CTLE) is generally used at the front end of the receiver. CTLE has a high-pass transmission characteristic, which complements the low-pass characteristic of the channel, and can achieve frequency compensation to ultimately produce a relatively flat frequency response. The typical CTLE schematic diagram is as follows: Figure 1 shown.

[0003] The role of CTLE is to offset the impact of channel insertion loss. Compensating for channel insertion loss as much as possible is of great significance for improving signal quality, increasing transmission distance and reliability, and adapting to different channel conditions. The attenuation of signals in different channels is different, and it will be affected by temperature and other factors. In addition, due to the high-pass characteristics of CTLE itself, changes in process (P), voltage (V) and temperature (T) will affect its performance. Therefore, it is very important to accurately compensate for channel insertion loss.

[0004] For a typical source-degenerated CTLE, a resistor array and a capacitor array are generally preset, and the equalization degree is adjusted through programmable switch control to achieve the best compensation effect. However, in many application scenarios, it is difficult for the receiver to estimate the insertion loss of the channel. It is difficult to effectively compensate for the insertion loss of the channel only by relying on the above method. Therefore, the CTLE needs to be able to automatically adjust the equalization degree according to the high-frequency loss degree of the input signal to achieve an adaptive effect.

[0005] There are two types of CTLE adaptive equalization structures in the prior art, one is spectrum balancing and the other is spectrum comparison.

[0006] Spectrum balancing structure such as Figure 2 As shown, the problem with this structure is that the preset cutoff frequency is fixed, the theoretical value is 0.28 , It is the signal rate. In the actual circuit, the cutoff frequency of the filter will be affected by PVT, resulting in a shift in the comparison of high-frequency and low-frequency components, making the CTLE equalization effect not optimal. In some extreme cases, the adaptive equalization may even fail, limiting the application scenarios of the spectrum balancing structure.

[0007] The principle of spectrum comparison is to connect a limiter to the output of CTLE. The signal output by the limiter is close to the ideal signal. By comparing the output of CTLE and the output signal of the limiter, the comparison result is used to control the equalization degree of CTLE to achieve self-adaptation. The problem with spectrum comparison is that compared with spectrum balancing, it requires the addition of a limiter and additional filters, rectifiers, comparators, and feedback control modules, which requires a larger chip area and power consumption. Summary of the invention

[0008] The purpose of the present invention is to provide a method and circuit for CTLE adaptive equalization convergence, so as to solve the technical problem that the prior art proposed in the above background technology adopts a fixed cutoff frequency, resulting in poor or invalid adaptive equalization.

[0009] To achieve the above object, the present invention provides the following technical solutions:

[0010] A CTLE adaptive equalization convergence circuit comprises a continuous time linear equalizer CTLE and a variable gain amplifier VGA. The adaptive equalization convergence circuit further comprises a high-pass filter, a low-pass filter, a power detection circuit, a comparator and a digital control unit. The power detection circuit converts the high-frequency signal and the low-frequency signal output by the high-pass filter and the low-pass filter into a DC signal that can be compared. The comparator is used to compare the values ​​of the high-frequency component and the low-frequency component. After the comparison result is processed by the digital control unit, the equalization value of the CTLE, the cutoff frequency of the high-pass filter and the low-pass filter are adjusted. Make adjustments.

[0011] Preferably, the digital control unit includes a cut-off frequency Calibration unit and equalization control unit.

[0012] Preferably, the equalized data signal output by the CTLE is used as one input of the high-pass filter and one input of the low-pass filter, and the cut-off frequency The calibration code generated by the calibration unit is used as two inputs of the high-pass filter and the two inputs of the low-pass filter. The outputs of the high-pass filter and the low-pass filter are used as inputs of the power detection circuit respectively. The output of the power detection circuit is used as input of the comparator. The signal output by the comparator is processed by the digital control unit. The equalization value generated by the equalization control unit is used to adjust the equalization value of the CTLE.

[0013] Another object of the present invention is to provide a CTLE adaptive equalization convergence method, which is applied to the above CTLE adaptive equalization convergence circuit, and the adaptive equalization starts by controlling the register, firstly setting the default value of the CTLE equalization and the cutoff frequencies of the high-pass filter and the low-pass filter. The maximum value of the digital control unit, after receiving the signal output by the comparator, performs the following processing: when the signal is 1, reduce the equalization value; when the signal is 0, increase the equalization value; then determine whether the comparator outputs a long 0 in a specific clock cycle, if it appears, reduce the cutoff frequency, when it does not appear, reduce and lock the cutoff frequency; after locking, the digital control unit detects whether the output of the comparator appears 0101 in a certain period, if 0101 appears, it is determined that the equalization value adjusted by the digital control unit is near the optimal equalization value, at this time, the digital control unit will lock the equalization value to complete the adaptive equalization.

[0014] Preferably, the specific clock cycle refers to 16 clock cycles, and the certain cycle refers to more than 8 clock cycles.

[0015] The present invention has the following beneficial effects:

[0016] 1. Use a digital control unit to determine the convergence of adaptive equalization.

[0017] 2. Use a digital control unit to control the calibration of the filter cutoff frequency.

[0018] Compared with the traditional spectrum comparison and equalization structure, the present invention adopts a spectrum balancing structure, which greatly saves power consumption and area. Compared with the traditional spectrum balancing equalization structure, digital control is used to perform the convergence of adaptive equalization, which is more controllable than using analog units to converge. The digital circuit is less affected by PVT, has good robustness, and has higher convergence accuracy. At the same time, the cutoff frequency of the filter that is significantly affected by PVT is calibrated through the digital control unit, which further improves the convergence accuracy of the adaptive equalization and has a wider range of application scenarios. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings required for describing the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other accompanying drawings can be obtained based on these accompanying drawings without paying creative work.

[0020] Figure 1 It is a typical CTLE schematic diagram of the prior art;

[0021] Figure 2The schematic diagram of spectrum balancing of the prior art;

[0022] Figure 3 It is a schematic diagram of the CTLE adaptive equalization structure of the present invention;

[0023] Figure 4 This is the implementation process of the adaptive equalization of the present invention. DETAILED DESCRIPTION

[0024] The following will be combined with the accompanying drawings to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0025] See also Figure 3-4 As shown, a CTLE adaptive equalization convergence circuit has a structure as shown in Figure 3 As shown, it includes a continuous time linear equalizer (CTLE), a variable gain amplifier (VGA), a high-pass filter, a low-pass filter, a power detection circuit, a comparator, and a digital control unit, wherein the digital control unit includes a cut-off frequency Calibration unit, equalization control unit.

[0026] The CTLE equalizes the input signal to compensate for the frequency selective fading of the channel. By adjusting its gain and frequency response characteristics, the high-frequency components in the signal are enhanced to offset the attenuation of the high-frequency signal by the channel. The CTLE usually has the characteristics of a high-pass filter, which can enhance the high-frequency part of the signal, make the signal flatter over the entire frequency range, and reduce inter-symbol interference.

[0027] The VGA is used to adjust the amplitude of the input signal. In the adaptive equalization convergence circuit, the gain of the VGA can be dynamically adjusted according to different input signal strengths and system requirements. By adjusting the gain of the VGA, the amplitude of the input signal can be kept within a suitable range for subsequent circuit processing.

[0028] The high-pass filter is used to filter the low-frequency components in the CTLE output signal.

[0029] The low-pass filter is used to filter the high-frequency components in the CTLE output signal. In the adaptive equalization convergence circuit, the low-pass filter and the high-pass filter are used together to select the same cut-off frequency to separate the high-frequency components and the low-frequency components in the CTLE output signal.

[0030] The power detection circuit converts the high-frequency signal and the low-frequency signal output by the high-pass filter and the low-pass filter into a direct current signal that can be compared, and inputs the direct current signal into the comparator.

[0031] The comparator is used to compare the values ​​of the high-frequency component and the low-frequency component. After the comparison result is processed by the digital control unit, the equalization value of the CTLE, the cutoff frequency of the high-pass filter and the low-pass filter are adjusted. Make adjustments.

[0032] The digital control unit is the core control part of the whole adaptive equalization convergence circuit. The digital control unit receives the feedback information of the comparator and adjusts the cutoff frequency according to the preset algorithm and strategy. The calibration unit and the equalization control unit output a calibration code and an equalization value respectively, wherein the calibration code is used as a control signal of the cutoff frequency of the high-pass filter and the low-pass filter, and the equalization value is used as a control signal of the CTLE.

[0033] The equalized data signal output by the CTLE is used as one input of the high-pass filter and one input of the low-pass filter. The calibration code generated by the calibration unit is used as two inputs of the high-pass filter and the two inputs of the low-pass filter. The outputs of the high-pass filter and the low-pass filter are used as inputs of the power detection circuit respectively. The output of the power detection circuit is used as input of the comparator. The signal output by the comparator is processed by the digital control unit. The equalization value generated by the equalization control unit in the digital control unit is used to adjust the equalization value of the CTLE.

[0034] The CTLE adaptive equalization convergence process of the present invention includes an analog part and a digital part. The process of the analog part is as follows: after the signal attenuated by the link enters the CTLE, the cutoff frequency is The high-pass filter and the low-pass filter filter the low-frequency component and the high-frequency component of the signal respectively. After filtering, the high-frequency signals output by the high-pass filter and the low-pass filter are converted into low-frequency signals that can be compared through the power detection circuit. The comparator compares the values ​​of the high-frequency component and the low-frequency component. After the comparison result is processed by the digital control unit, the equalization value of the CTLE and the cutoff frequencies of the high-pass filter and the low-pass filter are adjusted.

[0035] The CTLE adaptive equalization digital part implementation process of the present invention is as follows: Figure 4As shown, adaptive equalization starts by controlling the register. First, the default value of CTLE equalization and the maximum value of the cutoff frequency of the high-pass filter and the low-pass filter are set. After the digital control unit receives the signal output by the comparator, it performs the following processing: when the signal is 1, the equalization value is reduced; when the signal is 0, the equalization value is increased; then it is determined whether the comparator output has a long 0, that is, when 0 appears in 16 clock cycles, the cutoff frequency is reduced, and when it does not appear, the cutoff frequency is reduced and locked. The digital control unit will detect whether the cutoff frequency is locked. Only after locking, the digital control unit will detect whether the signal appears 0101 within a certain period. When the equalization value adjusted by the digital control unit is close to the optimal value, the output of the comparator will appear 0101. The certain period is generally more than 8 clock cycles. When 0101 appears within a certain period, it can be determined that the equalization value adjusted by the digital control unit is close to the optimal equalization value. The digital control unit will lock the equalization value and complete the adaptive equalization.

[0036] Since the performance of analog circuits is significantly affected by PVT, in the above-mentioned spectrum balance, the change of the filter's cutoff frequency will seriously affect the equalization effect of the adaptive equalization. When the cutoff frequency is too high, the low-frequency component of the filter output will be too high and the high-frequency component will be too low; when the cutoff frequency is too low, the low-frequency component of the filter output will be too low and the high-frequency component will be too high. When the above two situations occur, the adaptive equalization may not converge, that is, the signal output by the comparator may be long 0 or long 1, which means that the high-frequency component and the low-frequency component are still not equal when the equalization value is adjusted to the minimum or maximum. Based on the existing spectrum balance structure, the present invention uses a comparator and a digital control unit to replace the analog V / I converter and the charge pump to control the adaptive equalization. At the same time, in view of the shortcomings of the traditional structure, the present invention automatically adjusts the filter's cutoff frequency through digital algorithm control, so that the filter's cutoff frequency is always near a reasonable value and is not affected by PVT.

[0037] The preferred embodiments of the present invention disclosed above are only used to help explain the present invention. The preferred embodiments do not describe all the details in detail, nor do they limit the invention to the specific implementation methods described. Obviously, many modifications and changes can be made according to the content of this specification. This specification selects and specifically describes these embodiments in order to better explain the principles and practical applications of the present invention, so that those skilled in the art can understand and use the present invention well.

Claims

1. A CTLE adaptive equalization convergence circuit, comprising a continuous time linear equalizer CTLE and a variable gain amplifier VGA, characterized in that: The adaptive equalization convergence circuit also includes a high-pass filter, a low-pass filter, a power detection circuit, a comparator and a digital control unit. The power detection circuit converts the high-frequency signal and the low-frequency signal output by the high-pass filter and the low-pass filter into a DC signal that can be compared. The comparator is used to compare the values ​​of the high-frequency component and the low-frequency component. After the comparison result is processed by the digital control unit, the equalization value of the CTLE, the cutoff frequency of the high-pass filter and the low-pass filter are adjusted. To adjust, the digital control unit includes a cut-off frequency The calibration unit and the equalization control unit, the equalized data signal output by the CTLE is used as one input of the high-pass filter and one input of the low-pass filter, and the cutoff frequency The calibration code generated by the calibration unit is used as two inputs of the high-pass filter and the two inputs of the low-pass filter. The outputs of the high-pass filter and the low-pass filter are used as inputs of the power detection circuit respectively. The output of the power detection circuit is used as input of the comparator. The signal output by the comparator is processed by the digital control unit. The equalization value generated by the equalization control unit is used to adjust the equalization value of the CTLE.

2. A CTLE adaptive equalization convergence method, applied to the CTLE adaptive equalization convergence circuit of claim 1, characterized in that: Start by controlling the adaptive equalization through registers, first setting the default values ​​of the CTLE equalization and the high-pass filter and low-pass filter cutoff frequencies The digital control unit performs the following processing after receiving the signal output by the comparator: when the signal is 1, the equalization value is reduced; When the signal is 0, the equalization value is increased; then it is determined whether the comparator outputs a long 0 in a specific clock cycle, if so, the cutoff frequency is reduced, and when not, the cutoff frequency is reduced and locked; After locking, the digital control unit detects whether the output of the comparator appears 0101 within a certain period. If 0101 appears, it is determined that the equalization value adjusted by the digital control unit is near the optimal equalization value. At this time, the digital control unit will lock the equalization value and complete the adaptive equalization.

3. A CTLE adaptive equalization convergence method according to claim 2, characterized in that: The specific clock cycle refers to 16 clock cycles, and the certain cycle refers to more than 8 clock cycles.

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