Semiconductor structure manufacturing method and semiconductor structure

Abstract

The present disclosure provides a method for manufacturing a semiconductor structure and a semiconductor structure. The method includes: providing a substrate on which a stacked structure is formed, the stacked structure including alternating sacrificial layers and active layers, and the stacked structure includes a first portion and a second portion adjacent to each other; patterning the active layer in the first portion and removing the sacrificial layer in the first portion, with the remaining active layer in the first portion constituting a plurality of first active pillars arranged at intervals; forming a first filling layer, with the first filling layer filling the gaps between adjacent first active pillars; patterning the active layer in the second portion and removing the sacrificial layer in the second portion, with the remaining active layer constituting a plurality of second active pillars arranged at intervals, with the second active pillars contacting and connecting with the first active pillars to form active pillars; and forming a second filling layer, with the second filling layer filling the gaps between adjacent second active pillars. The present disclosure can trim at least the sidewalls of the first filling layer and the second filling layer.

Description

Technical Field

[0001] The embodiments of the present disclosure relate to the field of semiconductor technology, and in particular to a method for manufacturing a semiconductor structure and a semiconductor structure. Background Art

[0002] As the integration density of dynamic memory devices increases, higher requirements are placed on the arrangement and size of transistors in the dynamic memory array structure. For example, the morphology of the gate structure and the spacing between gate structures in the dynamic memory currently depend on the process conditions used to form the gate structure. However, these process conditions cannot precisely control the morphology of the gate structure, which may result in different morphologies for different gate structures, affecting the performance of the dynamic memory. In addition, the structural stability of the stacked active pillars in the dynamic memory needs to be improved. Summary of the Invention

[0003] The embodiments of the present disclosure provide a method for manufacturing a semiconductor structure and a semiconductor structure, which are at least helpful in solving the problem of irregular sidewalls of the first filling layer and the second filling layer.

[0004] According to some embodiments of the present disclosure, on the one hand, an embodiment of the present disclosure provides a method for manufacturing a semiconductor structure, comprising: providing a substrate on which a stacking structure is formed, the stacking structure comprising alternating sacrificial layers and active layers, and the stacking structure comprising a first part and a second part adjacent to each other; patterning the active layer in the first part, and removing the sacrificial layer in the first part, the active layer remaining in the first part constituting a plurality of first active pillars arranged at intervals along a second direction and a third direction, the first active pillars extending along a first direction, the first direction, the second direction and the third direction intersecting in pairs; forming a first filling layer, the first filling layer filling the gaps between adjacent first active pillars; patterning the active layer in the second part, and removing the sacrificial layer in the second part, the active layer remaining in the second part constituting a plurality of second active pillars arranged at intervals along the second direction and the third direction, and the second active pillars are in contact with and connected to the first active pillars to constitute active pillars; forming a second filling layer, the second filling layer filling the gaps between adjacent second active pillars.

[0005] In some embodiments, the steps of patterning the active layer in the first part and removing the sacrificial layer in the first part include: forming a first mask layer, the first mask layer covering the entire top surface of the second part of the stacked structure, and also covering a portion of the top surface of the first part of the stacked structure, wherein the first mask layer directly above the first part has a plurality of first openings arranged at intervals; using the first mask layer as a mask, etching the stacked structure along the first opening, and the remaining active layer in the first part constitutes the first active pillar; and using a lateral etching process to remove the sacrificial layer in the first part.

[0006] In some embodiments, the steps of patterning the active layer in the second part and removing the sacrificial layer in the second part include: patterning the first mask layer directly above the second part to form a plurality of second openings arranged at intervals, wherein the second openings are connected to the first openings along the first direction; using the first mask layer as a mask, etching the stacked structure along the second openings to form the second active pillars in the second part, each of the second active pillars being adjacent to a first active pillar along the first direction; and using a lateral etching process to remove the sacrificial layer in the second part.

[0007] In some embodiments, in the step of removing the sacrificial layer in the first part, the sacrificial layer on the side wall of the second part facing the first part is also etched, and a first gap is formed between the remaining sacrificial layer and the active layer of the second part; in the step of forming the first filling layer, the first filling layer also fills the first gap; in the step of removing the sacrificial layer in the second part, the first filling layer located in the first gap is also removed.

[0008] In some embodiments, after removing the sacrificial layer in the second part, part of the first filling layer remains in the first gap, and part of the sacrificial layer remains in the area adjacent to the first gap in the second part; before forming the second filling layer, it also includes: removing the first filling layer and the sacrificial layer remaining in the second part.

[0009] In some embodiments, the first filling layer and the remaining sacrificial layer in the second portion are removed by a same etching process, wherein an etching selectivity ratio of the etching process to the first filling layer and the sacrificial layer is 1-2.

[0010] In some embodiments, the stacked structure includes a third part surrounding the first part and the second part; before patterning the active layer in the first part, it also includes: removing the third part to expose the substrate facing the third part, and removing a portion of the thickness of the substrate facing the third part; forming a support structure, which is located in the area where the third part is removed and covers the side of the stacked structure.

[0011] In some embodiments, after removing the third portion and before forming the support structure, it also includes: laterally removing part of the sacrificial layer remaining at the edge of the stacked structure so that the remaining sacrificial layer and the active layer form a second gap; in the step of forming the support structure, the support structure also fills the second gap.

[0012] In some embodiments, the step of removing the third part includes: forming a second mask layer, the second mask layer is located on the top surfaces of the first part and the second part, and exposes the top surface of the third part; etching the third part using the second mask layer as a mask; in the process step of forming the support structure, the support structure also covers the side of the second mask layer; after forming the support structure, retaining the second mask layer; and patterning the second mask layer to form a first mask layer.

[0013] In some embodiments, after forming the second filling layer, the method further includes:

[0014] forming a plurality of first through holes, wherein the first through holes penetrate the first filling layer between adjacent first active pillars spaced apart along the second direction;

[0015] A third filling layer is formed, the third filling layer completely filling the first through hole; at least a portion of the third filling layer is removed to expose at least a portion of the surface of the first active pillar; and a gate is formed, the gate covering at least a portion of the exposed surface of the first active pillar.

[0016] In some embodiments, removing at least a portion of the third filling layer includes: forming a third mask layer, the third mask layer covering the top surface of the second filling layer, the top surface of the third filling layer and the remaining top surface of the first filling layer, and the third mask layer having a plurality of third openings passing through the third mask layer, the third openings being located directly above the corresponding first active pillars and directly above a portion of the third filling layer; using the third mask layer as a mask, etching the third filling layer exposed by the third opening and the first filling layer directly opposite the third opening to expose the surface of the first active pillar directly below the third opening.

[0017] According to some embodiments of the present disclosure, on the other hand, embodiments of the present disclosure further provide a semiconductor structure, comprising: a substrate; a plurality of active pillars, which are arranged on the substrate at intervals along a second direction and a third direction, and the active pillars extend along a first direction, wherein the active pillars include a first active pillar and a second active pillar that are connected, the first active pillar is located in a first part, and the second active pillar is located in a second part adjacent to the first part, and the first direction, the second direction and the third direction intersect in pairs; a first filling layer, the first filling layer fills the gaps between adjacent first active pillars; and a second filling layer, the second filling layer fills the gaps between adjacent second active pillars.

[0018] In some embodiments, the method further includes: a supporting structure, the supporting structure being located on the substrate and covering opposite side surfaces of each active pillar along the first direction.

[0019] In some embodiments, the support structure is further located between ends of adjacent active pillars arranged along the third direction.

[0020] In some embodiments, the material of the first filling layer is different from the material of the second filling layer.

[0021] The technical solution provided by the embodiments of the present disclosure has at least the following advantages:

[0022] The present disclosure provides a method for manufacturing a semiconductor structure, which divides a stacked structure into a first portion and a second portion adjacent to each other, first forming a first active column in the first portion, in which a sacrificial layer and a portion of an active layer in the first portion need to be removed, and the second portion can play a supporting role for the formed first active column to prevent the first active column from collapsing. In addition, a portion of the sacrificial layer may remain on the sidewall of the first portion adjacent to the second portion; forming a first filling layer, which fills the gap between adjacent first active columns; forming a second active column in the second portion, in which the first filling layer and the second filling layer can play a supporting role for the second active column, and after removing the sacrificial layer and the second portion, the sacrificial layer and the second filling layer can be removed. During the process of forming a portion of the active layer, the sacrificial layer and the active layer remaining in the first portion can be removed. In this way, the edges of the filled first filling layer and the second filling layer are relatively regular, which is beneficial to reducing the possibility of irregular structures such as gates and capacitors formed based on the first filling layer and the second filling layer in the future. If the edge areas of the first filling layer and the second filling layer are irregular, the size of the first filling layer or the second filling layer in some areas is small. The small size will lead to poor dielectric properties of the first filling layer or the second filling layer, and leakage may occur. However, in the method for manufacturing a semiconductor structure provided by the embodiment of the present disclosure, the edges of the first filling layer and the second filling layer are relatively regular, which can reduce the possibility of leakage.

[0023] In addition, in the related art, in the step of manufacturing the active pillar, the entire stacked structure is directly processed to manufacture the active pillar at one time, and thus an additional step is required to first form multiple supporting structures for supporting the formed active pillar. Compared with the related art, the manufacturing method of the semiconductor structure provided by the embodiment of the present disclosure manufactures the first active pillar and the second active pillar in partitions. In the step of manufacturing one of the active pillars, the filling layer filled in the area where the other active pillar is located can play a supporting role. There is no need for an additional step to make the supporting structure, which can reduce the complexity of the related process and streamline the process steps. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] One or more embodiments are exemplarily illustrated by the pictures in the corresponding drawings. These exemplified descriptions do not constitute a limitation on the embodiments. Unless otherwise stated, the pictures in the drawings do not constitute a scale limitation. In order to more clearly illustrate the embodiments of the present disclosure or the technical solutions in the traditional technology, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0025] Figures 1 to 38 A schematic structural diagram corresponding to each step of a method for manufacturing a semiconductor structure provided by an embodiment of the present disclosure;

[0026] Figure 39 A top view of a semiconductor structure provided in accordance with another embodiment of the present disclosure;

[0027] Figure 40 For the Figure 39 Cross-sectional view of section AA1;

[0028] Figure 41 For the Figure 39 Cross-sectional view of section BB1;

[0029] Figure 42 A top view of another semiconductor structure provided in accordance with another embodiment of the present disclosure;

[0030] Figure 43 For the Figure 42 Cross-sectional view of section AA1;

[0031] Figure 44 For the Figure 42 Cross-sectional view of section BB1;

[0032] Figure 45 For the Figure 42 Cross-sectional view of section CC1 in Figure 2. DETAILED DESCRIPTION

[0033] As can be seen from the background art, the current technology for manufacturing gate structures and active pillars needs to be improved.

[0034] The present disclosure provides a method for manufacturing a semiconductor structure, which divides a stacked structure into an adjacent first part and a second part. First, a first active pillar is formed in the first part. In this step, a sacrificial layer and a portion of the active layer in the first part need to be removed. A portion of the sacrificial layer may remain on the sidewall of the first part adjacent to the second part, and in this step, the second part can support the formed first active pillar to prevent the first active pillar from collapsing. A first filling layer is formed, and the first filling layer fills the gaps between adjacent first active pillars. Then, a second active pillar is formed in the second part. In this step, the first filling layer and the second filling layer can support the second active pillar, and in the process of removing the sacrificial layer and the portion of the active layer in the second area, the remaining sacrificial layer and the active layer in the first part can be removed. In this way, the edges of the filled first filling layer and the second filling layer are more regular, which is conducive to reducing the possibility of irregular structures such as gates and capacitors formed subsequently based on the first filling layer and the second filling layer. The more regular edges of the first filling layer and the second filling layer can reduce the thickness difference of the filling layer in different areas, thereby reducing the possibility of leakage.

[0035] In addition, the manufacturing method of the semiconductor structure provided by the embodiment of the present disclosure manufactures the first active column and the second active column in partitioned manner. In the step of manufacturing one of the active columns, the filling layer filled in the area where the other active column is located can play a supporting role. No additional steps are required to make a supporting structure for supporting the active column, which can reduce the complexity of the related process and streamline the process steps.

[0036] The following describes various embodiments of the present disclosure in detail with reference to the accompanying drawings. However, those skilled in the art will appreciate that many technical details are provided in the various embodiments of the present disclosure to facilitate a better understanding of the present disclosure. However, even without these technical details and the various variations and modifications based on the following embodiments, the technical solutions claimed in the present disclosure can still be implemented.

[0037] Figures 1 to 38 A schematic structural diagram corresponding to each step of a method for manufacturing a semiconductor structure provided by an embodiment of the present disclosure.

[0038] refer to Figures 1 to 3 ,in, Figure 2 For the Figure 1 The cross-sectional view of section AA1 in the figure, Figure 3 For the Figure 1 A substrate 100 is provided, on which a stacked structure is formed. The stacked structure includes sacrificial layers 101 and active layers 102 that are alternately arranged, and the stacked structure includes a first portion 10 and a second portion 20 that are adjacent to each other.

[0039] The substrate 100 may be made of an elemental semiconductor material or a crystalline inorganic compound semiconductor material. The elemental semiconductor material may be silicon or germanium; the crystalline inorganic compound semiconductor material may be silicon carbide, silicon germanium, gallium arsenide, or indium gallium.

[0040] The material of the sacrificial layer 101 may be silicon germanium, silicon nitride, or silicon oxide; the material of the active layer 102 may be semiconductor materials such as silicon and germanium.

[0041] The semiconductor structure to be formed may include an adjacent first region 1 and a second region 2, wherein a substrate 100 spans the first region 1 and the second region 2, a first portion 10 is located in the first region 1, and a second portion 20 is located in the second region 2, and subsequent steps process the stacked structure to form a first active column located in the first region 1 and a second active column located in the second region 2.

[0042] In some embodiments, the semiconductor structure to be formed may further include a third region 3, the third region 3 surrounding the first region 1 and the second region 2, with a portion of the substrate 100 located in the third region 3. The stacked structure may further include a third portion 30 surrounding the first portion 10 and the second portion 20, with the third portion located in the third region 3. In other embodiments, the third region 3 may be located only on two opposite sides of the first region 1 and the second region 2, and the stacked structure may further include the third portion 30 located on two opposite sides of the first portion 10 and the second portion 20.

[0043] refer to Figures 10 to 15 ,in, Figure 11 For the Figure 10 The cross-sectional view of section AA1 in the figure, Figure 12 For the Figure 10 The cross-sectional view of the BB1 ​​section, Figure 14 For the Figure 13 The cross-sectional view of section AA1 in the figure, Figure 15 For the Figure 13 Cross-sectional view taken along section BB1. The active layer 102 in the first portion 10 is patterned, and the sacrificial layer 101 in the first portion 10 is removed. The remaining active layer 102 in the first portion 10 forms a plurality of first active pillars 103 arranged at intervals along the second direction Y and the third direction Z. The first active pillars 103 extend along the first direction X, and the first direction X, the second direction Y, and the third direction Z intersect with each other.

[0044] In some embodiments, the steps of patterning the active layer 102 in the first portion 10 and removing the sacrificial layer 101 in the first portion 10 may include: Figures 10 to 12, forming a first mask layer 104, the first mask layer 104 covers the entire top surface of the second portion 20 of the stacked structure, and also covers a portion of the top surface of the first portion 10 of the stacked structure, wherein the first mask layer 104 located directly above the first portion 10 has a plurality of first openings 105 arranged at intervals; continue to refer to Figures 10 to 12 , using the first mask layer 104 as a mask, etching the stacked structure along the first opening 105 to remove the sacrificial layer 101 and the active layer 102 facing the first opening 105, and the remaining active layer 102 in the first portion 10 constitutes the first active pillar 103; Figures 13 to 15 , a lateral etching process is used to remove the remaining sacrificial layer 101 in the first portion 10.

[0045] The material of the first mask layer 104 may be silicon nitride, silicon oxide or silicon oxynitride.

[0046] refer to Figure 14 In some embodiments, in the step of removing the sacrificial layer 101 in the first portion 10, the sidewall of the sacrificial layer 101 in the second portion 20 facing the first portion 10 may also be etched, and a first gap 107 is formed between the remaining sacrificial layer 101 and the active layer of the second portion 20. That is, when the sacrificial layer 101 in the first portion 10 is removed by a lateral etching process, a portion of the sacrificial layer 101 on the sidewall of the second portion 20 adjacent to the first portion 10 may also be laterally removed.

[0047] In some embodiments, in the steps of patterning the active layer 102 in the first part 10 and removing the sacrificial layer 101 in the first part 10, the substrate 100 having a thickness corresponding to the first part can also be removed to ensure that the bottom sacrificial layer 101 in the first part 10 is completely removed.

[0048] refer to Figures 4 to 12 ,in, Figure 5 For the Figure 4 The cross-sectional view of section AA1 in the figure, Figure 6 For the Figure 4 The cross-sectional view of the BB1 ​​section, Figure 8 For the Figure 7 The cross-sectional view of section AA1 in the figure, Figure 9 For the Figure 7A cross-sectional view of the cross section taken along section BB1 in FIG. In some embodiments, before patterning the active layer in the first portion 10, the following steps may be performed: removing the third portion 30 to expose the substrate 100 directly opposite the third portion 30, and removing a portion of the thickness of the substrate 100 directly opposite the third portion 30; and forming a support structure 108. The support structure 108 is located in the region where the third portion 30 is removed and covers the side surfaces of the stacked structure. By forming the support structure 108, the support structure 108 can support the first and second active pillars formed in subsequent steps, preventing the first and second active pillars from collapsing, thereby improving the yield rate of the semiconductor structure manufacturing process.

[0049] It can be understood that in the related art, in the step of forming the active pillar, multiple support structures need to be formed, and the multiple support structures are located between the ends of the formed active pillars. Compared with the related art, in the manufacturing method of the semiconductor structure provided by the embodiment of the present disclosure, the support structure 108 is located on the side of the stacked structure, and the manufacturing difficulty is relatively small.

[0050] The material of the support structure 108 may be silicon oxide, silicon nitride or silicon oxynitride.

[0051] refer to Figures 4 to 6 The step of removing the third portion may include: forming a second mask layer 113, the second mask layer 113 is located on the top surface of the first portion 10 and the second portion 20, and exposes the top surface of the third portion 30; using the second mask layer 113 as a mask, etching the third portion 30.

[0052] During the process of forming the support structure 108 , the support structure 108 also covers the side surfaces of the second mask layer 113 .

[0053] After forming the support structure 108, the second mask layer 113 is retained. In subsequent steps, the second mask layer 113 can be patterned to form a first mask layer. In this way, there is no need to remove the second mask layer 113. The second mask layer 113 can continue to be used to manufacture the subsequent first active pillar and the second active pillar, which can reduce process costs.

[0054] In some embodiments, in the step of removing the third portion 30, a portion of the thickness of the substrate 100 opposite to the third portion 30 can also be removed to avoid insufficient etching resulting in incomplete removal of the sacrificial layer 101 at the bottom layer of the third portion 30, and the subsequently formed support structure 108 can be embedded in the substrate 100, having a larger contact area with the substrate 100, so that the support structure 108 is more stable.

[0055] refer to Figures 7 to 9In some embodiments, after removing the third portion 30 and before forming the support structure 108, the step may further include laterally removing part of the sacrificial layer 101 at the edge of the remaining stacked structure so that the remaining sacrificial layer 101 and the active layer 102 form a second gap 109; in the step of forming the support structure 108, the support structure 108 also fills the second gap 109, thereby increasing the contact area between the support structure 108 and the active layer 102, so that the support structure 108 has a larger contact area with the first active pillar and the second active pillar formed in subsequent steps, which is beneficial to improving the support capacity of the support structure 108 for the first active pillar and the second active pillar.

[0056] refer to Figure 12 In some embodiments, in the step of etching the stacked structure along the first opening 105 using the first mask layer 104 as a mask to form the first active pillar 103, the support structure 108 directly opposite the first opening 105 can also be removed to avoid the phenomenon that the support structure 108 directly opposite the first opening 105 collapses due to the removal of the active layer 102 and the sacrificial layer 101 directly opposite the first opening 105.

[0057] It is understandable that in the step of removing the sacrificial layer 101 in the first portion 10, there may be etching residues, that is, there may be sacrificial layer 101 residues at the first notch 107. The residual sacrificial layer 101 will cause the edge shape of the first filling layer that subsequently fills the gap between adjacent first active pillars 103 to be irregular (refer to Figure 13 ), and in the process of forming the first active pillar 103, part of the active layer 102 may remain on the side wall of the first part 10 close to the second part 20. The remaining active layer 102 will also cause the edge of the subsequently formed first filling layer to be irregular, and the subsequent steps will need to remove the remaining active layer 102 and the sacrificial layer 101.

[0058] refer to Figures 16 to 18 ,in, Figure 17 For the Figure 16 The cross-sectional view of section AA1 in the figure, Figure 18 For the Figure 16 A first filling layer 106 is formed to fill the gaps between adjacent first active pillars 103 . The first filling layer 106 is used to support the first active pillars 103 during the subsequent manufacturing of the second active pillars to prevent the first active pillars 103 from collapsing.

[0059] The material of the first filling layer 106 can be silicon oxide, silicon nitride, or silicon oxynitride. In some embodiments, the material of the first filling layer 106 can be different from the material of the first mask layer 104. For example, the material of the first filling layer 106 can be silicon oxide, and the material of the first mask layer 104 can be silicon nitride. The first mask layer 104 can be used to make the gate located in the first filling layer 106. By setting the material of the first filling layer 106 to be different from the material of the first mask layer 104, during the process of etching the first filling layer 106 to form the trench to be formed with the gate, the opening of the first filling layer 106 in the first mask layer 104 can be made more regular, so that the gate structure formed is more regular, which is conducive to ensuring the electrical performance of the formed semiconductor structure. It is understandable that the material of the first filling layer 106 can also be set to be the same as the material of the first mask layer 104, and the mask layer can be replaced to make the gate later.

[0060] The first filling layer 106 can also fill the first opening 105 , so that in the subsequent step of etching the second portion 20 using the first mask layer 104 as a mask, the first filling layer 106 in the first opening 105 can protect the first active pillar 103 from being corroded.

[0061] In some embodiments, the first filling layer 106 may also fill the first gap 107 formed in the aforementioned step.

[0062] It can be understood that in the aforementioned step of manufacturing the first active pillar 103, there may be remnants of the sacrificial layer 101 in the first notch 107, and there may be remnants of the active layer 102 on the side wall of the first part 10 close to the second part 20, which will cause the edge of the formed first filling layer 106 toward the second part 20 to be wavy and irregular. The irregular edge may cause the shape of the gate, capacitor and other structures subsequently formed based on the first filling layer to be irregular, and the size of the first filling layer 106 in some areas may be smaller. The dielectric properties of the first filling layer 106 in this area are poor, which may cause leakage in the formed semiconductor structure. Therefore, the subsequent steps need to trim the irregular side walls of the first filling layer 106.

[0063] refer to Figures 19 to 24 ,in, Figure 20 For the Figure 19 The cross-sectional view of section AA1 in the figure, Figure 21 For the Figure 19 The cross-sectional view of the BB1 ​​section, Figure 23 For the Figure 22 The cross-sectional view of section AA1 in the figure, Figure 24 For the Figure 22The active layer 102 in the second portion 20 is patterned, and the sacrificial layer 101 in the second portion 20 is removed. The remaining active layer 102 in the second portion 20 forms a plurality of second active pillars 110 arranged at intervals along the second direction Y and the third direction Z. The second active pillars 110 are in contact with and connected to the first active pillars 103 to form active pillars.

[0064] It can be understood that, in the process of patterning the active layer 102 in the second part 20 and removing the sacrificial layer 101 in the second part 20, the remaining sacrificial layer 101 in the first part 10 and the remaining active layer 102 in the first notch 107 can be removed simultaneously to achieve the trimming of the side wall shape of the first filling layer 106, and the side wall shape of the second filling layer that subsequently fills the gap between adjacent second active pillars 110 is also regular, and subsequently it is necessary to form gate, capacitor and other structures based on the first filling layer 106 and the second filling layer. In this way, the shapes of the gate, capacitor and other structures formed subsequently are more regular, which is beneficial to improving the electrical performance of the formed semiconductor structure.

[0065] In some embodiments, during the step of removing the sacrificial layer 101 in the second portion 20, the first filling layer 106 in the first gap 107 (eg, Figure 19 As shown, the irregular edge area of ​​the first filling layer 106 toward the second part 20 is further trimmed to achieve the further trimming of the sidewall shape of the first filling layer 106, further reducing the possibility of irregular shapes of structures such as gates and capacitors formed subsequently, which is beneficial to improving the yield and reliability of the formed semiconductor structure.

[0066] In some embodiments, the steps of patterning the active layer 102 in the second portion 20 and removing the sacrificial layer 101 in the second portion 20 may include: referring to Figures 19 to 21 , patterning the first mask layer 104 directly above the second portion 20 to form a plurality of second openings 111 arranged at intervals, wherein the second openings 111 are connected to the first openings 105 along the first direction X; continue to refer to Figures 19 to 21 , using the first mask layer 104 as a mask, etching the stacked structure along the second opening 111, removing the sacrificial layer 101 and the active layer 102 opposite the second opening 111, so as to form second active pillars 110 in the second portion 20, each second active pillar 110 being adjacent to a first active pillar 103 along the first direction X; Figures 22 to 24 , a lateral etching process is used to remove the remaining sacrificial layer 101 in the second portion 20 .

[0067] refer to Figures 25 to 27 ,in, Figure 26 For the Figure 25 The cross-sectional view of section AA1 in the figure, Figure 27 For the Figure 25A second filling layer 112 is formed to fill the gaps between adjacent second active pillars 110 .

[0068] The material of the second filling layer 112 can be silicon oxide, silicon nitride, or silicon oxynitride. Since different structures need to be formed in the first filling layer 106 and the second filling layer 112 in subsequent steps, in some embodiments, the material of the second filling layer 112 can be different from that of the first filling layer 106. In the same process step, the first filling layer 106 and the second filling layer 112 are etched at different rates, thereby ensuring that when one of the first filling layer 106 and the second filling layer 112 is etched, the other is less corroded.

[0069] In some embodiments, the second filling layer 112 may also completely fill the second opening 111 .

[0070] It is also understandable that after removing the sacrificial layer 101 in the second portion 20 in the aforementioned step, part of the first filling layer 106 may remain in the first notch 107, and part of the sacrificial layer 101 may remain in the area of ​​the second portion 20 adjacent to the first notch 107. Figure 19 The edge of the second portion 20 facing the first filling layer 106 is V-shaped, and a portion of the sacrificial layer 101 may remain at the sharp corner of the V-shaped edge.

[0071] In some embodiments, before forming the second filling layer 112, it can also include: removing the remaining first filling layer 106 and sacrificial layer 101 in the second part, so that the formed second filling layer 112 can have a more regular side wall, and further trimming of the side wall of the first filling layer 106 is achieved, so that the gate, capacitor and other structures formed subsequently based on the first filling layer 106 and the second filling layer 112 have a more regular shape, and ensure that the thickness of the first filling layer 106 and the second filling layer 112 is relatively uniform, which can reduce the possibility of leakage of the formed semiconductor structure due to uneven thickness of the filling layer, thereby helping to improve the electrical performance of the formed semiconductor structure.

[0072] The same etching process is used to remove the first filling layer 106 and the remaining sacrificial layer 101 in the second part 20, wherein the etching process has an etching selectivity ratio of 1 to 2 for the first filling layer 108 and the sacrificial layer 101. For example, the etching selectivity ratio can be 1, 1.3, 1.7 or 2. Within this etching selectivity range, the first filling layer 108 and the sacrificial layer 101 are etched at similar rates, and the remaining sacrificial layer 101 and the first filling layer 108 can be uniformly etched to ensure that the sidewalls of the remaining first filling layer 108 are relatively regular, so that the shapes of structures such as the gate formed subsequently based on the first filling layer 108 are relatively regular, which is beneficial to improving the performance of the semiconductor structure.

[0073] refer to Figures 28 to 38 ,in, Figure 29 For the Figure 28 The cross-sectional view of section AA1 in the figure, Figure 30 For the Figure 28 The cross-sectional view of the BB1 ​​section, Figure 32 For the Figure 31 The cross-sectional view of section AA1 in the figure, Figure 33 For the Figure 31 The cross-sectional view of the BB1 ​​section, Figure 34 For the Figure 31 The cross-sectional view of the CC1 section, Figure 36 For the Figure 35 The cross-sectional view of section AA1 in the figure, Figure 37 For the Figure 35 The cross-sectional view of the BB1 ​​section, Figure 38 For the Figure 35 After forming the second filling layer 112, the following steps may be performed: forming a plurality of first through holes 114, each of which penetrates the first filling layer 106 between adjacent first active pillars 103 spaced apart along the second direction Y; forming a third filling layer 115, each of which completely fills the first through holes 114; removing at least a portion of the third filling layer 115 to expose at least a portion of the surface of the first active pillar 103; and forming a gate 116, each of which covers at least a portion of the exposed surface of the first active pillar 103.

[0074] In some embodiments, the material of the first filling layer 106 can be set to be different from the material of the first mask layer 104; in the step of forming a plurality of first through holes 114, the first mask layer 104 can be used as a mask to form a plurality of first through holes 114; since the material of the first filling layer 106 is different from the material of the first mask layer 104, in the step of etching the first filling layer 106 in the first mask layer 104, the first filling layer 106 is mainly etched, and the first mask layer 104 is not etched, so that the opening of the first through hole 114 in the first mask layer 104 is relatively regular, and subsequent etching downward along the opening can ensure that the first through hole 114 is formed more regularly, so that the shape of the subsequently formed gate 116 is more regular, which can reduce the possibility of irregular shape of the gate 116, and is conducive to improving the electrical performance of the formed semiconductor structure.

[0075] refer to Figures 31 to 34The step of removing at least a portion of the third filling layer 115 may include: forming a third mask layer 117, the third mask layer 117 covering the top surface of the second filling layer 112, the top surface of the third filling layer 112 and the top surface of the remaining first filling layer 106, and the third mask layer 117 having a plurality of third openings 118 penetrating the third mask layer 117, the third openings 118 being located directly above the corresponding first active pillars 103 and directly above a portion of the third filling layer 115; using the third mask layer 117 as a mask, etching the third filling layer 115 exposed by the third openings 118 and the first filling layer 106 directly opposite the third openings 118 to expose the surface of the first active pillar 103 directly below the third openings 118.

[0076] Among them, the step of etching the third filling layer 115 exposed by the third opening 118 using the third mask layer 117 as a mask may include: using the third mask layer 117 as a mask, longitudinally etching the third filling layer 115 on the opposite side walls of the first active pillars 103 along the second direction Y along the third opening 118 to expose the first filling layer 106 between adjacent first active pillars 103 arranged along the third direction Z; using a lateral etching process to remove the first filling layer 106 between adjacent first active pillars 103 arranged along the third direction Z, and retaining the third filling layer 115 outside the position directly opposite the third opening 118, this part of the third filling layer 115 is used to isolate the first active pillars 103 arranged at intervals along the second direction Y and the adjacent gates formed subsequently.

[0077] In some embodiments, the material of the third filling layer 115 can be different from that of the first filling layer 106. In this way, in the same etching process step, the third filling layer 115 and the first filling layer 106 are etched at different rates. When the third filling layer 115 and the first filling layer 106 are sequentially etched along the third opening 118, the groove morphology formed after the etching is relatively regular. For example, the material of the third filling layer 115 can be silicon nitride, and the material of the first filling layer 106 can be silicon oxide. In the same etching process step, the etching selectivity between the first filling layer 106 and the third filling layer 115 is relatively large. In the process of etching the first filling layer 106 along the third opening 118, the third filling layer 115 is less eroded, which can reduce the erosion of the third filling layer 115 outside the position directly opposite the third opening 118, thereby preventing leakage of the formed semiconductor structure.

[0078] refer to Figures 35 to 38After etching the third filling layer 115 along the third opening 118 using the third mask layer 117 as a mask to expose the surface of the first active pillar 103, a gate 116 is formed. The gate is arranged around the sidewall of the corresponding first active pillar 103. This is conducive to improving the gate control capability of the gate 116. The gate 116 extends along the third direction and contacts a row of first active pillars 103 arranged at intervals along the third direction Z.

[0079] In some embodiments, a capacitor (not shown) may be formed in the second filling layer 112 in subsequent steps. The capacitor is disposed around the second active pillar 110 . The second filling layer 112 and the first filling layer 106 are used to isolate the capacitor from the gate 116 .

[0080] In some embodiments, the material of the first filling layer 106 and the material of the second filling layer 112 can be different, so that in the same etching process step, the first filling layer 106 and the second filling layer 112 are etched at different rates, so as to reduce the erosion of the first filling layer 106 in the process of etching the second filling layer 112 to form a capacitor, reduce the possibility of leakage of the formed semiconductor structure, and be able to form a groove with a more regular morphology, so that the morphology of the capacitor formed in this groove is more regular, which is beneficial to improving the electrical performance of the formed semiconductor structure.

[0081] The manufacturing method of the semiconductor structure provided by the above-mentioned disclosed embodiment divides the stacked structure into regions for processing. First, the sacrificial layer 101 and part of the active layer 102 in the first part 10 are removed to form a first active pillar 103 in the first part 10. In this step, the second part 20 can support the first active pillar 103; a first filling layer is formed, and the first filling layer 106 fills the gap between adjacent first active pillars 102; then the sacrificial layer 101 and part of the active layer 102 in the second part 20 are removed to form a second active pillar 110 in the second part 20. In this step, the first filling layer 106 and the first active pillar 103 support the second active pillar 110; in this way, the embodiment of the present disclosure does not require an additional step to form a support structure for supporting the active pillar, which can reduce the process complexity.

[0082] In addition, in the step of forming the first active pillar 103, there may be residues of the sacrificial layer 101 and the active layer 102 in the area adjacent to the first region 1 and the second region 2. The residual sacrificial layer 101 and the active layer 102 will cause the side walls of the first filling layer 103 to be irregular. In the step of forming the second active pillar 110, the residual sacrificial layer 101 and the active layer 102 can be removed simultaneously to trim the side walls of the first filling layer 103, and the subsequently formed second filling layer 112 can have more regular side walls. In this way, the thickness difference between the first filling layer and the second filling layer in different regions is reduced. The first filling layer 103 and the second filling layer 112 are used to isolate the devices subsequently formed in the first region 1 and the second region 2, which can reduce the leakage phenomenon of the formed semiconductor structure due to the difference in the thickness of the filling layers, and the gate 116 subsequently formed in the first filling layer 106 and the capacitor formed in the second filling layer 112 have more regular morphologies, which is beneficial to improving the electrical performance of the formed semiconductor structure.

[0083] Accordingly, another embodiment of the present disclosure further provides a semiconductor structure. The semiconductor structure provided in another embodiment of the present disclosure can be manufactured using the manufacturing method of the semiconductor structure provided in the aforementioned embodiment. The semiconductor structure provided in another embodiment of the present disclosure will be described in detail below with reference to the accompanying drawings. For parts that are identical or corresponding to the aforementioned embodiment, reference can be made to the corresponding description of the aforementioned embodiment and will not be repeated in detail below. Figure 39 A top view of a semiconductor structure provided in another embodiment of the present disclosure is shown. Figure 40 For the Figure 39 The cross-sectional view of section AA1 in the figure, Figure 41 For the Figure 39 The cross-sectional view of the BB1 ​​section, Figure 42 A top view of another semiconductor structure provided in another embodiment of the present disclosure is provided. Figure 43 For the Figure 42 The cross-sectional view of section AA1 in the figure, Figure 44 For the Figure 42 The cross-sectional view of the BB1 ​​section, Figure 45 For the Figure 42 Cross-sectional view of section CC1 in Figure 2.

[0084] refer to Figures 39 to 41The semiconductor structure includes a substrate 100. The semiconductor structure includes a plurality of active pillars arranged on the substrate 100 along a second direction Y and a third direction Z, and the active pillars extend along a first direction X. The active pillars include a first active pillar 103 and a second active pillar 110 connected to each other. The first active pillar 103 is located in a first portion 10, and the second active pillar 110 is located in a second portion 20 adjacent to the first portion 10. The first direction X, the second direction Y, and the third direction Z intersect with each other. The semiconductor structure includes a first filling layer 106, which fills the gaps between adjacent first active pillars 103. The semiconductor structure includes a second filling layer 112, which fills the gaps between adjacent second active pillars 110.

[0085] The semiconductor structure further includes a first region 1 and a second region 2 adjacent to each other, wherein the substrate 100 spans the first region 1 and the second region 2 , the first active pillar 103 and the first filling layer 103 are located in the first region 1 , and the second active pillar 110 and the second filling layer 112 are located in the second region 2 .

[0086] It is understandable that in the semiconductor structure provided by the embodiment of the present disclosure, the first active pillar 103 and the second active pillar 110 are formed in different steps. For example, the first active pillar 103 can be formed first. In the step of forming the first active pillar 103, the film layer in the second region 2 where the second active pillar 110 is to be formed can play a supporting role for the first active pillar 103. Then, the first filling layer 106 is formed, and then the second active pillar 110 is formed. In the step of forming the second active pillar 110, the first active pillar 103 and the first filling layer 106 can play a supporting role for the second active pillar 110. In this way, there is no need to form a supporting structure before forming the first active pillar 103 and the second active pillar 110, which can reduce the process complexity of forming the semiconductor structure and improve the process efficiency. In some embodiments, the second active pillar 110 and the second filling layer 112 can also be formed first, and then the first active pillar 103 and the first filling layer 106 are formed.

[0087] In some embodiments, the semiconductor structure may further include a third region 3 , which is disposed around the first region 1 and the second region 2 , and the substrate 100 is also located in the third region 3 .

[0088] In some embodiments, the semiconductor structure may further include a support structure 108 located in the third region 3. The support structure 108 is located on the substrate 100 and covers the opposite sides of each active column along the first direction X. The support structure 108 can support the first active column 103 and the second active column 110 during the manufacturing process of the first active column 103 and the second active column 110, thereby preventing the first active column 103 and the second active column 110 from collapsing, thereby improving the yield of forming the semiconductor structure.

[0089] In some embodiments, the support structure 108 may also be located between the ends of adjacent active pillars arranged along the third direction Z. In this way, the contact area between the support structure 108 and the active pillars is larger, which can improve the supporting effect of the support structure 108 on the active pillars.

[0090] The material of the first filling layer 106 may be silicon nitride, silicon oxide, or silicon oxynitride; the material of the second filling layer 112 may be silicon nitride, silicon oxide, or silicon oxynitride.

[0091] A capacitor (not shown) may also be provided in the second filling layer 112. The capacitor is provided around the second active pillar 110. The second filling layer 112 and the first filling layer 106 are used to isolate the capacitor from the conductive structure in the first filling layer 106. For example, the second filling layer 112 and the first filling layer 106 are used to isolate the capacitor from the gate. In some embodiments, the material of the first filling layer 106 and the material of the second filling layer 112 may be different to reduce erosion of the first filling layer 106 during the process of etching the second filling layer 112 to form the capacitor, thereby ensuring the dielectric properties of the first filling layer 106. The trench formed in this step may have a more regular morphology, so that the morphology of the capacitor formed in the trench is more regular, which is beneficial to improving the electrical performance of the formed semiconductor structure.

[0092] refer to Figures 42 to 45 The semiconductor structure may further include a gate 116 and a third filling layer 115 located in the first region 1. The gate 116 extends along the third direction Z and is arranged around the sidewalls of the corresponding first active pillars 103. This is beneficial to improving the gate control capability of the gate 116, and the gate is in contact with a column of first active pillars 103 arranged at intervals along the third direction Z. The third filling layer 115 is located between adjacent gates 116 and is used to isolate adjacent gates 116 and adjacent active pillars.

[0093] Those skilled in the art will appreciate that the above-described embodiments are specific examples for implementing the present disclosure, and that in actual applications, various changes in form and detail may be made thereto without departing from the spirit and scope of the present disclosure. Any person skilled in the art may make various changes and modifications without departing from the spirit and scope of the present disclosure. Therefore, the scope of protection of the present disclosure shall be subject to the scope defined in the claims.

Claims

1. A method for manufacturing a semiconductor structure, characterized in that: include: Providing a substrate, on which a stacked structure is formed, the stacked structure including sacrificial layers and active layers alternately arranged, and the stacked structure including a first portion and a second portion adjacent to each other; The active layer in the first portion is patterned, and the sacrificial layer in the first portion is removed, so that the remaining active layer in the first portion forms a plurality of first active pillars arranged at intervals along a second direction and a third direction, wherein the first active pillars extend along the first direction, and the first direction, the second direction, and the third direction intersect with each other; forming a first filling layer, wherein the first filling layer completely fills the gaps between adjacent first active pillars; Patterning the active layer in the second portion and removing the sacrificial layer in the second portion, so that the remaining active layer in the second portion constitutes a plurality of second active pillars spaced apart along the second direction and the third direction, and the second active pillars are in contact with and connected to the first active pillars to form active pillars; forming a second filling layer, wherein the second filling layer completely fills the gaps between adjacent second active pillars; After forming the second filling layer, the method further includes: forming a plurality of first through holes, wherein the first through holes penetrate the first filling layer between adjacent first active pillars spaced apart along the second direction; forming a third filling layer, wherein the third filling layer completely fills the first through hole; removing at least a portion of the third filling layer to expose at least a portion of the surface of the first active pillar; A gate is formed, where the gate covers at least a portion of the exposed surface of the first active pillar.

2. The method for manufacturing a semiconductor structure according to claim 1, wherein: The steps of patterning the active layer in the first portion and removing the sacrificial layer in the first portion include: forming a first mask layer, wherein the first mask layer covers the entire top surface of the second portion of the stacked structure and also covers a portion of the top surface of the first portion of the stacked structure, wherein the first mask layer directly above the first portion has a plurality of first openings arranged at intervals; Using the first mask layer as a mask, etching the stacked structure along the first opening, so that the remaining active layer in the first portion constitutes the first active pillar; The sacrificial layer in the first portion is removed by a lateral etching process.

3. The method for manufacturing a semiconductor structure according to claim 2, wherein: The steps of patterning the active layer in the second portion and removing the sacrificial layer in the second portion include: Patterning the first mask layer directly above the second portion to form a plurality of second openings arranged at intervals, wherein the second openings are connected to the first opening along the first direction; Using the first mask layer as a mask, etching the stacked structure along the second opening to form the second active pillars in the second portion, each of the second active pillars being adjacent to a first active pillar along the first direction; The sacrificial layer in the second portion is removed by a lateral etching process.

4. The method for manufacturing a semiconductor structure according to claim 1, wherein: In the step of removing the sacrificial layer in the first portion, the sacrificial layer on the sidewall of the second portion facing the first portion is also etched, so that a first gap is formed between the remaining sacrificial layer and the active layer of the second portion; In the step of forming the first filling layer, the first filling layer also fills the first gap; In the step of removing the sacrificial layer in the second portion, the first filling layer in the first gap is also removed.

5. The method for manufacturing a semiconductor structure according to claim 4, wherein: After removing the sacrificial layer in the second portion, a portion of the first filling layer remains in the first notch, and a portion of the sacrificial layer remains in an area of ​​the second portion adjacent to the first notch; Before forming the second filling layer, the method further includes: The first filling layer and the sacrificial layer remaining in the second portion are removed.

6. The method for manufacturing a semiconductor structure according to claim 5, wherein: The first filling layer and the remaining sacrificial layer in the second portion are removed by using the same etching process, wherein the etching selectivity ratio of the etching process to the first filling layer and the sacrificial layer is 1-2.

7. The method for manufacturing a semiconductor structure according to claim 1, wherein: The stacked structure includes a third portion surrounding the first portion and the second portion; Before patterning the active layer in the first portion, the method further includes: removing the third portion to expose the substrate facing the third portion, and removing a portion of the substrate facing the third portion; A support structure is formed, the support structure being located in the region where the third portion is removed and covering a side surface of the stacked structure.

8. The method for manufacturing a semiconductor structure according to claim 7, wherein: After removing the third portion and before forming the support structure, the method further includes: Laterally removing a portion of the sacrificial layer remaining at an edge of the stacked structure, so that the remaining sacrificial layer and the active layer form a second gap; In the step of forming the support structure, the support structure also fills the second gap.

9. The method for manufacturing a semiconductor structure according to claim 7, wherein: The step of removing the third portion comprises: forming a second mask layer, wherein the second mask layer is located on top surfaces of the first portion and the second portion and exposes a top surface of the third portion; using the second mask layer as a mask to etch the third portion; In the process step of forming the support structure, the support structure also covers the side surfaces of the second mask layer; After forming the support structure, retaining the second mask layer; The second mask layer is patterned to form a first mask layer.

10. The method for manufacturing a semiconductor structure according to claim 1, wherein: The removing at least a portion of the third filling layer comprises: forming a third mask layer, where the third mask layer covers a top surface of the second filling layer, a top surface of the third filling layer, and a remaining top surface of the first filling layer, and the third mask layer has a plurality of third openings penetrating the third mask layer, and the third openings are located directly above corresponding first active pillars and directly above a portion of the third filling layer; The third mask layer is used as a mask to etch the third filling layer exposed by the third opening and the first filling layer opposite to the third opening to expose the surface of the first active pillar directly below the third opening.

11. A semiconductor structure prepared according to any one of the methods of claims 1 to 10, characterized in that: include: substrate; a plurality of active pillars arranged on the substrate along a second direction and a third direction at intervals, and extending along the first direction, wherein the active pillars include a first active pillar and a second active pillar connected to each other, the first active pillar being located in a first portion, the second active pillar being located in a second portion adjacent to the first portion, and the first direction, the second direction, and the third direction intersecting in pairs; a first filling layer, wherein the first filling layer fills the gaps between adjacent first active pillars; A second filling layer is provided, wherein the second filling layer fills the gaps between adjacent second active pillars.

12. The semiconductor structure according to claim 11, wherein: Also includes: A supporting structure is located on the substrate and covers opposite side surfaces of each active pillar along the first direction.

13. The semiconductor structure according to claim 12, wherein: The support structure is also located between ends of adjacent active pillars arranged along the third direction.

14. The semiconductor structure according to claim 11, wherein: The material of the first filling layer is different from the material of the second filling layer.

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