Method, apparatus and device for supporting virtualized gpio controller implementation

Abstract

The application discloses a kind of support virtualization's GPIO controller implementation method, device and equipment, it is related to communication control technical field, the method includes the hardware isolation of the GPIO corresponding to saf_gpio_unit, and based on the number of GPIO corresponding to next group register of GPIO controller, register is mapped in the virtualization of same number of 4k field;Based on the number of GPIO and the number of GIC, the address space of GPIO is cut into the 4k field of set number;First number of 4k field is respectively assigned to the internal reg of each GPIO, and second number of 4k field is respectively assigned to each GIC.This application can solve the problem of access conflict of multiple operating systems to the same GPIO controller, and ensure that interrupt grouping is flexible and can be configured.

Description

Technical Field

[0001] The present application relates to the field of communication control technology, and in particular to a method, apparatus, and device for implementing a GPIO controller that supports virtualization. Background Art

[0002] Currently, the entire GPIO (General-purpose input / output) controller occupies only a 4KB domain. For example, a 32-bit GPIO controller contains a set of 32-bit registers that control 32 GPIOs, with each bit corresponding to a GPIO. Software configuration of these registers allows each GPIO to be configured to various desired modes, such as input or output, interrupt debounce, debounce time, level-triggered or edge-triggered interrupts, and interrupt clearing. For interrupts, a GPIO controller typically combines the 32 interrupts from each of the 32 GPIOs into a single interrupt line.

[0003] The above solution works fine for a single operating system. However, for multiple operating systems, since they cannot control each other, it's easy for them to accidentally overwrite the same GPIO controller. For example, if operating system 1 only wants to configure GPIO1 on the GPIO controller, it might accidentally overwrite the configuration of 31 other GPIOs. Existing SoCs (System on Chips) typically have a multi-core heterogeneous architecture and support multiple operating systems. While the following three methods can resolve conflicts, none of them are ideal:

[0004] Method 1: Read first, then write. However, if two operating systems configure the same controller at the same time, conflicts will still occur, causing unexpected consequences. This is difficult to avoid, especially for automotive chips with high functional safety requirements. This error may cause unacceptable safety issues.

[0005] Method 2: Use a firewall to allocate a GPIO controller to only one operating system to solve the problem of accidental overwriting. However, this will greatly limit the flexibility of the entire SoC system and also cause a large amount of GPIO waste.

[0006] Method 3: A GPIO controller contains only one GPIO. However, if there are a large number of GPIOs, then more instantiations will occupy a large amount of chip area. In addition, one GPIO corresponds to one interrupt line. Each GIC (Generic Interrupt Controller) must be connected to all GPIO interrupt lines. For example, if there are 200 GPIOs, each GIC must be connected to 200 GPIO interrupt lines, which poses a relatively large challenge to layout and routing. In addition, the number of SPI interfaces in GIC is limited, so this method is also a huge waste of SPI interfaces. Summary of the Invention

[0007] The present application provides a method, apparatus, and device for implementing a GPIO controller that supports virtualization, which can solve the problem of access conflicts between multiple operating systems to the same GPIO controller and ensure flexible and configurable interrupt grouping.

[0008] In a first aspect, an embodiment of the present application provides a method for implementing a GPIO controller that supports virtualization, the method comprising:

[0009] The GPIO corresponding to saf_gpio_unit is hardware isolated, and based on the number of GPIOs corresponding to a group of registers under the GPIO controller, the registers are virtually mapped in the same number of 4k domains;

[0010] Based on the number of GPIOs and the number of GICs, the GPIO address space is divided into a set number of 4k domains;

[0011] Allocate the first number of 4k domains to the internal regs of each GPIO respectively, and allocate the second number of 4k domains to each GIC respectively;

[0012] The set quantity is the sum of the first quantity and the second quantity.

[0013] In conjunction with the first aspect, in one embodiment, the GPIO corresponding to the saf_gpio_unit is hardware isolated, and based on the number of GPIOs corresponding to a group of registers under the GPIO controller, the registers are virtualized and mapped in the same number of 4k domains, specifically including:

[0014] Get the 32 GPIOs corresponding to saf_gpio_unit and perform hardware isolation on the 32 GPIOs obtained;

[0015] A set of 32-bit registers under the GPIO controller is virtually mapped in 32 4k domains.

[0016] In conjunction with the first aspect, in one embodiment, dividing the GPIO address space into a set number of 4k domains based on the number of GPIOs and the number of GICs specifically includes:

[0017] Get the number of GPIOs and GICs, and divide the GPIO address space into 37 4k domains, where the number of GPIOs obtained is 32 and the number of GICs is 5.

[0018] In conjunction with the first aspect, in one embodiment, allocating the first number of 4k domains to the internal regs of each GPIO and allocating the second number of 4k domains to each GIC specifically includes:

[0019] Of the 37 4k domains, 32 4k domains are allocated to the internal regs of the 32 GPIOs, and 5 4k domains are allocated to the 5 GICs, where each GPIO corresponds to a 4k domain and each GIC corresponds to a 4k domain.

[0020] In combination with the first aspect, in one implementation, the 37 4k domains are divided, occupying 18 bits of the address, and the 18 bits include the upper 6 bits, the lower 8 bits and the other 4 bits.

[0021] In combination with the first aspect, in one implementation, the upper 6 bits are used to distinguish 4k domains, the lower 8 bits are used for internal reg addressing of 32 GPIOs, and the other 4 bits are all set to 0, indicating no meaning.

[0022] In combination with the first aspect, in one embodiment, the GPIO controller implementation method further includes:

[0023] A GIC ID is allocated to each GPIO, and the GIC ID is used to identify the GIC to which the GPIO belongs. When the GPIO completes the GIC ID allocation, the GPIO interrupts are grouped.

[0024] In combination with the first aspect, in one implementation, the interrupt status of the GPIO in each group can only be read from the corresponding 4k field of the GIC corresponding to the current group.

[0025] In a second aspect, an embodiment of the present application provides a GPIO controller implementation device supporting virtualization, the GPIO controller implementation device supporting virtualization comprising:

[0026] The mapping module is used to isolate the GPIO corresponding to the saf_gpio_unit by hardware and virtualize the registers in the same number of 4k domains based on the number of GPIOs corresponding to the next set of registers under the GPIOcontroller;

[0027] A splitting module, which is used to split the GPIO address space into a set number of 4k domains based on the number of GPIOs and the number of GICs;

[0028] An allocation module, configured to allocate a first number of 4k domains to internal regs of each GPIO, and allocate a second number of 4k domains to each GIC;

[0029] The set quantity is the sum of the first quantity and the second quantity.

[0030] In a third aspect, an embodiment of the present application provides a GPIO controller implementation device that supports virtualization, wherein the GPIO controller implementation device that supports virtualization includes a processor, a memory, and a GPIO controller implementation program that supports virtualization stored on the memory and can be executed by the processor, wherein when the GPIO controller implementation program that supports virtualization is executed by the processor, the steps of the above-mentioned GPIO controller implementation method that supports virtualization are implemented.

[0031] The beneficial effects of the technical solutions provided in the embodiments of the present application include:

[0032] Without increasing the chip area, increasing the pressure on back-end layout and routing, and occupying too much of the GIC's SPI (Serial Peripheral Interface), the problem of conflicting access to the same GPIO controller by multiple operating systems is resolved, and flexible interrupt grouping is ensured. At the same time, considering the pressure on back-end routing and the limited number of SPIs on the GIC, through design improvements, flexible access by multiple virtual machines is achieved, with high security, convenient software operation, and reduced chip manufacturing costs. This greatly reduces the pressure on back-end layout and routing, greatly reduces the number of SPIs on the GIC, and allows flexible interrupt configuration. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] Figure 1 This is a flowchart of a method for implementing a virtualized GPIO controller supported by this application;

[0034] Figure 2 This is the functional block diagram corresponding to the implementation method of the GPIO controller supporting virtualization in this application;

[0035] Figure 3 This is a functional module diagram of a device that supports virtualized GPIO controller implementation in this application;

[0036] Figure 4 This is a hardware diagram of the GPIO controller that supports virtualization in this application. DETAILED DESCRIPTION

[0037] In order to enable those skilled in the art to better understand the present invention, the following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0038] In order to make the objectives, technical solutions and advantages of this application clearer, the implementation methods of this application will be further described in detail below with reference to the accompanying drawings.

[0039] On the first aspect, the embodiments of the present application provide a method for implementing a GPIO controller that supports virtualization. This method solves the problem of access conflicts between multiple operating systems to the same GPIO controller without increasing the chip area, increasing the pressure on back-end layout and wiring, and occupying too much of the GIC's SPI (Serial Peripheral Interface), and ensures that interrupt grouping is flexible and configurable.

[0040] In one embodiment, referring to Figure 1 , Figure 1 This is a flow chart of the method for implementing a virtualized GPIO controller supported by this application. Figure 1 As shown, the implementation method of the GPIO controller supporting virtualization includes:

[0041] S1: Perform hardware isolation on the GPIO corresponding to saf_gpio_unit and, based on the number of GPIOs corresponding to a group of registers under the GPIO controller, virtually map the registers in the same number of 4k domains.

[0042] It should be noted that saf_gpio_unit, namely GPIO secure access unit, is a main functional module used to implement register configuration and interrupt processing.

[0043] Furthermore, in one embodiment, the GPIO corresponding to saf_gpio_unit is hardware isolated, and based on the number of GPIOs corresponding to a group of registers under the GPIOcontroller, the registers are virtualized and mapped in the same number of 4k domains, specifically including:

[0044] S101: Obtain 32 GPIOs corresponding to saf_gpio_unit, and perform hardware isolation on the obtained 32 GPIOs;

[0045] S102: A set of 32bit registers under the GPIO controller is mapped in 32 4k domains.

[0046] Specifically, 32 GPIOs of the saf_gpio_unit are hardware isolated, and a set of 32bit registers under the GPIO controller is mapped in 32 4k domains.

[0047] S2: Based on the number of GPIOs and the number of GICs, the address space of the GPIOs is divided into a set number of 4k domains.

[0048] Further, in an embodiment, based on the number of GPIOs and the number of GICs, the address space of the GPIOs is divided into a set number of 4k domains, specifically including: taking WIDTH = 32 and GIC_NUM = 5 as an example, the number of GPIOs and the number of GICs are obtained, and the address space of the GPIOs is divided into 37 4k domains, wherein the number of GPIOs obtained is 32, and the number of GICs is 5.

[0049] Referring to Figure 2 The figure shows the function block diagram corresponding to the GPIO controller implementation method supported by the application, Figure 2 is taken as an example of WIDTH = 32 and GIC_NUM = 5, wherein WIDTH represents the number of GPIOs, GIC_NUM represents the number of GICs, and both WIDTH and GIC_NUM are parameters, which can be configured according to specific use scenarios when the module is instantiated. The address space of the GPIOs is divided into 37 4k domains. Figure 2 In the figure, intr[i] represents an interrupt line. The NVIC represents an embedded vector interrupt controller, which is a type of GIC.

[0050] S3: A first number of 4k domains are respectively allocated to the internal regs of the GPIOs, and a second number of 4k domains are respectively allocated to the GICs; the set number is the sum of the first number and the second number.

[0051] Further, in an embodiment, a first number of 4k domains are respectively allocated to the internal regs of the GPIOs, and a second number of 4k domains are respectively allocated to the GICs, specifically including: for the 37 4k domains divided, 32 4k domains are respectively allocated to the internal regs (i.e. register, an abbreviation for register) of the 32 GPIOs, and 5 4k domains are allocated to the 5 GICs, wherein each GPIO corresponds to a 4k domain, and each GIC corresponds to a 4k domain. Figure 2In the figure, GPIO0~GPIO31 represent 32 GPIO domains, GIC0, GIC1, GIC2, NVIC0, NVIC1 represent 5 GICs, intr0(GIC0), intr1(GIC1), intr2(GIC2), intr3(NVIC0), intr4(NVIC1) represent 5 GIC domains. Address Re-Mapping represents address mapping, Address Decoder represents address decoder.

[0052] Specifically, for the split GPIO address space, 37 4k domains are obtained, and the first 32 4k domains are respectively allocated to the internal regs of the 32 GPIOs, and the other 5 4k domains are allocated to the 5 GICs.

[0053] It should be noted that for the 37 4k domains, 18 bits of address are occupied, and the 18 bits include high 6 bits, low 8 bits and other 4 bits, the high 6 bits are used to distinguish the 4k domains, the low 8 bits are used for internal reg addressing of the 32 GPIOs, and the other 4 bits are all set to 0, indicating no meaning. Specifically, for the 37 4k domains, 18 bits of address are occupied, and only the low 18 bits are valid, wherein the high 6 bits in the 18 bits are used to distinguish different 4k domains, and the low 8 bits are used for internal reg addressing of the 32 GPIOs, which will cause that 4 bits are not used, so the bits not used are all set to “0”.

[0054] Further, the GPIO controller implementation method of the application further comprises: allocating a GIC ID (encoding) to each GPIO, the GIC ID is used to identify the GIC to which the GPIO belongs, and when the GIC ID allocation of the GPIO is completed, the grouping of the GPIO interrupt is realized.

[0055] Specifically, a GIC ID is allocated to each GPIO, and a total of 32 GIC IDs are allocated, and the 32 GIC IDs are respectively used to identify the GIC to which the GPIO belongs, and when the GIC ID is configured, the corresponding bit of the intr_status register of the corresponding GIC ID will be opened, and when the GIC ID of the 32 GPIOs is configured, the grouping of the GPIO interrupts is realized. For the interrupt status of the GPIOs in each group, only the corresponding 4k domain of the GIC corresponding to the current group can be read.

[0056] The access permission of each 4k domain of the GPIO controller to which operating system is configured by the firewall. That is, which operating system each GPIO belongs to is configured by the firewall. For example, GPIO0 and GPIO3 can be configured to OS1, and GPIO1 and GPIO2 can be configured to OS2.

[0057] The scheme of the present application occupies a total of 37 (WIDTH+GIC_NUM) 4k address spaces, which is 36 more than the existing scheme. However, by using the virtualization method, the access conflict of multiple operating systems is avoided, the flexibility of scheme three in the background technology is possessed, only the hardware overhead of scheme one and scheme two is had, the software operation is simpler and more convenient than scheme one and scheme two, and it is as convenient as scheme three.

[0058] For the virtualization-supported GPIO controller implementation method of the present application, the following describes the software operation process in the actual application process, assuming that the firewall has been configured, the steps are as follows:

[0059] Step one: configure the GIC ID of the GPIO (configure the GIC ID of the GPIO to be used, and the GPIO not used can not be configured);

[0060] Step two: configure the DDR of the GPIO, that is, the in / out direction;

[0061] Step three: configure INTMASK;

[0062] Step four: configure INTTYPE;

[0063] Step five: configure INTPOL;

[0064] Step six: configure DEBTIME;

[0065] Step seven: configure DEBEN (interrupt debouncing enabled, GPIO_in will be used after two taps synchronization, DEBEN will not be enabled, and will not cause metastable state, GPIO_in two taps synchronization intr);

[0066] Step eight: configure INTEN;

[0067] Step nine: assume that GPIO0 and GPIO2 belong to GIC1 (assume that they are both input), if GPIO0_in or GPIO2_in is triggered, the corresponding SPI of GIC1 will be triggered, and the 4k domain of the corresponding GIC will be read to obtain the interrupt state of the GIC domain;

[0068] Step 10: APB write writes 1 to the INTSTATUS of the corresponding GPIO to clear the corresponding interrupt.

[0069] The method for implementing a virtualized GPIO controller in an embodiment of the present application addresses the shortcomings of existing designs and solves the access conflict issue to the same GPIO controller under multiple operating systems. While taking into account factors such as the pressure of back-end layout and routing and the limited number of SPIs in the GIC, the improved design achieves the following beneficial effects:

[0070] 1. Flexible access to multiple virtual machines avoids access conflicts between multiple operating systems on the same GPIO controller. In conjunction with Firewall, any GPIO under a GPIO controller can be configured for use by any operating system. Different operating systems accessing the same GPIO controller will not cause access conflicts. That is, if operating system 1 configures the GPIO under operating system 1, it will not overwrite the GPIO of operating system 2. This avoids access conflicts between operating systems while being extremely flexible and eliminating GPIO waste.

[0071] 2. High security, avoiding functional safety issues caused by accidental rewriting access conflicts in multiple operating systems. This is especially important for automotive chips with high functional safety requirements;

[0072] 3. The software is easy to operate. The software operation is convenient and flexible. You no longer need to consider the GPIO configuration under other operating systems. You only need to focus on the GPIO configuration of the current operating system, which makes the software development code simple and concise, saves the running time when the GPIO configuration instructions are issued, and improves the response speed;

[0073] 4. Reduce chip manufacturing costs. The number of GPIOs a GPIO controller contains can be configured during instantiation, supporting up to 32. This facilitates instantiation and significantly reduces chip area. Compared with the solution where "a GPIO controller contains only one GPIO," the area is reduced by nearly 31 times.

[0074] 5. Greatly reduces the pressure on back-end layout and routing. The instantiation is simple and the number of instantiations is small, which greatly reduces the pressure on back-end layout and the number of interrupt lines. For a GPIO controller with 32 GPIOs, only one interrupt line is connected to one GIC, which greatly reduces the pressure on back-end routing.

[0075] 6. Greatly save the number of SPI on GIC and greatly reduce the number of interrupt lines. The number of SPI occupied is 1 / 32 of the solution "one GPIO controller contains only one GPIO";

[0076] 7. Interrupt configuration is flexible and supports interrupt grouping by GIC. How to group can be configured by software, which is extremely flexible and all GPIO functions are retained.

[0077] In a second aspect, an embodiment of the present application further provides a GPIO controller implementation device that supports virtualization.

[0078] In one embodiment, referring to Figure 3 , Figure 3 This is a functional module diagram of the GPIO controller implementation device that supports virtualization in this application. Figure 3 As shown, the GPIO controller implementation device supporting virtualization includes: a mapping module, a segmentation module, and an allocation module.

[0079] The mapping module is used to isolate the GPIO corresponding to the saf_gpio_unit by hardware and virtualize the registers in the same number of 4k domains based on the number of GPIOs corresponding to the next set of registers under the GPIOcontroller;

[0080] The segmentation module is used to divide the GPIO address space into a set number of 4k domains based on the number of GPIOs and the number of GICs; the allocation module is used to allocate a first number of 4k domains to the internal reg of each GPIO, and a second number of 4k domains to each GIC; wherein the set number is the sum of the first number and the second number.

[0081] Among them, the functional implementation of each module in the above-mentioned GPIO controller implementation device supporting virtualization corresponds to the various steps in the above-mentioned embodiment of the GPIO controller implementation method supporting virtualization, and their functions and implementation processes are no longer repeated here.

[0082] In a third aspect, an embodiment of the present application provides a GPIO controller implementation device that supports virtualization. The GPIO controller implementation device that supports virtualization may be a personal computer (PC), a laptop, a server, or other device with data processing capabilities.

[0083] Reference Figure 4 , Figure 4 Schematic diagram of the hardware structure of the GPIO controller implementation device supporting virtualization involved in the embodiment of the present application. In the embodiment of the present application, the GPIO controller implementation device supporting virtualization may include a processor, a memory, a communication interface and a communication bus.

[0084] The communication bus may be of any type and is used to interconnect the processor, memory, and communication interface.

[0085] Communication interfaces include input / output (I / O) interfaces, physical interfaces, and logical interfaces. These interfaces are used by virtualized GPIO controllers to interconnect internal devices and other devices (such as other computing devices or user devices). Physical interfaces can include Ethernet, fiber, and ATM interfaces; user devices can include displays and keyboards.

[0086] The memory can be various types of storage media, such as random access memory (RAM), read-only memory (ROM), non-volatile RAM (NVRAM), flash memory, optical storage, hard disk, programmable ROM (PROM), erasable PROM (EPROM), electrically erasable PROM (EEPROM), etc.

[0087] The processor may be a general-purpose processor that can invoke a virtualization-supporting GPIO controller implementation program stored in a memory and execute the virtualization-supporting GPIO controller implementation method provided in the embodiments of the present application. For example, the general-purpose processor may be a central processing unit (CPU). The method executed when the virtualization-supporting GPIO controller implementation program is invoked can be referenced in the various embodiments of the virtualization-supporting GPIO controller implementation method of the present application and will not be further described here.

[0088] Those skilled in the art will understand that Figure 4 The hardware structure shown in the figure does not constitute a limitation to the present application and may include more or fewer components than shown in the figure, or a combination of certain components, or a different arrangement of components.

[0089] It should be noted that the serial numbers of the above-mentioned embodiments of the present application are for description only and do not represent the advantages or disadvantages of the embodiments.

[0090] The terms “include,” “comprise,” “have,” and any variations thereof, in the Specification and in the Claims of the present application, and the above-mentioned drawings, are intended to cover a non-exclusive inclusion. For example, a process, method, system, product, or device that includes a list of steps or units is not limited to the listed steps or units, but can optionally further include steps or units not listed, or can optionally further include other steps or units inherent to such processes, methods, products, or devices. The terms “first,” “second,” and “third” and the like descriptions are used to distinguish different objects, and do not represent a sequence or limit the types of “first,” “second,” and “third.”

[0091] In the description of the embodiments of the present application, “exemplary”, “for example”, or “for instance” is used to represent an example, an illustration, or a description. Any embodiment or design scheme described as “exemplary”, “for example”, or “for instance” in the embodiments of the present application should not be interpreted as more preferred or more advantageous than other embodiments or design schemes. Rather, the words “exemplary”, “for example”, or “for instance” are intended to present the relevant concept in a specific manner.

[0092] In the description of the embodiments of the present application, unless otherwise specified, “ / ” represents the meaning of or, for example, A / B can represent A or B; “and / or” in the text only represents a description of the relationship between the associated objects, which means that there can be three relationships, for example, A and / or B can represent the three cases of A alone, A and B together, and B alone. In addition, in the description of the embodiments of the present application, “multiple” means two or more than two.

[0093] In some of the processes described in the embodiments of the present application, a plurality of operations or steps are included in a specific order, but it should be understood that these operations or steps can be executed or performed in parallel or in an order different from that in which they appear in the embodiments of the present application. The serial number of the operation is only used to distinguish different operations, and the serial number itself does not represent any execution order. In addition, these processes can include more or fewer operations, and these operations or steps can be executed in sequence or in parallel, and these operations or steps can be combined.

[0094] From the above description of the embodiments, those skilled in the art can clearly understand that the above-mentioned embodiment method can be realized by means of software and a general hardware platform as required, of course, it can also be realized by hardware, but in many cases the former is a better embodiment. Based on such understanding, the technical solutions of the present application can be embodied in the form of a software product, which is stored in a storage medium (such as a ROM / RAM, a magnetic disk, an optical disk) as described above, and includes a plurality of instructions for causing a terminal device to execute the methods described in the embodiments of the present application.

[0095] The preferred embodiments of the present application have been described above with the illustrated embodiments, and are not intended to limit the scope of patent protection for the present application. Any equivalent structure or equivalent process variations, which directly or indirectly incorporate the contents of the specification and drawings of the present application, are also intended to be included within the scope of patent protection for the present application.

Claims

1. A method for implementing a GPIO controller supporting virtualization, characterized in that: The method for implementing the GPIO controller supporting virtualization includes: The GPIO corresponding to saf_gpio_unit is hardware isolated, and based on the number of GPIOs corresponding to a group of registers under the GPIO controller, the registers are virtually mapped in the same number of 4k domains; Based on the number of GPIOs and the number of GICs, the GPIO address space is divided into a set number of 4k domains; Allocate the first number of 4k domains to the internal regs of each GPIO respectively, and allocate the second number of 4k domains to each GIC respectively; Wherein, the set quantity is the sum of the first quantity and the second quantity; The hardware isolation of the GPIO corresponding to the saf_gpio_unit and the virtualization mapping of the registers in the same number of 4k domains based on the number of GPIOs corresponding to a group of registers under the GPIO controller specifically include: Get the 32 GPIOs corresponding to saf_gpio_unit and perform hardware isolation on the 32 GPIOs obtained; Virtualize a set of 32-bit registers under the GPIO controller into 32 4k domains; The method of dividing the GPIO address space into a set number of 4k domains based on the number of GPIOs and the number of GICs specifically includes: Get the number of GPIOs and GICs, and divide the GPIO address space into 37 4k domains, where the number of GPIOs obtained is 32 and the number of GICs is 5; The GPIO controller implementation method further includes: Each GPIO is assigned a GIC ID, which is used to identify the GIC to which the GPIO belongs. Once the GPIO completes the GICID assignment, the GPIO interrupts are grouped. The interrupt status of the GPIO in each group can only be read from the corresponding 4k domain of the GIC corresponding to the current group.

2. A method for implementing a GPIO controller supporting virtualization according to claim 1, characterized in that: The first number of 4k domains are allocated to the internal reg of each GPIO, and the second number of 4k domains are allocated to each GIC, specifically including: Of the 37 4k domains, 32 4k domains are allocated to the internal regs of the 32 GPIOs, and 5 4k domains are allocated to the 5 GICs, where each GPIO corresponds to a 4k domain and each GIC corresponds to a 4k domain.

3. The method for implementing a GPIO controller supporting virtualization according to claim 1, wherein: The 37 4k domains occupy 18 bits of address, and the 18 bits include the high 6 bits, the low 8 bits and the other 4 bits.

4. A method for implementing a GPIO controller supporting virtualization according to claim 3, characterized in that: The upper 6 bits are used to distinguish 4k domains, the lower 8 bits are used for internal reg addressing of 32 GPIOs, and the other 4 bits are all set to 0, indicating no meaning.

5. A GPIO controller implementation device supporting virtualization, characterized in that: The GPIO controller implementation device supporting virtualization includes: The mapping module is used to isolate the GPIO corresponding to the saf_gpio_unit by hardware and virtualize the registers in the same number of 4k domains based on the number of GPIOs corresponding to the next set of registers under the GPIOcontroller; A splitting module, which is used to split the GPIO address space into a set number of 4k domains based on the number of GPIOs and the number of GICs; An allocation module, configured to allocate a first number of 4k domains to internal regs of each GPIO, and allocate a second number of 4k domains to each GIC; Wherein, the set quantity is the sum of the first quantity and the second quantity; The hardware isolation of the GPIO corresponding to the saf_gpio_unit and the virtualization mapping of the registers in the same number of 4k domains based on the number of GPIOs corresponding to a group of registers under the GPIO controller specifically include: Get the 32 GPIOs corresponding to saf_gpio_unit and perform hardware isolation on the 32 GPIOs obtained; Virtualize a set of 32-bit registers under the GPIO controller into 32 4k domains; The method of dividing the GPIO address space into a set number of 4k domains based on the number of GPIOs and the number of GICs specifically includes: Get the number of GPIOs and GICs, and divide the GPIO address space into 37 4k domains, where the number of GPIOs obtained is 32 and the number of GICs is 5; The GPIO controller implementation method further includes: Each GPIO is assigned a GIC ID, which is used to identify the GIC to which the GPIO belongs. Once the GPIO completes the GICID assignment, the GPIO interrupts are grouped. The interrupt status of the GPIO in each group can only be read from the corresponding 4k domain of the GIC corresponding to the current group.

6. A GPIO controller implementation device supporting virtualization, characterized in that: The virtualization-supporting GPIO controller implementation device includes a processor, a memory, and a virtualization-supporting GPIO controller implementation program stored on the memory and executable by the processor, wherein when the virtualization-supporting GPIO controller implementation program is executed by the processor, the steps of the virtualization-supporting GPIO controller implementation method according to any one of claims 1 to 4 are implemented.

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