A system, method and device for transmitting write response information based on PCIe protocol

Abstract

The present invention relates to the field of chip technology, and in particular, to a system, method and device for transmitting write response information based on the PCIe protocol. The system includes an AXI bus transmitter, which sends a memory read and write request through an address channel ar, and then sends data through a write data channel w; an interface controller module is used to realize conversion between different protocols and arbitration and processing of read and write requests and responses; a PCIe controller is used to adapt and convert the read and write request and response signals of the AXI protocol into a data packet format of the PCIe protocol; and the AXI bus receiver is used to receive write requests and write data converted through the PCIe protocol. Through the coordination of the arbitrator, the correct write response is returned to the local bus of the initiator, so that the write response of the data bus is transmitted between PCIe devices. Users do not need to consider the restrictions on data transmission at the PCIe protocol level during use, making data transmission more universal and efficient.

Description

Technical Field

[0001] The present invention relates to the field of chip technology, and in particular to a system, method and device for transmitting write response information based on a PCIe protocol. Background Art

[0002] At present, with the vigorous development of GPU (graphics processing unit) chip technology and applications, especially the rapid growth of applications in deep learning, scientific computing and large-scale graphics rendering, the demand for multi-GPU collaborative work has increased sharply, and the demand for multi-chip interconnection has also increased day by day.

[0003] Currently, there are interconnection solutions for CPU and GPU chips in the field of chip technology, especially the PCIe protocol, which is the most mature and reliable. The PCIe protocol has excellent performance in data transmission rate, low latency, stability, flexibility and scalability, and is easier to adapt to different application scenarios and changes in demand.

[0004] However, when the PCIe protocol is used to interconnect multiple GPU chips, it has some limitations in the transmission of data paths. The main problem is the lack of adaptability at the protocol level. For example, the commonly used chip on-chip network bus interfaces AXI and APB in the industry, these interface protocols all need to implement the transmission of write response information. Since the PCIe protocol itself is not designed for chip interconnection, it naturally cannot support the transmission of write response information. Directly using the PCIe protocol controller as an interconnection device for the on-chip network bus will have defects at the data transmission level. Therefore, a system, method and device for transmitting write response information based on the PCIe protocol are provided. Summary of the invention

[0005] The purpose of the present invention is to provide a system, method and device for transmitting write response information based on the PCIe protocol, so as to solve the problem that the PCIe protocol controller proposed in the above background technology as an interconnection device of the on-chip network bus will have defects in the data transmission level.

[0006] To achieve the above object, the present invention provides a system for transmitting write response information based on the PCIe protocol, comprising:

[0007] AXI bus transmitter, which sends a memory read / write request through the address channel ar, carrying the target address and related control information, and then sends data through the write data channel w. After the write operation is completed, the write response channel b receives the write response signal returned by the target device to confirm whether the write is successful;

[0008] An interface controller module, which is used to implement conversion between different protocols and arbitration and processing of read and write requests and responses;

[0009] The transmitting end interface control module includes a baw to b module, a write request arbitrator, a write response to write request module a and a write request to write response module a;

[0010] Among them, the baw to b module is used to extract the write request baw carrying the write response information from the PCIe write request data packet (mwr tlp), and convert the baw back to the write response (b response) and return it to the write response channel b of the initiator bus. The write request arbitrator combines and sends the normal write request aw and the write request baw with the write response information of this section; when the PCIe controller gives a local response (local ack) for a certain write request operation, the write response to write request module a embeds this local ack information into a new write request packet, generates a write request baw data packet carrying the response information, and sends it to the peer system through the PCIe interface, so that the peer can obtain the status feedback of this write operation. Finally, the write request to write response module a is responsible for screening and processing all received PCIe write request data packets, identifying the write request baw data packets carrying the write response information, and extracting the corresponding write response content from them, and restoring them to the write response (b response) under the AXI protocol after format conversion. This converted write response is then submitted to the write response arbitrator, which schedules it uniformly and finally sends it to the local bus of the initiator, thus completing the entire closed-loop response information transmission process;

[0011] The receiving end interface control module includes a b to baw module, a write response arbitrator, a write response to write request module b and a write request to write response module b;

[0012] Among them, when the receiving end interface control module receives the standard write response (bresponse) transmitted through the PCIe link, the b to baw module converts the write response (b response) returned by the receiving end bus into a write request (aw request) and maps it to the PCIe write request data packet (mwr tlp) and sends it to the initiator. Subsequently, the baw data generated after the conversion by the b to baw module enters the write response arbiter, which is responsible for managing and scheduling all write responses (b response) and the converted baw data packet, ensuring that in the case of multi-source concurrency, the appropriate write response can be accurately and timely fed back to the local bus according to the preset priority or rules. The arbitrator also needs to be effectively synchronized with other modules to correctly determine when the write response should be converted into baw form for transmission; the write response conversion request module b converts the confirmation signal of the local device for the received write request into a new write request, and attaches relevant response information, generates a baw data packet, and feeds back the completion status of the local device to the initiator to maintain the bidirectionality and integrity of the PCIe link communication. The write request conversion response module b is used to decouple the baw data packet from the peer system, extract the original write response information from it, and convert it back to the write response format (b response) that complies with AXI or other local bus protocols; then, the reconstructed write response will be sent to the local bus to notify the corresponding component about the result of the previous write operation;

[0013] Among them, the write request carrying the write response information is called baw;

[0014] Wherein, the interface controller module includes a transmitting end interface control module and a receiving end interface control module;

[0015] A PCIe controller, the PCIe controller is used to adapt and convert the read and write request and response signals of the AXI protocol into a data packet format of the PCIe protocol, so as to perform efficient data transmission between PCIe-based systems;

[0016] Wherein, the PCIe controller includes a sending channel and a receiving channel;

[0017] AXI bus receiving end, the AXI bus receiving end is used to receive the write request and write data converted through the PCIe protocol, and perform the corresponding data write operation. When the write operation is completed, the AXI bus receiving end generates a write response signal and transmits it back to the AXI bus master device that initiated the request through the interface controller module.

[0018] As a further improvement of the technical solution, the sending channel is used to initiate a read return, a read request and a write request;

[0019] Among them, read return is used for the PCIe controller to read data from the target device, package the data into a read return data packet (cpld tlp), and send it back to the initiator through the sending channel;

[0020] When the bus initiates a read request, the PCIe controller converts the request into a read request packet (mrd tlp) of the PCIe protocol;

[0021] When the bus initiates a write request, the PCIe controller converts the request into a write request packet (mwr tlp) of the PCIe protocol.

[0022] As a further improvement of the technical solution, the receiving channel is used to initiate a write request, a read request and a read return;

[0023] When the PCIe controller receives a write request packet (mwr tlp), the write request decapsulates the packet and converts it into a write request of the bus protocol, extracts the address and data information in the packet, and sends it to the target device on the bus;

[0024] When the PCIe controller receives a read request packet (mrd tlp), the read request decapsulates the packet and converts it into a read request of the bus protocol; the PCIe controller extracts the address information in the packet and sends it to the target device on the bus;

[0025] When the PCIe controller receives a read return packet (cpld tlp), the read return decapsulates the packet and converts it into a read return of the bus protocol; the PCIe controller extracts the data information in the packet and sends it to the device that initiated the read request.

[0026] On the other hand, the present invention provides a method for transmitting write response information based on the PCIe protocol, which is used in any one of the above-mentioned systems for transmitting write response information based on the PCIe protocol, comprising the following steps:

[0027] S1. The specific processing flow of the read request is as follows:

[0028] S1.1. The initiating side bus interface sends a read request to the peer chip; the read address is 0x1000, the length is 1, and the read request number (arid) is 1; wherein the initiating side bus interface is the AXI bus transmitter or the AXI bus receiver;

[0029] S1.2, the interface controller module maps the corresponding AXI read request information to the corresponding bit field of the PCIe read request data packet (mrdtlp) and sends it to the other party; the AXI read request address can be directly mapped to the address bit field of the PCIe read request data packet (mrdtlp), and the AXI read request length will be mapped to the length bit field of the mrd tlp packet. The read request number (arid) does not need to be passed to the other party;

[0030] S1.3, the opposite end interface controller module performs the opposite processing, that is, converts the PCIe read request data packet (mrd tlp) back to the AXI read request and sends it to the opposite end bus interface; the read address is 0x1000, the length is 1, and the read request number (arid) is a (the arid used by the opposite end may be different from that of the initiating side); wherein the opposite end interface controller module is the transmitting end interface control module or the receiving end interface control module;

[0031] S1.4, the peer interface controller module waits for the read response of the peer bus interface, maps it to the corresponding bit field of the PCIe read response data packet (cpld) and returns it; the read response data is 0xffff, and the read response number (rid) is a (corresponding to arid in step S1.3);

[0032] S1.5, the initiating side interface control module waits for the cpld packet returned by the other end, and converts it into an AXI write response and returns it to the initiating test bus interface; the read response data is 0xffff, and the read response number (rid) is 1 (corresponding to the arid in step S1.1); the initiating side interface control module is the transmitting end interface control module or the receiving end interface control module;

[0033] S2. The specific processing flow of the write request is as follows:

[0034] S2.1. The initiating bus interface initiates a write request to the peer chip; the write address is 0x1000, the write data is 0xffff, the write length is 1, and the write request number (awid) is 2;

[0035] S2.2, the transmitting interface control module maps the corresponding AXI write request information to the corresponding bit field of the PCIe write request data packet (mwr tlp) and sends it to the other party; the write address, write data and write length have one-to-one corresponding bit fields to store, and the write request number (awid) needs to be passed to the other party by means of a data packet prefix (tlp prefix);

[0036] S2.3, the receiving interface control module performs the opposite processing, that is, converts the PCIe write request data packet (mwr tlp) back to the AXI write request and sends it to the opposite bus interface; the write address sent to the bus interface is 0x1000, the length is 1, the write data is 0xffff, and the write request number (awid) is b;

[0037] S2.4, the receiving end interface control module needs to parse out the awid information of the initiator stored in the data packet prefix (tlp prefix) and store its mapping relationship with the local awid;

[0038] S2.5, the receiving interface control module waits for and receives the write response returned by the bus interface (the response number bid of the write response is b, the response status bresp is success, and the response custom content buser is 0xabcd), and converts the write response to the write request (b2baw), that is, converts the write response of the AXI bus into a PCIe write request (mwr tlp) carrying special write response information, and sends it back to the other end together with other ordinary PCIe write requests. This type of write request carrying special information is called baw;

[0039] S2.6. At the same time, the receiving interface control module will reversely infer the response number according to the previously recorded mapping relationship of awid (b to 2), and store the response number, response status, and response custom content in the baw packet prefix (tlp prefix). The remaining information of baw can be encapsulated into a zero-length write request with a fixed address, that is, the write address is 0x0, the write data is 0x0, and the length is 0 (bit field FBE=0, LBE=0);

[0040] S2.7, the transmitting end interface control module receives the PCIe write request (mwr tlp) from the receiving end interface control module, and determines whether the mwr tlp is a general write request or baw according to the packet prefix;

[0041] S2.8, if it is a general write request, convert the write request (mwr tlp) into a write request of the AXI interface and pass it to the AXI bus receiving end;

[0042] S2.9. If it is a baw, a write request is converted into a write response (baw2b). The sending end interface control module converts the relevant information in the tlp prefix in the baw packet into AXI write response information and returns it to the initiating side bus interface, and determines the response status; the write response content is the response number (bid) is 2, the response status (bresp) is success, and the response custom content (buser) is 0xabcd.

[0043] As a further improvement of the technical solution, the initiating side bus interface is an AXI bus transmitting end or an AXI bus receiving end.

[0044] As a further improvement of the technical solution, the opposite end interface controller module is a sending end interface control module or a receiving end interface control module.

[0045] As a further improvement of the present technical solution, the initiating side interface control module is a sending end interface control module or a receiving end interface control module.

[0046] On the other hand, the present invention provides a device for transmitting write response information based on the PCIe protocol, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein when the processor executes the computer program, the steps of any one of the above-mentioned methods for transmitting write response information based on the PCIe protocol are implemented.

[0047] Compared with the prior art, the present invention has the following beneficial effects:

[0048] In a system, method and device for transmitting write response information based on the PCIe protocol, the write response information is encapsulated into a PCIe write data packet in a special format and is specially processed and converted at the sending side and the receiving side. The sending end interface control module converts the local ACK information into a BAW data packet through a BAW to B module and sends it to the opposite end. After receiving the BAW, the opposite end interface control module extracts the write response information in the BAW through a write request to write response module and converts it back to a write response format (B Response) that complies with AXI or other local bus protocols. Then, through coordination by an arbitrator, the correct write response is returned to the local bus of the initiator, thereby realizing the transmission of the write response of the data bus between PCIe devices. The user does not need to consider the restrictions on data transmission at the PCIe protocol layer during use, making data transmission more universal and efficient. BRIEF DESCRIPTION OF THE DRAWINGS

[0049] Figure 1 This is a flowchart of the overall system for transmitting write response information based on the PCIe protocol in Example 1 of the present invention.

[0050] The meaning of each number in the figure is:

[0051] 1. AXI bus transmitting end; 2. Interface controller module; 21. Transmitting end interface control module; 22. Receiving end interface control module; 3. PCIe controller; 31. Transmitting channel; 32. Receiving channel; 4. AXI bus receiving end. DETAILED DESCRIPTION

[0052] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0053] Embodiment 1:

[0054] See also Figure 1 As shown, a system for transmitting write response information based on the PCIe protocol is provided, including an AXI bus transmitter 1, which sends a memory read / write request through an address channel ar, carries a target address and related control information, and then sends data through a write data channel w. After the write operation is completed, a write response signal returned by the target device is received by a write response channel b to confirm whether the write is successful;

[0055] Interface controller module 2, which is used to realize conversion between different protocols and arbitration and processing of read and write requests and responses;

[0056] The interface controller module 2 includes a transmitting end interface control module 21 and a receiving end interface control module 22;

[0057] The interface controller module 2 also includes an address channel ar, a write data channel w, a write response channel b, a send channel r, and a write request channel aw;

[0058] PCIe controller 3, PCIe controller 3 is used to adapt and convert the read and write request and response signals of the AXI protocol into the data packet format of the PCIe protocol, so as to perform efficient data transmission between PCIe-based systems;

[0059] Wherein, the PCIe controller 3 includes a sending channel 31 and a receiving channel 32;

[0060] AXI bus receiving end 4, AXI bus receiving end 4 is used to receive write requests and write data converted through the PCIe protocol, and perform corresponding data writing operations. When the write operation is completed, the AXI bus receiving end 4 generates a write response signal and transmits it back to the AXI bus master device that initiated the request through the interface controller module 2.

[0061] In this embodiment, the transmitting end interface control module 21 includes a baw to b module, a write request arbitrator, a write response to write request module a and a write request to write response module a; the baw to b module is a module for processing write response information conversion in a specific interface controller, and is used to extract the originally encapsulated write response information from the received PCIe write request data packet (mwr TLP), and convert it back to the write response format (b response) of the original bus protocol (such as AXI protocol), and then correctly return the write response information to the initiator through the write response channel (b) of the local bus;

[0062] Among them, the baw to b module is used to extract the write request baw carrying the write response information from the PCIe write request data packet (mwr tlp), and convert the baw back to the write response (b response) and return it to the write response channel b of the initiator bus. The write request arbitrator combines and sends the normal write request aw and the write request baw with the write response information of this section; when the PCIe controller 3 gives a local response (local ack) for a certain write request operation, the write response to write request module a embeds the local ack information into a new write request packet, generates a write request baw data packet carrying the response information, and sends it to the peer system through the PCIe interface, so that the peer can obtain the status feedback of this write operation. Finally, the write request to write response module a is responsible for screening and processing all received PCIe write request data packets, identifying the write request baw data packet carrying the write response information, and extracting the corresponding write response content therefrom, and restoring it to the write response (b response) under the AXI protocol after format conversion. This converted write response is then submitted to the write response arbitrator, which schedules it uniformly and finally sends it to the local bus of the initiator, thus completing the entire closed-loop response information transmission process.

[0063] In this embodiment, the receiving end interface control module 22 includes a b to baw module, a write response arbitrator, a write response to write request module b and a write request to write response module b; the b to baw module is responsible for converting the original write response signal (b response) from the receiving end bus into a special form of write request, which contains the original write response information and encapsulates it into a PCIe write request data packet (mwr TLP);

[0064] When the receiving interface control module 22 receives a standard write response (bresponse) transmitted through the PCIe link, the b to baw module converts the write response (b response) returned by the receiving bus into a write request (aw request) and maps it to a PCIe write request data packet (mwr). tlp) is sent to the initiator, and then the baw data generated after conversion by the b to baw module enters the write response arbiter. The write response arbiter is responsible for managing and scheduling all write responses (bresponse) and converted baw data packets to ensure that in the case of multi-source concurrency, the appropriate write response can be accurately and timely fed back to the local bus according to the preset priority or rules. The arbiter also needs to be effectively synchronized with other modules to correctly determine when the write response should be converted into baw form for transmission; the write response to write request module b converts the confirmation signal of the local device for the received write request into a new write request, and attaches relevant response information, generates a baw data packet, and feeds back the completion status of the local device to the initiator to maintain the bidirectionality and integrity of the PCIe link communication. The write request to write response module b is used to decouple the baw data packet from the peer system, extract the original write response information from it, and convert it back to the write response format (b response) that complies with AXI or other local bus protocols; then, the reconstructed write response will be sent to the local bus to notify the corresponding component about the result of the previous write operation.

[0065] Among them, the write request carrying the write response information is called baw.

[0066] Specifically, for local responses:

[0067] When the local PCIe controller completes the write request, it generates a local ack signal, indicating that the write operation has been successfully executed or failed. The write response arbiter can receive and identify these local ack signals, and choose whether to return these local ack information as a write response to the requester on the local bus according to the configuration policy set by the user;

[0068] For peer write response:

[0069] The write response converted by the write request to write response module comes from the peer system. When a special write request (baw) carrying write response information is received, the write response to write request module b will convert it back to the standard write response format (b response) under the local bus protocol; at this time, the write response arbitrator needs to analyze and integrate the received peer write responses, and decide whether and when to return these peer response information to the local bus based on the user configuration strategy.

[0070] The write response arbitrator is used to weigh and allocate write response resources from different sources according to actual conditions, which not only meets the needs of the peer system for write operation results, but also ensures that the local system has real-time control of the write operation status, ensuring the stable and efficient operation of the entire interconnection interface.

[0071] In this embodiment, the sending channel 31 is used to initiate read returns, read requests, and write requests;

[0072] The read return is used for the PCIe controller 3 to read data from the target device, package the data into a read return data packet (cpld tlp), and send it back to the initiator through the sending channel;

[0073] When the bus initiates a read request, the PCIe controller 3 converts the request into a read request packet (mrd tlp) of the PCIe protocol;

[0074] When the bus initiates a write request, the PCIe controller 3 converts the request into a write request data packet (mwr tlp) of the PCIe protocol.

[0075] In this embodiment, the receiving channel 32 is used to initiate write requests, read requests and read returns;

[0076] When the PCIe controller 3 receives a write request data packet (mwr tlp), the write request decapsulates the data packet and converts it into a write request of the bus protocol; the PCIe controller 3 extracts the address and data information in the data packet and sends it to the target device on the bus;

[0077] When the PCIe controller 3 receives a read request packet (mrd tlp), the read request decapsulates the packet and converts it into a read request of the bus protocol; the PCIe controller 3 extracts the address information in the packet and sends it to the target device on the bus;

[0078] When the PCIe controller 3 receives a read return data packet (cpld tlp), the read return decapsulates the data packet and converts it into a read return of the bus protocol; the PCIe controller 3 extracts the data information in the data packet and sends it to the device that initiated the read request.

[0079] Embodiment 2:

[0080] The difference between Example 2 of the present invention and Example 1 is that this example introduces a static mechanical properties collection and analysis method used by a system for transmitting write response information based on the PCIe protocol.

[0081] A middle station management method for laboratory automation, used in any of the above-mentioned systems for transmitting write response information based on the PCIe protocol, comprising the following steps:

[0082] S1. The specific processing flow of the read request is as follows:

[0083] S1.1, the initiating side bus interface sends a read request to the peer chip; the read address is 0x1000, the length is 1, and the read request number (arid) is 1; wherein the initiating side bus interface is AXI bus transmitter 1 or AXI bus receiver 4;

[0084] S1.2, the interface controller module 2 maps the corresponding AXI read request information to the corresponding bit field of the PCIe read request data packet (mrdtlp) and sends it to the other party; the AXI read request address can be directly mapped to the address bit field of the PCIe read request data packet (mrdtlp), and the AXI read request length will be mapped to the length bit field of the mrd tlp packet. The read request number (arid) does not need to be passed to the other party;

[0085] S1.3, the opposite end interface controller module performs the opposite processing, that is, converts the PCIe read request data packet (mrd tlp) back to the AXI read request and sends it to the opposite end bus interface; the read address is 0x1000, the length is 1, and the read request number (arid) is a (the arid used by the opposite end may be different from that of the initiating side); wherein the opposite end interface controller module is the transmitting end interface control module 21 or the receiving end interface control module 22;

[0086] S1.4, the peer interface controller module waits for the read response of the peer bus interface, maps it to the corresponding bit field of the PCIe read response data packet (cpld) and returns it; the read response data is 0xffff, and the read response number (rid) is a (corresponding to arid in step S1.3);

[0087] S1.5, the initiating side interface control module waits for the cpld packet returned by the other end, and converts it into an AXI write response and returns it to the initiating test bus interface; the read response data is 0xffff, and the read response number (rid) is 1 (corresponding to the arid in step S1.1); the initiating side interface control module is the transmitting end interface control module 21 or the receiving end interface control module 22;

[0088] S2. The specific processing flow of the write request is as follows:

[0089] S2.1. The initiating bus interface initiates a write request to the peer chip; the write address is 0x1000, the write data is 0xffff, the write length is 1, and the write request number (awid) is 2;

[0090] S2.2, the transmitting end interface control module 21 maps the corresponding AXI write request information to the corresponding bit field of the PCIe write request data packet (mwr tlp) and sends it to the other party; the write address, write data and write length have one-to-one corresponding bit fields to store, and the write request number (awid) needs to be passed to the other party by means of a data packet prefix (tlp prefix);

[0091] S2.3, the receiving end interface control module 22 performs the opposite processing, that is, converts the PCIe write request data packet (mwr tlp) back to an AXI write request and sends it to the opposite end bus interface; the write address sent to the bus interface is 0x1000, the length is 1, the write data is 0xffff, and the write request number (awid) is b;

[0092] S2.4, the receiving end interface control module 22 needs to parse out the awid information of the initiator stored in the data packet prefix (tlp prefix) and store the mapping relationship between it and the local awid;

[0093] S2.5, the receiving end interface control module 22 waits for and receives the write response returned by the bus interface (the response number bid of the write response is b, the response status bresp is success, and the response custom content buser is 0xabcd), and converts the write response to the write request (b2baw), that is, converts the write response of the AXI bus into a PCIe write request (mwr tlp) carrying special write response information, and sends it back to the peer end together with other ordinary PCIe write requests. This type of write request carrying special information is called baw;

[0094] S2.6. At the same time, the receiving end interface control module 22 will reversely infer the response number according to the previously recorded mapping relationship of the awid (b to 2), and store the response number, response status, and response custom content in the baw packet prefix (tlp prefix). The remaining information of the baw can be encapsulated into a zero-length write request with a fixed address, that is, the write address is 0x0, the write data is 0x0, and the length is 0 (bit field FBE=0, LBE=0);

[0095] S2.7, the transmitting end interface control module 21 receives the PCIe write request (mwrtlp) from the receiving end interface control module 22, and determines whether the mwr tlp is a general write request or baw according to the packet prefix;

[0096] S2.8, if it is a general write request, convert the write request (mwr tlp) into a write request of the AXI interface and transmit it to the AXI bus receiving end 4;

[0097] S2.9. If it is a baw, a write request is converted into a write response (baw2b). The sending end interface control module 21 converts the relevant information in the tlp prefix in the baw packet into AXI write response information and returns it to the initiating side bus interface, and determines the response status; the write response content is the response number (bid) is 2, the response status (bresp) is success, and the response custom content (buser) is 0xabcd.

[0098] The above operation on the write request is a special processing method of the device of the present invention. The difference between it and the general processing method is that there is no direct correspondence between the write response of the bus and the data packet (tlp) type defined by the PCIe protocol, and the user needs to do additional special processing:

[0099] When the local system completes the operation of the write request, a local confirmation signal (local ack) is generated. This confirmation signal represents the success or failure of the write operation. In the present invention, this confirmation information is not directly returned in the standard AXI or similar local bus protocol write response format, but is encapsulated into the PCIe write request data packet to form a special write request, called baw (write request with write response information; the baw data packet contains not only normal write request information (such as write address, write data, write length, etc.), but also carries the write request number (awid) of the initiator and the relevant information of the write response in the data packet prefix (tlp prefix), such as the response number (bid), the response status (bresp, the response custom content (buser); the sending end interface control module converts the local ack information into a baw data packet through the baw to b module and sends it to the opposite end. After receiving the baw, the opposite end interface control module extracts the write response information in the baw through the write request to write response module, and converts it back to the write response format (b response) that complies with the AXI or other local bus protocols, and then coordinates through the arbitrator to return the correct write response to the local bus of the initiator;

[0100] The device of the present invention realizes the transmission of write responses of the data bus between PCIe devices by encapsulating the write response information into a PCIe write data packet in a special format and performing special processing and conversion on the sending side and the receiving side. Therefore, this conversion method is a special processing flow for the device of the present invention to transmit write responses.

[0101] The present invention also provides a device for transmitting write response information based on the PCIe protocol, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor. When the processor executes the computer program, the processor implements any one of the steps of the method for transmitting write response information based on the PCIe protocol.

[0102] The above shows and describes the basic principles, main features and advantages of the present invention. Those skilled in the art should understand that the present invention is not limited by the above embodiments. The above embodiments and descriptions are only preferred examples of the present invention and are not intended to limit the present invention. Without departing from the spirit and scope of the present invention, the present invention may have various changes and improvements, which fall within the scope of the present invention. The scope of protection of the present invention is defined by the attached claims and their equivalents.

Claims

1. A system for transmitting write response information based on PCIe protocol, characterized in that: include: An AXI bus transmitter (1), wherein the AXI bus transmitter (1) sends a memory read / write request through an address channel ar, carrying a target address and related control information, and then sends data through a write data channel w. After the write operation is completed, a write response signal returned by the target device is received through a write response channel b to confirm whether the write operation is successful; An interface controller module (2), the interface controller module (2) being used to implement conversion between different protocols and arbitration and processing of read and write requests and responses; The interface controller module (2) comprises a transmitting end interface control module (21) and a receiving end interface control module (22); Specifically, the transmitting end interface control module (21) comprises a baw to b module, a write request arbitrator, a write response to write request module a and a write request to write response module a; The baw-to-b module is used to extract the write request baw carrying the write response information from the PCIe write request data packet mwr tlp, and convert the baw back to the write response b response and return it to the write response channel b of the initiator bus. The write request arbitrator combines and sends the normal write request aw and the write request baw carrying the write response information of this section. When the PCIe controller (3) gives a local response local ack for a certain write request operation, the write response-to-write request module a embeds the local ack information into a new write request packet, generates a write request baw data packet carrying the response information, and sends it to the peer system through the PCIe interface. Finally, the write request-to-write response module a is responsible for screening and processing all received PCIe write request data packets, identifying the write request baw data packets carrying the write response information, extracting the corresponding write response content from them, and restoring them to the write response b response under the AXI protocol after format conversion. The receiving end interface control module (22) comprises a b to baw module, a write response arbitrator, a write response to write request module b and a write request to write response module b; When the receiving end interface control module (22) receives a standard write response bresponse transmitted via a PCIe link, the b to baw module converts the write response b response returned by the receiving end bus into a write request awrequest and maps it to a PCIe write request data packet mwr tlp and sends it to the initiator. Subsequently, the baw data generated after the conversion by the b to baw module enters the write response arbiter, and the write response arbiter is responsible for managing and scheduling all write response bresponses and converted baw data packets. The write response to write request module b converts the confirmation signal of the local device for the received write request into a new write request, and attaches relevant response information to generate a baw data packet. The write request to write response module b is used to decouple the baw data packet from the opposite end system, extract the original write response information therefrom, and convert it back into a write response format b response that complies with AXI or other local bus protocols. A PCIe controller (3), the PCIe controller (3) being used to adapt and convert read and write request and response signals of the AXI protocol into a data packet format of the PCIe protocol, so as to perform efficient data transmission between PCIe-based systems; Wherein, the PCIe controller (3) comprises a sending channel (31) and a receiving channel (32); An AXI bus receiving end (4) is used to receive a write request and write data converted via a PCIe protocol and to perform a corresponding data write operation. When the write operation is completed, the AXI bus receiving end (4) generates a write response signal and transmits it back to the AXI bus master device that initiated the request via an interface controller module (2).

2. The system for transmitting write response information based on the PCIe protocol according to claim 1, characterized in that: The sending channel (31) is used to initiate a read return, a read request and a write request; The read return is used by the PCIe controller (3) to package the data into a read return data packet cpld tlp after reading the data from the target device, and send it back to the initiator through the sending channel; When the bus initiates a read request, the PCIe controller (3) converts the request into a read request data packet mrd tlp of the PCIe protocol; When the bus initiates a write request, the PCIe controller (3) converts the request into a write request data packet mwr tlp of the PCIe protocol.

3. The system for transmitting write response information based on the PCIe protocol according to claim 1, characterized in that: The receiving channel (32) is used to initiate a write request, a read request and a read return; When the PCIe controller (3) receives a write request data packet mwr tlp, the write request decapsulates the data packet and converts it into a write request of the bus protocol, extracts the address and data information in the data packet, and sends it to a target device on the bus; When the PCIe controller (3) receives a read request data packet mrd tlp, the read request decapsulates the data packet and converts it into a read request of the bus protocol; When the PCIe controller (3) receives a read return packet cpld tlp, the read return decapsulates the packet and converts it into a read return of the bus protocol.

4. A method for transmitting write response information based on the PCIe protocol, used in a system for transmitting write response information based on the PCIe protocol as claimed in any one of claims 1 to 3, characterized in that: The steps include: S1. The specific processing flow of the read request is as follows: S1.1, the initiator bus interface sends a read request to the peer chip; S1.2, the interface controller module (2) maps the corresponding AXI read request information to the corresponding bit field of the PCIe read request data packet mrd tlp and sends it to the other side; S1.3, the opposite end interface controller module performs the opposite processing, that is, converts the PCIe read request data packet mrd tlp back to AXI read request and sends it to the opposite end bus interface; S1.4, the peer interface controller module waits for the read response of the peer bus interface, maps it to the corresponding bit field of the PCIe read response data packet cpld and returns it; S1.5, the initiating side interface control module waits for the cpld packet returned by the other end, and converts it into an AXI write response and returns it to the initiating test bus interface; S2. The specific processing flow of the write request is as follows: S2.1, the initiating side bus interface initiates a write request to the peer chip; S2.2, the transmitting end interface control module (21) maps the corresponding AXI write request information to the corresponding bit field of the PCIe write request data packet mwrtlp and sends it to the other end; S2.3, the receiving end interface control module (22) performs the opposite processing, that is, converts the PCIe write request data packet mwr tlp back to an AXI write request and sends it to the opposite end bus interface; S2.4, the receiving end interface control module (22) needs to parse out the awid information of the initiator stored in the data packet prefix tlp prefix at the same time, and store the mapping relationship between it and the local awid; S2.5, the receiving end interface control module (22) waits for and receives the write response returned by the bus interface, and performs a conversion b2baw from the write response to a write request, that is, converts the write response of the AXI bus into a PCIe write request mwr tlp carrying special write response information, and sends it back to the other end together with other common PCIe write requests; S2.

6. At the same time, the receiving end interface control module (22) will reversely infer the response number based on the previously recorded mapping relationship of the awid, and store the response number, response status, and response custom content in the baw packet prefix tlp prefix. The remaining information of the baw can be encapsulated into a zero-length write request with a fixed address; S2.7, the transmitting end interface control module (21) receives the PCIe write request mwrtlp from the receiving end interface control module (22), and determines whether the mwr tlp is a general write request or a baw according to the packet prefix; S2.

8. If it is a general write request, convert the write request mwr tlp into a write request of the AXI interface and pass it to the AXI bus receiving end (4). S2.9, if it is a baw, the write request is converted into a response baw2b, and the sending end interface control module (21) converts the relevant information in the tlp prefix in the baw packet into AXI write response information and returns it to the initiating side bus interface, and determines the response status.

5. The method for transmitting write response information based on the PCIe protocol according to claim 4, characterized in that: The initiating side bus interface is an AXI bus transmitting end (1) or an AXI bus receiving end (4).

6. The method for transmitting write response information based on the PCIe protocol according to claim 4, characterized in that: The opposite end interface controller module is a sending end interface control module (21) or a receiving end interface control module (22).

7. The method for transmitting write response information based on the PCIe protocol according to claim 4, characterized in that: The initiating side interface control module is a sending end interface control module (21) or a receiving end interface control module (22).

8. A device for transmitting write response information based on the PCIe protocol, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that: When the processor executes the computer program, the steps of the method for transmitting write response information based on the PCIe protocol as described in any one of claims 4 to 7 are implemented.

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