Display device, display control method, related apparatus and computer program product

Abstract

The application provides a display device, a display control method, related equipment and a computer program product. The display device comprises a control unit configured to send a partition control instruction to a timing driving unit in response to a display panel being in a partition refresh state. The timing driving unit is electrically coupled to the control unit and configured to receive and analyze the partition control instruction. The analyzed partition control instruction is sent to a source driving unit. The source driving unit is electrically coupled to the timing driving unit and configured to receive the analyzed partition control instruction and forward it to a gate driving circuit. The gate driving circuit is electrically coupled to the source driving unit and configured to receive the analyzed partition control instruction and control the display panel based on the analyzed partition control instruction. The display panel is connected to the control unit, the source driving unit and the gate driving circuit, respectively, and configured to display a picture in each display partition according to control information.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of display, in particular to a display device, a display control method, related equipment and a computer program product. BACKGROUND

[0002] In the field of display, more and more electronic products of mobile terminals use organic light emitting diode (OLED) display screens. Among them, the OLED display screen has the advantages of fast response speed, excellent display effect and low power consumption. In order to obtain a smoother picture quality experience, the refresh rate of the OLED display screen is developing towards a higher direction, and the problem of high display power consumption follows. In order to reduce the display power consumption, a partition variable frequency scheme is proposed, that is, a display panel is divided into multiple regions, and each partition can set different refresh rates. However, for the separated driving chip architecture, there is no feasible partition variable frequency scheme. SUMMARY

[0003] Therefore, the purpose of the present application is to provide a display device, a display control method, related equipment and a computer program product to at least partially solve the problem that the separated driving chip architecture cannot realize partition variable frequency.

[0004] To achieve the above purpose, the first aspect of the present application provides a display device, comprising:

[0005] a control unit, configured to send a partition control instruction to a timing driving unit in response to the display panel being in a partition refresh state; the partition control instruction comprises control information related to the refresh frequency of each display partition of the display panel;

[0006] a timing driving unit, electrically coupled to the control unit, configured to receive the partition control instruction, analyze the partition control instruction, and send the analyzed partition control instruction to a source driving unit;

[0007] a source driving unit, electrically coupled to the timing driving unit, configured to receive the analyzed partition control instruction and forward the analyzed partition control instruction to a gate driving circuit;

[0008] a gate driving circuit, electrically coupled to the source driving unit, configured to receive the analyzed partition control instruction and control the display panel based on the analyzed partition control instruction;

[0009] a display panel, connected to the control unit, the source driving unit and the gate driving circuit respectively, configured to display a picture in each display partition according to the control information;

[0010] The source driving unit and the gate driving circuit control the display panel to display based on the parsed partition control instruction.

[0011] Optionally, the partition control instruction includes a first refresh frequency corresponding to each display partition; and the timing driving unit is configured to:

[0012] determine a first clock signal and a first control signal corresponding to each row of pixel units in the display partition according to a basic refresh frequency of the display panel and the first refresh frequency, and take the first clock signal and the first control signal as the parsed partition control instruction; wherein the first control signal can change a period of a pulse signal in the first clock signal, so that the refresh frequency of the display partition under the control of the first clock signal and the first control signal is equal to the first refresh frequency.

[0013] Optionally, the timing driving unit is configured to:

[0014] determine the first clock signal according to the basic refresh frequency, and determine the first control signal according to the first refresh frequency.

[0015] Optionally, the first clock signal includes a first sub-clock signal and a second sub-clock signal; when the first control signal is a first level, the first sub-clock signal is a first level, and the second sub-clock signal is a second level.

[0016] Optionally, the first clock signal includes a first sub-clock signal and a second sub-clock signal; when the first control signal is a second level, the first sub-clock signal is a first level, and the second sub-clock signal is a second level.

[0017] Optionally, the parsed partition control instruction further includes a start row identifier and an end row identifier corresponding to each display partition; and the source driving unit is configured to:

[0018] send the start row identifier, the end row identifier, the first clock signal and the first control signal to the gate driving circuit, so that the gate driving circuit controls each pixel unit in the display partition determined by the start row identifier and the end row identifier to be switched on or off according to the first clock signal and the first control signal.

[0019] Optionally, the parsed partition control instruction further includes display data corresponding to each display partition; and the timing driving unit is configured to:

[0020] The display data corresponding to each display partition is sent to the source driver unit, so that when the pixel unit switch in each display partition is turned on, the source driver unit inputs the corresponding display data to the pixel unit.

[0021] Optionally, before parsing the partition control instructions, the timing drive unit is configured as follows:

[0022] The partition control command is detected, and in response to determining that there is an anomaly in the partition control command, anomaly information related to the partition control command is fed back to the control unit.

[0023] A second aspect of this application also provides a display control method applied to the display device described in the first aspect, comprising:

[0024] The system receives a partition control command issued by a control unit connected to the timing control unit; wherein the partition control command is issued by the control unit when the display panel is in a partition refresh state, and the partition control command includes control information related to the refresh frequency of each display partition of the display panel;

[0025] The partition control command is parsed, and the parsed partition control command is sent to the source drive unit connected to the timing control unit. The source drive unit then sends the parsed partition control command to the gate drive circuit connected to the source drive unit, so that the source drive unit and the gate drive circuit control the display panel to display based on the parsed partition control command, so that each display partition displays the image according to the control information.

[0026] A third aspect of this application also provides an electronic device including a memory, a processor, and a computer program stored in the memory and executable by the processor, wherein the processor, when executing the computer program, implements the method as described in the second aspect.

[0027] A fourth aspect of this application also provides a non-transitory computer-readable storage medium storing computer instructions for causing a computer to perform the method as described in the second aspect.

[0028] The fifth aspect of this application also provides a computer program product including computer program instructions that, when executed on a computer, cause the computer to perform the method as described in the second aspect.

[0029] As can be seen from the above description, the display device provided in this application includes a control unit, which sends a partition control command to a timing drive unit in response to the display panel being in a partition refresh state. The partition control command includes control information related to the refresh frequency of each display partition of the display panel. When the display panel requires partition refresh, the control unit sends a corresponding partition control command to the timing control unit, so that the timing control unit can convert the partition control command into a signal that the source drive unit and the gate drive circuit can understand. The timing drive unit, electrically coupled to the control unit, receives the partition control command, parses the partition control command, and after parsing, generates timing signals related to the partition refresh of the display panel and display data for display in the pixel units. The parsed partition control command is sent to the source driver unit. The source driver unit, electrically coupled to the timing driver unit, receives the parsed partition control command and forwards it to the gate driver circuit. The gate driver circuit, electrically coupled to the source driver unit, receives the parsed partition control command and controls the display panel based on the parsed partition control command. The display panel is connected to the control unit, the source driver unit, and the gate driver circuit, respectively, and displays the image in each display partition according to the control information. The source driver unit and the gate driver circuit control the display panel to display based on the parsed partition control command. The display driver architecture of this application is a separate driver architecture; the timing control unit and the source driver unit exist independently in the display module, which differs from an integrated driver architecture. The source driver unit and the gate driver circuit control the display panel to display based on the parsed partition control command, so that each display partition displays the image according to the control information. In the discrete driving architecture of this application, to achieve zoned frequency conversion control of the display panel, it is necessary to control and coordinate the signal transmission and reception and signal processing between different units. This application uses a timing control unit to parse the zoned control commands and sends the parsed information containing the refresh frequency of the display zones to the source driving unit and the gate driving circuit respectively. This allows each display zone to display according to the control information under the control of the source driving unit and the gate driving circuit, thus meeting the refresh frequency requirements of each display zone. While ensuring that the user's smooth picture quality experience of the display panel is met, the power consumption loss of the display device using the discrete driving architecture is reduced, especially solving the problem of high power consumption in medium and large mobile terminals. Attached Figure Description

[0030] To more clearly illustrate the technical solutions in this application or related technologies, the drawings used in the description of the embodiments or related technologies will be briefly introduced below. Obviously, the drawings described below are only embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0031] Figure 1 A schematic diagram illustrating the statistical duration of user usage on the terminal display panel in an embodiment of this application;

[0032] Figure 2 This is a schematic diagram of refresh rates in common application scenarios of terminal display panels according to embodiments of this application;

[0033] Figure 3A This is a schematic diagram of the row partition refresh scheme for a mobile phone product according to an embodiment of this application;

[0034] Figure 3B This is a schematic diagram of the column partition refresh scheme for a mobile phone product according to an embodiment of this application;

[0035] Figure 4 This is a schematic diagram of the separate driver architecture according to an embodiment of this application;

[0036] Figure 5 This is a flowchart illustrating the display control method according to an embodiment of this application;

[0037] Figure 6 This is a schematic diagram of a display device for a zoned frequency conversion display according to an embodiment of this application;

[0038] Figure 7 This is a control timing diagram for partitioned frequency conversion refresh according to an embodiment of this application;

[0039] Figure 8 This is a control timing diagram for partitioned frequency conversion refresh according to another embodiment of this application;

[0040] Figure 9 This is a control timing diagram for partitioned frequency conversion refresh according to another embodiment of this application;

[0041] Figure 10 This is a schematic diagram of pixel rows in a display panel according to an embodiment of this application;

[0042] Figure 11 This is a schematic diagram of the display control device according to an embodiment of this application;

[0043] Figure 12 This is a schematic diagram of the hardware structure of an electronic device according to an embodiment of this application. Detailed Implementation

[0044] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with specific embodiments and the accompanying drawings.

[0045] It should be noted that, unless otherwise defined, the technical or scientific terms used in the embodiments of this application should have the ordinary meaning understood by one of ordinary skill in the art to which this application pertains. The terms "first," "second," and similar terms used in the embodiments of this application do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as "comprising" or "including" mean that the element or object preceding the word encompasses the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Terms such as "connected" or "linked" are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. Terms such as "upper," "lower," "left," and "right" are only used to indicate relative positional relationships; when the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0046] OLED displays, with their advantages of being thin and light, having high contrast, and fast response times, are increasingly favored as the mainstream display medium in various fields of society today, and are widely used in products such as mobile phones, touch panel PCs (TPCs), and notebook computers (NBs). To achieve a smoother picture quality experience, the refresh rate of OLED displays continues to increase. To mitigate the increased power consumption caused by the increased refresh rate, those skilled in the art have proposed methods to reduce power consumption, specifically including reducing the power consumption of the main processor (Application Processor, AP) or reducing the power consumption of the display module.

[0047] As consumers demand ultra-low power consumption in displays, low-temperature polycrystalline oxide (LTPO) display panels have been designed to achieve low-frequency displays, as low as 1Hz, thus reducing power consumption. However, continuously using low refresh rates in display panels cannot meet users' demands for high image quality. Figure 1 This diagram illustrates the statistical duration of user interaction with the terminal's display panel. (For example...) Figure 1 As shown, the user's usage time on the terminal display panel consists of three parts: video display time, game display time, and webpage display time. The display time for each part is basically the same. Figure 2 This diagram illustrates refresh rates for common application scenarios on a terminal display panel. For example... Figure 2As shown, the common refresh rates for terminal display panels when displaying video are 30Hz or 60Hz. Specifically, the refresh rate is 30Hz for LTPO display panels and 60Hz for LTPS (Low Temperature Poly-Silicon) display panels. The refresh rate is lower when displaying web pages; for static images, it can be as low as 1Hz, and for navigation interfaces, it can be as low as 10Hz. The refresh rate is higher when displaying games, reaching up to 120Hz. Therefore, it is evident that users require different refresh rates for different application scenarios when using terminal display panels. Thus, continuously using a low refresh rate cannot meet users' demands for high image quality. Furthermore, display panels may display several different application scenarios simultaneously. If all refresh rates are set to the highest, significant power consumption will result; if all refresh rates are set to the lowest, the refresh rate requirements of individual application scenarios may not be met.

[0048] In this context, those skilled in the art have proposed partitioned driving of display panels, which involves dividing a display panel into multiple regions, each with a different refresh rate. Different refresh rates can meet the needs of different application scenarios. Partitioned refresh allows for updating only certain areas while retaining the previous frame's data in areas that don't require updating, thus saving display power consumption. For mobile phone products, since their driver chip is integrated—there is only one display driver chip (DIC)—data transmission and reception can be handled independently, making partitioned control relatively easy to implement. Figure 3A and Figure 3B This diagram illustrates a partitioned refresh scheme for mobile phone products. Figure 3A This diagram illustrates the row partition refresh scheme for mobile phone products. Figure 3A In this design, the phone's display screen is divided into upper and lower display areas. The upper display area has a refresh rate of 30Hz, while the lower display area has a refresh rate of 60Hz. Figure 3B The diagram illustrates a column partitioning refresh scheme for a mobile phone product. The phone screen is divided into two display areas, left and right. The refresh rate of the left display area is 30Hz, and the refresh rate of the right display area is 120Hz.

[0049] However, for some mobile terminal products with medium to large displays, the driving architecture used is a separate driving chip architecture, such as the Tcon+Source separate architecture. Figure 4A schematic diagram of a Tcon+Source split architecture is shown. This architecture includes a main processor (Application Processor, AP) 01, a timing controller (TCON) 02, a source driver 03, a power management IC (PMIC) 04, and a display panel 05. The display panel 05 can be an active-matrix organic light-emitting diode (AMOLED) display panel. The display panel 05 integrates a gate driving circuit, which can be a GOA (Gate on Array) circuit. The main processor 01 communicates with the timing controller 02 via an eDP (Embedded Display Port) interface, with the main processor 01 transmitting video data to the timing controller 02. The timing controller 02 is connected to both the source driver 03 and the power management IC 04. The timing control unit 02 and the source drive unit 03 communicate via a P2P protocol, specifically through the ISP (Integrated-Stream Protocol) within the P2P protocol. The timing control unit 02 sends power control signals to the power management unit 04. The source drive unit 03 is connected to the display panel 05, and the main processor 01 is also connected to the display panel 05. The power management unit 04 is connected to the main processor 01, the timing control unit 02, the source drive unit 03, and the power management unit 04, and supplies power to these components. The source drive unit 03 outputs a gate drive signal to the gate drive circuit of the display panel 05 and a source drive signal to the source drive circuit. The main processor 01 outputs a power signal vin to the power management unit 04. The main processor 01 also outputs a positive drive voltage (ELVDD) and a negative drive voltage (ELVSS) for electroluminescence to the display panel 05. In the aforementioned split architecture, if partitioned frequency conversion is to be implemented, the various units need to work together and the signal transmission and reception methods and signal processing methods between the various units need to be reasonably designed. The control process is relatively complex. Therefore, there is currently no feasible partitioned frequency conversion solution.

[0050] In view of this, this application proposes a display control method. In a discrete driving architecture, a timing control unit receives partition control commands sent by a control unit, parses the partition control commands, and sends the parsed partition control commands to the source driving unit and the gate driving circuit. Based on the parsed partition control commands, the source driving unit and the gate driving circuit can realize partitioned display of the display interface. Each display partition can be refreshed according to the control commands related to the refresh frequency in the partition control commands.

[0051] The embodiments of this application will be described in detail below with reference to the accompanying drawings.

[0052] This application proposes a display device, such as... Figure 4 As shown, it includes:

[0053] Control unit 01 is used to send a partition control command to timing drive unit 02 in response to the display panel 05 being in a partition refresh state; the partition control command includes control information related to the refresh frequency of each display partition of the display panel 05;

[0054] The timing drive unit 02 is electrically coupled to the control unit 01 and is used to receive the partition control command, parse the partition control command, and send the parsed partition control command to the source drive unit 03.

[0055] The source drive unit 03 is electrically coupled to the timing drive unit 02 and is used to receive the parsed partition control command and forward the parsed partition control command to the gate drive circuit.

[0056] A gate driving circuit, electrically coupled to the source driving unit 03, is used to receive the parsed partition control command and control the display panel 05 based on the parsed partition control command.

[0057] Display panel 05 is connected to the control unit 01, the source drive unit 03 and the gate drive circuit respectively, and is used to display the screen in each display zone according to the control information;

[0058] The source driving unit 03 and the gate driving circuit control the display panel 05 to display based on the parsed partition control instructions.

[0059] Specifically, the control unit in this embodiment can be Figure 4 The main processor 01 in the system. Partition refresh status means that the display panel 05 has different display partitions, and different display partitions need to be displayed at different refresh rates. Figure 6 A schematic diagram of a display device with zoned frequency conversion display is shown. Figure 6In this display device, the display interface is divided into three parts: an upper display area, a middle display area, and a lower display area. The refresh rate of the upper display area is 120Hz, the refresh rate of the middle display area is 60Hz, and the refresh rate of the lower display area is 120Hz. Source drive units (SDIC1 to SDIC4) and timing drive units (TCON) are located at the lower part of the display device. When the control unit 01 detects that the display panel 05 is in a partitioned refresh state, it determines and generates partition control instructions, which are control information related to the refresh rate of each display partition. Furthermore, the partition control instructions may include pixel row identifiers corresponding to each display partition, which may include start row identifiers and end row identifiers. The start row identifiers and end row identifiers determine the specific position of each display partition on the display panel 05. The partition control instructions may also include the refresh rate corresponding to each display partition.

[0060] Furthermore, after the control unit 01 generates the partition control instruction, it can store it in a register. When it needs to be sent to the timing control unit 02, the partition control instruction is extracted from the register and sent to the source drive unit 03 in the form of a packet. For example, the control unit 01 generates the instruction code DPCD00170h[4] = 1, where DPCD (DisplayPort Configuration Data) represents a register, 00170h represents the address of the register, and [4] represents the bit sequence number in the register address. When the instruction code DPCD00170h[4] is set to 1, it means that the partition control instruction stored in the 4th bit of the register storage space at address 00170h is sent to the timing control unit 02.

[0061] Control unit 01 sends packets to timing control unit 02 via eDP interface. The partition control command may also include display data to be displayed on display panel 05 during partition refresh, and the display data may include audio and video data. After receiving the packets, timing control unit 02 converts the partition control command into signals that can be recognized by source drive unit 03 and gate drive circuit, so as to perform partition frequency conversion drive display on display panel 05.

[0062] Upon receiving a partition control command, the timing control unit 02 parses the command, converting it into signals recognizable by the source drive unit 03 and the gate drive circuit. During parsing, the timing control unit 02 generates different timing signals based on the partition control command according to the control logic. These different timing signals satisfy certain execution logic during execution, and the refresh frequency within each display partition is controlled and adjusted through the synergistic effect of these different timing signals. This ensures that each display partition can display at the refresh frequency indicated by the partition control command, thereby achieving partition frequency conversion control.

[0063] The parsed partition control instructions include a first timing signal for controlling the source drive unit 03, a second timing signal for controlling the gate drive circuit, and display data corresponding to each display partition. Further, the parsed partition control instructions include a first timing signal, a second timing signal, and display data for each display partition. Under the control of the first and second timing signals corresponding to each display partition, the screen can be displayed in that display partition at the refresh rate indicated in the partition control instructions.

[0064] In Figure 4 In the example of the separate drive architecture, the timing control unit 04 sends the parsed partition control command to the source drive unit 03. The source drive unit 03 controls the pixel units in the display panel according to the first timing signal. Simultaneously, the source drive unit 03 also forwards the parsed partition control command to the gate drive circuit in the display panel 05. The gate drive circuit controls the pixel units in the display panel according to the second timing signal therein. The gate drive circuit opens or closes the pixel unit switch according to the second timing signal. When the pixel unit switch is open, the source drive unit 03 inputs the display data corresponding to the display partition into the pixel unit according to the first timing signal.

[0065] Based on the parsed partition control instructions, the source drive unit 03 and the gate drive circuit can control the display panel 05 to perform partitioned frequency conversion display. For each display partition, it can control the display partition to display according to the refresh frequency in the partition control instructions, for example, to achieve... Figure 6 The three display zones shown have different refresh rates.

[0066] Based on steps 102 to 104 above, this application embodiment proposes a display device, including a control unit, configured to send a partition control command to a timing drive unit in response to the display panel being in a partition refresh state; the partition control command includes control information related to the refresh frequency of each display partition of the display panel. When the display panel requires partition refresh, the control unit sends a corresponding partition control command to the timing control unit, so that the timing control unit can convert the partition control command into a signal understandable by the source drive unit and the gate drive circuit. The timing drive unit, electrically coupled to the control unit, is configured to receive the partition control command, parse the partition control command, and after parsing, generate timing signals related to the partition refresh of the display panel and display data for display in pixel units. The parsed partition control command is sent to the source driver unit. The source driver unit, electrically coupled to the timing driver unit, receives the parsed partition control command and forwards it to the gate driver circuit. The gate driver circuit, electrically coupled to the source driver unit, receives the parsed partition control command and controls the display panel based on the parsed partition control command. The display panel is connected to the control unit, the source driver unit, and the gate driver circuit, respectively, and displays the image in each display partition according to the control information. The source driver unit and the gate driver circuit control the display panel to display based on the parsed partition control command. The display driver architecture of this application is a separate driver architecture; the timing control unit and the source driver unit exist independently in the display module, which differs from an integrated driver architecture. The source driver unit and the gate driver circuit control the display panel to display based on the parsed partition control command, so that each display partition displays the image according to the control information. In the discrete driving architecture of this application, to achieve zoned frequency conversion control of the display panel, it is necessary to control and coordinate the signal transmission and reception and signal processing between different units. This application uses a timing control unit to parse the zoned control commands and sends the parsed information containing the refresh frequency of the display zones to the source driving unit and the gate driving circuit respectively. This allows each display zone to display according to the control information under the control of the source driving unit and the gate driving circuit, thus meeting the refresh frequency requirements of each display zone. While ensuring that the user's smooth picture quality experience of the display panel is met, the power consumption loss of the display device using the discrete driving architecture is reduced, especially solving the problem of high power consumption in medium and large mobile terminals.

[0067] The following specific examples illustrate the method by which the timing control unit parses partition control commands.

[0068] In some embodiments, the partition control instruction includes a first refresh rate corresponding to each display partition; the timing drive unit is configured to:

[0069] Based on the basic refresh rate of the display panel and the first refresh rate, a first clock signal and a first control signal corresponding to each row of pixel units within the display partition are determined, and the first clock signal and the first control signal are used as parsed partition control instructions; wherein, the first control signal can change the period of the pulse signal in the first clock signal so that, under the control of the first clock signal and the first control signal, the refresh rate of the display partition is equal to the first refresh rate.

[0070] Specifically, when controlling each row of pixel units in the display panel, the clock signal controlling that row of pixel units needs to be determined based on the first refresh frequency of the area where that row is located. The first clock signal and the first control signal correspond to the first refresh frequency. Under the control of the first clock signal and the first control signal, each pixel unit in each row is switched on or off regularly to achieve display of the image in the display partition at the first refresh frequency. If the entire display panel displays at the same basic refresh frequency, then the first clock signal corresponding to each row of pixel units is the same. The basic refresh frequency can be the maximum refresh frequency of the display panel. However, in order to control the display panel to perform partitioned frequency conversion display, it is necessary to adjust the first clock signal based on the basic refresh frequency of the display panel so that the refresh frequency in the display partition is equal to the first refresh frequency. Based on this, in this embodiment, the timing control unit also generates a first control signal, which changes the pulse signal period in the first clock signal to achieve the refresh frequency in the display partition being equal to the first refresh frequency. For example, if it is necessary to reduce the refresh frequency in the display partition, the first control signal can be applied to the first clock signal to extend the pulse signal period of the first clock signal, thereby reducing the refresh frequency in the display partition. For example, the refresh frequency corresponding to the first clock signal is 120Hz. After the first control signal is applied to the first clock signal, the refresh frequency is reduced from 120Hz to 60Hz.

[0071] Furthermore, by applying the first control signal to the first clock signal, the state of the first clock signal can be changed through the state of the first control signal. The first control signal can be a timing signal, including a first level state and a second level state. Control logic is set between the first control signal and the first clock signal. When the first control signal is at the first level, the first clock signal corresponds to one state; when the first control signal is at the second level, the first clock signal remains unchanged. The first level is the effective level of the first control signal, thereby achieving the regulation of the first clock signal.

[0072] Alternatively, it can be understood that, based on the first clock signal controlling the pixel unit switch to turn off or on at a certain refresh frequency, the frequency of the pixel unit switch turning off or on is changed by the first control signal, such as extending the duration of the pixel unit switch being off. During the process of the pixel unit switch being off, the source driver chip cannot write display data into the pixel unit, and the pixel unit retains the display data of the previous frame, which means reducing the refresh frequency of the pixel unit, thereby changing the refresh frequency within the display partition.

[0073] The method in this embodiment allows the timing control unit to generate a first clock signal and a first control signal based on partition control instructions. The first control signal is applied to the first clock signal to change the period of the pulse signal in the first clock signal, thereby realizing frequency conversion control of the display partition. This achieves partition frequency conversion control under a separate drive architecture, solving the problem that medium and large display panels cannot achieve partition frequency conversion and effectively reducing the power consumption of the display device.

[0074] The method for determining the first clock signal and the first control signal is illustrated below through specific embodiments.

[0075] In some embodiments, the timing drive unit is configured as follows:

[0076] The first clock signal is determined based on the base refresh frequency, and the first control signal is determined based on the first refresh frequency.

[0077] Specifically, the first clock signal is determined based on the base refresh rate. Under the control of the first clock signal, the refresh rate of the display panel equals the base refresh rate. The base refresh rate can be the highest refresh rate of the display screen, for example, 120Hz. The first control signal is determined based on the first refresh rate. By applying the first control signal to the first clock signal, the refresh rate of the display panel can be adjusted from the base refresh rate to the first refresh rate, which can be 10Hz. That is, under the action of the first control signal, the refresh rate of the display panel controlled by the first clock signal decreases from 120Hz to 10Hz.

[0078] The following specific example illustrates how the first control signal adjusts the first clock signal.

[0079] In some embodiments, the first clock signal includes a first sub-clock signal and a second sub-clock signal. When the first control signal is at a first level, the first sub-clock signal is at a first level and the second sub-clock signal is at a second level.

[0080] In this embodiment, the first level and the second level only represent that the signal level has two states, and do not represent that the first level or the second level has a specific value. The first level can be a high level, and the second level can be a low level. When the first control signal is at the first level, it can change the state of the first clock signal, that is, change the state of the first sub-clock signal and the second sub-clock signal. At this time, the first level is the effective level of the first control signal.

[0081] Figure 7 The diagram shows a control timing diagram for partitioned frequency conversion refresh according to an embodiment of this application. Figure 7 In the middle, the display panel is divided into three display zones, namely the first display zone, the second display zone, and the third display zone. Figure 7 The left part of the text is the write frame. Figure 7 The right-hand portion of the image represents the partition holding frame. GSTV indicates the gate frame start signal. The first clock signal includes a first sub-clock signal and a second sub-clock signal, which are a pair of clock signals with opposite phases. The first sub-clock signal can be the GCK signal, and the second sub-clock signal can be the GCB signal. GCK1 and GCB1 are the first clock signals for each row of pixel units in the first display partition, and MS1 is the first control signal for the first display partition. GCK2 and GCB2 are the first clock signals for each row of pixel units in the second display partition, and MS2 is the first control signal for the second display partition. GCK3 and GCB3 are the first clock signals for each row of pixel units in the third display partition, and MS3 is the first control signal for the third display partition. In the write frame, the GCK and GCB signals for each display partition are the same, and the refresh rate for each display partition is the same. The MS1 to MS3 signals are all in a low-level state. In the digital signal control logic preset in the timing control unit, it is specified that when the MS signal is in a low-level state, it does not affect the first clock signal. For example, at this time, the refresh rate of all three display zones is the base refresh rate, which can be 120Hz.

[0082] In the partition hold frame, the required first refresh frequency for the second display area is 10Hz. The first clock signal in the second display area needs to be adjusted to reduce the refresh frequency from the base refresh frequency to the first refresh frequency. In the partition hold frame, the MS2 signal is changed from a low level to a high level. The digital signal control logic pre-set in the timing control unit specifies that when the MS signal is high, the state of the first clock signal can be changed; specifically, the first sub-clock signal changes to a high level, and the second sub-clock signal changes to a low level. Since the MS2 signal remains high in the partition hold frame, the first sub-clock signal GCK2 remains high, and the second sub-clock signal GCB2 remains low. This means that the second display partition does not refresh in the partition hold frame. Since the first refresh frequency of the second display area is 10Hz, this is equivalent to refreshing 10 times per second. The refresh frequencies of the first and third display partitions are 120Hz, equivalent to refreshing 120 times per second. Compared to the first and third display partitions, the second display partition refreshes 10 frames and stops for 110 frames per second. If the 120 frames are divided into 10 groups, in each group, the second display partition refreshes 1 frame and stops for 11 frames, while the first and third display partitions continuously refresh 12 frames. For the first and third display partitions, refresh is performed according to the first clock signal during the write frame and the subsequent 11 partition hold frames (one group of frames), and the refresh rate of the first and third display partitions is always 120Hz. For the second display partition, refresh is only performed during the write frame; no refresh is performed during the subsequent 11 partition hold frames. This method can adjust the refresh rate of the second display area to 10Hz.

[0083] In some embodiments, the first clock signal includes a first sub-clock signal and a second sub-clock signal. When the first control signal is at a second level, the first sub-clock signal is at a first level, and the second sub-clock signal is at a second level.

[0084] In this embodiment, the first level can be a high level, and the second level can be a low level. When the first control signal is at the second level, it can change the state of the first clock signal, that is, change the state of the first sub-clock signal and the second sub-clock signal. At this time, the second level is the effective level of the first control signal.

[0085] Figure 8 The diagram shows a control timing diagram for partitioned frequency conversion refresh according to another embodiment of this application. Figure 7The difference lies in the timing control unit. In the write frame, signals MS1 through MS3 are all at a high level. The pre-set digital signal control logic in the timing control unit specifies that the first clock signal is not affected when the MS signal is high. For example, the refresh frequency of all three display zones is the base refresh frequency, which can be 120Hz. In the partition hold frame, the required first refresh frequency for the second display area is 10Hz. The first clock signal in the second display area needs to be adjusted to reduce the refresh frequency from the base refresh frequency to the first refresh frequency. The MS2 signal is adjusted from a high level to a low level. The pre-set digital signal control logic in the timing control unit specifies that when the MS signal is low, the first sub-clock signal changes to a high level, and the second sub-clock signal changes to a low level. Since the MS2 signal remains low in the partition hold frame, the first sub-clock signal GCK2 remains high, and the second sub-clock signal GCB2 remains low. Essentially, the second display zone is not refreshed in the partition hold frame. Similarly, for the first and third display partitions, refresh is performed according to the first clock signal during the write frame and the subsequent 11 partition holding frames, and the refresh rate of the first and third display partitions is always 120Hz. For the second display partition, refresh is performed only during the write frame, and not during the subsequent 11 partition holding frames. This method can also be used to adjust the refresh rate of the second display area to 10Hz.

[0086] Figure 9 The diagram shows a control timing diagram for partitioned frequency conversion refresh according to another embodiment of this application. Figure 9 In this design, the display screen is divided into three display zones: the first display zone, the second display zone, and the third display zone. Figure 7 The difference is, Figure 9 The diagram shows a write frame and two partition hold frames. The two partition hold frames are partition hold frame 1 and partition hold frame 2.

[0087] At this point, the required refresh rate for the second display area is 10Hz. In partition hold frame 1, the first clock signal in the second display area needs to be adjusted to reduce the refresh rate from the base refresh rate to the first refresh rate. In partition hold frame 1, the MS2 signal is changed from a low level to a high level. Since the MS2 signal remains high in partition hold frame 1, the first sub-clock signal GCK2 remains high, and the second sub-clock signal GCB2 remains low. Essentially, the second display partition does not refresh in partition hold frame 1.

[0088] At this point, the required refresh rate for the third display area is 20Hz, equivalent to 20 refreshes per second. Compared to the first display partition, the third display partition refreshes 20 frames and pauses for 100 frames per second. If these 120 frames are divided into 10 groups, in each group, the third display partition refreshes 2 frames and pauses for 10 frames, while the first display partition continuously refreshes 12 frames. Following the same determination method as the MS2 signal, in partition hold frame 2, the first clock signal in the third display area needs to be adjusted so that the refresh rate in the third display area decreases from the base refresh rate to the corresponding first refresh rate of 20Hz for the third display partition. In partition hold frame 2, the MS3 signal is adjusted from a low level to a high level. Since the MS3 signal remains high in partition hold frame 2, the first sub-clock signal GCK3 remains high, and the second sub-clock signal GCB3 remains low. Essentially, in partition hold frame 2, the third display partition does not refresh. Then, by keeping the frame rate of the subsequent 9 partitions the same as that of partition 2, and not refreshing the third display partition, the refresh rate of the third display partition can be adjusted from 120Hz to 20Hz.

[0089] Similarly, for the first display partition, refresh is performed according to the first clock signal in the write frame, partition hold frame 1, partition hold frame 2, and subsequent partition hold frames, and the refresh rate of the first display partition is always 120Hz. For the second display partition, refresh is performed only in the write frame, and not in the subsequent 11 partition hold frames. This method can adjust the refresh rate of the second display area to 10Hz. For the third display partition, refresh is performed only in the write frame and partition hold frame 1, and not in the subsequent 10 partition hold frames. This method can adjust the refresh rate of the third display area to 20Hz. In the above three specific examples, the logical relationship between the first clock signal and the first control signal is preset in the timing control unit. By changing the first control signal, the first clock signal can be adjusted, thereby adjusting the refresh rate in the display partition. This allows the display partition to flexibly control the refresh rate according to the partition control command, realizing partition frequency conversion display in the split drive architecture.

[0090] In some embodiments, the parsed partition control instructions further include a start line identifier and an end line identifier corresponding to each display partition; the source drive unit is configured to:

[0091] The start row identifier, the end row identifier, the first clock signal, and the first control signal are sent to the gate driving circuit so that the gate driving circuit controls the switching of each pixel unit in the display partition determined by the start row identifier and the end row identifier to be turned on or off according to the first clock signal and the first control signal.

[0092] Specifically, after receiving the partition control command from the control unit, the timing control unit parses the partition control command to obtain the start row identifier, end row identifier, first clock signal, and first control signal. Figure 4 In the illustrated split-drive architecture, the timing control unit sends the start row identifier, end row identifier, first clock signal, and first control signal to the gate drive circuit via the source drive unit. The gate drive circuit accurately locates the position of the display partition within the display panel based on the start and end row identifiers. For example, the display panel includes 1500 rows of pixel units, with the start row identifier for each display partition being the 100th row and the end row identifier being the 300th row. After determining the position of the display partition, the gate drive circuit adjusts the refresh rate within the display partition according to the first clock signal and the first control signal, ensuring that the refresh rate of the display partition equals the first refresh rate, thus achieving variable-frequency refresh of the row partitions under the split-drive architecture. This reduces the power consumption of the display device using the split-drive architecture. Displaying the screen in partitions can meet the image quality requirements of different application scenarios displayed on the same interface, improving user satisfaction.

[0093] In some embodiments, the parsed partition control instructions further include display data corresponding to each display partition; the timing drive unit is configured to:

[0094] The display data corresponding to each display partition is sent to the source driver unit, so that when the pixel unit switch in each display partition is turned on, the source driver unit inputs the corresponding display data to the pixel unit.

[0095] Specifically, the data sent via the partition control command also includes display data. After receiving the display data, the source drive unit writes the corresponding display data into the pixel unit when the gate drive circuit controls the pixel unit switch to turn on. Since each display partition displays a different application scenario, each display partition has corresponding display data. The timing control unit sends the display data corresponding to each display partition to the source drive unit to enable each display unit to display the corresponding application scenario. Through the method of this embodiment, when the gate drive circuit controls the display unit to refresh at the first refresh frequency, the source drive unit writes the display data of the display unit into the pixel unit. That is, the source drive single domain and the gate drive circuit cooperate to realize the partitioned frequency conversion refresh of the display unit, reducing the power consumption of the display device using a separate drive architecture.

[0096] After the timing control unit receives the partition control command, it can also perform corresponding anomaly detection on the partition control command before parsing it, so as to ensure that the subsequent display data can be displayed correctly on the display panel.

[0097] In some embodiments, before parsing the partition control instructions, the timing drive unit is configured to:

[0098] The partition control command is detected, and in response to determining that there is an anomaly in the partition control command, anomaly information related to the partition control command is fed back to the control unit.

[0099] Specifically, the partition control command received by the timing control unit includes the pixel row identifier of each display partition and the first refresh rate. Figure 10 This diagram illustrates the pixel rows in the display panel. (As shown...) Figure 10 As shown, the area enclosed by the box is the display panel area, which contains three display zones (A1, A2, and A3). Each display zone has a start row identifier denoted as 's', an end row identifier denoted as 'e', ​​and a detection identifier denoted as 'c'. The detection identifier can be set after the end row identifier to perform anomaly detection on the position of each display zone. Specific detection content may include: checking whether the start and end row identifiers are contained within the pixel row identifiers of the display panel. For example, if the display panel contains 1500 rows of pixels, and there are instances where the start and end row identifiers exceed 1500 rows, then the zone control command is determined to be abnormal. Another example is when the pixel rows of two display zones overlap. For instance, if the end row identifier of the first display zone is row 100, and the start row identifier of the second display zone is row 89, then the two display zones have overlapping pixel rows, and the zone control command is determined to be abnormal (e.g., there is overlap between display zones A2 and A3).

[0100] When an anomaly is detected in the partition control command, the timing control unit can report the anomaly information to the control unit. This information can include the specific cause of the anomaly, facilitating troubleshooting and resolution by the control unit. The timing control unit's detection of the partition control command ensures that subsequent display partitions can be displayed correctly on the display panel, preventing display anomalies and optimizing the display module's display driving logic.

[0101] Figure 5 This application illustrates a display control method according to an embodiment of the present application. The method is applied to a timing control chip, such as... Figure 5 As shown, it includes the following steps:

[0102] Step 102: Receive a partition control command issued by the control unit connected to the timing control unit; wherein the partition control command is issued by the control unit when the display panel is in the partition refresh state, and the partition control command includes control information related to the refresh frequency of each display partition of the display panel.

[0103] Specifically, the control unit in this embodiment can be Figure 4 The main processor 01 in the system. Partition refresh status refers to the display panel having different display partitions, and different display partitions need to be displayed at different refresh rates. Figure 6 A schematic diagram of a display device with zoned frequency conversion display is shown. Figure 6 In this display device, the display interface is divided into three parts: an upper display area, a middle display area, and a lower display area. The refresh rate of the upper display area is 120Hz, the middle display area is 60Hz, and the lower display area is 120Hz. Source drive units (SDIC1 to SDIC4) and timing drive units (TCON) are located at the bottom of the display device. When the control unit detects that the display panel is in a partitioned refresh state, it determines and generates partition control instructions, which are control information related to the refresh rate of each display partition. Furthermore, the partition control instructions may include pixel row identifiers corresponding to each display partition, which may include start row identifiers and end row identifiers. The start and end row identifiers determine the specific position of each display partition on the display panel. The partition control instructions may also include the refresh rate corresponding to each display partition.

[0104] Furthermore, after the control unit generates the partition control instruction, it can be stored in a register. When it needs to be sent to the timing control unit, the partition control instruction is extracted from the register and sent to the source driver unit in the form of a packet. For example, the control unit generates instruction code DPCD00170h[4] = 1, where DPCD (DisplayPortConfiguration Data) represents the register, 00170h represents the address of the register, and [4] represents the bit sequence number in the register address. When the instruction code DPCD00170h[4] is set to 1, it means that the partition control instruction stored in the 4th bit of the register storage space at address 00170h is sent to the timing control unit.

[0105] The control unit sends packets to the timing control unit via the eDP interface. The partition control command may also include display data to be displayed on the display panel during partition refresh, which may include audio and video data. After receiving the packets, the timing control unit converts the partition control command into signals that can be recognized by the source drive unit and the gate drive circuit, so as to perform partition frequency conversion drive display on the display panel.

[0106] Step 104: Parse the partition control command, send the parsed partition control command to the source drive unit connected to the timing control unit, and send the parsed partition control command to the gate drive circuit connected to the source drive unit through the source drive unit, so that the source drive unit and the gate drive circuit control the display panel to display based on the parsed partition control command, so that each display partition displays the image according to the control information.

[0107] Specifically, after receiving the partition control command, the timing control unit parses the command, converting it into signals recognizable by the source drive unit and the gate drive circuit. During parsing, the timing control unit generates different timing signals based on the partition control command according to the control logic. These different timing signals satisfy certain execution logic during execution, and the refresh frequency within the display partition is controlled and adjusted through the synergistic effect of these different timing signals. This ensures that each display partition can display at the refresh frequency indicated by the partition control command, thereby achieving partition frequency conversion control.

[0108] The parsed partition control instructions include a first timing signal for controlling the source drive unit, a second timing signal for controlling the gate drive circuit, and display data corresponding to each display partition. Further, the parsed partition control instructions include a first timing signal, a second timing signal, and display data for each display partition. Under the control of the first and second timing signals corresponding to each display partition, the screen can be displayed in that display partition at the refresh rate indicated in the partition control instructions.

[0109] In Figure 4 In the example of the separate drive architecture, the timing control unit 04 sends the parsed partition control command to the source drive unit 03. The source drive unit 03 controls the pixel units in the display panel according to the first timing signal. Simultaneously, the source drive unit 03 also forwards the parsed partition control command to the gate drive circuit in the display panel 05. The gate drive circuit controls the pixel units in the display panel according to the second timing signal therein. The gate drive circuit opens or closes the pixel unit switch according to the second timing signal. When the pixel unit switch is open, the source drive unit 03 inputs the display data corresponding to the display partition into the pixel unit according to the first timing signal.

[0110] Based on the parsed partition control instructions, the source drive unit 03 and the gate drive circuit can control the display panel to perform partitioned frequency conversion display. For each display partition, it can control the display partition to display according to the refresh frequency in the partition control instructions, for example, to achieve... Figure 6 The three display zones shown have different refresh rates.

[0111] Based on steps 102 to 104 above, this application proposes a display control method applied to a timing control unit. The method includes receiving a partition control command issued by a control unit connected to the timing control unit. The partition control command is issued by the control unit when the display panel is in a partition refresh state, and includes control information related to the refresh frequency of each display partition of the display panel. When the display panel requires partition refresh, the control unit issues a corresponding partition control command to the timing control unit, enabling the timing control unit to convert the partition control command into a signal understandable by the source driver unit and the gate driver circuit. The partition control command is parsed, and after parsing, timing signals related to the partition refresh of the display panel and display data for display in pixel units are generated. The parsed partition control command is sent to the source driver unit connected to the timing control unit, and the source driver unit sends the parsed partition control command to the gate driver circuit connected to the source driver unit. The display driver architecture of this application is a separate driver architecture; the timing control unit and the source driver unit exist independently in the display module and are not part of an integrated driver architecture. The source driving unit and the gate driving circuit control the display panel to display based on the parsed partition control instructions, so that each display partition displays the image according to the control information. In the separate driving architecture of this application, in order to realize the partition frequency conversion control of the display panel, it is necessary to control and coordinate the signal transmission and reception and signal processing between different units. This application parses the partition control instructions through a timing control unit and sends the parsed information containing the refresh frequency of the display partition to the source driving unit and the gate driving circuit respectively, so that each display partition displays according to the control information under the control of the source driving unit and the gate driving circuit, thus realizing the refresh frequency requirement of each display partition. While ensuring that the user's smooth picture quality experience of the display panel can be met, the power consumption loss of the display device using the separate driving architecture is reduced, especially solving the problem of high display power consumption in medium and large mobile terminals.

[0112] It should be noted that the method in this embodiment can be executed by a single device, such as a computer or server. The method can also be applied in a distributed scenario, where multiple devices cooperate to complete the task. In such a distributed scenario, one of these devices may execute only one or more steps of the method in this embodiment, and the multiple devices will interact with each other to complete the method described.

[0113] It should be noted that the above description describes some embodiments of this application. Other embodiments are within the scope of the appended claims. In some cases, the actions or steps recorded in the claims can be performed in a different order than that shown in the above embodiments and still achieve the desired result. Furthermore, the processes depicted in the drawings do not necessarily require a specific or sequential order to achieve the desired result. In some embodiments, multitasking and parallel processing are also possible or may be advantageous.

[0114] Based on the same inventive concept, corresponding to any of the above embodiments, this application also provides a display control device.

[0115] refer to Figure 11 The display control device, applied to the timing control unit, includes:

[0116] The receiving module 202 is configured to receive a partition control command issued by the control unit connected to the timing control unit; wherein the partition control command is issued by the control unit when the display panel is in a partition refresh state, and the partition control command includes control information related to the refresh frequency of each display partition of the display panel;

[0117] The parsing module 204 is configured to parse the partition control command, send the parsed partition control command to the source drive unit connected to the timing control unit, and send the parsed partition control command to the gate drive circuit connected to the source drive unit through the source drive unit, so that the source drive unit and the gate drive circuit control the display panel to display based on the parsed partition control command, so that each display partition displays the image according to the control information.

[0118] In some embodiments, the partition control instruction includes a first refresh frequency corresponding to each display partition; the parsing module 204 is further configured to determine a first clock signal and a first control signal corresponding to each row of pixel units within the display partition based on the base refresh frequency of the display panel and the first refresh frequency, and use the first clock signal and the first control signal as the parsed partition control instruction; wherein, the first control signal can change the period of the pulse signal in the first clock signal so that the refresh frequency of the display partition is equal to the first refresh frequency under the control of the first clock signal and the first control signal.

[0119] In some embodiments, the parsing module 204, which analyzes the display panel based on its base refresh frequency and the first refresh frequency, is further configured to determine the first clock signal based on the base refresh frequency and the first control signal based on the first refresh frequency.

[0120] In some embodiments, the first clock signal includes a first sub-clock signal and a second sub-clock signal. When the first control signal is at a first level, the first sub-clock signal is at a first level and the second sub-clock signal is at a second level.

[0121] In some embodiments, the first clock signal includes a first sub-clock signal and a second sub-clock signal. When the first control signal is at a second level, the first sub-clock signal is at a first level, and the second sub-clock signal is at a second level.

[0122] In some embodiments, the parsed partition control instructions further include a start row identifier and an end row identifier corresponding to each display partition; the parsing module 204 is further configured to send the start row identifier, the end row identifier, the first clock signal, and the first control signal to the gate driving circuit, so that the gate driving circuit controls the switching on or off of each pixel unit in the display partition determined by the start row identifier and the end row identifier according to the first clock signal and the first control signal.

[0123] In some embodiments, the parsed partition control instructions further include display data corresponding to each display partition; the parsing module 204 is also configured to send the display data corresponding to each display partition to the source drive unit, so that when the pixel unit switch in each display partition is turned on, the source drive unit inputs the corresponding display data to the pixel unit.

[0124] In some embodiments, before parsing the partition control instructions, a detection module is further included, configured to detect the partition control instructions and, in response to determining that there is an anomaly in the partition control instructions, to feed back anomaly information related to the partition control instructions to the control unit.

[0125] For ease of description, the above devices are described in terms of function, divided into various modules. Of course, in implementing this application, the functions of each module can be implemented in one or more software and / or hardware.

[0126] The apparatus of the above embodiments is used to implement the corresponding display control method in any of the foregoing embodiments, and has the beneficial effects of the corresponding method embodiments, which will not be repeated here.

[0127] Based on the same inventive concept, corresponding to the methods of any of the above embodiments, this application also provides an electronic device, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the program to implement the display control method described in any of the above embodiments.

[0128] Figure 12 This embodiment illustrates a more specific hardware structure of an electronic device, which may include a processor 1010, a memory 1020, an input / output interface 1030, a communication interface 1040, and a bus 1050. The processor 1010, memory 1020, input / output interface 1030, and communication interface 1040 are interconnected internally via the bus 1050.

[0129] The processor 1010 can be implemented using a general-purpose CPU (Central Processing Unit), microprocessor, application-specific integrated circuit (ASIC), or one or more integrated circuits, and is used to execute relevant programs to implement the technical solutions provided in the embodiments of this specification.

[0130] The memory 1020 can be implemented in the form of ROM (Read Only Memory), RAM (Random Access Memory), static storage device, dynamic storage device, etc. The memory 1020 can store the operating system and other applications. When the technical solutions provided in the embodiments of this specification are implemented by software or firmware, the relevant program code is stored in the memory 1020 and is called and executed by the processor 1010.

[0131] The input / output interface 1030 is used to connect input / output modules to realize information input and output. Input / output modules can be configured as components within the device (not shown in the figure) or externally connected to the device to provide corresponding functions. Input devices may include keyboards, mice, touchscreens, microphones, various sensors, etc., while output devices may include displays, speakers, vibrators, indicator lights, etc.

[0132] The communication interface 1040 is used to connect a communication module (not shown in the figure) to enable communication between this device and other devices. The communication module can communicate via wired means (such as USB, Ethernet cable, etc.) or wireless means (such as mobile network, WIFI, Bluetooth, etc.).

[0133] Bus 1050 includes a pathway for transmitting information between various components of the device, such as processor 1010, memory 1020, input / output interface 1030, and communication interface 1040.

[0134] It should be noted that although the above-described device only shows the processor 1010, memory 1020, input / output interface 1030, communication interface 1040, and bus 1050, in specific implementations, the device may also include other components necessary for normal operation. Furthermore, those skilled in the art will understand that the above-described device may only include the components necessary for implementing the embodiments of this specification, and not necessarily all the components shown in the figures.

[0135] The electronic devices described above are used to implement the corresponding display control methods in any of the foregoing embodiments and have the beneficial effects of the corresponding method embodiments, which will not be repeated here.

[0136] Based on the same inventive concept, corresponding to the methods of any of the above embodiments, this application also provides a non-transitory computer-readable storage medium that stores computer instructions for causing the computer to execute the display control method as described in any of the above embodiments.

[0137] The computer-readable medium of this embodiment includes permanent and non-permanent, removable and non-removable media, and information storage can be implemented by any method or technology. Information can be computer-readable instructions, data structures, program modules, or other data. Examples of computer storage media include, but are not limited to, phase-change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technologies, CD-ROM, digital versatile optical disc (DVD) or other optical storage, magnetic tape, magnetic magnetic disk storage or other magnetic storage devices, or any other non-transfer medium that can be used to store information accessible by a computing device.

[0138] The computer instructions stored in the storage medium of the above embodiments are used to cause the computer to execute the display control method as described in any of the above embodiments, and have the beneficial effects of the corresponding method embodiments, which will not be repeated here.

[0139] Based on the same concept, corresponding to any of the above embodiments, this application also provides a computer program product, including computer program instructions, which, when run on a computer, cause the computer to perform the method described in any of the above embodiments, and have the beneficial effects of the corresponding method embodiments, which will not be repeated here.

[0140] Those skilled in the art should understand that the discussion of any of the above embodiments is merely exemplary and is not intended to imply that the scope of this application is limited to these examples; under the concept of this application, the technical features of the above embodiments or different embodiments can also be combined, the steps can be implemented in any order, and there are many other variations of different aspects of the embodiments of this application as described above, which are not provided in detail for the sake of brevity.

[0141] Additionally, to simplify the description and discussion, and to avoid obscuring the embodiments of this application, the well-known power / ground connections to integrated circuit (IC) chips and other components may or may not be shown in the provided drawings. Furthermore, the apparatus may be shown in block diagram form to avoid obscuring the embodiments of this application, and this also takes into account the fact that the details of the implementation of these block diagram apparatuses are highly dependent on the platform on which the embodiments of this application will be implemented (i.e., these details should be fully understood by those skilled in the art). While specific details (e.g., circuits) have been set forth to describe exemplary embodiments of this application, it will be apparent to those skilled in the art that the embodiments of this application can be implemented without these specific details or with variations thereof. Therefore, these descriptions should be considered illustrative rather than restrictive.

[0142] Although this application has been described in conjunction with specific embodiments thereof, many substitutions, modifications, and variations of these embodiments will be apparent to those skilled in the art from the foregoing description. For example, other memory architectures (e.g., dynamic RAM (DRAM)) may be used with the embodiments discussed.

[0143] The embodiments of this application are intended to cover all such substitutions, modifications, and variations that fall within the broad scope of this application. Therefore, any omissions, modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the embodiments of this application should be included within the protection scope of this application.

Claims

1. A display device, characterized by comprising: The display panel comprises: a control unit configured to send a partition control instruction to a timing driving unit in response to the display panel being in a partition refresh state; the partition control instruction comprises control information related to a refresh frequency of each display partition of the display panel; a timing driving unit electrically coupled to the control unit and configured to receive the partition control instruction, analyze the partition control instruction, and send the analyzed partition control instruction to a source driving unit; the partition control instruction comprises a first refresh frequency corresponding to each display partition; according to a base refresh frequency of the display panel and the first refresh frequency, a first clock signal and a first control signal corresponding to each row of pixel units in the display partition are determined, and the first clock signal and the first control signal are taken as the analyzed partition control instruction; the first control signal can change the period of a pulse signal in the first clock signal, so that under the control of the first clock signal and the first control signal, the refresh frequency of the display partition is equal to the first refresh frequency; the first clock signal comprises a first sub-clock signal and a second sub-clock signal, and when the first control signal is at a second level, the first sub-clock signal is at a first level and the second sub-clock signal is at a second level; a source driving unit electrically coupled to the timing driving unit and configured to receive the analyzed partition control instruction and forward the analyzed partition control instruction to a gate driving circuit; a gate driving circuit electrically coupled to the source driving unit and configured to receive the analyzed partition control instruction and control the display panel based on the analyzed partition control instruction; a display panel connected to the control unit, the source driving unit, and the gate driving circuit, and configured to display a picture in each display partition according to the control information; wherein the source driving unit and the gate driving circuit control the display panel to display based on the analyzed partition control instruction.

2. The display device according to claim 1, wherein The timing driving unit is configured to: determine the first clock signal according to the base refresh frequency and determine the first control signal according to the first refresh frequency.

3. The display device according to claim 1, wherein The first clock signal comprises a first sub-clock signal and a second sub-clock signal, and when the first control signal is at a first level, the first sub-clock signal is at a first level and the second sub-clock signal is at a second level.

4. The display device according to claim 1, wherein The analyzed partition control instruction further comprises a start row identifier and an end row identifier corresponding to each display partition; the source driving unit is configured to: send the start row identifier, the end row identifier, the first clock signal, and the first control signal to the gate driving circuit, so that the gate driving circuit controls each pixel unit in the display partition determined by the start row identifier and the end row identifier to be switched on or off according to the first clock signal and the first control signal.

5. The display device according to claim 1, wherein The analyzed partition control instruction further comprises display data corresponding to each display partition; the timing driving unit is configured to: The display data corresponding to each display partition is sent to the source driving unit, so that the source driving unit inputs the corresponding display data to the pixel unit when the pixel unit switch in each display partition is turned on.

6. The display device according to claim 1, wherein Before analyzing the partition control instruction, the timing driving unit is configured to: detect the partition control instruction, and in response to determining that the partition control instruction is abnormal, feed back abnormal information related to the partition control instruction to the control unit.

7. A display control method characterized by comprising: The display device of any one of claims 1-6, comprising: receiving a partition control instruction issued by a control unit connected to the timing driving unit; wherein the partition control instruction is issued by the control unit when the display panel is in a partition refresh state, and the partition control instruction includes control information related to the refresh frequency of each display partition of the display panel; analyzing the partition control instruction, sending the analyzed partition control instruction to a source driving unit connected to the timing driving unit, and sending the analyzed partition control instruction to a gate driving circuit connected to the source driving unit through the source driving unit, so that the source driving unit and the gate driving circuit control the display panel to display based on the analyzed partition control instruction, so that each display partition displays a picture according to the control information.

8. An electronic device comprising a memory, a processor, and a computer program stored on the memory and running on the processor, characterized in that, The processor implements the method of claim 7 when executing the program.

9. A non-transitory computer-readable storage medium storing computer instructions, wherein, The computer instructions are used to make the computer execute the method of claim 7.

10. A computer program product comprising computer program instructions, characterised in that, When the computer program instructions run on the computer, the computer executes the method of claim 7.

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