Power module and power device having the same

Abstract

The present invention provides a power module and a power device having the same, the power module includes a liner and a plurality of chips, a first conductive structure and a second conductive structure are arranged on the liner, the first conductive structure and the second conductive structure are both axisymmetric structures, the axes of symmetry of the first conductive structure and the second conductive structure extend along a first direction, a plurality of chips are arranged on the first conductive structure and the second conductive structure, and the plurality of chips on the first conductive structure and the plurality of chips on the second conductive structure are symmetrically arranged on both sides of the axis of symmetry. The technical solution provided by the present application can solve the problem that the chip layout position of the power module in the related art is relatively concentrated.

Description

Technical Field

[0001] The present invention relates to the technical field of power devices, and in particular to a power module and a power device having the same. Background Art

[0002] With the continuous growth of global energy demand and increasing concern for the environment, high-efficiency and high-reliability power conversion and control technologies have become essential. As the core components in power electronics systems, power devices play an important role in power conversion, distribution and control. These devices are widely used in industrial motor drives, power management, renewable energy systems, electric vehicles and various consumer electronic devices. Power devices refer to electronic components that can process and control electrical energy. They are used in high-power circuits and can carry large currents and voltages. They are used to convert electrical energy from one form to another or transmit electrical energy to other devices.

[0003] The fully controlled device power field effect transistor (MOSFET) is considered to be an ideal switching device due to its advantages such as high input impedance, fast switching speed and low driving requirements. However, the power handling capacity of traditional silicon-based power MOSFET devices in the high voltage field is limited by the internal resistance of the chip. How to reduce the chip on-resistance and increase the chip breakdown voltage is the research focus of the next generation of power MOSFET devices. In related technologies, wide bandgap semiconductor materials represented by silicon carbide materials are considered to be ideal materials for the next generation of high-voltage power devices due to their excellent material properties: wide bandgap width, high critical breakdown field strength, and high saturated carrier mobility. Among all silicon carbide devices, silicon carbide MOSFET has the advantages of low on-resistance, fast switching speed, and high withstand voltage, and has gradually replaced silicon-based MOSFET and IGBT devices. Due to the low current level of a single chip, multiple chips are generally packaged in parallel to form a high-efficiency module in high-current applications.

[0004] However, in the related art, in the existing power module layout mode, the layout form is generally a planar layout form, and the chip layout position is relatively concentrated. Summary of the invention

[0005] The present invention provides a power module and a power device having the same, so as to solve the problem that the chip layout position of the power module in the related art is relatively concentrated.

[0006] According to one aspect of the present invention, a power module is provided, the power module comprising a liner and a plurality of chips, a first conductive structure and a second conductive structure are arranged on the liner, the first conductive structure and the second conductive structure are both axisymmetric structures, the axes of symmetry of the first conductive structure and the second conductive structure extend along a first direction, a plurality of chips are arranged on the first conductive structure and the second conductive structure, and the plurality of chips on the first conductive structure and the plurality of chips on the second conductive structure are symmetrically arranged on both sides of the axis of symmetry.

[0007] Furthermore, the first conductive structure includes a first sub-conductive layer and two second sub-conductive layers, the first sub-conductive layer and the second sub-conductive layer are arranged at intervals, the axis of the first sub-conductive layer is coaxial with the axis of symmetry, the two second sub-conductive layers are respectively located on both sides of the first sub-conductive layer in a second direction perpendicular to the first direction, chips are arranged on the two second sub-conductive layers, the upper surfaces of the chips on the two second sub-conductive layers are conductively connected to the first sub-conductive layer, and the first sub-conductive layer is conductively connected to the second conductive structure.

[0008] Furthermore, the first sub-conductive layer includes a first segment and a second segment which are perpendicular to each other, the axis of the first segment is coaxial with the axis of symmetry, one end of the first segment is connected to the middle of the second segment, the second segment is arranged between the first segment and the second conductive structure, and the two second sub-conductive layers are respectively located on both sides of the first segment in the second direction, the upper surfaces of the chips on the two second sub-conductive layers are conductively connected to the first segment, and the second segment is conductively connected to the second conductive structure.

[0009] Furthermore, the second sub-conductive layer is a rectangular structure, which includes a first side and a second side perpendicular to each other, the first side is arranged away from the second segment and is flush with an end of the first segment away from the second segment, and the second side is arranged away from the first segment and is flush with an end of the second segment.

[0010] Furthermore, the second conductive structure includes a third sub-conductive layer and a fourth sub-conductive layer, the third sub-conductive layer has a notch at one end facing the first sub-conductive layer in the first direction, the fourth sub-conductive layer extends into the notch, the axis of the fourth sub-conductive layer is coaxial with the axis of symmetry, chips are provided at positions on both sides of the notch in the third sub-conductive layer in the second direction, the first sub-conductive layer is conductively connected to the third sub-conductive layer, and the upper surface of the chip on the third sub-conductive layer is conductively connected to the fourth sub-conductive layer.

[0011] Furthermore, the third sub-conductive layer includes a third segment, a fourth segment and a fifth segment, the third segment and the fifth segment are located on the same side of the fourth segment, the third segment and the fifth segment are respectively connected to two ends of the fourth segment, the side wall of the third segment, the side wall of the fourth segment and the side wall of the fifth segment together form a gap, and the fourth segment is arranged at an end of the third segment away from the first conductive structure.

[0012] Further, one end of the third segment away from the fourth segment, one end of the fifth segment away from the fourth segment, and one end of the fourth sub-conductive layer away from the fourth segment are flush with each other.

[0013] Furthermore, the gap includes a first groove segment, a second groove segment and a third groove segment which are connected in sequence, an end of the first groove segment away from the second groove segment forms a mouth of the gap, the groove width of the first groove segment is greater than the groove width of the third groove segment, the groove width of the second groove segment gradually decreases in the direction from the first groove segment to the third groove segment, and the shape of the fourth sub-conductive layer is adapted to the shape of the gap.

[0014] Furthermore, the power module also includes a first interconnection component, which includes: a main body segment, the lower surface of which is conductively connected to the first sub-conductive layer or the fourth sub-conductive layer; a first interface interconnection segment, which is located on the side of the main body segment and connected to the main body segment, and the lower surface of the first interface interconnection segment is conductively connected to the upper surface of one of the two symmetrically arranged chips; a second interface interconnection segment, which is located on the side of the main body segment and connected to the main body segment, and the lower surface of the second interface interconnection segment is conductively connected to the upper surface of the other of the two symmetrically arranged chips.

[0015] Further, at least one of the lower surface of the main body segment, the lower surface of the first interface interconnection segment, and the lower surface of the second interface interconnection segment is provided with a wetting groove.

[0016] Further, the first interconnection member also includes a first connecting section, which is located on the side of the main body section, and the two ends of the first connecting section are respectively connected to the main body section and the first interface interconnection section, and the lower surface of the first connecting section is higher than the lower surface of the main body section and / or the lower surface of the first interface interconnection section; the first interconnection member also includes a second connecting section, which is located on the side of the main body section, and the two ends of the second connecting section are respectively connected to the main body section and the second interface interconnection section, and the lower surface of the second connecting section is higher than the lower surface of the main body section and / or the lower surface of the second interface interconnection section.

[0017] Furthermore, the power module also includes a second interconnection component, which includes: a third interface interconnection segment, the lower surface of which is conductively connected to the third sub-conductive layer; a fourth interface interconnection segment, the lower surface of which is conductively connected to the first sub-conductive layer; and a third connecting segment, the two ends of which are respectively connected to the third interface interconnection segment and the fourth interface interconnection segment, and the lower surface of the third connecting segment is higher than the lower surface of the third interface interconnection segment and / or the lower surface of the fourth interface interconnection segment.

[0018] Furthermore, the second interconnection component also includes a fourth connecting segment, the third interface interconnection segment, the fourth interface interconnection segment and the third connecting segment constitute an interconnection main segment, the second interconnection component includes two interconnection main segments, both ends of the fourth connecting segment are respectively connected to the two interconnection main segments, and the lower surface of the fourth connecting segment is conductively connected to the first sub-conductive layer.

[0019] Furthermore, the power module also includes a control component, which includes a mounting substrate and a resistor element arranged on the mounting substrate; wherein a mounting position is arranged on the surface of the first conductive structure and / or the second conductive structure, the mounting position is located between two adjacent chips, one of the surfaces of the mounting substrate in its thickness direction is connected to the mounting position, and the resistor element is located on the other surface of the mounting substrate in its thickness direction.

[0020] Further, the mounting substrate includes a substrate body and a first metal layer arranged on the substrate body, the substrate body is connected to the mounting position, and the resistor element is arranged on the first metal layer; or, the mounting substrate includes a substrate body and a first metal layer and a second metal layer arranged on the substrate body, the first metal layer and the second metal layer are respectively located on both sides of the substrate body, the resistor element is arranged on the first metal layer, and the second metal layer is connected to the mounting position.

[0021] Further, the resistance element includes a gate resistance.

[0022] According to another aspect of the present invention, a power device is provided, and the power device includes the power module provided above.

[0023] Furthermore, the power device includes two power modules, and the two power modules are spaced apart and symmetrically arranged in the second direction.

[0024] Furthermore, the power device also includes a power terminal, which includes a terminal pin, a first plate segment, a second plate segment and a lead-out segment connected in sequence, the terminal pin and the second plate segment are respectively arranged at an angle to the first plate segment, the terminal pin and the second plate segment extend in opposite directions, and the lead-out segment is arranged at an end of the second plate segment away from the first plate segment.

[0025] The technical solution of the present invention is applied, and the power module includes a liner and a plurality of chips. The liner is provided with a first conductive structure and a second conductive structure, and the first conductive structure and the second conductive structure are both axisymmetric structures, and the axes of symmetry of the first conductive structure and the second conductive structure extend along the first direction. The first conductive structure and the second conductive structure are provided with a plurality of chips, and the plurality of chips on the first conductive structure and the plurality of chips on the second conductive structure are symmetrically arranged on both sides of the axis of symmetry. With the above structure, by setting the first conductive structure and the second conductive structure as axisymmetric structures, the chips can be arranged symmetrically, so that the interconnection length between the upper surface of the chip and the conductive structure can be equal. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] The drawings constituting a part of the present application are used to provide a further understanding of the present invention. The exemplary embodiments of the present invention and their descriptions are used to explain the present invention and do not constitute an improper limitation of the present invention. In the drawings:

[0027] Figure 1 A schematic diagram of a part of the structure of a power device provided in an embodiment of the present invention without power terminals is shown;

[0028] Figure 2 A top view of a partial structure of a power device provided with power terminals according to an embodiment of the present invention is shown;

[0029] Figure 3 Shows Figure 1 A schematic structural diagram of a first interconnection member in;

[0030] Figure 4 Shows Figure 1 A schematic structural diagram of the first interconnection member from another perspective;

[0031] Figure 5 Shows Figure 1 A schematic structural diagram of a second interconnection member in;

[0032] Figure 6 Shows Figure 1 Exploded diagram of the control components in;

[0033] Figure 7 Shows Figure 1 A top view of the control assembly in FIG.

[0034] Figure 8 A partial structural schematic diagram of a power device provided with power terminals according to an embodiment of the present invention is shown;

[0035] Fig. 9 A side view of a partial structure of a power device provided with a power terminal according to an embodiment of the present invention is shown;

[0036] Fig.10 A front view of a partial structure of a power device provided with power terminals according to an embodiment of the present invention is shown.

[0037] The above drawings include the following reference numerals:

[0038] 10. lining plate; 11. first conductive structure; 111. first sub-conductive layer; 1111. first section; 1112. second section; 112. second sub-conductive layer; 1121. first side edge; 1122. second side edge; 12. second conductive structure; 121. third sub-conductive layer; 1211. notch; 12111. first slot section; 12112. second slot section; 12113. third slot section; 1212. third section; 1213. fourth section; 1214. fifth section; 122. fourth sub-conductive layer; 13. driving signal connection conductive layer; 14. first lining plate; 15. second lining plate;

[0039] 20. Chip;

[0040] 30. first interconnection member; 31. main body section; 32. first interface interconnection section; 33. second interface interconnection section; 34. wetting groove; 35. first connection section; 36. second connection section; 37. connection groove;

[0041] 40. second interconnection member; 41. third interface interconnection section; 42. fourth interface interconnection section; 43. third connection section; 44. fourth connection section;

[0042] 50, control component; 51, mounting substrate; 511, substrate body; 512, first metal layer; 513, second metal layer; 52, resistor element;

[0043] 60, power terminal; 61, terminal pin; 62, first plate section; 63, second plate section; 64, lead section; 65, first terminal; 66, second terminal; 67, third terminal;

[0044] 70. Power module. DETAILED DESCRIPTION

[0045] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, rather than all the embodiments. The following description of at least one exemplary embodiment is actually only illustrative and is by no means intended to limit the present invention and its application or use. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0046] like Figures 1 to 10As shown, an embodiment of the present invention provides a power module, which includes a liner 10 and a plurality of chips 20, wherein a first conductive structure 11 and a second conductive structure 12 are arranged on the liner 10, wherein the first conductive structure 11 and the second conductive structure 12 are both axisymmetric structures, and the axes of symmetry of the first conductive structure 11 and the second conductive structure 12 extend along a first direction, and a plurality of chips 20 are arranged on the first conductive structure 11 and the second conductive structure 12, and the plurality of chips 20 on the first conductive structure 11 and the plurality of chips 20 on the second conductive structure 12 are symmetrically arranged on both sides of the axis of symmetry.

[0047] By using the power module provided in this embodiment, the first conductive structure 11 and the second conductive structure 12 are set as axisymmetric structures, so that the chip 20 can be symmetrically arranged, the symmetry axis of the multiple chips 20 on the first conductive structure 11 is the same as the symmetry axis of the first conductive structure 11 and the second conductive structure 12, and the symmetry axis of the multiple chips 20 on the second conductive structure 12 is the same as the symmetry axis of the first conductive structure 11 and the second conductive structure 12, so that the interconnection length between the upper surface of the chip 20 and the conductive structure can be equal and of moderate length.

[0048] In the related art, the chip layout is relatively concentrated, resulting in different and generally longer interconnection lengths between the chip upper surface and the upper copper layer (conductive structure).

[0049] It should be noted that the lining plate 10 is provided with a first conductive structure 11 and a second conductive structure 12, including the following two structures: the first is that the lining plate 10 is an integrated structure, and the integrated lining plate 10 is provided with the first conductive structure 11 and the second conductive structure 12; the second is that the lining plate 10 is a split structure, that is, the lining plate 10 includes a first lining plate 14 and a second lining plate 15 which are spaced apart, the first lining plate 14 is provided with the first conductive structure 11, and the second lining plate 15 is provided with the second conductive structure 12.

[0050] In this embodiment, the lining plate 10 is of the second structure and includes two first lining plates 14 and two second lining plates 15 .

[0051] like Figure 1 and Figure 2As shown, the first conductive structure 11 includes a first sub-conductive layer 111 and two second sub-conductive layers 112, the first sub-conductive layer 111 and the second sub-conductive layer 112 are arranged at intervals, the axis of the first sub-conductive layer 111 is coaxial with the axis of symmetry, the two second sub-conductive layers 112 are respectively located on both sides of the first sub-conductive layer 111 in a second direction perpendicular to the first direction, the two second sub-conductive layers 112 are provided with a chip 20, the upper surfaces of the chips 20 on the two second sub-conductive layers 112 are conductively connected to the first sub-conductive layer 111, and the first sub-conductive layer 111 is conductively connected to the second conductive structure 12. By separating the two second sub-conductive layers 112 with the first sub-conductive layer 111 and providing the chips 20 on the two second sub-conductive layers 112, the spacing between the chips 20 can be further increased, so that the chips 20 are arranged as dispersedly as possible, and the heat dissipation performance is improved.

[0052] The first direction is the length direction of the power module, and the second direction is the width direction of the power module.

[0053] like Figure 1 As shown, the first sub-conductive layer 111 includes a first segment 1111 and a second segment 1112 which are perpendicular to each other, the axis of the first segment 1111 is coaxial with the axis of symmetry, one end of the first segment 1111 is connected to the middle of the second segment 1112, the second segment 1112 is arranged between the first segment 1111 and the second conductive structure 12, the two second sub-conductive layers 112 are respectively located on both sides of the first segment 1111 in the second direction, the upper surfaces of the chips 20 on the two second sub-conductive layers 112 are conductively connected to the first segment 1111, and the second segment 1112 is conductively connected to the second conductive structure 12. With the above structure, the perpendicular first segment 1111 and the second segment 1112 together form a T-shaped structure.

[0054] Specifically, the first section 1111 is used to separate the two second sub-conductive layers 112, so as to facilitate the dispersed arrangement of the chips 20. In addition, the second section 1112 is disposed between the first section 1111 and the second conductive structure 12, and then the second section 1112 is conductively connected to the second conductive structure 12, so as to reduce the distance between the first sub-conductive layer 111 and the second conductive structure 12, and facilitate the conductive connection between the first sub-conductive layer 111 and the second conductive structure 12.

[0055] It should be noted that the ratio of the width of the second sub-conductive layer 112 to the width of the first section 1111 is between 1.5 and 1.8. The lower limit (1.5) of the value ensures the distance between the edge of the chip 20 and the edge of the second sub-conductive layer 112 in the second direction, and the lower limit (1.5) of the value ensures the distance between the edge of the main section 31 of the first interconnection member 30 and the edge of the first section 1111 in the second direction, so that there is a minimum distance in the second direction that meets the insulation requirements. The upper limit (1.8) of the value enables the main section 31 of the first interconnection member 30 to have a sufficient width (dimension along the second direction) on the basis of (precondition that) the edge of the main section 31 of the first interconnection member 30 and the edge of the first section 1111 have a minimum distance in the second direction that meets the insulation requirements, so as to meet the requirements of reliable interface interconnection, and at the same time have a relatively ideal heat dissipation effect (because the connection area with the first section 1111 is large).

[0056] The width of the first segment 1111 and the width of the second sub-conductive layer 112 are both dimensions in the second direction.

[0057] like Figure 1 and Figure 2 As shown, the second sub-conductive layer 112 is a rectangular structure, which includes a first side 1121 and a second side 1122 that are perpendicular to each other, the first side 1121 is arranged away from the second section 1112 and is flush with an end of the first section 1111 away from the second section 1112, and the second side 1122 is arranged away from the first section 1111 and is flush with the end of the second section 1112. With the above structure, the appearance of the first conductive structure 11 is more regular, which facilitates the uniform and dispersed arrangement of the chips 20.

[0058] It should be noted that the first side 1121 is arranged away from the second section 1112 and is flush with the end of the first section 1111 away from the second section 1112, wherein “the first side 1121 is arranged away from the second section 1112” means that the side of the four sides of the rectangular structure that is farthest from the second section 1112 is the first side 1121.

[0059] It should be noted that the second side 1122 is arranged away from the first section 1111 and is flush with the end of the second section 1112 , wherein “the second side 1122 is arranged away from the first section 1111 ” means that the side of the four sides of the rectangular structure that is farthest from the first section 1111 is the second side 1122 .

[0060] In this embodiment, the second sub-conductive layer 112 is a rectangular structure, which means that the second sub-conductive layer 112 is rectangular in the plane as a whole, but due to manufacturing and other reasons, its four corners are “rounded”.

[0061] like Figure 1 and Figure 2 As shown, in this embodiment, the second conductive structure 12 includes a third sub-conductive layer 121 and a fourth sub-conductive layer 122, the third sub-conductive layer 121 has a notch 1211 at one end facing the first sub-conductive layer 111 in the first direction, the fourth sub-conductive layer 122 extends into the notch 1211, the axis of the fourth sub-conductive layer 122 is coaxial with the axis of symmetry, the third sub-conductive layer 121 is provided with chips 20 at positions on both sides of the notch 1211 in the second direction, the first sub-conductive layer 111 is conductively connected to the third sub-conductive layer 121, and the upper surface of the chip 20 on the third sub-conductive layer 121 is conductively connected to the fourth sub-conductive layer 122. The fourth sub-conductive layer 122 is used to separate the chips 20 on the third sub-conductive layer 121, so that the spacing between the chips 20 can be further increased, so that the chips 20 are arranged as dispersedly as possible, and the heat dissipation performance is improved.

[0062] In this embodiment, the third sub-conductive layer 121 includes a third section 1212, a fourth section 1213 and a fifth section 1214. The third section 1212 and the fifth section 1214 are located on the same side of the fourth section 1213. The third section 1212 and the fifth section 1214 are respectively connected to the two ends of the fourth section 1213. The side walls of the third section 1212, the fourth section 1213 and the fifth section 1214 together form a gap 1211. The fourth section 1213 is arranged at an end of the third section 1212 away from the first conductive structure 11. With the above structure, the third section 1212, the fourth section 1213 and the fifth section 1214 together form a U-shaped structure. The two legs of the U-shaped structure are arranged opposite to the second section 1112 of the T-shaped structure, which can further improve the symmetry of the power module.

[0063] It should be noted that one end of the third segment 1212 away from the fourth segment 1213, one end of the fifth segment 1214 away from the fourth segment 1213, and one end of the fourth sub-conductive layer 122 away from the fourth segment 1213 are flush. With the above structure, the shape of the second conductive structure 12 is more regular, which facilitates the uniform and dispersed arrangement of the chips 20.

[0064] like Figure 1 As shown, the gap 1211 includes a first slot segment 12111, a second slot segment 12112 and a third slot segment 12113 which are connected in sequence, and the end of the first slot segment 12111 away from the second slot segment 12112 forms the mouth of the gap 1211, the slot width of the first slot segment 12111 is greater than the slot width of the third slot segment 12113, and the slot width of the second slot segment 12112 gradually decreases in the direction from the first slot segment 12111 to the third slot segment 12113, and the shape of the fourth sub-conductive layer 122 is adapted to the shape of the gap 1211.

[0065] In this embodiment, the ratio of the width of the third segments 1212 located on both sides of the third slot segment 12113 to the width of the fourth sub-conductive layer 122 located in the third slot segment 12113 is between 1.5 and 1.8. The above width ratio has a similar effect to that of "the ratio of the width of the second sub-conductive layer 112 to the width of the first segment 1111 is between 1.5 and 1.8", which will not be described in detail.

[0066] The power device further includes a power terminal 60 , and the power terminal 60 includes a terminal pin 61 . The power terminal 60 is connected to the conductive structure via the terminal pin 61 .

[0067] In this embodiment, by making the slot width of the first slot segment 12111 greater than the slot width of the third slot segment 12113, the slot width of the second slot segment 12112 gradually decreases in the direction from the first slot segment 12111 to the third slot segment 12113, the fourth sub-conductive layer 122 has a sufficient width, and thus the power terminal 60 correspondingly connected to the fourth sub-conductive layer 122 has a sufficient connection surface.

[0068] like Figures 8 to 10 As shown, the power device further includes a power terminal 60, which includes a terminal pin 61, a first plate segment 62, a second plate segment 63, and a lead-out segment 64 connected in sequence. In this embodiment, the power terminal 60 includes a first terminal 65, a second terminal 66, and a third terminal 67, and the first terminal 65, the second terminal 66, and the third terminal 67 all include a terminal pin 61, a first plate segment 62, a second plate segment 63, and a lead-out segment 64 connected in sequence.

[0069] Specifically, the first slot section 12111 is wider than the third slot section 12113, which is intended to allow the terminal foot 61 of the second terminal 66 to have a larger width (the width of the fourth sub-conductive layer 122 at the notch 1211 minus the distance required for insulation is the maximum width of the terminal foot under a given conductive layer width). The increase in the width of the terminal foot is beneficial to: 1. Increasing the reliability of the interconnection between the terminal foot and the conductive layer (a. The interface interconnection area is increased; b. If solder interconnection is used, the larger width also allows a more suitable wetting groove design); 2. The increase in the width of the terminal foot leads to an increase in the cross-sectional area of ​​the corresponding first plate section and second plate section of the terminal, thereby increasing the current carrying capacity of the terminal.

[0070] In other embodiments, if the current is small, so that the width of the terminal pin 61 is appropriately reduced, the slot width of the first slot section 12111 can be equal to the slot width of the third slot section 12113 .

[0071] like Figure 3 and Figure 4As shown, the power module further includes a first interconnection member 30, which includes a main body section 31, a first interface interconnection section 32, and a second interface interconnection section 33. The lower surface of the main body section 31 is conductively connected to the first sub-conductive layer 111 or the fourth sub-conductive layer 122. The first interface interconnection section 32 is located at the side of the main body section 31 and connected to the main body section 31, and the lower surface of the first interface interconnection section 32 is conductively connected to the upper surface of one of the two symmetrically arranged chips 20. The second interface interconnection section 33 is located at the side of the main body section 31 and connected to the main body section 31, and the lower surface of the second interface interconnection section 33 is conductively connected to the upper surface of the other of the two symmetrically arranged chips 20. Since the first interconnection member 30 connects at least two chips, it can reduce the number of connectors in the related art, reduce the space occupied in the power module, improve the space utilization, and facilitate the arrangement of devices.

[0072] It should be noted that in the related art, the power current conduction between the components inside the power module relies on the metal interconnection interface set on the components and the connectors connecting the metal interconnection interfaces. For example, the interconnection between the upper surface of the chip and the upper copper layer. However, the existing connectors are mostly used to realize the electrical connection of two interconnection interfaces. When there are multiple pairs of interfaces that need to be interconnected, such as when there are multiple pairs of chips on a liner, multiple connectors are required, which will occupy a larger space in the module, resulting in low device space utilization and placing greater restrictions on device layout.

[0073] Specifically, at least one of the lower surface of the main body section 31, the lower surface of the first interface interconnection section 32, and the lower surface of the second interface interconnection section 33 is provided with a wetting groove 34. The wetting groove 34 can be used to wet the solder to form a solder layer with a concave upper surface, which increases the wetting boundary length of the interconnection material compared to the case where there is no groove at the interconnection interface, thereby improving the strength of the interface connection.

[0074] It should be noted that the wetting groove 34 extends along the length direction of the first interconnection member 30, so that the wetting groove 34 on the first interconnection member 30 has a larger length, thereby making the first interconnection member 30 and the chip have a larger wetting boundary length, thereby improving the strength of the interface connection.

[0075] like Figure 3As shown, the first interconnection member 30 further includes a first connection segment 35, which is located at the side of the main body segment 31, and the two ends of the first connection segment 35 are respectively connected to the main body segment 31 and the first interface interconnection segment 32, and the lower surface of the first connection segment 35 is higher than the lower surface of the main body segment 31 and / or the lower surface of the first interface interconnection segment 32. The first interconnection member 30 further includes a second connection segment 36, which is located at the side of the main body segment 31, and the two ends of the second connection segment 36 are respectively connected to the main body segment 31 and the second interface interconnection segment 33, and the lower surface of the second connection segment 36 is higher than the lower surface of the main body segment 31 and / or the lower surface of the second interface interconnection segment 33. The main body segment 31 and the first interface interconnection segment 32 are connected by the first connection segment 35, and the main body segment 31 and the second interface interconnection segment 33 are connected by the second connection segment 36, which has the advantages of simple structure and easy processing.

[0076] In this embodiment, the first connecting section 35 and the second connecting section 36 are both provided with connecting grooves 37, which can effectively increase the flexibility of the first interconnection member 30, reduce the maximum interlayer stress when relative displacement occurs between different interconnection interfaces, and help improve the reliability of the interconnection interface.

[0077] Specifically, the connection groove 37 is connected to the wetting groove 34, which is convenient for processing.

[0078] Since the chip is disposed on the substrate, the main body section 31 is connected to the conductive structure of the substrate, and the interface interconnection section is connected to the chip, so that there is a height difference between the main body section 31 and the interface interconnection section. Generally speaking, the lower surface of the interface interconnection section is higher than the lower surface of the main body section 31.

[0079] like Figure 5 As shown, in this embodiment, the power module further includes a second interconnection member 40, and the second interconnection member 40 includes a third interface interconnection segment 41, a fourth interface interconnection segment 42, and a third connection segment 43. The lower surface of the third interface interconnection segment 41 is conductively connected to the third sub-conductive layer 121. The lower surface of the fourth interface interconnection segment 42 is conductively connected to the first sub-conductive layer 111. Both ends of the third connection segment 43 are respectively connected to the third interface interconnection segment 41 and the fourth interface interconnection segment 42, and the lower surface of the third connection segment 43 is higher than the lower surface of the third interface interconnection segment 41 and / or the lower surface of the fourth interface interconnection segment 42.

[0080] The second interconnection member 40 can be used to achieve a conductive connection between the first sub-conductive layer 111 and the third sub-conductive layer 121 , thereby achieving a conductive connection between the first conductive structure 11 and the second conductive structure 12 .

[0081] like Figure 5As shown, the second interconnection member 40 further includes a fourth connection segment 44, the third interface interconnection segment 41, the fourth interface interconnection segment 42 and the third connection segment 43 constitute an interconnection main segment, the second interconnection member 40 includes two interconnection main segments, the two ends of the fourth connection segment 44 are respectively connected to the two interconnection main segments, and the lower surface of the fourth connection segment 44 is conductively connected to the first sub-conductive layer 111. By providing the fourth connection segment 44, the connection area between the first conductive structure 11 and the second conductive structure 12 can be increased, and the connection reliability can be improved.

[0082] In other embodiments, the third interface interconnection segment 41 and the fourth interface interconnection segment 42 also have a wetting groove that is arranged throughout the thickness direction thereof, and the wetting groove on the second interconnection member 40 extends along the arrangement direction of the third interface interconnection segment 41, the third connecting segment 43 and the fourth interface interconnection segment 42.

[0083] It should be noted that, in this embodiment, the first interconnection member 30 and the second interconnection member 40 are both sheet structures, which have a large heat dissipation area and can ensure rapid conduction of current heat flow, thereby improving the heat dissipation capacity of the power module.

[0084] In this embodiment, the width of the first interconnecting member 30 is between 1.5 mm and 3.0 mm, and can be specifically 1.5 mm, 2 mm, 2.5 mm, 3.0 mm, and any other value between 1.5 mm and 3.0 mm.

[0085] The width dimension of the first interconnection member 30 refers to the width dimensions of the first interface interconnection segment 32 , the second interface interconnection segment 33 , the first connection segment 35 and the second connection segment 36 .

[0086] In this embodiment, the width of the second interconnecting member 40 is between 1.5 mm and 4.0 mm, and can be specifically 1.5 mm, 2.0 mm, 3.0 mm, 4.0 mm, or any other value between 1.5 mm and 4.0 mm.

[0087] The width dimension of the second interconnection member 40 refers to the width dimensions of the third interface interconnection segment 41 , the fourth interface interconnection segment 42 and the third connection segment 43 .

[0088] The ratio of the width of the first interconnection member 30 to the width of the chip 20 is between 0.3 and 0.6, and can be 0.3, 0.4, 0.5, 0.6, or any other value between 0.3 and 0.6.

[0089] In this embodiment, the lower limit of the numerical range of the interconnection component size width (1.5 mm) is to ensure that the interconnection component has a larger width, with three considerations: a. A larger width can allow the interconnection component to have a wetting groove in the interface interconnection section, which can achieve a three-dimensional interface layer morphology when using welding operations, and increase the interface interconnection strength. b. The increased width allows a larger interface interconnection area, increases the energy required for interface debonding, and is conducive to improving the reliability of interface interconnection. c. When the thickness of the interconnection component is constant, a larger width corresponds to a larger cross-sectional area, which increases the flow capacity of the interconnection component.

[0090] It should be noted that the increase in the thickness of the interconnecting components can also increase the cross-sectional area of ​​the interconnecting components, and thus increase the flow capacity of the interconnecting components. However, the increase in the thickness of the interconnecting components has a "cubic" effect on the increase in the stiffness of the interconnecting components, which is much stronger than the "linear" effect of increasing the width on the increase in stiffness, which is not conducive to the reliability of the interface interconnection.

[0091] In this embodiment, the upper limit of the numerical range of the interconnection member size width is determined by the width of the interface to be interconnected. For example, the width of the interface interconnection section of the first interconnection member 30 in the interconnectable area on the upper surface of the chip 20 is 3.07 mm, so 3.0 mm is taken downward. The width of the conductive layer of the second interconnection member 40 in the interconnection area near the first groove section 12111 is 6 mm. Considering that the third interface interconnection section 41 of the second interconnection member 40 and the third sub-conductive layer 121 at the boundary of the first groove section 12111 must have a recommended minimum distance of 1 mm in the second direction to meet the insulation requirements, the upper limit is 4 mm.

[0092] It should be noted that the recommended minimum distance is the minimum distance recommended from the insulation perspective during design, but this minimum distance is not the minimum limit value in the physical sense.

[0093] The first interface interconnection section 32 and the second interface interconnection section 33 are both flat plate structures, which can increase the contact area between the interface interconnection section and the chip, thereby improving the connection strength and heat dissipation capability. In addition, the main body section 31 is a flat plate structure, which can increase the contact area between the main body section 31 and the conductive structure, thereby improving the connection strength and heat dissipation capability.

[0094] Specifically, the first connecting section 35 and / or the second connecting section 36 are both arched plate structures, the highest point of the upper surface of the first connecting section 35 is higher than the highest point of the upper surface of the main section 31 and the highest point of the upper surface of the first interface interconnection section 32, and the highest point of the upper surface of the second connecting section 36 is higher than the highest point of the upper surface of the main section 31 and the highest point of the upper surface of the second interface interconnection section 33.

[0095] In this embodiment, the first connecting section 35 and the second connecting section 36 are both arched plate structures.

[0096] The third interface interconnection segment 41 and the fourth interface interconnection segment 42 are both flat plate structures, which can increase the contact area between the third interface interconnection segment 41 and the fourth interface interconnection segment 42 and the conductive structure, thereby improving the connection strength and heat dissipation capability.

[0097] like Figure 6 and Figure 7 As shown, in this embodiment, the power module further includes a control component 50, and the control component 50 includes a mounting substrate 51 and a resistor element 52 disposed on the mounting substrate 51. A mounting position is disposed on the surface of the first conductive structure 11 and / or the second conductive structure 12, and the mounting position is located between two adjacent chips 20. One surface of the mounting substrate 51 in the thickness direction thereof is connected to the mounting position, and the resistor element 52 is located on another surface of the mounting substrate 51 in the thickness direction thereof.

[0098] like Figure 6 As shown, in this embodiment, the mounting substrate 51 includes a substrate body 511 and a first metal layer 512 and a second metal layer 513 arranged on the substrate body 511, the first metal layer 512 and the second metal layer 513 are respectively located on both sides of the substrate body 511, the resistor element 52 is arranged on the first metal layer 512, and the second metal layer 513 is connected to the mounting position, and the second metal layer 513 is beneficial to the interface interconnection reliability between the mounting substrate 51 and the conductive layer.

[0099] In other embodiments, the mounting substrate 51 includes a substrate body 511 and a first metal layer 512 disposed on the substrate body 511, the substrate body 511 is connected to the mounting position, and the resistor element 52 is disposed on the first metal layer 512. The first metal layer 512 is conductively connected to the resistor element 52. The substrate body 511 is connected to the mounting position by welding, sintering or bonding, so that the mounting substrate 51 is fixed on the liner 10.

[0100] It should be noted that a control component 50 is disposed between two adjacent chips, and the control component 50 can be used to separate the two adjacent chips, so as to further make the chips evenly dispersed and arranged.

[0101] In this embodiment, two adjacent chips refer to two adjacent chips on the same conductive layer.

[0102] Specifically, the first metal layer 512 is copper. Copper has high electrical conductivity, can reduce resistance, and improve current transmission efficiency. In addition, copper also has good thermal conductivity, which helps to dissipate heat of power devices and improve the stability and life of power devices.

[0103] Specifically, the substrate body 511 is a ceramic substrate, which can provide a good insulation effect and effectively avoid the influence of heat on the power side on the resistance element, thereby improving the reliability of the device under high-temperature applications.

[0104] Ceramic substrates help improve the efficiency, stability and safety of power electronic systems through their unique thermal, mechanical and electrical properties. Ceramic substrates have high thermal conductivity, large heat capacity and strong heat diffusion function, which can effectively conduct the heat generated by the chip in the power module to the outside to achieve good heat dissipation effect. Ceramic substrates have strong electrical insulation capabilities, protecting users from the impact of the electrical system while ensuring electrical safety inside the module.

[0105] Specifically, ceramic substrates can be made of ceramic materials such as aluminum oxide, aluminum nitride, silicon nitride, zirconium oxide, and beryllium oxide. Aluminum oxide has excellent mechanical strength and chemical corrosion resistance, and is suitable for applications with high durability requirements. Zirconia is known for its outstanding toughness and high temperature resistance, and performs well in high temperature and high stress environments. Aluminum nitride has high thermal conductivity and low expansion coefficient, can effectively dissipate heat, and is suitable for high-power electronic devices. The diversity and excellent properties of these ceramic materials provide a wide range of choices and significant performance improvements for the design and application of silicon carbide devices.

[0106] It should be noted that the process of mounting the substrate 51 includes: active metal brazing ceramic substrate (AMB) or direct copper clad ceramic substrate (DBC) or direct copper plated ceramic substrate (DPC).

[0107] In other embodiments, the substrate body 511 may be made of a polymer composite board.

[0108] In this embodiment, the second metal layer 513 is connected to the mounting position by melting and then solidifying (welding) the solder, which has the advantage of a firm connection.

[0109] In other embodiments, the second metal layer 513 is connected to the mounting position by bonding, which has the advantages of simple connection and easy assembly.

[0110] In this embodiment, the resistor element 52 includes a gate resistor. The power device controls the switching characteristics of the silicon carbide device in the form of a series gate resistor, thereby effectively alleviating the module oscillation problem under switching transients.

[0111] Specifically, this embodiment separates the gate circuit area and the power area into upper and lower side structures, aiming to avoid failure of the entire liner due to gate resistance failure caused by the process and high temperature, thereby improving the overall packaging yield.

[0112] Since the control components are miniaturized and discrete, batch production can be used to complete the interconnection of gate resistors. Since the gate resistors are not heat resistant enough, there is a probability of failure at high process temperatures. Screening can be introduced after the interconnection process to avoid potential failures. Then the control components can be flexibly fixed to the liner according to the liner layout.

[0113] like Figure 1 and Figure 2 As shown, another embodiment of the present invention provides a power device, the power device includes the power module provided above. Therefore, the power device can also be arranged in a symmetrical manner by setting the first conductive structure 11 and the second conductive structure 12 as an axisymmetric structure, so that the chip 20 can be laid out symmetrically, and the symmetry axis of the chip 20 is the same as the symmetry axis of the first conductive structure 11 and the second conductive structure 12, so that the interconnection length between the upper surface of the chip 20 and the conductive structure can be equal and of moderate length.

[0114] In this embodiment, the power device includes two power modules 70 , and the two power modules 70 are arranged in a spaced manner and symmetrically in the second direction to further improve the symmetry of the power device.

[0115] It should be noted that, in the second direction, the driving signal connection conductive layer 13 is provided on the sides of the two power modules 70 that are close to each other, which can further increase the spacing between the chips on the power modules, so that the chips are further dispersedly arranged.

[0116] like Figures 8 to 10 As shown, the power device further includes a power terminal 60, which includes a terminal pin 61, a first plate section 62, a second plate section 63 and a lead section 64 connected in sequence, the terminal pin 61 and the second plate section 63 are respectively arranged at an angle with the first plate section 62, the terminal pin 61 and the second plate section 63 extend in opposite directions, and the lead section 64 is arranged at one end of the second plate section 63 away from the first plate section 62. With the above structure, the power terminal can realize an "L"-shaped structure, so that the ultrasonic terminal welding technology can be applied to the interconnection interface at the power terminal pin, thereby improving the reliability of the terminal interconnection.

[0117] In the related art, the layout of power devices is generally a planar layout, and the chip layout position is relatively concentrated, which easily causes the power terminal to be bent greater than 90 degrees (such as 180 degrees) near the interconnection interface between it and the upper copper layer, making it impossible to use ultrasonic terminal welding technology.

[0118] It should be noted that the ultrasonic terminal welding involved in this embodiment uses a "rod-shaped probe" to squeeze the terminal pins of the power terminal in the direction perpendicular to the interconnection interface and vibrate at a high frequency to achieve the effect of interface interconnection. This embodiment involves three power terminals that are all L-shaped structures near their terminal pins, and the terminal pins are not blocked relative to the interconnection interface, so the "rod-shaped probe" can be used for ultrasonic terminal welding technology. In the related art, due to layout reasons, the power terminals are prone to bending more than 90 degrees (such as 180 degrees) at the terminal pins, resulting in overlapping projections of the power terminals in the plane of the interconnection interface, making it impossible to use ultrasonic terminal welding, that is, the terminal portion above the terminal pin blocks the "rod-shaped probe", making it unable to work normally.

[0119] Moreover, in this embodiment, the power terminal 60 includes a first terminal 65, a second terminal 66 and a third terminal 67. The number of terminal pins 61 of the first terminal 65 and the number of terminal pins 61 of the third terminal 67 are both greater than the number of terminal pins 61 of the second terminal 66, so that the first terminal 65 and the third terminal 67 have a higher current carrying capacity.

[0120] Specifically, the number of the terminal pins 61 of the first terminal 65 and the number of the terminal pins 61 of the third terminal 67 are both four, and the number of the terminal pins 61 of the second terminal 66 is two.

[0121] The device provided by the embodiment has the following beneficial effects:

[0122] (1) Using "U"-shaped and "T"-shaped upper copper layer patterns (conductive structures) on different substrates allows the chip to be laid out symmetrically and evenly;

[0123] (2) The high symmetry of this layout means that the interconnection length between the chip surface and the upper copper layer can be equal and moderate;

[0124] (3) Due to the high symmetry of the layout, a copper strip device (interconnection component) that can interconnect multiple pairs of interfaces at the same time can be easily applied, so that the power circuit of the module has no bonding wires, thereby improving the interconnection reliability of the module;

[0125] (4) In this layout, the three power terminals can simultaneously realize an "L"-shaped structure, so that the ultrasonic terminal welding technology can be applied to the interconnection interface at the three power terminal pins at the same time, thereby improving the reliability of the terminal interconnection;

[0126] (5) In this layout, some power terminals can have 4 terminal pins, which enables them to have a higher current carrying capacity;

[0127] (6) In the module layout, a small liner (mounting substrate 51 of the control component 50) can be used to form a three-dimensional spatial structure. Chip resistors (resistance elements 52) can be added to the upper copper layer surface of the small liner, thereby improving the module space utilization.

[0128] It should be noted that the terms used herein are only for describing specific embodiments and are not intended to limit the exemplary embodiments according to the present application. As used herein, unless the context clearly indicates otherwise, the singular form is also intended to include the plural form. In addition, it should be understood that when the terms "comprise" and / or "include" are used in this specification, it indicates the presence of features, steps, operations, devices, components and / or combinations thereof.

[0129] Unless otherwise specifically stated, the relative arrangement, numerical expressions and numerical values ​​of the parts and steps set forth in these embodiments do not limit the scope of the present invention. Meanwhile, it should be understood that, for ease of description, the sizes of the various parts shown in the accompanying drawings are not drawn according to the actual proportional relationship. The technology, method and equipment known to those of ordinary skill in the relevant art may not be discussed in detail, but in appropriate cases, the technology, method and equipment should be considered as a part of the specification. In all examples shown and discussed here, any specific value should be interpreted as being merely exemplary, rather than as a limitation. Therefore, other examples of exemplary embodiments may have different values. It should be noted that similar reference numerals and letters represent similar items in the following drawings, and therefore, once a certain item is defined in an accompanying drawing, it does not need to be further discussed in subsequent drawings.

[0130] In the description of the present invention, it is necessary to understand that the directions or positional relationships indicated by directional words such as "front, back, up, down, left, right", "lateral, vertical, perpendicular, horizontal" and "top, bottom" are usually based on the directions or positional relationships shown in the drawings. They are only for the convenience of describing the present invention and simplifying the description. Unless otherwise specified, these directional words do not indicate or imply that the devices or elements referred to must have a specific direction or be constructed and operated in a specific direction. Therefore, they cannot be understood as limiting the scope of protection of the present invention. The directional words "inside and outside" refer to the inside and outside relative to the contours of each component itself.

[0131] For ease of description, spatially relative terms such as "above", "above", "on the upper surface of", "above", etc. may be used here to describe the spatial positional relationship between a device or feature and other devices or features as shown in the figure. It should be understood that spatially relative terms are intended to include different orientations of the device in use or operation in addition to the orientation described in the figure. For example, if the device in the accompanying drawings is inverted, the device described as "above other devices or structures" or "above other devices or structures" will be positioned as "below other devices or structures" or "below other devices or structures". Thus, the exemplary term "above" can include both "above" and "below". The device can also be positioned in other different ways (rotated 90 degrees or in other orientations), and the spatially relative descriptions used here are interpreted accordingly.

[0132] In addition, it should be noted that the use of terms such as "first" and "second" to limit components is only for the convenience of distinguishing the corresponding components. If not otherwise stated, the above terms have no special meaning and therefore cannot be understood as limiting the scope of protection of the present invention.

[0133] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. For those skilled in the art, the present invention may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

Claims

1. A power module, characterized in that: The power module comprises a liner (10) and a plurality of chips (20); a first conductive structure (11) and a second conductive structure (12) are arranged on the liner (10); the first conductive structure (11) and the second conductive structure (12) are both axisymmetric structures; the axes of symmetry of the first conductive structure (11) and the second conductive structure (12) extend along a first direction; a plurality of chips (20) are arranged on the first conductive structure (11) and the second conductive structure (12); the plurality of chips (20) on the first conductive structure (11) and the plurality of chips (20) on the second conductive structure (12) are symmetrically arranged on both sides of the axis of symmetry; The first conductive structure (11) comprises a first sub-conductive layer (111) and two second sub-conductive layers (112); the first sub-conductive layer (111) and the second sub-conductive layer (112) are arranged at intervals; the axis of the first sub-conductive layer (111) is coaxial with the symmetry axis; the two second sub-conductive layers (112) are respectively located on both sides of the first sub-conductive layer (111) in a second direction perpendicular to the first direction; the chip (20) is arranged on each of the two second sub-conductive layers (112); the upper surfaces of the chips (20) on the two second sub-conductive layers (112) are conductively connected to the first sub-conductive layer (111); and the first sub-conductive layer (111) is conductively connected to the second conductive structure (12).

2. The power module according to claim 1, characterized in that: The first sub-conductive layer (111) comprises a first section (1111) and a second section (1112) which are perpendicular to each other, the axis of the first section (1111) being coaxial with the axis of symmetry, one end of the first section (1111) being connected to the middle of the second section (1112), the second section (1112) being arranged between the first section (1111) and the second conductive structure (12), the two second sub-conductive layers (112) being respectively arranged on both sides of the first section (1111) in the second direction, the upper surfaces of the chip (20) on the two second sub-conductive layers (112) being conductively connected to the first section (1111), and the second section (1112) being conductively connected to the second conductive structure (12).

3. The power module according to claim 2, characterized in that: The second sub-conductive layer (112) is a rectangular structure, comprising a first side (1121) and a second side (1122) which are perpendicular to each other, the first side (1121) being arranged away from the second section (1112) and being flush with an end of the first section (1111) away from the second section (1112), and the second side (1122) being arranged away from the first section (1111) and being flush with an end of the second section (1112).

4. The power module according to claim 1, characterized in that: The second conductive structure (12) comprises a third sub-conductive layer (121) and a fourth sub-conductive layer (122); the third sub-conductive layer (121) has a notch (1211) at one end facing the first sub-conductive layer (111) in the first direction; the fourth sub-conductive layer (122) extends into the notch (1211); the axis of the fourth sub-conductive layer (122) is coaxial with the symmetry axis; the chips (20) are arranged at positions on both sides of the notch (1211) of the third sub-conductive layer (121) in the second direction; the first sub-conductive layer (111) is conductively connected to the third sub-conductive layer (121); and the upper surface of the chip (20) on the third sub-conductive layer (121) is conductively connected to the fourth sub-conductive layer (122).

5. The power module according to claim 4, characterized in that: The third sub-conductive layer (121) comprises a third section (1212), a fourth section (1213) and a fifth section (1214); the third section (1212) and the fifth section (1214) are located on the same side of the fourth section (1213); the third section (1212) and the fifth section (1214) are respectively connected to two ends of the fourth section (1213); the side wall of the third section (1212), the side wall of the fourth section (1213) and the side wall of the fifth section (1214) together form the gap (1211); and the fourth section (1213) is arranged at an end of the third section (1212) away from the first conductive structure (11).

6. The power module according to claim 5, characterized in that: One end of the third segment (1212) away from the fourth segment (1213), one end of the fifth segment (1214) away from the fourth segment (1213), and one end of the fourth sub-conductive layer (122) away from the fourth segment (1213) are flush with each other.

7. The power module according to claim 4, characterized in that: The notch (1211) comprises a first slot section (12111), a second slot section (12112) and a third slot section (12113) which are connected in sequence; an end of the first slot section (12111) which is away from the second slot section (12112) forms a mouth of the notch (1211); a slot width of the first slot section (12111) is greater than a slot width of the third slot section (12113); a slot width of the second slot section (12112) gradually decreases in a direction from the first slot section (12111) to the third slot section (12113); and a shape of the fourth sub-conductive layer (122) matches a shape of the notch (1211).

8. The power module according to claim 4, characterized in that: The power module further comprises a first interconnection member (30), the first interconnection member (30) comprising: a main body segment (31), wherein a lower surface of the main body segment (31) is conductively connected to the first sub-conductive layer (111) or the fourth sub-conductive layer (122); a first interface interconnection section (32), located at a side of the main body section (31) and connected to the main body section (31), wherein a lower surface of the first interface interconnection section (32) is conductively connected to an upper surface of one of the two symmetrically arranged chips (20); The second interface interconnection section (33) is located at the side of the main body section (31) and is connected to the main body section (31), and the lower surface of the second interface interconnection section (33) is conductively connected to the upper surface of the other chip (20) of the two symmetrically arranged chips (20).

9. The power module according to claim 8, characterized in that: At least one of the lower surface of the main body section (31), the lower surface of the first interface interconnection section (32), and the lower surface of the second interface interconnection section (33) is provided with a wetting groove (34).

10. The power module according to claim 8, characterized in that: The first interconnection member (30) further comprises a first connection section (35), the first connection section (35) being located at a side of the main body section (31), the two ends of the first connection section (35) being respectively connected to the main body section (31) and the first interface interconnection section (32), the lower surface of the first connection section (35) being higher than the lower surface of the main body section (31) and / or the lower surface of the first interface interconnection section (32); The first interconnecting member (30) further comprises a second connecting section (36), the second connecting section (36) being located at a side of the main section (31), the two ends of the second connecting section (36) being respectively connected to the main section (31) and the second interface interconnecting section (33), and the lower surface of the second connecting section (36) being higher than the lower surface of the main section (31) and / or the lower surface of the second interface interconnecting section (33).

11. The power module according to claim 4, characterized in that: The power module further comprises a second interconnection member (40), wherein the second interconnection member (40) comprises: A third interface interconnection segment (41), the lower surface of the third interface interconnection segment (41) being conductively connected to the third sub-conductive layer (121); a fourth interface interconnection segment (42), wherein a lower surface of the fourth interface interconnection segment (42) is conductively connected to the first sub-conductive layer (111); A third connecting section (43), wherein two ends of the third connecting section (43) are respectively connected to the third interface interconnection section (41) and the fourth interface interconnection section (42), and a lower surface of the third connecting section (43) is higher than a lower surface of the third interface interconnection section (41) and / or a lower surface of the fourth interface interconnection section (42).

12. The power module according to claim 11, characterized in that: The second interconnection member (40) further comprises a fourth connection segment (44); the third interface interconnection segment (41), the fourth interface interconnection segment (42) and the third connection segment (43) constitute an interconnection main segment; the second interconnection member (40) comprises two interconnection main segments; two ends of the fourth connection segment (44) are respectively connected to the two interconnection main segments; and the lower surface of the fourth connection segment (44) is conductively connected to the first sub-conductive layer (111).

13. The power module according to any one of claims 1 to 12, characterized in that: The power module further comprises a control component (50), wherein the control component (50) comprises a mounting substrate (51) and a resistance element (52) arranged on the mounting substrate (51); A mounting position is provided on the surface of the first conductive structure (11) and / or the second conductive structure (12), the mounting position is located between two adjacent chips (20), one surface of the mounting substrate (51) in the thickness direction thereof is connected to the mounting position, and the resistor element (52) is located on another surface of the mounting substrate (51) in the thickness direction thereof.

14. The power module according to claim 13, characterized in that: The mounting substrate (51) comprises a substrate body (511) and a first metal layer (512) arranged on the substrate body (511), the substrate body (511) is connected to the mounting position, and the resistor element (52) is arranged on the first metal layer (512); or, The mounting substrate (51) comprises a substrate body (511) and a first metal layer (512) and a second metal layer (513) arranged on the substrate body (511), the first metal layer (512) and the second metal layer (513) being located on two sides of the substrate body (511), respectively, the resistor element (52) being arranged on the first metal layer (512), and the second metal layer (513) being connected to the mounting position.

15. The power module according to claim 13, characterized in that: The resistance element (52) comprises a gate resistor.

16. A power device, characterized in that: The power device comprises the power module according to any one of claims 1 to 15.

17. The power device according to claim 16, characterized in that: The power device comprises two power modules (70), and the two power modules (70) are arranged at intervals and symmetrically in the second direction.

18. The power device according to claim 16, characterized in that: The power device further comprises a power terminal (60), the power terminal (60) comprising a terminal pin (61), a first plate segment (62), a second plate segment (63) and a lead-out segment (64) connected in sequence, the terminal pin (61) and the second plate segment (63) being arranged at an angle to the first plate segment (62), the terminal pin (61) and the second plate segment (63) extending in opposite directions, and the lead-out segment (64) being arranged at an end of the second plate segment (63) away from the first plate segment (62).

Images