Semiconductor packaging structure

Abstract

The present invention provides a semiconductor packaging structure, wherein the semiconductor packaging structure comprises: a packaging shell, including a substrate; a first chip module, connected to the substrate, the first chip module comprises a plurality of first semiconductor chips, the plurality of the first semiconductor chips are connected in parallel; a second chip module, connected to the substrate, the second chip module is connected in series with the first chip module; a first power terminal, conductively connected to the first chip module; a second power terminal, conductively connected to the second chip module. The technical solution of the present application can effectively solve the problem that power semiconductor devices in the related art are difficult to balance high voltage levels and costs.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a semiconductor packaging structure. Background Art

[0002] With the continuous development of science and technology, power semiconductor devices, as the core of power electronics technology, are widely used in new energy power generation, smart grid, rail transit, electric vehicles, industrial control and household appliances. In power grid applications, based on the increasingly high requirements of turning "rough electricity" into "fine electricity", the voltage level of power semiconductor devices is gradually increasing. A 50% increase in the voltage of power semiconductor devices can reduce the area of ​​the flexible straight valve by about 31%, reduce the weight of the valve tower by about 3.3%, and reduce the loss by about 10-20%. Therefore, it is crucial to increase the voltage level of the power semiconductor module. However, at present, only silicon carbide semiconductor chips can meet the requirements of voltage levels above 6.5kV. If faced with higher voltage levels, how to balance high voltage levels and costs has become a problem that needs to be solved in this field. Summary of the invention

[0003] The main purpose of the present invention is to provide a semiconductor packaging structure to solve the problem in the related art that power semiconductor devices are difficult to balance high voltage levels and costs.

[0004] In order to achieve the above-mentioned objectives, the present invention provides a semiconductor packaging structure, including: a packaging shell, including a substrate; a first chip module, connected to the substrate, the first chip module including a plurality of first semiconductor chips, the plurality of first semiconductor chips being connected in parallel; a second chip module, connected to the substrate, the second chip module being connected in series with the first chip module; a first power terminal, conductively connected to the first chip module; and a second power terminal, conductively connected to the second chip module.

[0005] Furthermore, the second chip module includes a plurality of second semiconductor chips, and the plurality of second semiconductor chips are connected in parallel.

[0006] Furthermore, the semiconductor package structure further includes a first insulating rib connected to the substrate, and the first chip module and the second chip module are respectively located on two sides of the first insulating rib.

[0007] Furthermore, the semiconductor packaging structure also includes a first gate terminal and a second insulating rib, the first gate terminal is located on a side of the first chip module away from the first insulating rib, the second insulating rib is located between the first gate terminal and the first chip module, the first gate terminal is conductively connected to multiple first semiconductor chips, and the first power terminal is located between the first insulating rib and the second insulating rib.

[0008] Furthermore, the semiconductor packaging structure also includes a second gate terminal and a third insulating rib, the second gate terminal is located on a side of the second chip module away from the first insulating rib, the third insulating rib is located between the second gate terminal and the second chip module, the second gate terminal is conductively connected to the second chip module, and the second power terminal and the second gate terminal are located on the same side of the third insulating rib.

[0009] Furthermore, the packaging shell also includes a surrounding plate connected to the substrate, the surrounding plate includes a first side plate and a second side plate arranged opposite to each other, the first power terminal passes through the first side plate, and the second power terminal passes through the second side plate.

[0010] Furthermore, the enclosure also includes a third side plate, which is connected between the first end of the first side plate and the first end of the second side plate, the first chip module is located between the third side plate and the first insulating rib, and the first gate terminal is located at the connection between the third side plate and the second side plate.

[0011] Furthermore, the enclosure also includes a fourth side plate, which is connected between the second end of the first side plate and the second end of the second side plate, the second chip module is located between the fourth side plate and the first insulating rib, and the second gate terminal is arranged adjacent to the fourth side plate and spaced apart from the second side plate.

[0012] Furthermore, the semiconductor packaging structure also includes a first conductive connection portion arranged on the substrate, the first chip module is arranged on the first conductive connection portion, the first chip module also includes a first freewheeling structure, the first freewheeling structure is arranged on the first conductive connection portion, the source of the first freewheeling structure is conductively connected to the drain of a first semiconductor chip through the first conductive connection portion, and the drain of the first freewheeling structure is conductively connected to the source of the first semiconductor chip.

[0013] Furthermore, the semiconductor packaging structure also includes a second conductive connection portion arranged on the substrate, the second chip module is arranged on the second conductive connection portion, the semiconductor packaging structure also includes a conductive interconnection and an insulating adhesive layer, the conductive interconnection is connected between the first semiconductor chip and the second conductive connection portion, the insulating adhesive layer is filled and arranged on the substrate, and the conductive interconnection and the first insulating rib are both located in the insulating adhesive layer.

[0014] Further, the conductive interconnection includes bonding wires, at least part of which crosses the first insulating rib; and / or the conductive interconnection includes a metal guide plate, the first insulating rib is provided with a through hole, and the metal guide plate is passed through the through hole.

[0015] Furthermore, the semiconductor packaging structure further includes a chamfered connection portion, which is connected between the substrate and the enclosure; and / or the chamfered connection portion is connected between the substrate and the first insulating rib.

[0016] Furthermore, the height of the first insulating rib is between 0 and 3 mm; and / or the width of the first insulating rib is between 0 and 2 mm.

[0017] Furthermore, the packaging shell is made of ceramic; and / or the substrate and the enclosure are an integrated structure.

[0018] Furthermore, the semiconductor packaging structure also includes a heat sink connected to the outer surface of the substrate.

[0019] By applying the technical solution of the present invention, the package shell provides protection for various components of the semiconductor package structure, the package shell includes a substrate, the substrate provides a mounting base for various components of the semiconductor package structure, the first power terminal is conductively connected to the first chip module, the second power terminal is conductively connected to the second chip module, the first power terminal and the second power terminal enable the semiconductor package structure to be conductively connected to other external structures, so that the semiconductor package structure forms a current loop of the first power terminal, the first chip module, the second chip module, and the second power terminal, that is, the first chip module and the second chip module are connected in series; for the first chip module, the first chip module includes a plurality of first semiconductor chips, and the plurality of first semiconductor chips are connected in parallel; The multiple first semiconductor chips in the first chip module are connected in parallel, so that the current of the first chip module is the sum of the currents of the multiple first semiconductor chips, so that the current of the first chip module is larger than that of a single chip, and the first chip module and the second chip module are arranged in series, so that the voltage of the semiconductor package structure is the sum of the voltage of the first chip module and the voltage of the second chip module, so that the voltage of the semiconductor package structure is larger, and the semiconductor package structure has a higher voltage level. In the above manner, the overall voltage level of the semiconductor package structure can be improved by using multiple chips with relatively low voltage levels, and the cost of chips with relatively low voltage levels is also relatively low, so that the cost of the semiconductor package structure can be controlled. Therefore, the technical solution of the present application can effectively solve the problem that power semiconductor devices in the related art are difficult to balance high voltage levels and costs. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] The drawings constituting a part of the present application are used to provide a further understanding of the present invention. The exemplary embodiments of the present invention and their descriptions are used to explain the present invention and do not constitute an improper limitation of the present invention. In the drawings:

[0021] Figure 1 A schematic diagram of a three-dimensional structure of an embodiment of a semiconductor packaging structure according to the present invention is shown;

[0022] Figure 2 Shows Figure 1 A schematic top view of a semiconductor package structure;

[0023] Figure 3 Shows Figure 1 A schematic diagram of a three-dimensional structure of a semiconductor packaging structure after removing a cover plate;

[0024] Figure 4 Shows Figure 3 A schematic top view of a semiconductor package structure;

[0025] Figure 5 Shows Figure 1 A schematic diagram of a three-dimensional structure of a semiconductor packaging structure after removing a packaging shell;

[0026] Figure 6 Shows Figure 5 A schematic top view of a partial structure of a semiconductor package structure;

[0027] Figure 7 Shows Figure 1 A schematic three-dimensional structural diagram of a partial structure of a packaging shell of a semiconductor packaging structure;

[0028] Figure 8 Shows Figure 7 A schematic top view of a partial structure of a packaging shell of a semiconductor packaging structure;

[0029] Fig. 9 Shows Figure 1 A schematic diagram of a three-dimensional structure of a cover plate of a semiconductor packaging structure;

[0030] Fig.10 Shows Fig. 9 A schematic top view of a cover plate of a semiconductor packaging structure.

[0031] The above drawings include the following reference numerals:

[0032] 10. Encapsulation shell; 11. Base plate; 12. Cover plate; 13. Enclosure plate; 131. First side plate; 132. Second side plate; 133. Third side plate; 134. Fourth side plate;

[0033] 20. a first conductive connection portion;

[0034] 30. a second conductive connection portion;

[0035] 40. first chip module; 41. first chip; 42. second chip; 43. first freewheeling structure;

[0036] 50. Second chip module; 51. Third chip; 52. Fourth chip;

[0037] 61. First power terminal; 62. Second power terminal; 63. First gate terminal; 64. First drive terminal; 65. Second gate terminal; 66. Second drive terminal;

[0038] 71, first insulating rib; 72, second insulating rib; 73, third insulating rib;

[0039] 80. Conductive interconnects; 81. Bonding wires;

[0040] 90. Chamfered connection. DETAILED DESCRIPTION

[0041] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, rather than all the embodiments. The following description of at least one exemplary embodiment is actually only illustrative and is by no means intended to limit the present invention and its application or use. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0042] It should be noted that the terms used herein are only for describing specific embodiments and are not intended to limit the exemplary embodiments according to the present application. As used herein, unless the context clearly indicates otherwise, the singular form is also intended to include the plural form. In addition, it should be understood that when the terms "comprise" and / or "include" are used in this specification, it indicates the presence of features, steps, operations, devices, components and / or combinations thereof.

[0043] Unless otherwise specifically stated, the relative arrangement, numerical expressions and numerical values ​​of the parts and steps set forth in these embodiments do not limit the scope of the present invention. Meanwhile, it should be understood that, for ease of description, the sizes of the various parts shown in the accompanying drawings are not drawn according to the actual proportional relationship. The technology, method and equipment known to those of ordinary skill in the relevant art may not be discussed in detail, but in appropriate cases, the technology, method and equipment should be considered as a part of the specification. In all examples shown and discussed here, any specific value should be interpreted as being merely exemplary, rather than as a limitation. Therefore, other examples of exemplary embodiments may have different values. It should be noted that similar reference numerals and letters represent similar items in the following drawings, and therefore, once a certain item is defined in an accompanying drawing, it does not need to be further discussed in subsequent drawings.

[0044] like Figures 1 to 6As shown, the present application provides a semiconductor packaging structure. An embodiment of the semiconductor packaging structure of the present application includes: a packaging shell 10, a first chip module 40, a second chip module 50, a first power terminal 61, and a second power terminal 62; the packaging shell 10 includes a substrate 11; the first chip module 40 is connected to the substrate 11, and the first chip module 40 includes a plurality of first semiconductor chips, and the plurality of first semiconductor chips are connected in parallel; the second chip module 50 is connected to the substrate 11, and the second chip module 50 is connected in series with the first chip module 40; the first power terminal 61 is conductively connected to the first chip module 40; the second power terminal 62 is conductively connected to the second chip module 50.

[0045] By applying the technical solution of this embodiment, the packaging shell 10 provides protection for various components of the semiconductor packaging structure. The packaging shell 10 includes a substrate 11. The substrate 11 provides an installation basis for various components of the semiconductor packaging structure. The first power terminal 61 is conductively connected to the first chip module 40, and the second power terminal 62 is conductively connected to the second chip module 50. The first power terminal 61 and the second power terminal 62 enable the semiconductor packaging structure to be conductively connected to other external structures, so that the semiconductor packaging structure forms a current loop of the first power terminal 61, the first chip module 40, the second chip module 50, and the second power terminal 62, that is, the first chip module 40 and the second chip module 50 are connected in series; for the first chip module 40, the first chip module 40 includes multiple first semiconductor chips, multiple The first semiconductor chips are connected in parallel; the multiple first semiconductor chips in the first chip module 40 are connected in parallel, so that the current of the first chip module 40 is the sum of the currents of the multiple first semiconductor chips, so that the current of the first chip module 40 is larger than that of a single chip, and the first chip module 40 and the second chip module 50 are arranged in series, so that the voltage of the semiconductor package structure is the sum of the voltage of the first chip module 40 and the voltage of the second chip module 50, so that the voltage of the semiconductor package structure is larger, and the semiconductor package structure has a higher voltage level. In the above manner, the overall voltage level of the semiconductor package structure can be improved by using multiple chips with relatively low voltage levels, and the cost of the chips with relatively low voltage levels is also relatively low, so that the cost of the semiconductor package structure can be controlled. Therefore, the technical solution of this embodiment can effectively solve the problem that it is difficult for power semiconductor devices in related technologies to take into account both high voltage levels and costs.

[0046] It should be noted that in the field of 10,000-volt power semiconductors, the total power of 10,000-volt high-voltage silicon carbide chips is lower than that of silicon carbide chips with lower voltages. For example, the current of a 10kV chip is 17A and the power is 170kW, while the 1.2kV chip currently on the market can reach 200A and the power can reach 240kW under the same conditions. In addition, the cost of 10,000-volt high-voltage silicon carbide chips is much higher than that of silicon carbide chips with lower voltages. Taking the above two chips as an example, the price of a 10kV chip is more than 10,000 yuan, while the price of a 1.2kV chip is between 100-200 yuan. In addition, the on-resistance (loss) of 10,000-volt high-voltage silicon carbide chips is much higher than that of silicon carbide chips with lower voltages. Taking the above two chips as an example, the on-resistance of a 10kV chip is more than 300mΩ, while that of a 1.2kV chip is only about 7mΩ. Therefore, by adopting the technical solution of this embodiment, it is possible to use multiple 1.2kV chips to improve the overall voltage level of the semiconductor packaging structure. In this embodiment, the voltage level of the semiconductor package structure is between 10Kv and 15Kv and the cross-sectional area of ​​the inner cavity of the package shell 10 is 800mm 2 Up to 1200mm 2 between.

[0047] Specifically, in the present embodiment, the semiconductor package structure further includes a first conductive connection portion 20 and a second conductive connection portion 30, the first conductive connection portion 20 and the second conductive connection portion 30 are arranged on the substrate 11 at an interval, the first chip module 40 is connected to the substrate 11 through the first conductive connection portion 20, the second chip module 50 is connected to the substrate 11 through the second conductive connection portion 30, the drain of the first chip module 40 is conductively connected to the first conductive connection portion 20, the first end of the first power terminal 61 is conductively connected to the first conductive connection portion 20, the second end of the first power terminal 61 extends to the outside of the package shell 10, the drain of the second chip module 50 is conductively connected to the second conductive connection portion 30, and the first end of the second power terminal 62 is conductively connected to the power source of the second chip module 50 , the second end of the second power terminal 62 extends to the outside of the packaging shell 10; for the first chip module 40, the first semiconductor chip includes a first chip 41 and a second chip 42, the drain of the first chip 41 and the drain of the second chip 42 are both conductively connected to the first conductive connection part 20, the power source of the first chip 41 and the power source of the second chip 42 are both conductively connected to the second conductive connection part 30, that is, the first chip 41 and the second chip 42 are arranged in parallel inside the first chip module 40; the first conductive connection part 20 and the second conductive connection part 30 are arranged at intervals from each other, so that there is a certain surface distance between the first chip module 40 and the second chip module 50, thereby meeting the insulation requirements of the semiconductor packaging structure and ensuring the reliability of the semiconductor packaging structure.

[0048] It should be noted that "creepage distance" refers to the shortest path along the surface of the insulating material between two conductive parts. Creepage distance / creepage distance design is a necessary measure taken by electrical equipment at different voltage levels to prevent tracking and creepage discharge.

[0049] In addition, it should be noted that, in other embodiments, the semiconductor packaging structure may include more chip modules in addition to the first chip module and the second chip module, and the first chip module may include more chips in addition to the first chip and the second chip. The chips inside the same chip module are arranged in parallel, and multiple chip modules are arranged in series.

[0050] In addition, it should be noted that the first chip module 40 and the first conductive connection part 20, as well as the second chip module 50 and the second conductive connection part 30, are connected by a sintering process. More specifically, the sintering process may be a nanosilver sintering process. The first chip module 40 and the first conductive connection part 20, as well as the second chip module 50 and the second conductive connection part 30, are made by the nanosilver sintering process, so that the semiconductor packaging structure can withstand an operating temperature of more than 300°C, which is higher than the operating temperature of the chip module and the conductive connection part made by the traditional welding process. The nanosilver sintering process is an innovative material connection technology, which is particularly suitable for the manufacture of electronic packaging and high-power devices. The process forms a connection layer with high conductivity and high thermal conductivity by sintering nano-scale silver particles at low temperature, and has significant technical advantages and wide application potential. The nanosilver sintering process has become an important technology in the manufacture of electronic packaging and high-power devices with its low-temperature sintering, high conductivity, high thermal conductivity, structural strength and environmental protection characteristics. The nanosilver sintering process not only improves the performance and reliability of semiconductor packaging structures, but also provides a green and environmentally friendly solution. The benefits of using the nanosilver sintering process are as follows: 1. Low-temperature sintering: A major advantage of the nanosilver sintering process is its low-temperature sintering characteristics. Traditional metal sintering processes usually require high temperatures (over 800°C) to achieve effective sintering, while nanosilver sintering can be completed between 200°C and 300°C. This low-temperature sintering characteristic makes the process particularly suitable for temperature-sensitive electronic components and materials, such as certain semiconductors and organic materials, thereby avoiding thermal damage and material degradation that may be caused by high temperatures. 2. High conductivity: The connection layer formed by nanosilver particles after sintering has excellent conductive properties. As a metal, silver has the highest conductivity among all metals. The nanosilver sintering process can achieve close connection between silver particles at a lower temperature, thereby forming a low-resistance connection layer. This can significantly improve performance and efficiency for electronic devices and circuit boards that require efficient electrical transmission. 3. High thermal conductivity: In addition to high conductivity, the nanosilver sintered layer also has high thermal conductivity. This means that it can effectively dissipate heat and avoid failure or performance degradation of electronic devices due to overheating. In high-power devices such as power semiconductors, LEDs, and high-frequency communication equipment, good thermal management is a key factor in ensuring their stability and long life. 4. Structural strength and stability: The nanosilver sintering process can achieve close bonding of silver particles at a lower temperature to form a connection layer with high structural strength and stability. Compared with traditional welding methods, the nanosilver sintered layer has higher reliability and durability, and can better resist fatigue and damage caused by stress and thermal cycles. 5. Environmental protection characteristics: The nanosilver sintering process does not contain lead and meets environmental protection requirements. Traditional welding processes often use lead-containing solder, which, despite its superior performance, is harmful to the environment and health. Nanosilver sintering provides a green alternative that is in line with the future environmental protection development trend in the field of electronic packaging and manufacturing.6. Process flexibility: Nanosilver sintering materials are usually in the form of pastes and can be coated and printed by a variety of methods such as screen printing, spraying or dispensing. This flexibility enables the process to adapt to different manufacturing needs and design requirements, providing higher design freedom and manufacturing efficiency.

[0051] like Figures 4 to 6 As shown, the second semiconductor chip includes a third chip 51 and a fourth chip 52, the third chip 51 and the fourth chip 52 are arranged on the second conductive connection part 30, the drain of the third chip 51 and the drain of the fourth chip 52 are both conductively connected to the second conductive connection part 30, and the power source of the third chip 51 and the power source of the fourth chip 52 are both conductively connected to the second power terminal 62. Specifically, the third chip 51 and the fourth chip 52 inside the second chip module 50 are also arranged in parallel, so that the current of the second chip module 50 is the sum of the current of the third chip 51 and the current of the fourth chip 52, and further makes the sum of the voltage of the first chip module 40 and the voltage of the second chip module 50 larger, that is, further makes the voltage level of the semiconductor package structure larger.

[0052] like Figures 1 to 4 as well as Figures 7 to 10 As shown, the package shell 10 further includes a cover plate 12 and a surrounding plate 13 disposed between the substrate 11 and the cover plate 12, and the semiconductor package structure further includes a first insulating rib 71, and the first chip module 40 and the second chip module 50 are respectively located on both sides of the first insulating rib 71. Specifically, the first insulating rib 71 is disposed so that the surface distance between the first chip module 40 and the second chip module 50 includes not only the inner surface of the substrate 11 but also the outer surface of the first insulating rib 71. Compared with the solution in which the surface distance only includes the inner surface of the substrate 11, the first insulating rib 71 makes the surface distance between the first chip module 40 and the second chip module 50 larger, thereby ensuring the insulation performance of the semiconductor package structure and further enhancing the reliability of the semiconductor package structure.

[0053] like Figures 3 to 8As shown, the semiconductor package structure further includes a first gate terminal 63 and a second insulating rib 72. The first gate terminal 63 is located on a side of the first chip module 40 away from the first insulating rib 71. The second insulating rib 72 is located between the first gate terminal 63 and the first chip module 40. The first end of the first gate terminal 63 is conductively connected to the gate of the first chip 41 and the gate of the second chip 42. The second end of the first gate terminal 63 extends to the outside of the package shell 10. The first power terminal 61 is located between the first insulating rib 71 and the second insulating rib 72. The semiconductor package structure further includes a second gate terminal 65 and a third insulating rib 73. The second gate terminal 65 is located on a side of the second chip module 50 away from the first insulating rib 71. The third insulating rib 73 is located between the second gate terminal 65 and the second chip module 50. The first end of the second gate terminal 65 is conductively connected to the gate of the second chip module 50. The second end of the second gate terminal 65 extends to the outside of the package shell 10. The second power terminal 62 and the second gate terminal 65 are located on the same side of the third insulating rib 73.

[0054] Specifically, Figure 4 For example, the first insulating rib 71, the second insulating rib 72, and the third insulating rib 73 are all along Figure 4 The two ends of each insulating rib are connected to the two inner surfaces of the enclosure 13. The first insulating rib 71, the second insulating rib 72, and the third insulating rib 73 are connected along the Figure 4 The three insulating ribs are arranged at intervals in the left and right directions, and the substrate 11 is divided into a first area, a second area, a third area and a fourth area which are isolated from each other from left to right; the first gate terminal 63 is located in the first area, the first power terminal 61, the first chip module 40 and the first conductive connection part 20 are located in the second area, the second chip module 50 and the second conductive connection part 30 are located in the third area, the second power terminal 62 and the second gate terminal 65 are located in the fourth area, the first insulating rib 71, the second insulating rib 72 and the third insulating rib 73 increase the surface distance between the components in the two adjacent areas, thereby ensuring the insulation performance of the semiconductor packaging structure. In this embodiment, the potential of the components in the first area is 6.5Kv, the potential of the components in the second area is 13Kv, the potential of the components in the third area is 6.5Kv, and the potential of the components in the fourth area is 10v. In addition, the semiconductor packaging structure of this embodiment also includes a first driving terminal 64 and a second driving terminal 66. The first driving terminal 64 is located in the first region, and the auxiliary source of the first chip 41 and the auxiliary source of the second chip 42 are both conductively connected to the first driving terminal 64. The second driving terminal 66 is located in the fourth region, and the auxiliary source of the third chip 51 and the auxiliary source of the fourth chip 52 are both conductively connected to the second driving terminal 66.

[0055] like Figures 1 to 8 As shown, the enclosure 13 includes a first side plate 131 and a second side plate 132 that are oppositely disposed, the second end of the first power terminal 61 passes through the first side plate 131, and the second end of the second power terminal 62 passes through the second side plate 132. Specifically, since the first power terminal 61 and the second power terminal 62 pass through the oppositely disposed side plates of the enclosure 13, respectively, the creepage distance between the first power terminal 61 and the second power terminal 62 is increased, thereby further ensuring the insulation performance of the semiconductor packaging structure.

[0056] like Figures 1 to 8 As shown, the enclosure 13 further includes a third side plate 133, the third side plate 133 is connected between the first end of the first side plate 131 and the first end of the second side plate 132, the first chip module 40 is located between the third side plate 133 and the first insulating rib 71, and the first gate terminal 63 is located at the connection between the third side plate 133 and the second side plate 132. Specifically, in this arrangement, the first gate terminal 63 is arranged in the first region at a position relatively far from the first power terminal 61 in the second region, so that there is a large creepage distance between the first gate terminal 63 and the first power terminal 61.

[0057] like Figures 1 to 8 As shown, the enclosure 13 further includes a fourth side plate 134, the fourth side plate 134 is connected between the second end of the first side plate 131 and the second end of the second side plate 132, the second chip module 50 is located between the fourth side plate 134 and the first insulating rib 71, and the second gate terminal 65 is disposed adjacent to the fourth side plate 134 and spaced from the second side plate 132. Specifically, the second gate terminal 65 is disposed adjacent to the fourth side plate 134 so that the second gate terminal 65 is disposed at Figure 4 The second gate terminal 65 is spaced apart from the second side plate 132 so that the second gate terminal 65 is located at a distance from the first power terminal 61 in the left-right direction. Figure 4 The second gate terminal 65 is farther away from the first power terminal 61 in the vertical direction, so that the creepage distance between the second gate terminal 65 and the first power terminal 61 is larger.

[0058] like Figures 3 to 6As shown, the first chip module 40 also includes a first freewheeling structure 43, which is arranged on the first conductive connection portion 20, and the source of the first freewheeling structure 43 is conductively connected to the drain of the first chip 41 through the first conductive connection portion 20, and the drain of the first freewheeling structure 43 is electrically connected to the source of the first chip 41. Specifically, the first freewheeling structure 43 is a freewheeling diode, and the first freewheeling structure 43 is conductively connected to the first chip 41 in an "anti-parallel" manner, so that when the first chip 41 is turned off, the remaining current of the first chip 41 is consumed, thereby protecting the first chip 41. In this embodiment, the semiconductor packaging structure includes a plurality of freewheeling structures, and the plurality of freewheeling structures are arranged one-to-one with the plurality of chips and conductively connected in the same manner, and play the same role as the first freewheeling structure 43.

[0059] like Figures 3 to 6 As shown, the semiconductor package structure also includes a conductive interconnect 80 and an insulating adhesive layer. The conductive interconnect 80 is connected between the power source electrode of the first chip 41 and the second conductive connection part 30. The insulating adhesive layer is filled and arranged on the substrate 11. The power source electrode and the first insulating rib 71 are both located in the insulating adhesive layer. Specifically, the inner cavity of the package shell 10 is also filled with an insulating colloid to form an insulating adhesive layer to ensure the insulation performance of the semiconductor package structure. The insulating adhesive layer can be made of silicone gel or silicone rubber. Silicone rubber has the following insulation advantages: Silicone rubber has excellent insulation performance, and its corona resistance and arc resistance are very good, which makes it very popular in electrical and electronic applications. The physical structural properties of silicone rubber are better than general rubber at high and low temperatures, which provides advantages for its insulation application in extreme environments. Silicone rubber also has good oil resistance and chemical resistance, which makes it very suitable as an insulating material in the chemical industry and oily environments. Silicone gel has the following insulation advantages: The softness of silicone gel after curing makes it perform well in applications requiring flexible insulation, such as filling and insulation inside electronic equipment. Silicone gel has good dustproof, moisture-proof and shockproof properties, which are essential for protecting electronic components from environmental influences. The insulating properties of silicone gel also include good thermal stability, which can be used in a wide temperature range, from -60℃ to 230℃.

[0060] like Figures 3 to 6 As shown, the conductive interconnection 80 includes a bonding wire 81, and at least part of the bonding wire 81 crosses the first insulating rib 71. The bonding wire 81 can be stably connected to the power source electrode of the first chip 41 and the second conductive connection part 30, thereby ensuring that the power source electrode of the first chip 41 and the second conductive connection part 30 are conductively connected. The conductive interconnection 80 can also be used for conductive connection between other components. In other embodiments, the conductive interconnection includes a metal guide plate, and a through hole is provided on the first insulating rib, and the metal guide plate is penetrated through the through hole.

[0061] like Figure 7 As shown, the semiconductor packaging structure further includes a chamfered connection portion 90, which is connected between the substrate 11 and the enclosure 13; and the chamfered connection portion 90 is connected between the substrate 11 and the first insulating rib 71. Specifically, the chamfered connection portion 90 reduces the sharp angle structure inside the packaging shell 10, which can effectively reduce the electric field inside the semiconductor packaging structure. On the other hand, it is helpful to reduce the defects of the potting insulation colloid process, which is beneficial to the degassing effect of the degassing step in the process of potting the insulation colloid to form the insulation glue layer, and reduces the possibility of residual bubbles.

[0062] In addition, in the present embodiment, the height of the first insulating rib 71 is between 0 and 3 mm; the width of the first insulating rib 71 is between 0 and 2 mm. Specifically, such a configuration can ensure that the surface distance between the structures on both sides of the first insulating rib 71 is large, thereby meeting the insulation requirements of the semiconductor packaging structure. The height of the first insulating rib 71 can be 0.6 mm, 1 mm, 1.7 mm, 2 mm, 2.3 mm or 3 mm; the width of the first insulating rib 71 can be 0.6 mm, 0.8 mm, 1 mm, 1.5 mm, 1.9 mm or 2 mm. It should be noted that the height of the first insulating rib 71 is greater than 0, and the width of the first insulating rib 71 is also greater than 0.

[0063] In addition, in the present embodiment, the substrate 11 and the enclosure 13 are an integral structure, so that the packaging shell 10 has a strong structural strength; the packaging shell 10 is made of ceramics, such as aluminum oxide, aluminum nitride, silicon nitride, zirconium oxide, silicon carbide, etc. Aluminum oxide has excellent structural strength and chemical corrosion resistance, and is suitable for applications with high durability requirements. Zirconium oxide is known for its outstanding toughness and high temperature resistance, and performs well in high temperature and high stress environments. Aluminum nitride has high thermal conductivity and low expansion coefficient, can effectively dissipate heat, and is suitable for high-power electronic devices. Silicon carbide not only has high hardness and high wear resistance, but also can remain stable at extremely high temperatures, making it very popular in high-temperature electronic devices and high-frequency applications. The diversity and excellent properties of these ceramic materials provide a wide range of choices and significant performance improvements for the design and application of semiconductor packaging structures.

[0064] In addition, in this embodiment, the first conductive connection part 20 and the second conductive connection part 30 can be made of copper, and the substrate 11 is made of ceramic, that is, the first conductive connection part 20 and the substrate 11 and the second conductive connection part 30 and the substrate 11 can be made by copper cladding on a ceramic substrate. The above copper-clad ceramic structure can be made in the following ways: DBC (Direct Bonded Copper): Through the hot melt bonding method, copper foil is directly sintered to the surface of Al2O3 and AlN ceramics at high temperature to form a composite substrate. Thanks to the high eutectic bonding strength between copper foil and ceramic, the copper thickness of the DBC substrate can generally be 100μm-600μm. At the same time, ceramic and copper have good thermal conductivity, and the thermal stability of the DBC substrate is also good. AMB (Active Metal Brazing): AMB is developed on the basis of DBC technology. At high temperature, AgCu solder containing active elements Ti and Zr wets and reacts at the interface between ceramic and metal, thereby realizing heterogeneous bonding between ceramic and metal.

[0065] In this embodiment, the AMB process is adopted, and the AMB process has the following advantages: Improve wettability: The active elements can significantly improve the wettability of the brazing material on the material to be welded, making it easier for the brazing material to flow and fill the weld. Reduce the brazing temperature: Since the active elements improve the wettability, the brazing process can be carried out at a lower temperature, thereby reducing the heat-affected zone and thermal stress. Reduce oxidation: During the active brazing process, the active elements can reduce the oxidation of the surface of the material to be welded, and improve the cleanliness and quality of the weld. Improve the strength of the joint: Active brazing can form a more uniform and denser weld, thereby improving the structural strength and durability of the joint. Improve corrosion resistance: The weld formed by active brazing has better corrosion resistance, especially in applications under harsh environments. Reduce brazing consumption: Since the active elements improve the fluidity of the brazing material, the amount of brazing material used can be reduced, reducing costs. Improve production efficiency: The active brazing process can shorten the welding time and improve production efficiency, especially in mass production. Strong adaptability: Active brazing is suitable for the welding of a variety of materials, including metals, ceramics and composite materials, which expands the application range of brazing. Reduced post-processing: Due to the improved weld quality, the need for post-processing after active brazing is reduced, such as grinding, cleaning, etc. Environmentally friendly: The active brazing process produces less harmful gases and solid waste, which has less impact on the environment. Improved welding quality: Active brazing can reduce welding defects such as pores, cracks and lack of fusion, thereby improving the overall quality of the welded joint.

[0066] In addition, in the present embodiment, the semiconductor packaging structure also includes a heat sink, which is connected to the outer surface of the substrate 11. The number of heat sinks is greater than 2, and the heat sink is a cylindrical structure, and a plurality of heat sinks are arranged in an array. In other embodiments, the heat sink can be a heat sink fin. In addition, in other embodiments, the semiconductor packaging structure also includes a heat sink, and the heat sink cover is arranged on the outer surface of the substrate so that a heat sink cavity is formed between the substrate and the heat sink, and the heat sink is provided with an inlet and an outlet connected to the heat sink cavity so that the heat sink medium can flow in the heat sink cavity, and the heat sink medium can take away the heat of the heat sink to achieve the effect of cooling the semiconductor chip, and the heat sink medium can be a heat transfer oil. In addition, the heat transfer medium can also be an electronic fluorinated liquid. The heat transfer oil can be a mineral heat transfer oil, an alkylbenzene heat transfer oil, an alkylnaphthalene heat transfer oil, an alkylbiphenyl heat transfer oil, a low-melting mixture of biphenyl and biphenyl ether, or an alkylbiphenyl ether heat transfer oil. The mineral heat transfer oil is a product of a certain distillation range in the petroleum refining process, and the main component is a mixture of long-chain alkanes and cycloalkanes. This type of heat transfer oil usually has good thermal conductivity and cost-effectiveness, and is suitable for medium and low temperature ranges; alkylbenzene type heat transfer oil is a compound with alkane side chains attached to the benzene ring, has a low vapor pressure, and does not vaporize under normal operation; it has good thermal stability and is suitable for applications below 300°C; alkylnaphthalene type heat transfer oil: The structure is a compound with alkane side chains attached to the benzene ring, which is suitable for gas phase heating systems in the range of 240~280°C; alkylbiphenyl type heat transfer oil is composed of a short-chain alkyl group combined with a biphenyl ring, has high thermal stability, and is suitable for use in the range of 300~340°C; biphenyl and biphenyl ether low-melting mixture type heat transfer oil is composed of 26.5% biphenyl and 73.5% biphenyl ether, has good thermal stability and high operating temperature (400°C), and is suitable for use in the range of 256~258°C; alkylbiphenyl ether type heat transfer oil is linked by an ether group in the middle of two benzene rings, has low viscosity and good fluidity, is suitable for use in low temperature environments, and the recommended maximum operating temperature does not exceed 330°C.

[0067] It should be noted that, taking the first chip module 40 and the first conductive connection part 20 as an example, the first chip module 40 is directly connected to the substrate 11 through the first conductive connection part 20. In the related art, the package shell of the power semiconductor device is usually made of polymer insulating material, the power semiconductor chip is arranged on the liner, and the liner is connected to the inner surface of the package shell through a connecting layer (generally a metal compound plate structure made of copper or aluminum). In addition to increasing the thermal resistance of the heat dissipation path from the power semiconductor chip to the package shell, the liner needs to be pre-bent because the thermal expansion coefficient of the plate body of the package shell connected to the liner is not matched with the liner itself, thereby increasing the stress on the liner and reducing the reliability of the power semiconductor device. Compared with the solution in the related art of connecting the packaging shell and the power semiconductor chip through a lining plate and a connecting part between the lining plate and the shell, this embodiment simplifies the heat dissipation path between the first chip module 40 and the substrate 11, and reduces the thermal resistance on the heat dissipation path, so that the heat generated by the first chip module 40 during operation can be better transferred to the packaging shell 10, which is more conducive to the heat dissipation of the first chip module 40.

[0068] In addition, a coating is provided on the first chip module 40 and the second chip module 50. In addition, a coating can be provided on the periphery of the conductive interconnect 80, between the insulating glue layer and the substrate 11, and between the conductive connection part and the substrate 11. The preferred coating can be a PI coating, which can include multiple layers. PI is polyimide. The PI coating can ensure the insulation, long-term temperature resistance and water vapor isolation of the first chip module 40 and the second chip module 50. There are many significant benefits to coating the first chip module 40 and the second chip module 50 with a PI coating, especially in improving the performance, reliability and durability of the first chip module 40 and the second chip module 50. The following are several main advantages of using a PI coating: 1. Excellent thermal stability: Polyimide material has excellent thermal stability and can maintain its physical and chemical properties in a high temperature environment. For chips working under high temperature conditions, the PI coating can effectively protect the chip from thermal stress, thereby extending the service life of the chip. PI materials are generally able to withstand high temperatures, which makes it very valuable in high-temperature electronic devices and high-power applications. 2. Electrical insulation performance: The PI coating has good electrical insulation performance and can prevent electrical short circuits and leakage inside the chip. Its high insulation ensures the safe operation of the chip in high voltage and high frequency environments, reducing the risk of electrical failure. This is especially important for electronic devices that require high reliability. 3. Structural strength and flexibility: Polyimide materials have both high structural strength and flexibility, and can resist external stress and impact. The PI coating applied to the surface of the chip can provide additional protection to prevent the chip from structural damage during manufacturing, transportation and use. At the same time, the flexibility of the PI coating enables it to adapt to slight deformations and stress changes on the surface of the chip, maintaining the integrity and effectiveness of the coating. 4. Chemical corrosion resistance: PI materials have excellent chemical corrosion resistance and can resist erosion by various chemical reagents, solvents and corrosive gases. Applying PI coating can effectively protect the chip from chemical corrosion, especially in some harsh working environments such as industrial control, chemical production and environmental monitoring equipment. 5. Low dielectric constant: Polyimide has a low dielectric constant, which is an important advantage for high-speed and high-frequency circuits. Low dielectric constant helps reduce loss and delay during signal transmission, improve signal transmission speed and integrity, and thus improve chip performance and efficiency. 6. Process compatibility: PI coating can be applied by a variety of process methods, such as spin coating, spray coating and dip coating, and the process is relatively simple and suitable for large-scale production. This process compatibility enables PI coating to be widely used in the manufacture of different types of chips and electronic devices, providing a flexible solution.

[0069] In the description of the present invention, it is necessary to understand that the directions or positional relationships indicated by directional words such as "front, back, up, down, left, right", "lateral, vertical, perpendicular, horizontal" and "top, bottom" are usually based on the directions or positional relationships shown in the drawings. They are only for the convenience of describing the present invention and simplifying the description. Unless otherwise specified, these directional words do not indicate or imply that the devices or elements referred to must have a specific direction or be constructed and operated in a specific direction. Therefore, they cannot be understood as limiting the scope of protection of the present invention. The directional words "inside and outside" refer to the inside and outside relative to the contours of each component itself.

[0070] For ease of description, spatially relative terms such as "above", "above", "on the upper surface of", "above", etc. may be used herein to describe the spatial positional relationship between a device or feature and other devices or features as shown in the figure. It should be understood that spatially relative terms are intended to include different orientations of the device in use or operation in addition to the orientation described in the figure. For example, if the device in the accompanying drawings is inverted, the device described as "above other devices or structures" or "above other devices or structures" will be positioned as "below other devices or structures" or "below other devices or structures". Thus, the exemplary term "above" may include both "above" and "below". The device may also be positioned in other different ways (rotated 90 degrees or in other orientations), and the spatially relative descriptions used herein are interpreted accordingly.

[0071] In addition, it should be noted that the use of terms such as "first" and "second" to limit components is only for the convenience of distinguishing the corresponding components. If not otherwise stated, the above terms have no special meaning and therefore cannot be understood as limiting the scope of protection of the present invention.

[0072] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. For those skilled in the art, the present invention may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

Claims

1. A semiconductor packaging structure, characterized in that: include: A packaging shell (10) comprising a substrate (11); A first chip module (40) connected to the substrate (11), the first chip module (40) comprising a plurality of first semiconductor chips, the plurality of first semiconductor chips being connected in parallel; A second chip module (50) connected to the substrate (11), the second chip module (50) being connected in series with the first chip module (40); A first power terminal (61) conductively connected to the first chip module (40); A second power terminal (62) conductively connected to the second chip module (50); The semiconductor packaging structure further comprises a first insulating convex rib (71) connected to the substrate (11), and the first chip module (40) and the second chip module (50) are respectively located on two sides of the first insulating convex rib (71); The semiconductor packaging structure further comprises a first gate terminal (63) and a second insulating rib (72), wherein the first gate terminal (63) is located on a side of the first chip module (40) away from the first insulating rib (71), the second insulating rib (72) is located between the first gate terminal (63) and the first chip module (40), the first gate terminal (63) is conductively connected to the plurality of first semiconductor chips, and the first power terminal (61) is located between the first insulating rib (71) and the second insulating rib (72).

2. The semiconductor package structure according to claim 1, wherein: The second chip module (50) comprises a plurality of second semiconductor chips, and the plurality of second semiconductor chips are connected in parallel.

3. The semiconductor package structure according to claim 1, wherein: The semiconductor packaging structure further comprises a second gate terminal (65) and a third insulating rib (73); the second gate terminal (65) is located on a side of the second chip module (50) away from the first insulating rib (71); the third insulating rib (73) is located between the second gate terminal (65) and the second chip module (50); the second gate terminal (65) is conductively connected to the second chip module (50); and the second power terminal (62) and the second gate terminal (65) are located on the same side of the third insulating rib (73).

4. The semiconductor package structure according to claim 3, characterized in that: The packaging shell (10) further comprises a surrounding plate (13) connected to the substrate (11), the surrounding plate (13) comprising a first side plate (131) and a second side plate (132) arranged opposite to each other, the first power terminal (61) passing through the first side plate (131), and the second power terminal (62) passing through the second side plate (132).

5. The semiconductor package structure according to claim 4, characterized in that: The enclosure (13) further comprises a third side plate (133), the third side plate (133) being connected between a first end of the first side plate (131) and a first end of the second side plate (132), the first chip module (40) being located between the third side plate (133) and the first insulating rib (71), and the first gate terminal (63) being located at a connection between the third side plate (133) and the second side plate (132).

6. The semiconductor package structure according to claim 5, characterized in that: The enclosure (13) further comprises a fourth side plate (134), the fourth side plate (134) being connected between the second end of the first side plate (131) and the second end of the second side plate (132), the second chip module (50) being located between the fourth side plate (134) and the first insulating rib (71), and the second gate terminal (65) being arranged adjacent to the fourth side plate (134) and spaced apart from the second side plate (132).

7. The semiconductor package structure according to any one of claims 1 to 6, characterized in that: The semiconductor packaging structure further comprises a first conductive connection portion (20) arranged on the substrate (11), the first chip module (40) being arranged on the first conductive connection portion (20), the first chip module (40) further comprising a first freewheeling structure (43), the first freewheeling structure (43) being arranged on the first conductive connection portion (20), the source of the first freewheeling structure (43) being conductively connected to a drain of the first semiconductor chip via the first conductive connection portion (20), and the drain of the first freewheeling structure (43) being conductively connected to the source of the first semiconductor chip.

8. The semiconductor package structure according to claim 1 or 3 or 4 or 5 or 6, characterized in that: The semiconductor packaging structure further comprises a second conductive connection portion (30) arranged on the substrate (11), the second chip module (50) being arranged on the second conductive connection portion (30), the semiconductor packaging structure further comprises a conductive interconnection member (80) and an insulating adhesive layer, the conductive interconnection member (80) being connected between the first semiconductor chip and the second conductive connection portion (30), the insulating adhesive layer being filled and arranged on the substrate (11), and the conductive interconnection member (80) and the first insulating rib (71) being both located within the insulating adhesive layer.

9. The semiconductor package structure according to claim 8, characterized in that: The conductive interconnect (80) comprises a bonding wire (81), at least part of the bonding wire (81) spans over the first insulating rib (71); and / or, The conductive interconnection member (80) comprises a metal guide plate, a through hole is provided on the first insulating convex rib (71), and the metal guide plate is passed through the through hole.

10. The semiconductor package structure according to any one of claims 4 to 6, characterized in that: The semiconductor packaging structure further comprises a chamfered connection portion (90), wherein the chamfered connection portion (90) is connected between the substrate (11) and the enclosure (13); and / or the chamfered connection portion (90) is connected between the substrate (11) and the first insulating rib (71).

11. The semiconductor package structure according to claim 1 or 3 or 4 or 5 or 6, characterized in that: The height of the first insulating rib (71) is greater than 0 and less than or equal to 3 mm; and / or, The width of the first insulating rib (71) is greater than 0 and less than or equal to 2 mm.

12. The semiconductor package structure according to any one of claims 4 to 6, characterized in that: The packaging shell (10) is made of ceramic; and / or, The base plate (11) and the enclosure plate (13) are an integral structure.

13. The semiconductor package structure according to any one of claims 1 to 6, characterized in that: The semiconductor packaging structure also includes a heat sink, which is connected to the outer surface of the substrate (11).

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