Horizontal structure LED chip and preparation method thereof

Abstract

The present invention discloses a horizontal structure LED chip and a preparation method thereof, and relates to the field of semiconductor optoelectronic devices. The preparation method of the LED chip comprises the following steps: S1, providing an epitaxial wafer; S2, etching the surface of the epitaxial wafer to form a plurality of protrusions; S3, forming a dielectric layer on the epitaxial wafer obtained in step S2; S4, etching the dielectric layer to form a first through hole; S5, forming a metal reflective layer; S6, forming a bonding layer on the metal reflective layer; S7, bonding with a second substrate; S8, removing the first substrate to expose the N-type semiconductor layer; S9, forming an N-electrode on the N-type semiconductor layer; S10, etching to form a second through hole etched to the P-type contact layer; S11, forming a P-electrode to obtain an LED wafer; the P-electrode is electrically connected to the P-electrode through the second through hole; S12, cutting the LED wafer to obtain a horizontal structure LED chip. Implementation of the present invention can improve light extraction efficiency and improve the reliability of the horizontal structure LED chip.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor optoelectronic devices, and in particular to a horizontal structure LED chip and a preparation method thereof. Background Art

[0002] Currently, the optical reflector (ODR) reflective structure, formed by combining a DBR layer with a metal layer, is a relatively new approach to improving the light extraction efficiency of LED chips. There are three main types of structures: one is a horizontal dielectric layer + a horizontal metal reflective layer. This ODR reflective structure has a small reflector area, making it difficult to effectively increase the reflective area and thus less effective in improving light extraction efficiency. Another approach is to etch away part of the active area to form a reflector with a certain angle. While this solution effectively increases the area of ​​the ODR reflector and changes the reflector angle, it requires etching away part of the active area, which reduces the effective light-emitting area. Furthermore, damage caused by etching the active area may cause reliability issues such as leakage. Another approach is to create a micro-vacuum structure with hemispherical grooves to improve light reflectivity. However, due to the presence of a quasi-vacuum cavity within the chip, this structure significantly increases the risk of epitaxial layer fracture when subjected to external pressure during die bonding and wire bonding. Summary of the Invention

[0003] The technical problem to be solved by the present invention is to provide a horizontal structure LED chip and a preparation method thereof, which can effectively improve the light extraction efficiency without damaging the active layer and has higher reliability.

[0004] In order to solve the above technical problems, the present invention provides a method for preparing a horizontal structure LED chip, which comprises the following steps:

[0005] S1. Providing an epitaxial wafer, the epitaxial wafer comprising a first substrate and an N-type semiconductor layer, an active layer, and a P-type semiconductor layer sequentially disposed on the first substrate; the P-type semiconductor layer comprising a first preset region and a second preset region;

[0006] S2. Etching the P-type contact layer to form a plurality of protrusions in a first predetermined area, with grooves provided between adjacent protrusions; the height of the protrusions being less than or equal to 50% of the thickness of the P-type contact layer;

[0007] S3. Forming a dielectric layer on the epitaxial wafer obtained in step S2, wherein the thickness of the dielectric layer is less than the depth of the groove, and the refractive index of the dielectric layer is less than the refractive index of the P-type contact layer;

[0008] S4, etching the dielectric layer to form a plurality of first through holes on top of the protrusions to expose the protrusions;

[0009] S5, forming a metal reflective layer on the epitaxial wafer obtained in step S4, wherein the metal reflective layer fills the groove;

[0010] S6, forming a bonding layer on the metal reflective layer;

[0011] S7, bonding the epitaxial wafer obtained in step S6 to the second substrate;

[0012] S8, removing the first substrate to expose the N-type semiconductor layer;

[0013] S9, forming an N electrode on the N-type semiconductor layer to obtain an intermediate;

[0014] S10, forming a plurality of second through holes etched to the P-type contact layer on the intermediate body; the second through holes are provided in the second predetermined area;

[0015] S11, forming a P electrode on the intermediate obtained in step S10 to obtain an LED wafer; the P electrode is electrically connected to the P electrode through the second through hole;

[0016] S12, cutting the LED wafer to obtain horizontal structure LED chips.

[0017] As an improvement to the above technical solution, step S10 includes:

[0018] S101: forming a plurality of second through holes etched to the P-type contact layer on the intermediate body, wherein the second through holes are provided in the second predetermined area;

[0019] S102: forming a plurality of third through holes etched to the metal reflective layer in the second through hole; the P electrode is electrically connected to the metal reflective layer through the third through holes.

[0020] As an improvement of the above technical solution, the bonding layer is an Au layer or an Ag layer, and its thickness is 300nm~800nm;

[0021] In step S7, a Ag layer or an Au layer is provided on the surface of the second substrate; the epitaxial wafer obtained in step S6 is bonded to the second substrate by thermal compression bonding, wherein the metal reflective layer and the bonding layer are pressed against each other during bonding to fill the gaps on the surface of the epitaxial wafer;

[0022] Among them, the bonding temperature is 200℃~360℃, and the bonding pressure is 8000kgf~15000kgf.

[0023] As an improvement to the above technical solution, step S5 includes:

[0024] S51: forming a metal reflective layer on the epitaxial wafer obtained in step S4;

[0025] S52: Annealing the epitaxial wafer obtained in step S51 so that the metal reflective layer forms an ohmic contact with the P-type contact layer.

[0026] As an improvement of the above technical solution, the thickness of the P-type contact layer is 1 μm to 10 μm, and its doping concentration is ≥ 1×10 18 cm -3 and / or

[0027] The protrusions are in the shape of a truncated cone, an ellipsoidal crown or a prism, the height of the protrusions is 0.5 μm to 5 μm, and the distance between adjacent protrusions is 0.5 μm to 10 μm; and / or

[0028] The height of the protrusion is 20% to 35% of the thickness of the P-type contact layer; and / or

[0029] The dielectric layer is one or more of a SiO2 layer, a MgF2 layer, a TiO2 layer, and a Ti2O5 layer; the thickness of the dielectric layer is 0.2 μm to 4 μm; and / or

[0030] The metal reflective layer is one or more of an Au layer, an Ag layer, and an Al layer, and the thickness of the metal reflective layer is 0.5 μm to 10 μm.

[0031] As an improvement of the above technical solution, the thickness of the P-type contact layer is 2 μm to 4 μm, and its doping concentration is 2×10 18 cm -3 ~5×10 20 cm -3 and / or

[0032] The protrusions are truncated cone-shaped, the height of the protrusions is 0.5 μm to 1.8 μm, and the distance between adjacent protrusions is 0.5 μm to 3 μm; and / or

[0033] The dielectric layer is a SiO2 layer with a thickness of 0.3 μm to 1 μm; and / or

[0034] The metal reflective layer is an Au layer, and its thickness is 0.8 μm to 2 μm.

[0035] As an improvement of the above technical solution, the doping concentration of the P-type contact layer increases from the side close to the active layer to the side close to the dielectric layer.

[0036] As an improvement of the above technical solution, the epitaxial wafer includes a first substrate, an N-type GaAs buffer layer, an N-type GaInP etching stop layer, an N-type semiconductor layer, an active layer, a P-type semiconductor layer and a P-type contact layer sequentially arranged on the first substrate;

[0037] The first substrate is a GaAs substrate;

[0038] The second substrate is a sapphire substrate;

[0039] The N-type semiconductor layer includes an N-type GaAs ohmic contact layer, an N-type AlGaInP roughening layer and an N-type AlGaInP current spreading layer, which are arranged on the N-type GaInP etching stop layer in sequence;

[0040] The P-type semiconductor layer is a P-type AlGaInP confinement layer;

[0041] The P-type contact layer is a P-type GaP window layer.

[0042] As an improvement of the above technical solution, in step S8, the first substrate and the N-type GaInP etching stop layer are removed to expose the N-type GaAs ohmic contact layer, and the N-type GaAs ohmic contact layer is etched to form a contact pattern;

[0043] In step S9, an N electrode is formed on the contact pattern, and the N-type AlGaInP roughening layer is roughened;

[0044] In step S11, a P electrode is first formed on the intermediate body obtained in step S10, and then a passivation protection layer is formed, and then etching is performed to expose the N electrode and the P electrode, thereby obtaining an LED wafer.

[0045] Correspondingly, the present invention also discloses a horizontal structure LED chip, which is prepared by the above-mentioned method for preparing the horizontal structure LED chip.

[0046] The implementation of the present invention has the following beneficial effects:

[0047] 1. In the preparation method of the horizontal structure LED chip of the present invention, a process of etching the P-type contact layer to form a protrusion - forming a dielectric layer - etching the dielectric layer to form a first through hole - forming a metal reflective layer is adopted to form a micro-mirror. Based on this process: First, by controlling the height of the protrusion to be less than or equal to 50% of the thickness of the P-type contact layer, excessive etching to damage the MQW active area is avoided, and the effective light-emitting area is not lost. Second, etching thins the P-type contact layer and reduces the light absorption of the P-type contact layer. Third, by controlling the refractive index of the dielectric layer to be less than the refractive index of the P-type contact layer, and the composite metal reflective layer, a micro-mirror structure is formed, which greatly increases the reflection area of ​​the micro-mirror, changes the reflection angle, improves the light reflectivity, and thus improves the light extraction efficiency. Fourth, the layers are tightly combined without gaps, which avoids damage to the LED chip during the later solidification and wire bonding, thereby improving reliability.

[0048] 2. In the preparation method of the horizontal structure LED chip of the present invention, the P electrode is electrically connected to the metal reflective layer through the third through hole, and the metal reflective layer is connected to the P-type contact layer through the first through hole of the array. Through this structure, the uniformity of current injection is greatly improved, the thickness of the P-type contact layer is reduced, the light absorption is reduced, the light extraction efficiency is further improved, and the production cost is also reduced.

[0049] 3. In the method for preparing a horizontal structure LED chip of the present invention, the shape of the protrusion is controlled to be an ellipsoidal crown, a truncated cone, or a prism. The protrusion is made small at the top and large at the bottom, and has an inclined surface, which can effectively increase the reflection area and change the reflection angle.

[0050] 4. In the preparation method of the horizontal structure LED chip of the present invention, by controlling the materials of the metal reflective layer and the bonding layer, and selecting the hot pressing bonding process, during the bonding process, the ductile metal is squeezed to fill the pits without leaving any gaps, that is, there is no cavity inside the chip. During the processes of solid crystal and wire bonding, the risk of the epitaxial layer being subjected to pressure and breaking can be greatly reduced. BRIEF DESCRIPTION OF THE DRAWINGS

[0051] Figure 1 1 is a schematic structural diagram of an epitaxial wafer in one embodiment of the present invention;

[0052] Figure 2 2 is a schematic diagram of the structure of the epitaxial wafer after step S2 in one embodiment of the present invention;

[0053] Figure 3 2 is a schematic diagram of the structure of the epitaxial wafer after step S4 in one embodiment of the present invention;

[0054] Figure 4 2 is a schematic diagram of the structure of the epitaxial wafer after step S6 in one embodiment of the present invention;

[0055] Figure 5 2 is a schematic diagram of the structure of the epitaxial wafer after step S7 in one embodiment of the present invention;

[0056] Figure 6 2 is a schematic diagram of the structure of the epitaxial wafer after step S8 in one embodiment of the present invention;

[0057] Figure 7 This is a schematic structural diagram of the intermediate after step S9 in one embodiment of the present invention;

[0058] Figure 8 2 is a schematic diagram of the structure of a horizontal structure LED chip after step S12 in one embodiment of the present invention;

[0059] Figure 9 1 is a schematic top view of a horizontally structured LED chip according to an embodiment of the present invention;

[0060] In the figure, 1 is an epitaxial wafer, 11 is a first substrate, 12 is an N-type semiconductor layer, 121 is an N-type GaAs ohmic contact layer, 122 is an N-type AlGaInP roughening layer, 123 is an N-type AlGaInP current spreading layer, 124 is an N-type AlGaInP limiting layer, 13 is an active layer, 14 is a P-type semiconductor layer, 15 is a P-type contact layer, 151 is a first preset area, 152 is a second preset area, 153 is a protrusion, 154 is a groove, 155 is a third through hole, 16 is an N-type GaAs buffer layer, 17 is an N-type GaInP corrosion stop layer, 2 is a dielectric layer, 21 is a first through hole, 3 is a metal reflective layer, 5 is a second substrate, 51 is a sub-bonding layer, 6 is an N-electrode, 61 is an N-electrode extension strip, 7 is an intermediate body, 71 is a second through hole, 8 is a P-electrode, and 9 is a passivation protection layer. DETAILED DESCRIPTION

[0061] In order to make the objectives, technical solutions and advantages of the present invention more clear, the present invention is described in further detail below.

[0062] The present invention provides a method for preparing a horizontal structure LED chip, which comprises the following steps:

[0063] S1: Provide epitaxial wafers;

[0064] Ginseng Figure 1 The epitaxial wafer 1 includes a first substrate 11, and an N-type semiconductor layer 12, an active layer 13, a P-type semiconductor layer 14, and a P-type contact layer 15 sequentially arranged on the first substrate 11. Specifically, the LED chip of the present invention can be a red, green, yellow, or purple LED chip. Based on the control of the emission wavelength, different types of semiconductor layers, active layers, and contact layers can be selected. Exemplarily, in one embodiment, when the LED chip is a blue LED chip or a green LED chip, the N-type semiconductor layer 12 can be an N-type GaN layer, the active layer 13 can be an InGaN-GaN type multi-quantum well layer, the P-type semiconductor layer 14 can be a P-type GaN layer, and the P-type contact layer 15 can be a P-type InGaN layer or a highly doped P-type GaN layer, but is not limited thereto. In another embodiment, when the LED chip is a purple LED chip, the N-type semiconductor layer 12 may be an N-type AlGaN layer, the active layer 13 may be an AlGaN-AlGaN type multi-quantum well layer, the P-type semiconductor layer 14 may be a P-type AlGaN layer, and the P-type contact layer 15 may be a P-type GaN layer, but is not limited thereto.

[0065] Preferably, in one embodiment, the LED chip is a red LED chip, and the epitaxial wafer 1 includes an N-type GaAs buffer layer 16, an N-type GaInP etching stop layer 17, an N-type semiconductor layer 12, an active layer 13, a P-type semiconductor layer 14, and a P-type contact layer 15, which are sequentially disposed on a first substrate 11. The first substrate 11 is a GaAs substrate. The N-type semiconductor layer 12 includes an N-type GaAs ohmic contact layer 121, an N-type AlGaInP roughening layer 122, an N-type AlGaInP current spreading layer 123, and an N-type AlGaInP confinement layer 124, which are sequentially disposed on the N-type GaInP etching stop layer 17; the P-type semiconductor layer is a P-type AlGaInP confinement layer; and the P-type contact layer 15 is a P-type GaP window layer. The following steps are described using a red LED chip, but the technical solutions of the present invention are not limited to the red LED chip described herein.

[0066] Specifically, the thickness of the P-type contact layer 15 is 1μm to 10μm. If it is too thin, the active layer 13 may be easily damaged when etching to form the protrusions 153, reducing luminous efficiency. This also affects the current spreading function of the P-type contact layer 15. Furthermore, the height of the formed protrusions 153 is small, which has a weak effect on improving light extraction efficiency. If the thickness is greater than 10μm, excessive light absorption occurs, reducing light extraction efficiency. Preferably, the thickness of the P-type contact layer 15 is 1μm to 5μm, and more preferably 1.5μm to 4μm.

[0067] The P-type contact layer 15 includes a first preset area 151 and a second preset area 152 . The first preset area is subsequently etched to form a protrusion 153 and a groove 154 . The P-type contact layer 15 in the second preset area 152 is not etched to form a protrusion 153 .

[0068] Specifically, the P-type doping concentration of the P-type contact layer 15 is ≥1×10 18 cm -3 Preferably, the P-type doping concentration of the P-type contact layer 15 is 2×10 18 cm -3 ~5×10 20 cm -3 More preferably, the doping concentration of the P-type contact layer 15 increases from the side close to the active layer 13 to the side close to the dielectric layer 2, that is, the doping concentration of the surface layer is greater than the doping concentration of the bottom layer. Based on the above-mentioned doping concentration control, on the one hand, the high-doping concentration P-type contact layer in the subsequent second preset area is retained, thereby improving the ohmic contact with the metal reflective layer; on the other hand, the use of a lower doping concentration in the bottom layer can reduce defects, reduce light absorption, and reduce the adverse effects of leakage channels formed by etching when forming the protrusions 153 and the grooves 154.

[0069] S2: etching the P-type contact layer to form a plurality of protrusions in the first predetermined area;

[0070] Among them, reference Figure 2 The protrusion 153 has a small top and a large bottom, and its sides have inclined, curved, or spherical surfaces, which effectively increase the reflection area, change the reflection angle, and improve light extraction efficiency. Preferably, the protrusion 153 is in the shape of a truncated cone, an ellipsoidal crown, or a prism, but is not limited thereto. A truncated cone is more preferred.

[0071] Specifically, the height of protrusion 153 is less than or equal to 50% of the thickness of P-type contact layer 15 to prevent over-etching and damage to active layer 13, without losing effective light-emitting area, and also to mitigate the adverse effects on the current spreading function of P-type contact layer 15. Preferably, the height of protrusion 153 is 20% to 40% of the thickness of P-type contact layer 15, and more preferably 20% to 35%.

[0072] Specifically, the height of the protrusion 153 is 0.5 μm to 5 μm, preferably 0.5 μm to 1.8 μm.

[0073] The protrusions 153 are arranged in an array, and the distance between adjacent protrusions 153 is 0.5 μm to 10 μm. If the distance is too small, the ohmic contact function of the P-type contact layer 15 is affected. If the distance is too large, less light is reflected, and the effect of improving the light extraction efficiency is limited. Preferably, the distance between adjacent protrusions 153 is 0.5 μm to 4 μm, and more preferably 0.5 μm to 3 μm. Grooves 154 are provided between adjacent protrusions 153. Preferably, in one embodiment, reference Figure 9 The protrusions 153 cover the entire first preset area (ie, the light-emitting area), which can improve the light-emitting efficiency and further optimize the current distribution.

[0074] Specifically, the P-type contact layer 15 can be etched by dry etching or wet etching, but is not limited thereto. Preferably, the P-type contact layer 15 is etched by dry etching, which has high etching precision and can better control the distribution and shape of the protrusions 153.

[0075] S3: forming a dielectric layer on the epitaxial wafer obtained in step S2;

[0076] The refractive index of dielectric layer 2 is lower than that of P-type contact layer 15, allowing it to combine with protrusion 153 to improve light reflectivity. Specifically, dielectric layer 2 is one or more of, but not limited to, a SiO2 layer, a MgF2 layer, a TiO2 layer, or a Ti2O5 layer. Such dielectric layer 2 not only improves light reflectivity but also effectively passivates damage caused by etching, preventing electrical leakage. More preferably, dielectric layer 2 is a SiO2 layer.

[0077] Among them, see Figure 3The thickness of the dielectric layer 2 is smaller than the depth of the groove 154 . Specifically, the thickness of the dielectric layer 2 is 0.2 μm to 4 μm, preferably 0.3 μm to 1 μm.

[0078] S4: etching the dielectric layer to form a plurality of first through holes exposing the protrusions on top of the protrusions;

[0079] The first through hole 21 can be formed on the top of the protrusion 153 by dry etching or wet etching, but is not limited thereto. Preferably, the dielectric layer 2 is etched by dry etching to form the first through hole 21, which has high etching precision.

[0080] S5: forming a metal reflective layer on the epitaxial wafer obtained in step S4;

[0081] Among them, see Figure 4 The metal reflective layer 3 can be one or more of, but not limited to, an Au layer, an Ag layer, or an Al layer. Preferably, the Au layer has better adhesion, a reflectivity close to that of Ag, and can form a good ohmic contact with the protrusion 153. Furthermore, the Au layer has the smallest decrease in reflectivity after high-temperature annealing.

[0082] Specifically, the thickness of the metal reflective layer 3 is 0.5 μm to 10 μm. The metal reflective layer 3 in the present invention fills the groove 154 of the P-type contact layer 15. Preferably, the thickness of the metal reflective layer 3 is 0.8 μm to 2 μm.

[0083] Preferably, in one embodiment, step S5 includes:

[0084] S51: forming a metal reflective layer on the epitaxial wafer obtained in step S4;

[0085] S52: Annealing the epitaxial wafer obtained in step S51.

[0086] Among them, the annealing temperature is 360℃~500℃. Through annealing, the ohmic contact between the metal reflective layer 3 and the P-type contact layer 15 can be greatly optimized. The current injected through the P electrode can be evenly distributed to the entire ohmic P-type contact layer 15 through the metal reflective layer 3, which greatly optimizes the current expansion uniformity, thereby reducing the thickness of the P-type contact layer 15, reducing light absorption, and improving luminous efficiency. It should be noted that in conventional horizontally structured LED chips, the increase in the size of the LED chip makes the current expansion more uneven. The commonly used solutions are to prepare P-electrode extension strips and to increase the thickness of the P-type contact layer, which can usually reach 8μm~12μm. The present invention distributes the current through the metal reflective layer, so there is no need to prepare P-electrode extension strips, and the thickness of the P-type contact layer can also be reduced.

[0087] S6: forming a bonding layer on the metal reflective layer;

[0088] Depending on the subsequent bonding process, the bonding layer 4 can be formed on the metal reflective layer 3 using different materials. For example, when a eutectic bonding process is used, an Au layer, a Cu layer, an In layer, a Pb layer, or a Sn layer can be used, but is not limited thereto. For another example, when a hot compression bonding process is used, an Au layer, a Cu layer, an Ag layer, or an Al layer can be used as the bonding layer 4, but is not limited thereto.

[0089] Preferably, in one embodiment, a hot pressing bonding process is adopted for bonding, that is, the bonding layer 4 is selected from an Au layer or an Ag layer. The bonding layer 4 can assist the metal reflective layer 3 to improve the reflectivity of light; secondly, low-temperature hot pressing bonding can be adopted. During hot pressing bonding, the metal reflective layer 3 and the bonding layer 4 have ductility under the joint action of temperature and pressure, so that the metal is squeezed to fill the gaps on the surface of the epitaxial wafer, that is, the resulting chip has no cavity, and can withstand higher pressure without breaking in the later process of solid crystal and wire bonding, thereby greatly improving the yield rate. At the same time, it also further optimizes the ohmic contact between the metal reflective layer 3 and the P-type contact layer 15, further improving the uniformity of current distribution.

[0090] The thickness of the bonding layer 4 is 300 nm to 800 nm, preferably 300 nm to 500 nm.

[0091] S7: bonding the epitaxial wafer obtained in step S6 to the second substrate;

[0092] Specifically, the epitaxial wafer and the second substrate 5 can be bonded by eutectic bonding, thermal compression bonding, etc., but are not limited thereto. Preferably, thermal compression bonding is used. The bonding temperature is 200°C to 360°C, and the bonding pressure is 8000kgf to 15000kgf. The epitaxial wafer structure obtained after bonding is as follows: Figure 5 shown.

[0093] Specifically, when the thermocompression bonding process is adopted, a sub-bonding layer 51 is provided on the surface of the second substrate 5 , which is an Ag layer or an Au layer, to complete the bonding.

[0094] The second substrate 5 is a common substrate in the art, such as a silicon substrate, a sapphire substrate or a silicon carbide substrate, but is not limited thereto. Preferably, in one embodiment, the second substrate 5 is a sapphire substrate.

[0095] S8: removing the first substrate to expose the N-type semiconductor layer;

[0096] Specifically, the first substrate may be removed by an alkali polishing process or a laser lift-off process, but is not limited thereto. Preferably, the first substrate is removed by a laser lift-off process.

[0097] During the removal of the first substrate, the buffer layer, intrinsic GaN layer, etc. disposed on its surface are also removed. In one embodiment of the present invention, when the LED is a red LED chip, the first substrate (GaAs substrate), N-type GaAs buffer layer 16, and N-type GaInP etching stop layer 17 are removed.

[0098] S9: forming an N electrode on the N-type semiconductor layer to obtain an intermediate;

[0099] The N electrode 6 may be formed by evaporation, sputtering or other processes, and may be made of one or more of the commonly used Cr layer, Al layer, Pt layer, Au layer, AuBe composite layer, AuZn composite layer, etc. in the art, but is not limited thereto.

[0100] Preferably, when the LED is a red LED chip, the N-type GaAs ohmic contact layer is first patterned by a photolithography and etching process, and then the N-electrode 6 is formed, and then the N-type AlGaInP roughening layer is roughened 122 .

[0101] S10: forming a plurality of second through holes etched to the P-type contact layer on the intermediate body;

[0102] The intermediate body can be etched by dry etching or wet etching to form a plurality of second through holes 71 . The second through holes 71 are arranged in the second preset area 152 and etched to the P-type contact layer 15 . The second through holes 71 are used to subsequently form the P-electrode 8 .

[0103] Preferably, in one embodiment, step S10 includes:

[0104] S101: forming a plurality of second through holes etched to the P-type contact layer on the intermediate body;

[0105] S102: forming a plurality of third through holes in the second through hole, which are etched to the metal reflective layer;

[0106] Specifically, the P-type contact layer 15 in the second through hole 71 is further etched to form a third through hole 155 etched to the metal reflective layer. The P electrode can be electrically connected to the metal reflective layer 3 through the third through hole 155, and the current injected by the P electrode 8 can be distributed to various parts of the P-type contact layer 15 through the metal reflective layer 3, thereby greatly improving the current expansion uniformity.

[0107] S11: forming a P electrode on the intermediate obtained in step S10 to obtain an LED wafer;

[0108] The P electrode 8 may be formed by evaporation, sputtering or other processes, and the P electrode 8 may be one or more of the Cr layer, Al layer, Pt layer, Au layer, AuBe composite layer, AuZn composite layer, etc. commonly used in the art, but is not limited thereto.

[0109] Preferably, in one embodiment, in step S11, a P electrode is first formed on the intermediate obtained in step S10, then a passivation protection layer is formed, and then etching is performed to expose the N electrode and the P electrode, thereby obtaining an LED wafer.

[0110] S12: Cut the LED wafer to obtain horizontal structure LED chips

[0111] Specifically, the second substrate is ground and thinned first, and then laser cut and split to obtain a horizontal structure LED chip. The structure of the horizontal structure LED chip is as follows Figure 8 shown.

[0112] The above is a preferred embodiment of the invention. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principles of the invention. These improvements and modifications are also considered to be within the scope of protection of the present invention.

Claims

1. A method for preparing a horizontal structure LED chip, characterized in that: The following steps are involved: S1. Providing an epitaxial wafer, the epitaxial wafer comprising a first substrate and an N-type semiconductor layer, an active layer, a P-type semiconductor layer, and a P-type contact layer sequentially disposed on the first substrate; the P-type contact layer comprising a first preset region and a second preset region; S2. Etching the P-type contact layer to form a plurality of protrusions in a first predetermined area, with grooves provided between adjacent protrusions; the height of the protrusions being less than or equal to 50% of the thickness of the P-type contact layer; S3. Forming a dielectric layer on the epitaxial wafer obtained in step S2, wherein the thickness of the dielectric layer is less than the depth of the groove, and the refractive index of the dielectric layer is less than the refractive index of the P-type contact layer; S4, etching the dielectric layer to form a plurality of first through holes on top of the protrusions to expose the protrusions; S5, forming a metal reflective layer on the epitaxial wafer obtained in step S4, wherein the metal reflective layer fills the groove; S6, forming a bonding layer on the metal reflective layer; S7, bonding the epitaxial wafer obtained in step S6 to the second substrate; S8, removing the first substrate to expose the N-type semiconductor layer; S9, forming an N electrode on the N-type semiconductor layer to obtain an intermediate; S10, forming a plurality of second through holes etched to the P-type contact layer on the intermediate body; the second through holes are provided in the second predetermined area; and forming a plurality of third through holes etched to the metal reflective layer in the second through holes; S11, forming a P electrode on the intermediate obtained in step S10 to obtain an LED wafer; the P electrode is electrically connected to the P-type contact layer through the second through hole; the P electrode is electrically connected to the metal reflective layer through the third through hole; S12, cutting the LED wafer to obtain horizontal structure LED chips.

2. The method for preparing a horizontal structure LED chip according to claim 1, wherein: The bonding layer is an Au layer or an Ag layer, and its thickness is 300nm~800nm; In step S7, a Ag layer or an Au layer is provided on the surface of the second substrate; the epitaxial wafer obtained in step S6 is bonded to the second substrate by thermal compression bonding, wherein the metal reflective layer and the bonding layer are pressed against each other during bonding to fill the gaps on the surface of the epitaxial wafer; Among them, the bonding temperature is 200℃~360℃, and the bonding pressure is 8000kgf~15000kgf.

3. The method for preparing a horizontal structure LED chip according to claim 1 or 2, wherein: Step S5 includes: S51: forming a metal reflective layer on the epitaxial wafer obtained in step S4; S52: Annealing the epitaxial wafer obtained in step S51 so that the metal reflective layer forms an ohmic contact with the P-type contact layer.

4. The method for preparing a horizontal structure LED chip according to claim 1 or 2, wherein: The thickness of the P-type contact layer is 1 μm to 10 μm, and its doping concentration is ≥ 1×10 18 cm -3 and / or The protrusions are in the shape of a truncated cone, an ellipsoidal crown or a prism, the height of the protrusions is 0.5 μm to 5 μm, and the distance between adjacent protrusions is 0.5 μm to 10 μm; and / or The height of the protrusion is 20% to 35% of the thickness of the P-type contact layer; and / or The dielectric layer is one or more of a SiO2 layer, a MgF2 layer, a TiO2 layer, and a Ti2O5 layer; the thickness of the dielectric layer is 0.2 μm to 4 μm; and / or The metal reflective layer is one or more of an Au layer, an Ag layer, and an Al layer, and the thickness of the metal reflective layer is 0.5 μm to 10 μm.

5. The method for preparing a horizontal structure LED chip according to claim 1 or 2, wherein: The thickness of the P-type contact layer is 2 μm to 4 μm, and the doping concentration is 2×10 18 cm -3 ~5×10 20 cm -3 and / or The protrusions are truncated cone-shaped, the height of the protrusions is 0.5 μm to 1.8 μm, and the distance between adjacent protrusions is 0.5 μm to 3 μm; and / or The dielectric layer is a SiO2 layer with a thickness of 0.3 μm to 1 μm; and / or The metal reflective layer is an Au layer, and its thickness is 0.8 μm to 2 μm.

6. The method for preparing a horizontal structure LED chip according to claim 1, wherein: The doping concentration of the P-type contact layer increases gradually from the side close to the active layer to the side close to the dielectric layer.

7. The method for preparing a horizontal structure LED chip according to claim 1, wherein: The epitaxial wafer comprises a first substrate, an N-type GaAs buffer layer, an N-type GaInP etching stop layer, an N-type semiconductor layer, an active layer, a P-type semiconductor layer and a P-type contact layer sequentially arranged on the first substrate; The first substrate is a GaAs substrate; The second substrate is a sapphire substrate; The N-type semiconductor layer includes an N-type GaAs ohmic contact layer, an N-type AlGaInP roughening layer and an N-type AlGaInP current spreading layer, which are arranged on the N-type GaInP etching stop layer in sequence; The P-type semiconductor layer is a P-type AlGaInP confinement layer; The P-type contact layer is a P-type GaP window layer.

8. The method for preparing a horizontal structure LED chip according to claim 7, wherein: In step S8, the first substrate and the N-type GaInP etching stop layer are removed to expose the N-type GaAs ohmic contact layer, and the N-type GaAs ohmic contact layer is etched to form a contact pattern; In step S9, an N electrode is formed on the contact pattern, and the N-type AlGaInP roughening layer is roughened; In step S11, a P electrode is first formed on the intermediate body obtained in step S10, and then a passivation protection layer is formed, and then etching is performed to expose the N electrode and the P electrode, thereby obtaining an LED wafer.

9. A horizontal structure LED chip, characterized in that: The horizontal structure LED chip is prepared by the preparation method of any one of claims 1 to 8.

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