Protocol analyzer system for fc and ethernet

Abstract

The application discloses a protocol analyzer system for FC and Ethernet, comprising: an analyzer upper layer management module, which is used for user control, monitoring and analysis of the protocol analyzer system for FC and Ethernet; an analyzer intermediate layer management module, which is used for analyzing command messages of the analyzer upper layer management module, sending data to an analyzer logic module through PCIe control, acquiring and processing data captured by the analyzer logic module, transmitting the data to the analyzer upper layer management module for analysis, and acquiring relevant state feedback of the analyzer logic module and feeding back the relevant state feedback to the analyzer upper layer management module; and the analyzer logic module, which is used for analyzing port data capture, testing port data sending, data storage and system relevant state monitoring. The application provides the protocol analyzer system for FC and Ethernet, supports FC and Ethernet protocol analysis and testing, and can be flexibly switched according to user requirements.

Description

Technical Field

[0001] The invention belongs to the fields of network technology and FPGA technology, and in particular relates to a protocol analyzer system for FC and Ethernet. Background Art

[0002] As the global informatization process accelerates, massive amounts of data and information permeate every aspect of our daily lives and work. In modern high-speed networks, both intensive data transmission and high-speed computing and storage place higher demands on network performance. Network protocols, as the fundamental rules and bridge for data and information exchange, play a vital role in ensuring reliable data transmission.

[0003] Among commonly used network protocols, in addition to the most widely used Ethernet protocol, the Fibre Channel (FC) protocol features high reliability, strong real-time performance, excellent manageability, strong scalability, high transmission bandwidth, low latency, and long transmission distances. Its flexible topology makes it ideally suited for high-performance networked storage and avionics applications. Both Ethernet and FC protocols have complete protocol standards and specifications with a clearly defined logical structure. As network transmission rates continue to increase, protocol complexity is increasing. Effectively verifying the interoperability and protocol compliance of network devices has become a critical issue. Protocol analyzers play a crucial role in this regard. They can capture data flows within network links, perform protocol analysis on data packets, and identify network faults. Furthermore, they can act as an end node in the network, sending data packets according to relevant protocol standards to perform performance testing on network equipment under development, improving equipment R&D efficiency.

[0004] The network architectures of large data storage centers or avionics are generally hybrid, consisting of several different networks. Analyzers that support multiple protocols are therefore of practical significance. Therefore, further research is needed on protocol analyzer technology solutions. Summary of the Invention

[0005] The present invention provides a protocol analyzer system for FC and Ethernet to solve the above-mentioned technical problems, specifically adopting the following technical solutions:

[0006] A protocol analyzer system for FC and Ethernet, comprising: an analyzer upper layer management module, an analyzer middle layer management module and an analyzer logic module;

[0007] The analyzer upper management module is set in the PC and is used by the user to control and monitor the protocol analyzer system for FC and Ethernet and analyze the analysis port data;

[0008] The analyzer middle-layer management module is set in the board CPU and is used to parse the command message of the analyzer upper-layer management module and control or send data to the analyzer logic module through PCIe, obtain and process the data captured by the analyzer logic module, transmit it to the analyzer upper-layer management module for parsing, and obtain the relevant status of the analyzer logic module and feed it back to the analyzer upper-layer management module;

[0009] The analyzer logic module is set in the board FPGA module and is used for analyzing port data capture, test port data transmission, data storage, and monitoring of system related status;

[0010] The upper management module of the analyzer communicates with the middle management module of the analyzer via Ethernet, and the middle management module of the analyzer and the logic module of the analyzer communicate with each other using PCIe to realize register reading and writing and data transmission.

[0011] Furthermore, the analyzer upper management module includes a command building unit, a first network interaction unit and a data parsing unit;

[0012] The command forming unit is used to form a command based on the command type and command parameters specified by the user through the interface;

[0013] The first network interaction unit encapsulates the formed command into a fixed network message format, issues the command message, and simultaneously receives the command response message and data message uploaded by the analyzer middle layer management module, and feeds back the command execution status and obtained data to the user;

[0014] The data parsing unit is used to write the received complete data message into a file in pcapng format and parse it.

[0015] Furthermore, the network message using the first network interaction unit has a fixed custom format, including a network header, a request / response header, data content and a network footer, and the communicating parties extract the message according to the format;

[0016] The first network interaction unit transmits via the TCP protocol, and the receiving end needs to perform a packet operation. The memory pool management can use memory blocks in a disorderly manner, and the received information is packetized to obtain a complete message, and the message can also be sent efficiently.

[0017] Command messages interact asynchronously through the "request-response" model, while data messages interact synchronously. The asynchronous process of command interaction is synchronized through signal pool management.

[0018] Furthermore, the first network interaction unit constructs a signal pool in the form of multi-linked list management; the first network interaction unit constructs four memory pools of data sending, data receiving, command sending, and command receiving in the form of multi-linked list management.

[0019] Furthermore, the analyzer middle layer management module includes a second network interaction unit, a PCIe interaction unit and a data processing unit;

[0020] The second network interaction unit is used to receive and parse the command message of the upper management module of the analyzer, and send data messages and command response messages;

[0021] The PCIe interaction unit controls the analyzer logic module by writing the command message of the analyzer upper management module parsed by the analyzer middle management module into the register of the analyzer logic module or reads the register of the analyzer logic module to obtain the required state, thereby realizing data interaction;

[0022] The data processing unit uses a circular FIFO to receive, manage, and time-sort the captured network frames of different analysis ports. The data processing unit includes a total receiving FIFO and a sorting FIFO corresponding to each analysis port. The analyzer middle layer management module sends the total receiving FIFO through the PCIe interaction unit, and after obtaining the data, it is transferred to each sorting FIFO for sorting.

[0023] Furthermore, the PCIe interaction unit supports PCIe mounting, obtains the bus number, driver number and device number through the hardware ID, obtains the configuration space and register base address according to the bus number, driver number and device number, obtains the MSI interrupt and mounts;

[0024] The PCIe interaction unit uses pipeline mode DMA operation to transfer data between software and hardware. The analyzer middle layer management module stores instructions in a certain format in the DMA ring. The analyzer logic module reads the corresponding instructions from the DDR of the analyzer middle layer management module for processing as needed.

[0025] Furthermore, the DMA ring includes a DMA command ring and a DMA completion ring. The DMA command ring includes a read command ring and a write command ring, which are respectively used to send DMA read commands and write commands. The DMA completion ring is used to receive the completion status of the DMA command ring.

[0026] Furthermore, the analyzer logic module includes a network analysis unit, a network testing unit and a status setting and monitoring unit;

[0027] The network analysis unit is used for data capture, data encapsulation, data storage and data reporting;

[0028] The network test unit is used to generate the test frame or clear the original example frame according to the example frame and control information issued by the PCIe interaction unit.

[0029] The state setting and monitoring unit is used to set the state of each port.

[0030] Further, the data capture includes packet loopback, packet filtering and packet triggering, the packet loopback is in the form of digital retiming mode, the packet filtering is used to select the type of packet required by the user, and all the packets not required by the user are discarded, so as to improve the effective processing speed of the whole system, and the packet triggering can be triggered according to the set condition, and the depth and position of the triggering are set.

[0031] The protocol analyzer system for FC and Ethernet provided by the application has the characteristics of multi-mode and high speed, supports FC and Ethernet protocol analysis and testing, can be switched flexibly according to the user demand, supports multiple data acquisition modes, can acquire data link layer frame data or PCS layer 8B / 10B and 64 / 66B code streams, has flexible storage and analysis modes, supports two capture modes of cycle coverage and full capture, supports two analysis modes of real-time online analysis and offline storage analysis, supports packet capture filtering and port condition triggering, can lock the data packet more clearly and quickly, improves the effective processing speed of the system, supports custom test packets, supports multiple example frame storage and multiple test frame sending modes, has comprehensive port state monitoring, has lively display modes such as flow curve diagram, and is convenient for the user to observe. BRIEF DESCRIPTION OF DRAWINGS

[0032] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the drawings needed to be used in the embodiments or the prior art description will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative labor.

[0033] Figure 1 It is a schematic diagram of the protocol analyzer system for FC and Ethernet of the present application;

[0034] Figure 2 It is a schematic diagram of the internal structure of the upper management module of the analyzer of the protocol analyzer system for FC and Ethernet of the present application;

[0035] Figure 3 It is a schematic diagram of the internal structure of the middle management module of the analyzer of the protocol analyzer system for FC and Ethernet of the present application;

[0036] Figure 4The figure is a schematic diagram of the internal structure of the analyzer logic module of the protocol analyzer system for FC and Ethernet according to the present invention. DETAILED DESCRIPTION

[0037] The following describes in detail embodiments of the present application. Examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are intended to be used to explain the present application, and should not be construed as limiting the present application.

[0038] like Figure 1 The present invention illustrates a protocol analyzer system for FC and Ethernet, comprising an analyzer upper-layer management module, an analyzer middle-layer management module, and an analyzer logic module. The analyzer upper-layer management module communicates with the analyzer middle-layer management module via Ethernet, while the analyzer middle-layer management module and the analyzer logic module interact using PCIe to read and write registers and transfer data.

[0039] The analyzer's upper-layer management module is installed on a PC running Windows. It allows users to control and monitor the FC and Ethernet protocol analyzer system and analyze data from the analysis port. Specifically, the upper-layer management module processes user commands, constructs command messages, and sends them to the analyzer's middle-layer management module via TCP / IP. It also receives data messages uploaded by the middle-layer module, encapsulates them into pcapng files, and parses them.

[0040] The analyzer's middle-layer management module, housed within the board's CPU, parses command messages from the analyzer's upper-layer management module and controls or sends data to the analyzer's logic module via PCIe. It then retrieves and processes data captured by the analyzer's logic module, transmitting it to the analyzer's upper-layer management module for analysis. It also retrieves and feeds back relevant status information from the analyzer's logic module. The middle-layer management module primarily processes command messages from the analyzer's upper-layer management module, parses command types and parameters, reads and writes to the analyzer's logic module registers via PCIe, and controls the analyzer's logic module to complete its functions. It receives status and captured data from the analyzer's logic module, organizes and sorts the captured data, and uploads command response messages and data messages based on command completion.

[0041] The analyzer logic module is located within the board's FPGA module. It is primarily responsible for logic processing and data storage. It is used for data capture at the analysis port, data transmission at the test port, data storage, and system status monitoring.

[0042] As a preferred embodiment, Figure 2As shown, the upper management module of the analyzer includes a command building unit, a first network interaction unit and a data parsing unit.

[0043] The command building unit is used to build the command type and command parameters specified by the user through the interface. Specifically, the user specifies the command type and command parameters through the interface, and the analyzer upper management module collects and compiles them into a format that can be used by the lower layer.

[0044] The first network interaction unit encapsulates the assembled command into a fixed network message format, sends the command message, and simultaneously receives the command response message and data message uploaded by the analyzer's middle layer management module, and feeds back the command execution status and obtained data to the user.

[0045] The data parsing unit is used to write the received complete data message into a file in the pcapng format and parse it. Specifically, the data parsing unit writes the received complete data message into a file in the pcapng format, calls Wireshark to parse it, and uses a self-designed plug-in to parse data types that Wireshark does not support, such as FC-AE-ASM protocol packets, FC primitives, etc. Specifically, the data parsing unit encapsulates multiple data messages in a pcapng file. After sending a command to view the captured data, it starts writing the pcapng file and writes the received data messages into the file in sequence until a data message containing an end identifier is received, indicating that the file can be ended. After the end, Wireshark is called to open the file for parsing. For the FC-AE-ASM protocol and underlying data that Wireshark does not support, a script is independently written according to the format of the data as a Wireshark plug-in to parse each field.

[0046] As a preferred embodiment, the network message using the first network interaction unit has a fixed custom format, including a network header, a request / response header, data content and a network tail. The network header contains information such as the header type, message length, message type, message command ID, message signal unit ID, message signal unit starting address, message sending time, message command type, device ID, etc. The network tail contains CRC check information, which is obtained by adding every two bytes of the network header, and the specific type and parameters of the message are filled in the request / response header. The data content depends on the situation and can be 0. In an embodiment of the present application, the network message contains values ​​such as message type, length, CRC check, and the communicating parties extract the message according to this format.

[0047] The first network interaction unit transmits through the TCP protocol, and the receiving end needs to perform a packet operation. The memory pool management can use memory blocks in a disorderly manner, packetize the received information to obtain a complete message, and can also send the message efficiently.

[0048] The command message is interacted asynchronously through a "request-response" mode, and the data message is interacted synchronously, and the asynchronous process of the command interaction is synchronized through signal pool management.

[0049] As a preferred embodiment, the first network interaction unit is constructed in the form of multi-linked list management.

[0050] Specifically, the structure of the signal pool includes: idle signal count, signal lock, idle signal linked list and used signal linked list, and the signal unit moves in the signal linked list during use.

[0051] The signal unit of the signal linked list includes: adjacent unit pointer, blocking semaphore, device ID, signal use flag, signal unit number, and command information using the signal unit.

[0052] The adjacent unit pointer is used for searching and using the signal unit.

[0053] The blocking semaphore is blocked after the command is sent, and is unblocked after the response of the command is obtained or timeout.

[0054] The device ID refers to the ID of the intermediate layer management module of the analyzer to be controlled by the command, and the upper layer management module of the analyzer can specify or identify the intermediate layer management module of the analyzer through the value.

[0055] The signal use flag indicates whether the signal unit is being used, and the flag is 1 when it is being used, and the flag is 0 when it is idle.

[0056] The signal unit number is used for managing and distinguishing the signal unit.

[0057] The command information using the signal unit includes command type, command ID, command sending time, command execution state, command specific content, and command return data.

[0058] As a preferred embodiment, the first network interaction unit constructs four memory pools of data sending, data receiving, command sending and command receiving in the form of multi-linked list management.

[0059] Specifically, the structure of the memory pool includes: idle memory count, packaged memory count, memory lock, idle memory linked list, packaging memory linked list, packaged memory linked list, and processing memory linked list, and the signal unit moves in the linked list according to the current state during use.

[0060] The memory unit of the memory linked list includes: adjacent unit pointer, data address, maximum storage capacity, data size and other information.

[0061] Adjacent cell pointers are used to locate and access memory cells. The data address points to the data using the cell. The maximum storage capacity refers to the maximum amount of data that can be stored in the cell. The data size is the size of the data currently using the cell.

[0062] Specifically, the first network interaction unit binds the constructed network message to an idle signal unit in the signal pool, blocks the signal unit, and transmits the message via the TCP stream to the analyzer's middle-layer management module using a socket interface. The signal pool contains two status lists: idle signals and used signals. Binding a signal unit modifies the status flag in the idle signal list to 1, updates the command ID and other information to the command, and moves the unit to the used signal list. After unblocking, the signal unit re-enters the idle signal list and changes its status flag back to 0.

[0063] The first network interaction unit simultaneously utilizes a memory pool to receive messages uploaded by the analyzer's middle-tier management module. This memory pool contains a free memory list, a packet-assembling-in-progress memory list, a packet-assembling-completed memory list, and a processing-in-progress memory list. A free memory cell is retrieved and moved into the packet-assembling-in-progress list. The incomplete message received is then assembled into a complete message and stored in this memory cell, which then enters the packet-assembling-completed list. The cell contents within this list are complete and processable, and the message type is determined based on their content. If it is a command response message, the corresponding signal unit is unblocked, and the command execution result in the message is retrieved and fed back to the user. If it is a data message, it is transferred to the data parsing unit.

[0064] As a preferred embodiment, Figure 3 As shown, the analyzer middle layer management module includes a second network interaction unit, a PCIe interaction unit and a data processing unit.

[0065] The second network interaction unit is used to receive and parse command messages from the analyzer's upper-level management module and send data messages and command response messages, eliminating the need for a signal pool to manage command transmission. The second network interaction unit, identical to the network interaction unit of the analyzer's upper-level management module, utilizes a memory pool to receive command messages from the analyzer's upper-level management module, package and parse them, and then control the analyzer's logic module to perform corresponding operations based on the message content. The second network interaction unit constructs the results and data of the analyzer's logic module's operations into data messages and command response messages, which are then sent to the analyzer's upper-level management module.

[0066] The PCIe interaction unit writes command messages from the analyzer's upper-layer management module, parsed by the analyzer's middle-layer management module, into the analyzer's logic module's registers to control the analyzer's upper-layer management module, or reads the analyzer's logic module's registers to obtain the desired state, thereby achieving data exchange. Specifically, the analyzer's middle-layer management module parses command messages from the analyzer's upper-layer management module and writes or reads these commands into or from the analyzer's logic module's registers via the PCIe interaction unit.

[0067] The data processing unit uses a circular FIFO to manage the reception and time-ordering of captured network frames from different analysis ports. The data processing unit includes a total receive FIFO and a sorting FIFO corresponding to each analysis port. The analyzer's middle-layer management module distributes the total receive FIFO through the PCIe interface unit, and after receiving the data, it transfers it to the sorting FIFO for sorting. Data from the same analysis port is already arranged in sequence, so only the timestamps of the first data point from different analysis ports need to be compared. Furthermore, the captured underlying data must be formatted to facilitate subsequent parsing by the analyzer's upper-layer management module, separating primitive data from frame data and counting primitive data.

[0068] As a preferred embodiment, the PCIe interaction unit supports PCIe mounting, obtaining the bus number, driver number, and device number through the hardware ID. Based on these numbers, the configuration space and register base address are retrieved, and the MSI interrupt is obtained and mounted. The interrupt service is used to notify the analyzer's middle-layer management module of the relevant status completed by the analyzer logic module. The middle-layer management module determines the interrupt number associated with an interrupt and processes the read or write interrupt. The main interrupt service routine communicates with the interrupt processing thread via the interrupt status FIFO.

[0069] The PCIe interaction unit uses pipeline mode DMA operation to transfer data between software and hardware. The analyzer middle layer management module stores the instructions in a certain format in the DMA ring. The analyzer logic module reads the corresponding instructions from the analyzer middle layer management module DDR for processing as needed.

[0070] As a preferred embodiment, the DMA ring is a circular FIFO. The DMA ring includes two types: a DMA command ring and a DMA completion ring. The DMA ring unit structure includes: data length, data address, and operation flag.

[0071] The DMA command ring includes a read command ring and a write command ring, which are used to send DMA read and write commands, respectively. The corresponding ring unit is used based on the current unit count. An operation flag of 0 indicates that the analyzer's middle layer management module is operational, while a flag of 1 indicates that the analyzer's logic module is operational. The operation content is determined by the data length and address.

[0072] The DMA completion ring is used to receive the status of the DMA command ring completion. When the analyzer middle layer management module receives an interrupt, it reads the DMA completion ring for processing. The operation flag is 0, indicating that there is no interrupt to process.

[0073] When reading the captured data, the analyzer middle layer management module writes the address and length of the free memory block into the DMA write command ring, the analyzer logic module writes the data stored in the DDR into the memory, and uses an interrupt to notify the analyzer middle layer management module, and the analyzer middle layer management module obtains the result according to the completion ring.

[0074] When sending test data, the analyzer middle layer management module writes the memory address and length containing the data into the DMA read command ring. The analyzer logic module reads the data from the memory for processing and feeds back the results through the completion ring.

[0075] Data processing unit: uses circular FIFO to manage the reception and time sorting of the captured network frames of different analysis ports, including a total reception FIFO and a sorting FIFO corresponding to each analysis port;

[0076] If the captured data is low-level data, the primitive data and frame data are judged and separated word by word, and the same primitive data captured at the same time are counted. Only the processed data is sent.

[0077] As a preferred embodiment, Figure 4 As shown, the analyzer logic module includes a network analysis unit, a network test unit, and a status setting and monitoring unit.

[0078] The network analysis unit is responsible for data capture, data encapsulation, data storage, and data reporting. Data capture is at the forefront. Message data from external devices is converted from serial to parallel data via the transceiver. This data is then encoded and decoded by the FC or Ethernet PCS / PMA soft core. The FC logic IP soft core or MAC then converts the data into the AXIS bus format. FC messages are also converted into FCoE messages. Finally, the filtering module filters the data. The captured data is encapsulated into the enhanced message block format supported by pcapng, stored in the PLDDR of the analyzer logic module, and reported to the analyzer's mid-layer management module via the PCIe interaction module.

[0079] The network test unit generates user-required test frames or clears existing sample frames at a specified port based on the sample frames and control information sent by the PCIe interaction unit. The sample frame content determines the test frame format, content, and quantity. The unit is responsible for storing sample frames, generating test frames, and controlling the transmission of test frames. It supports the transmission of ASM, ELS, and FCP frames.

[0080] The status setting and monitoring unit is used to set the status of each port, including switching FC / Ethernet mode, switching analysis / test mode, switching data capture mode, switching port rate, setting frame scrambling / descrambling, setting credit amount, setting minimum frame interval, controlling flow, etc. At the same time, the analyzer logic module can monitor these states, including port connection status, credit amount, bit error number, CRC error number, flow, rate, single frame sequence count, out-of-order sequence count, etc.

[0081] As a preferred implementation, data capture includes message loopback, message filtering, and message triggering.

[0082] The message loopback is implemented in a digital retiming mode. The optical signal is first converted into an analog electrical signal by a high-speed optical transceiver module. After entering the FPGA and being received by a high-speed serial transceiver, the analog signal is converted into a digital signal. It is then split into two paths. One path is extracted by the FPGA for protocol analysis, while the other path is converted back into an analog signal by another high-speed serial transceiver. This signal is then output to the optical transceiver module and converted back into an optical signal, completing the signal loopback.

[0083] Message filtering is used to select the message type required by the user and discard all messages that the user does not need, thereby improving the effective processing speed of the entire system. The analyzer logic module adopts a capture filtering method, and the core filtering unit uses an open source filtering module - a multi-functional message filter adapted for Wireshark, and on this basis, it expands the usage method and supports filtering message types. Message filtering is divided into two parts: instructions and data. The instruction part has an instruction storage space, which uses the AXI bus to read instructions from external registers and write them to the storage space; the data part has a data cache space to cache data received by the MAC or FC CORE, and uses the AXIS bus to transmit data streams; there is a command processing module between the data and the command to realize the execution of instructions and the filtering of data, completing the message filtering operation.

[0084] Message triggering allows you to set trigger depth and position based on predefined conditions. The analyzer logic module captures messages that meet the trigger conditions and then stops capturing messages equal to the trigger depth. You can choose to stop capturing data streams for a specific channel or for all channels.

[0085] In the embodiment of the present application, the example frame is defined as 64 bytes in length, including SOF, FC Header, Optional Header, Payload, CRC, and EOF. The SOF contains the sending port, service type, payload length, and number of header words of the test frame, and the EOF is the EOF of the last frame. The FC Header and Optional Header contain information about the FC header of the test frame, i.e., the extended header. The Payload contains information such as whether there is an extended header, the sending order, the payload type, the frame length type, the number of frames in a sequence, the number of sequences, the error frame type, and the payload length of the last frame in the sequence. The CRC is defined as the payload content.

[0086] The FC and Ethernet protocol analyzer system described in this application supports analysis and testing of both FC and Ethernet protocols. It accommodates FC rates of 2.125Gbps, 4.25Gbps, and 8.5Gbps, as well as Gigabit and 10Gbps Ethernet rates, and can be flexibly switched based on user needs. This FC and Ethernet protocol analyzer system extends the capabilities of Wireshark to include protocols not supported by Wireshark, enabling more comprehensive network link analysis.

[0087] The above shows and describes the basic principles, main features and advantages of the present invention. Those skilled in the art should understand that the above embodiments do not limit the present invention in any form, and any technical solutions obtained by equivalent replacement or equivalent transformation fall within the scope of protection of the present invention.

Claims

1. A protocol analyzer system for FC and Ethernet, characterized in that: Contains: analyzer upper layer management module, analyzer middle layer management module and analyzer logic module; The analyzer upper management module is set in the PC and is used by the user to control and monitor the protocol analyzer system for FC and Ethernet and analyze the analysis port data; The analyzer middle-layer management module is set in the board CPU and is used to parse the command message of the analyzer upper-layer management module and control or send data to the analyzer logic module through PCIe, obtain and process the data captured by the analyzer logic module, transmit it to the analyzer upper-layer management module for parsing, and obtain the relevant status of the analyzer logic module and feed it back to the analyzer upper-layer management module; The analyzer logic module is set in the board FPGA module and is used for analyzing port data capture, test port data transmission, data storage, and monitoring of system related status; The analyzer upper management module communicates with the analyzer middle management module via Ethernet, and the analyzer middle management module and the analyzer logic module use PCIe interaction to realize register reading and writing and data transmission; The analyzer upper management module includes a command building unit, a first network interaction unit and a data parsing unit; The first network interaction unit transmits through the TCP protocol, and the receiving end needs to perform a packet operation. The memory pool management can use memory blocks in a disorderly manner, and the received information is packetized to obtain a complete message, and the message can also be sent efficiently.

2. The protocol analyzer system for FC and Ethernet according to claim 1, characterized in that The command forming unit is used to form a command based on the command type and command parameters specified by the user through the interface; The first network interaction unit encapsulates the formed command into a fixed network message format, issues the command message, and simultaneously receives the command response message and data message uploaded by the analyzer middle layer management module, and feeds back the command execution status and obtained data to the user; The data parsing unit is used to write the received complete data message into a file in pcapng format and parse it.

3. The protocol analyzer system for FC and Ethernet according to claim 2, characterized in that: The network message using the first network interaction unit has a fixed custom format, including a network header, a request / response header, data content and a network footer, and the communicating parties extract the message according to the format; Command messages interact asynchronously through the "request-response" model, while data messages interact synchronously. The asynchronous process of command interaction is synchronized through signal pool management.

4. The protocol analyzer system for FC and Ethernet according to claim 3, characterized in that: The first network interaction unit constructs a signal pool in the form of multi-linked table management; The first network interaction unit adopts a multi-linked list management form to construct four memory pools for data sending, data receiving, command sending, and command receiving.

5. The protocol analyzer system for FC and Ethernet according to claim 2, characterized in that: The analyzer middle layer management module includes a second network interaction unit, a PCIe interaction unit and a data processing unit; The second network interaction unit is used to receive and parse the command message of the upper management module of the analyzer, and send data messages and command response messages; The PCIe interaction unit controls the analyzer logic module by writing the command message of the analyzer upper management module parsed by the analyzer middle management module into the register of the analyzer logic module or reads the register of the analyzer logic module to obtain the required state, thereby realizing data interaction; The data processing unit uses a circular FIFO to receive, manage, and time-sort the captured network frames of different analysis ports. The data processing unit includes a total receiving FIFO and a sorting FIFO corresponding to each analysis port. The analyzer middle layer management module sends the total receiving FIFO through the PCIe interaction unit, and after obtaining the data, it is transferred to each sorting FIFO for sorting.

6. The protocol analyzer system for FC and Ethernet according to claim 5, characterized in that: The PCIe interaction unit supports PCIe mounting, obtains the bus number, driver number and device number through the hardware ID, obtains the configuration space and register base address based on the bus number, driver number and device number, obtains the MSI interrupt and mounts; The PCIe interaction unit uses pipeline mode DMA operation to transfer data between software and hardware. The analyzer middle layer management module stores instructions in a certain format in the DMA ring. The analyzer logic module reads the corresponding instructions from the DDR of the analyzer middle layer management module for processing as needed.

7. The protocol analyzer system for FC and Ethernet according to claim 6, characterized in that: The DMA ring includes a DMA command ring and a DMA completion ring. The DMA command ring includes a read command ring and a write command ring, which are respectively used to send DMA read commands and write commands. The DMA completion ring is used to receive the completion status of the DMA command ring.

8. The protocol analyzer system for FC and Ethernet according to claim 5, characterized in that: The analyzer logic module includes a network analysis unit, a network testing unit and a status setting and monitoring unit; The network analysis unit is used for data capture, data encapsulation, data storage and data reporting; The network test unit is used to generate a test frame required by the user or clear the original sample frame at the designated port according to the sample frame and control information sent by the PCIe interaction unit; The status setting and monitoring unit is used to set the status of each port.

9. The protocol analyzer system for FC and Ethernet according to claim 8, characterized in that: The data capture includes message loopback, message filtering and message triggering. The message loopback is in the form of a digital retiming mode. The message filtering is used to select the message type required by the user and discard all messages that the user does not need, thereby improving the effective processing speed of the entire system. The message triggering can be triggered according to the set conditions and the trigger depth and position can be set.

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