Phase change material back-end integration processing method and device compatible with CMOS process

Abstract

The present invention discloses a CMOS-compatible back-end integrated processing method and device for phase-change materials. The processing method includes patterning, implanting, and ion-activating photonic devices on a silicon-on-insulator wafer; depositing silicon oxide on the upper layer, etching windows, and epitaxially growing a germanium layer as an etch stop; depositing silicon oxide on the upper layer and etching silicon oxide trenches above the germanium layer and doped silicon for metal filling; selectively etching the silicon oxide above the silicon waveguide in the functional area of ​​the wafer and removing the metal and germanium above the germanium layer; depositing a thin film of phase-change material in the functional area where the germanium layer has been removed by magnetron sputtering; stripping the trench windows using a lift-off process or etching them, followed by annealing, depositing an aluminum oxide protective layer, and exposing the metal electrodes. A CMOS-compatible germanium layer is introduced as an etch stop on the silicon waveguide, and deep silicon oxide trenches are etched with low insertion loss to integrate various phase-change materials, making the phase-change material compatible with existing silicon-based optoelectronic semiconductor manufacturing processes.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuits, and in particular to a back-end integrated processing method and device for phase change materials compatible with CMOS processes. Background Art

[0002] Silicon photonics holds broad practical application prospects in high-speed optical communications, microwave photonics, optical neural networks, and optical quantum computing. Precise modulation of the waveguide refractive index and absorption is crucial for the efficient implementation of functional units in silicon photonics, enabling precise control and tuning of functions within silicon photonic networks. However, modulation schemes in photonic chips primarily rely on modulation methods such as thermo-optical modulation and free-carrier dispersion in silicon, which exhibit weak variations in modulation intensity and require continuous power supply. This results in large device sizes and high static power consumption in photonic chips, limiting progress in large-scale optoelectronic integration. Introducing innovative materials for functional units in silicon photonics has become essential to achieve superior device performance and reduce power consumption. Various materials, such as electro-optic polymers and metal-insulator transition oxides, have been integrated for ultracompact or ultrafast volatile optical modulation. The ongoing trend toward integrating non-volatile modulation materials, such as charge-trapping materials, ferroelectrics, and chalcogenide phase-change materials, is crucial for reducing the static power consumption of reconfigurable photonic circuits. Despite significant progress in prototyping devices with exceptional performance, the manufacturing process flow is incompatible with existing silicon photonics foundry processes, making the established passive and active photonic component design kits unsuitable for direct application. Therefore, the modulation phase change materials used in silicon photonics in existing technology approaches are not compatible with existing semiconductor manufacturing processes. Summary of the Invention

[0003] The embodiments of the present invention provide a phase change material back-end integration processing method and device compatible with CMOS processes, aiming to solve the problem in the prior art that the modulated phase change materials of silicon photonics are not compatible with existing semiconductor manufacturing processes.

[0004] In a first aspect, an embodiment of the present invention provides a phase change material back-end integration processing method compatible with CMOS processes, wherein the processing method includes:

[0005] performing silicon etching on a silicon-on-insulator wafer using a mask to form a wafer having a device pattern;

[0006] Performing implantation and ion activation on a specific region of silicon in the wafer to form heavily doped silicon in the specific region of silicon;

[0007] Depositing silicon oxide of a specific thickness on the undoped silicon layer and etching a window, and epitaxially growing a germanium layer in the etched window as an etch stop layer;

[0008] Depositing silicon oxide on the wafer and etching silicon oxide trenches above the germanium layer and the doped silicon, followed by metal filling, thereby continuously laying multi-layer circuits and manufacturing metal electrodes;

[0009] Selectively etching the silicon oxide above the silicon waveguide in the functional area of ​​the wafer and removing the metal and germanium above the germanium layer using a wet etching process; removing the germanium layer above the functional area using the wet etching process; the silicon waveguide is undoped silicon;

[0010] Depositing a thin film of phase change material in the functional area where the germanium layer is removed by magnetron sputtering; the thin film of phase change material covers the silicon waveguide and the silicon dioxide trench around the silicon waveguide;

[0011] Stripping is performed using a stripping process in the groove window;

[0012] placing the chip in a protective gas and annealing it within a specific annealing temperature range;

[0013] Deposit an aluminum oxide protective layer of a specific thickness on the upper layer of the chip through the atomic layer deposition process;

[0014] The aluminum oxide above the metal electrode is etched to form a contact window and expose the metal electrode.

[0015] In a second aspect, an embodiment of the present invention further provides a semiconductor device, wherein the semiconductor device is manufactured using the processing method described in the first aspect above, and a pin-doped silicon waveguide or a Sb2Se3 / Si hybrid waveguide is integrated in the semiconductor device.

[0016] An embodiment of the present invention provides a back-end integrated processing method for phase change materials compatible with CMOS processes, the processing method comprising: patterning, implanting and ion activating photonic devices on a silicon-on-insulator wafer, depositing silicon oxide on the upper layer and etching a window, epitaxially growing a germanium layer in the etched window as an etch stop layer, then depositing silicon oxide on the upper layer and etching a silicon oxide groove above the germanium layer and doped silicon to fill it with metal, selectively etching the silicon oxide above the silicon waveguide in the functional area of ​​the wafer after continuously laying multiple layers of circuits through this method, and removing the metal and germanium above the germanium layer by a wet etching process, then depositing a thin film of phase change material in the functional area where the germanium layer has been removed by magnetron sputtering, then stripping the groove window using a stripping process and annealing, depositing an aluminum oxide protective layer and exposing the metal electrode. The above-mentioned processing method, through the full process flow of specific silicon photonics, introduces a CMOS-compatible germanium layer as an etch stop layer on the silicon waveguide, etches a deep silicon oxide trench with low insertion loss of the trench, and can be used to integrate various phase change materials; this method is based on the large-scale manufacturing technology of the CMOS platform without modifying the existing passive and active photonic component library, making phase change materials compatible with existing semiconductor manufacturing processes, expanding the application range of phase change materials in semiconductor devices, and is crucial for realizing various practical applications of non-volatile electrically programmable photonic chips based on PCM. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0018] Figure 1 A flow chart of a method for back-end integration of phase change materials compatible with CMOS processes provided by an embodiment of the present invention;

[0019] Figure 2 A process flow chart of a CMOS-compatible phase change material back-end integration processing method provided in Example 1 of the present invention;

[0020] Figure 3 This is a cross-sectional structural diagram of the intermediate product provided in Example 1 of the present invention;

[0021] Figure 4 A cross-sectional structural diagram of another intermediate product provided in Example 1 of the present invention;

[0022] Figure 5 A cross-sectional structural diagram of a chip provided in Example 1 of the present invention;

[0023] Figure 6A process flow chart of a CMOS-compatible phase change material back-end integration processing method provided in Example 2 of the present invention;

[0024] Figure 7 This is a cross-sectional structural diagram of the intermediate product provided in Example 2 of the present invention;

[0025] Figure 8 A cross-sectional structural diagram of another intermediate product provided in Example 2 of the present invention;

[0026] Figure 9 A cross-sectional structural diagram of a chip provided in Example 2 of the present invention;

[0027] Figure 10 A structural diagram of a semiconductor device provided in Example 2 of the present invention;

[0028] Figure 11 A structural diagram of another semiconductor device provided in Example 2 of the present invention;

[0029] Figure 12 This is a structural diagram of another semiconductor device provided in Example 2 of the present invention. DETAILED DESCRIPTION

[0030] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of them. All other embodiments obtained by ordinary technicians in this field based on the embodiments of the present invention without making any creative efforts shall fall within the scope of protection of the present invention.

[0031] It will be understood that when used in this specification and the appended claims, the terms “comprises” and “comprising” indicate the presence of described features, integers, steps, operations, elements and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or groups thereof.

[0032] It should also be understood that the terms used in the present specification are only for the purpose of describing particular embodiments and are not intended to limit the present invention. As used in the present specification and the appended claims, the singular forms "a", "an", and "the" are intended to include the plural forms unless the context clearly indicates otherwise.

[0033] It should be further understood that the term "and / or" used in the present description and the appended claims refers to and includes any and all possible combinations of one or more of the associated listed items.

[0034] Example 1

[0035] In this example, see Figure 1 As shown in the figure, an embodiment of the present invention provides a phase change material back-end integration processing method compatible with CMOS (Complementary Metal Oxide Semiconductor) process, wherein the method includes steps S110 to S200.

[0036] S110 , performing silicon etching on the silicon-on-insulator wafer using a mask to form a wafer having a device pattern.

[0037] First, a mask can be used to etch the silicon on the silicon-on-insulator wafer to form a wafer with a device pattern, that is, to achieve patterning of photonic devices on the silicon-on-insulator wafer. The specific structure of the silicon-on-insulator wafer is as follows: Figure 2 As shown in Figure (a), a silicon-on-insulator (SOI) wafer includes a buried oxide layer and a silicon layer on the buried oxide layer. The buried oxide layer is a silicon oxide layer. The thickness of the silicon oxide layer can be 3μm and the silicon oxide layer has insulating properties. The thickness of the silicon layer on the silicon oxide layer can be 220nm or other thickness values. The wafer structure obtained after silicon etching is as follows Figure 2 As shown in Figure (b).

[0038] S120 , performing implantation and ion activation on a specific region of silicon in the wafer to form heavily doped silicon in the specific region of silicon.

[0039] Afterwards, ion implantation and ion activation are performed in specific areas of silicon in the wafer, thereby forming heavily doped silicon in specific areas of silicon to serve as electrodes of semiconductor devices, such as the formation of heavily doped p-type (p++) silicon and heavily doped n-type (n++) silicon. The specific structure is as follows Figure 3 As shown. The chip structure obtained after this step is as follows Figure 2 As shown in Figure (c).

[0040] S130 , depositing silicon oxide of a specific thickness on the undoped silicon upper layer and etching a window, and epitaxially growing a germanium layer in the etching window as an etching stop layer.

[0041] Afterwards, a 300-500nm thick SiO2 layer is deposited as the upper cladding layer using plasma enhanced chemical vapor deposition (PECVD) technology, and a window is etched in this layer for the epitaxial growth of the germanium layer. Subsequently, a low-temperature two-step growth method combined with selective epitaxial growth is used to epitaxially grow a 300-500nm germanium layer as an etch stop layer. The wafer structure obtained after this step is as follows: Figure 2 As shown in Figure (d).

[0042] S140, depositing silicon oxide on the wafer and etching silicon oxide trenches above the germanium layer and the doped silicon, and then filling with metal, using this method to continuously lay multi-layer circuits and manufacture metal electrodes.

[0043] Furthermore, a 300-500nm thick SiO2 layer is deposited using PECVD technology, and then SiO2 grooves are etched above the middle Ge layer. The wafer structure obtained after this step is as follows: Figure 2 As shown in Figure (e) in the figure. Then, silicon oxide trenches are etched on top of the doped silicon. The wafer structure obtained after this step is as follows Figure 2 As shown in Figure (f) in the figure. The metal is filled in the groove and a metal electrode is manufactured. The wafer structure obtained after this step is as follows Figure 2 As shown in Figure (g) in the figure. According to the above method, three layers of circuits are laid out in total. The chip structure obtained after this step is as follows Figure 2 As shown in Figure (h), the number of circuit layers can be 1-7, and the metal filled and the metal electrodes are aluminum, copper, tungsten or aluminum-copper alloy.

[0044] S150, selectively etching the silicon oxide above the silicon waveguide in the functional area of ​​the wafer and removing the metal and germanium above the germanium layer using a wet etching process; using a wet etching process to remove the germanium layer above the functional area; the silicon waveguide is also undoped silicon.

[0045] A layer of silicon oxide is deposited on top, and the silicon oxide above the silicon waveguide is selectively etched. The wafer structure obtained after this step is as follows Figure 2 As shown in Figure (i). The metal above the germanium layer is removed by wet etching process, and then the germanium is removed. The wafer structure obtained after this step is as follows Figure 2 As shown in Figure (j) in the figure. A wet etching process is further used to remove the germanium layer above the functional area, thereby forming a deep silicon oxide trench for the subsequent step of integrating phase change materials. The specific structure is shown in FIG. Figure 4 Specifically, the wet etching process is to use hydrochloric acid solution for wet etching, and the wafer structure obtained after this step is as shown Figure 2 As shown in Figure (k).

[0046] S160, depositing a thin film of phase change material in the functional area where the germanium layer is removed by magnetron sputtering; the thin film of phase change material covers the silicon waveguide and the silicon dioxide trench outside the silicon waveguide.

[0047] Afterwards, a phase change material is deposited in the functional area where the germanium layer is removed to form a thin film. The thin film of the phase change material covers the upper layer of the silicon waveguide and the silicon dioxide trench outside the silicon waveguide. In other words, the thin film of the phase change material covers the inner wall of the silicon dioxide trench and the edge of the groove at the same time. The specific structure is as follows Figure 5The thin film covering the upper layer of the functional area is obtained by magnetron sputtering of a phase change material (PCM). The PCM is a compound formed by combining two to four elements of Ge, Sb, Se, Te, and S. Typical PCMs include Sb2Se3 and Ge2Sb2Se4Te1. The PCM is doped with one or more non-metallic elements and metallic elements.

[0048] Among them, the non-metallic elements include O, N, C, and Si; the metal elements include Sn, Ag, Cd, Bi, and In. For example, a trace amount of C element or a trace amount of Ag element can be doped into the above-mentioned Sb2Se3 or Ge2Sb2Se4Te1, and C element and Ag element can also be doped at the same time.

[0049] S170 , performing stripping on the groove window using a stripping process to obtain a chip.

[0050] The silicon dioxide trench window is subjected to a stripping process to strip the phase change material around the silicon dioxide trench window, wherein the processing temperature of the stripping process is not greater than 150°C. The chip structure obtained after this step is as follows Figure 2 As shown in Figure (l).

[0051] S180, placing the chip in a protective gas and annealing within a specific annealing temperature range.

[0052] The chip is placed in a protective gas atmosphere and heated to a specific annealing temperature range to perform an annealing process on the chip. Step S180 specifically includes placing the chip in an inert gas environment such as nitrogen or argon and annealing it at a temperature range of 150 to 400°C for 10 to 60 minutes to promote the crystallization of Sb2Se3 and Ge2Sb2Se4Te1 in the phase change material.

[0053] S190. Deposit an aluminum oxide protective layer of a specific thickness on the upper layer of the chip through an atomic layer deposition process.

[0054] An aluminum oxide protective layer is deposited on the upper layer of the chip through an atomic layer deposition process. The process temperature of the atomic layer deposition is not greater than 150°C, and the thickness of the deposited aluminum oxide protective layer is 20 to 50 nm. The chip structure obtained after this step is as follows Figure 2 As shown in Figure (m).

[0055] S200 , etching the aluminum oxide and silicon oxide above the metal electrode to form a contact window and expose the metal electrode.

[0056] Finally, the aluminum oxide protective layer at the contact window is etched to expose the metal electrode, wherein the etching temperature of the contact window above the metal electrode is not greater than 110°C. The chip structure obtained after this step is as follows Figure 2 As shown in Figure (n).

[0057] The final chip 10 is as follows: Figure 5 As shown, a silicon layer 2 is laid on the silicon oxide layer 1, and the silicon oxide layer 1 and the silicon layer 2 are combined to form a silicon-on-insulator wafer. Part of the silicon layer 2 forms heavily doped p-type silicon 21 and heavily doped n-type silicon 22. The heavily doped p-type silicon 21 and the heavily doped n-type silicon 22 are electrically connected to the metal electrode 3 respectively. The silicon waveguide 23 in the functional area of ​​the silicon layer 2 is a boss-shaped structure. Before depositing the silicon dioxide insulating layer 4, the upper layer of the silicon waveguide 23 is covered with a germanium layer 8. The specific structure is shown in FIG. Figure 3 As shown; the periphery of the metal electrode 3 is covered by a silicon dioxide insulating layer 4, and the silicon dioxide above the silicon waveguide 23 is etched to form a silicon oxide trench 5, the structure is as shown Figure 4 The phase change material film 6 covers the silicon waveguide 23 and the silicon dioxide trench 5 around the silicon waveguide, the aluminum oxide protective layer 7 covers the top layer of the chip, and the aluminum oxide at the metal electrode 3 is etched to form a contact window 31.

[0058] Example 2

[0059] In this example, see Figure 1 As shown in the figure, an embodiment of the present invention provides a phase change material back-end integration processing method compatible with CMOS (Complementary Metal Oxide Semiconductor) process, wherein the method includes steps S110 to S200.

[0060] S110 , performing silicon etching on the silicon-on-insulator wafer using a mask to form a wafer having a device pattern.

[0061] First, a mask can be used to etch the silicon on the silicon-on-insulator wafer to form a wafer with a device pattern, that is, to achieve patterning of photonic devices on the silicon-on-insulator wafer. The specific structure of the silicon-on-insulator wafer is as follows: Figure 6 As shown in Figure (a), a silicon-on-insulator (SOI) wafer includes a buried oxide layer and a silicon layer on the buried oxide layer. The buried oxide layer is a silicon oxide layer with a thickness of 3μm and insulating properties. The silicon layer on the silicon oxide layer can be 220nm thick. The wafer structure obtained after silicon etching is as follows: Figure 6 As shown in Figure (b).

[0062] S120 , performing implantation and ion activation on a specific region of silicon in the wafer to form heavily doped silicon in the specific region of silicon.

[0063] Afterwards, ion implantation and ion activation are performed in specific areas of silicon in the wafer, thereby forming heavily doped silicon in specific areas of silicon to serve as electrodes of semiconductor devices, such as the formation of heavily doped p-type (p++) silicon and heavily doped n-type (n++) silicon. The specific structure is as follows Figure 7 As shown. The chip structure obtained after this step is as follows Figure 6 As shown in Figure (c).

[0064] S130 , depositing silicon oxide of a specific thickness on the undoped silicon upper layer and etching a window, and epitaxially growing a germanium layer in the etching window as an etching stop layer.

[0065] Afterwards, a 300-500nm thick SiO2 layer is deposited as the upper cladding layer using plasma enhanced chemical vapor deposition (PECVD) technology, and a window is etched in this layer for the epitaxial growth of the germanium layer. Subsequently, a low-temperature two-step growth method combined with selective epitaxial growth is used to epitaxially grow a 300-500nm germanium layer as an etch stop layer. The wafer structure obtained after this step is as follows: Figure 6 As shown in Figure (d).

[0066] S140, depositing silicon oxide on the wafer and etching silicon oxide trenches above the germanium layer and the doped silicon, followed by metal filling, and continuously laying multi-layer circuits through this method to manufacture metal electrodes;

[0067] Furthermore, a 300-500nm thick SiO2 layer is deposited using PECVD technology and then silicon oxide trenches are etched on top of the doped silicon. The wafer structure obtained after this step is as follows Figure 6 As shown in Figure (e) in the figure. The metal is filled in the groove and a metal electrode is manufactured. The wafer structure obtained after this step is as follows Figure 6 As shown in Figure (f) in the figure. According to the above method, three layers of circuits are laid out in total. The chip structure obtained after this step is as follows Figure 6 As shown in Figure (g), the number of circuit layers can be 1-7, and the metal filled and the metal electrodes are aluminum, copper, tungsten or aluminum-copper alloy.

[0068] S150, selectively etching the silicon oxide above the silicon waveguide in the functional area of ​​the wafer and removing the metal and germanium above the germanium layer using a wet etching process; using a wet etching process to remove the germanium layer above the functional area; the silicon waveguide is also undoped silicon.

[0069] The silicon oxide above the silicon waveguide is selectively etched. Due to the high etching selectivity between SiO2 and Ge, the etching process effectively stops at the etch stop layer (germanium layer), thus avoiding damage to the silicon waveguide (Si); a wet etching process is used to remove the metal above the germanium layer, and then the germanium is removed. A further wet etching process is used to remove the germanium layer above the functional area, thereby forming a deep silicon oxide trench for the subsequent step of integrating the phase change material. The specific structure is as follows Figure 8 Specifically, the wet etching process is to use hydrochloric acid solution for wet etching, and the wafer structure obtained after this step is as shown Figure 2 As shown in Figure (h).

[0070] S160, depositing a thin film of phase change material in the functional area where the germanium layer is removed by magnetron sputtering; the thin film of phase change material covers the silicon waveguide and the silicon dioxide trench outside the silicon waveguide.

[0071] Afterwards, a phase change material is deposited in the functional area where the germanium layer is removed to form a thin film. The thin film of the phase change material covers the upper layer of the silicon waveguide and the silicon dioxide trench outside the silicon waveguide. In other words, the thin film of the phase change material covers the inner wall of the silicon dioxide trench and the edge of the groove at the same time. The specific structure is as follows Figure 9 The thin film covering the upper layer of the functional area is obtained by magnetron sputtering of a phase change material (PCM). The PCM is a compound formed by combining two to four elements of Ge, Sb, Se, Te, and S. Typical PCMs include Sb2Se3 and Ge2Sb2Se4Te1. The PCM is doped with one or more non-metallic elements and metallic elements.

[0072] Among them, the non-metallic elements include O, N, C, and Si; the metal elements include Sn, Ag, Cd, Bi, and In. For example, a trace amount of C element or a trace amount of Ag element can be doped into the above-mentioned Sb2Se3 or Ge2Sb2Se4Te1, and C element and Ag element can also be doped at the same time.

[0073] S170 , performing stripping on the groove window using a stripping process to obtain a chip.

[0074] The silicon dioxide trench window is subjected to a stripping process to strip the phase change material around the silicon dioxide trench window, wherein the processing temperature of the stripping process is not greater than 150°C. The chip structure obtained after this step is as follows Figure 6 As shown in Figure (j).

[0075] S180, placing the chip in a protective gas and annealing within a specific annealing temperature range.

[0076] The chip is placed in a protective gas atmosphere and heated to a specific annealing temperature range to perform an annealing process on the chip. Step S180 specifically includes placing the chip in an inert gas environment, such as nitrogen or argon, and annealing it at a temperature range of 150 to 400°C for 10 to 60 minutes to promote the crystallization of Sb2Se3 and Ge2Sb2Se4Te1 in the phase change material.

[0077] S190. Deposit an aluminum oxide protective layer of a specific thickness on the upper layer of the chip through an atomic layer deposition process.

[0078] An aluminum oxide protective layer is deposited on the upper layer of the chip through an atomic layer deposition process. The process temperature of the atomic layer deposition is not greater than 150°C, and the thickness of the deposited aluminum oxide protective layer is 20 to 50 nm. The chip structure obtained after this step is as follows Figure 6 As shown in Figure (k).

[0079] S200 , etching the aluminum oxide above the metal electrode to form a contact window and expose the metal electrode.

[0080] Finally, the aluminum oxide protective layer and silicon oxide at the contact window are etched to expose the metal electrode, wherein the etching temperature of the contact window above the metal electrode is not greater than 110°C. The chip structure obtained after this step is as follows Figure 6 As shown in Figure (l).

[0081] The final chip 10 is as follows: Figure 9 As shown, a silicon layer 2 is laid on the silicon oxide layer 1, and the silicon oxide layer 1 and the silicon layer 2 are combined to form a silicon-on-insulator wafer. Part of the silicon layer 2 forms heavily doped p-type silicon 21 and heavily doped n-type silicon 22. The heavily doped p-type silicon 21 and the heavily doped n-type silicon 22 are electrically connected to the metal electrode 3 respectively. The silicon waveguide 23 in the functional area of ​​the silicon layer 2 is a boss-shaped structure. Before depositing the silicon dioxide insulating layer 4, the upper layer of the silicon waveguide 23 is covered with a germanium layer 8. The specific structure is shown in FIG. Figure 7 As shown; the periphery of the metal electrode 3 is covered by a silicon dioxide insulating layer 4, and the silicon dioxide above the silicon waveguide 23 is etched to form a silicon oxide trench 5, the structure is as shown Figure 8 The phase change material film 6 covers the silicon waveguide 23 and the silicon dioxide trench 5 around the silicon waveguide, the aluminum oxide protective layer 7 covers the top layer of the chip, and the aluminum oxide at the metal electrode 3 is etched to form a contact window 31.

[0082] This technical method provides a trench etching process using metallic germanium as an etch stop layer for the integration of phase change materials in silicon photonics. By using a germanium layer compatible with standard silicon photonics processes as an etch stop layer, narrow SiO2 trenches are fabricated on the top surface of silicon waveguides. This enables post-deposition of various PCMs for large-scale non-volatile photonic device integration without impacting wafer-based, verified photonic devices.

[0083] An embodiment of the present application further discloses a semiconductor device, wherein the semiconductor device is manufactured using the processing method described in the above embodiment, and a pin-doped silicon waveguide or a Sb2Se3 / Si hybrid waveguide is integrated in the semiconductor device.

[0084] In the specific application of this application, three groups of semiconductor devices are manufactured using the above processing method. Among them, the first group of semiconductor devices is an MZI (Mach-Zehnder interferometer) manufactured using the above trench etching process, in which the phase shifter part uses a pin-doped silicon waveguide covered with a Sb2Se3 patch (phase change material). Its appearance structure is as follows Figure 10 The second group of semiconductor devices is an MRR (micro ring resonator) manufactured using the above trench etching process. The back end of the device integrates an 8μm long Sb2Se3 / Si hybrid waveguide. Its appearance and structure are shown in the figure. Figure 11 The third group of semiconductor devices is an MRM (micro ring modulator) manufactured using the above trench etching process. The back end of the device integrates a 5μm long Sb2Se3 / Si hybrid waveguide. Its appearance and structure are shown in the figure. Figure 12 shown.

[0085] The technical method of the present application is a CMOS process-compatible phase change material back-end integration processing method. Compared with the existing technology, the advantages of the present invention include: being able to achieve large-scale integration of photonic devices based on PCM (Phase Change Material). By customizing the entire process flow of silicon photonics and introducing a CMOS-compatible germanium layer as an etch stop layer on the silicon waveguide, a deep SiO2 trench is etched with low insertion loss for the subsequent integration of various PCMs (such as Sb2Se3 and Ge2Sb2Se4Te1). This processing method is based on large-scale manufacturing on a CMOS platform without modifying the existing passive and active photonic component library, and is crucial for realizing various practical applications of non-volatile electrically programmable photonic chips based on PCM.

[0086] In summary, this paper proposes a trench etching process that utilizes Ge as an etch stop layer to achieve deep SiO2 cladding etching above the functional region (PCM deposition site). This process is suitable for the development of CMOS integrated semiconductor devices using a variety of functional materials. The integration of phase-change materials is accomplished through a back-end process involving UV lithography and thin-film deposition, which has great potential for facilitating large-scale integration. A customized silicon photonics process employs a germanium (Ge) layer as an etch stop layer to protect the Si waveguide from damage during the SiO2 trench etching process, enabling the integration of phase-change materials on a smaller scale.

[0087] In an embodiment of the present invention, a back-end integrated processing method for phase change materials compatible with CMOS processes is provided, the processing method comprising: patterning, implanting and ion activating photonic devices on a silicon-on-insulator wafer, depositing silicon oxide on the upper layer and etching a window, and epitaxially growing a germanium layer in the etched window as an etch stop layer, then depositing silicon oxide on the upper layer and etching silicon oxide grooves above the germanium layer and doped silicon to fill metal, selectively etching the silicon oxide above the silicon waveguide in the functional area of ​​the wafer after continuously laying multiple layers of circuits through this method, and removing the metal and germanium above the germanium layer by a wet etching process, and then depositing a thin film of phase change material in the functional area where the germanium layer has been removed by magnetron sputtering, followed by stripping and annealing in the groove window by a stripping process, depositing an aluminum oxide protective layer and exposing the metal electrode. The above-mentioned processing method, through the full process flow of specific silicon photonics, introduces a CMOS-compatible germanium layer as an etch stop layer on the silicon waveguide, etches a deep silicon oxide trench with low insertion loss of the trench, and can be used to integrate various phase change materials; this method is based on the large-scale manufacturing technology of the CMOS platform without modifying the existing passive and active photonic component library, making phase change materials compatible with existing semiconductor manufacturing processes, expanding the application range of phase change materials in semiconductor devices, and is crucial for realizing various practical applications of non-volatile electrically programmable photonic chips based on PCM.

[0088] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any person skilled in the art can easily conceive of various equivalent modifications or substitutions within the technical scope disclosed in the present invention, and such modifications or substitutions are intended to be within the scope of protection of the present invention. Therefore, the scope of protection of the present invention shall be subject to the scope of protection of the claims.

Claims

1. A CMOS-compatible phase change material back-end integration processing method, characterized in that: The processing method comprises: performing silicon etching on a silicon-on-insulator wafer using a mask to form a wafer having a device pattern; Performing implantation and ion activation on a specific region of silicon in the wafer to form heavily doped silicon in the specific region of silicon; Depositing silicon oxide with a thickness of 300-500 nm on the undoped silicon layer and etching a window, and epitaxially growing a germanium layer in the etched window as an etch stop layer; Depositing silicon oxide on the wafer and etching silicon oxide trenches above the germanium layer and the doped silicon, followed by metal filling, thereby continuously laying multi-layer circuits and manufacturing metal electrodes; Selectively etching the silicon oxide above the silicon waveguide in the functional area of ​​the wafer and removing the metal and germanium above the germanium layer using a wet etching process; removing the germanium layer above the functional area using the wet etching process; the silicon waveguide is undoped silicon; Depositing a thin film of phase change material in the functional area where the germanium layer is removed by magnetron sputtering; the thin film of phase change material covers the silicon waveguide and the silicon dioxide trench around the silicon waveguide; The stripping process is used to strip the groove window to obtain a chip; Place the chip in an inert gas environment such as nitrogen or argon and anneal it at a temperature range of 150 to 400°C for 10 to 60 minutes; An aluminum oxide protective layer with a thickness of 20 to 50 nm is deposited on the upper layer of the chip through an atomic layer deposition process; the aluminum oxide and silicon oxide above the metal electrode are etched to form a contact window and expose the metal electrode.

2. The CMOS-compatible phase change material back-end integration processing method according to claim 1, characterized in that: The phase change material is a compound formed by combining two to four elements from Ge, Sb, Se, Te and S; the phase change material is doped with one or more elements from non-metallic elements and metallic elements.

3. The CMOS-compatible phase change material back-end integration processing method according to claim 2, characterized in that: The non-metallic elements include O, N, C, and Si; the metal elements include Sn, Ag, Cd, Bi, and In.

4. The CMOS-compatible phase change material back-end integration processing method according to any one of claims 1 to 3, characterized in that: The thickness of the germanium layer deposited on the undoped silicon is 300-500 nm.

5. The CMOS-compatible phase change material back-end integration processing method according to claim 4, characterized in that: The wet etching process is to use a hydrochloric acid solution for wet etching.

6. The CMOS process-compatible phase change material back-end integration processing method according to any one of claims 1 to 3, characterized in that: The processing temperature of the stripping process is no more than 150° C., and the processing temperature of etching the aluminum oxide and silicon oxide above the metal electrode is no more than 110° C.

7. The CMOS-compatible phase change material back-end integration processing method according to any one of claims 1 to 3, characterized in that: The process temperature of the atomic layer deposition is no greater than 150°C.

8. The CMOS-compatible phase change material back-end integration processing method according to any one of claims 1 to 3, characterized in that: The filled metal and the metal electrode are aluminum, copper, tungsten or aluminum-copper alloy.

9. A semiconductor device, characterized in that: The semiconductor device is manufactured by the processing method according to any one of claims 1 to 8, and a pin-doped silicon waveguide or a Sb2Se3 / Si hybrid waveguide is integrated into the semiconductor device.

Images