A fast transient response LDO circuit

Abstract

The present application discloses a fast transient response LDO circuit with overcurrent protection, comprising: an error amplifier for amplifying the difference between a reference voltage and a feedback voltage to obtain an error amplification voltage; a power adjustment tube connected to the output end of the error amplifier and outputting the output voltage through the output end; a feedback circuit connected to the power adjustment tube and performing voltage division processing on the output voltage to obtain a feedback voltage and coupling the feedback voltage to the error amplifier; and a transient enhancement circuit connected to the power adjustment tube and adjusting the gate voltage of the power adjustment tube to restore the output voltage to a stable value when a sudden change occurs in the output voltage. The present invention proposes a fast transient response LDO circuit for providing power to a digital module in a high-speed, high-precision analog-to-digital converter. A fast transient response enhancement circuit is designed in a traditional off-chip capacitor LDO to effectively improve the stability and transient response capability of the LDO circuit.

Description

Technical Field

[0001] The present application relates to the technical field of integrated circuits, and in particular to a fast transient response LDO circuit. Background Art

[0002] In many SoC chips or analog-to-digital / digital-to-analog conversion chips, an LDO circuit module is integrated internally to provide a stable and low-noise operating power supply voltage for other digital circuit modules or analog circuits. A high-performance LDO circuit needs to have advantages such as high stability, fast transient response, and high power supply rejection ratio. In traditional LDO circuits, a large off-chip capacitor needs to be connected to the voltage output port to improve the stability of the circuit. At the same time, the off-chip capacitor can provide or store additional output current when the load current jumps, thereby avoiding a large overshoot voltage at the output end. Because the off-chip capacitor LDO circuit not only requires additional off-chip capacitor overhead, but also has requirements for the ESR (equivalent series resistance) of the off-chip capacitor, if the type of off-chip capacitor is not selected properly, it may cause instability. Therefore, many frequency compensation methods or LDO technologies without off-chip capacitors have been proposed.

[0003] The transient response of an LDO circuit refers to the process by which the output voltage changes when the load current or supply voltage changes, and the subsequent return to a stable value through its own negative feedback system. Two key indicators of transient response are overshoot voltage and recovery time. Excessive overshoot voltage can affect the normal operation of other modules and even cause MOSFET breakdown in digital modules, rendering the chip inoperable. Therefore, improving the transient response capability of LDO circuits is crucial.

[0004] When used, LDO circuits may experience overheating, excessive current, or even short circuits, which can cause irreversible damage to the chip. Therefore, LDO circuits also require overtemperature and overcurrent protection circuits. The overtemperature protection circuit can be addressed by designing a temperature sensor module into the entire chip. Summary of the Invention

[0005] In view of the above-mentioned shortcomings of the prior art, the present application provides a fast transient response LDO circuit to solve at least one defect in the prior art.

[0006] To achieve the above and other objectives, the present application provides a fast transient response LDO circuit, the LDO circuit comprising:

[0007] An error amplifier, used to amplify the difference between the reference voltage and the feedback voltage to obtain an error amplified voltage;

[0008] a power adjustment tube, connected to the output end of the error amplifier, and outputting the output voltage through the output end;

[0009] a feedback circuit connected to the power adjustment tube, performing voltage division processing on the output voltage to obtain a feedback voltage and coupling the feedback voltage to the error amplifier;

[0010] The transient enhancement circuit is connected to the power adjustment tube and adjusts the gate voltage of the power adjustment tube when the output voltage suddenly changes so that the output voltage returns to a stable value.

[0011] In one embodiment of the present invention, the error amplifier includes:

[0012] a first amplifier circuit comprising a first input terminal and a second input terminal, wherein the first input terminal is connected to a reference voltage, and the second input terminal is connected to a feedback voltage, and the first amplifier circuit is configured to amplify a difference between the reference voltage and the feedback voltage for the first time to obtain a first amplified voltage;

[0013] The second amplifier circuit is connected to the output end of the first amplifier circuit and is used to amplify the first amplified voltage for a second time to obtain a second amplified voltage, namely the error amplified voltage.

[0014] In one embodiment of the present invention, the first amplifier circuit includes: a first transistor, a second transistor, a third transistor, a fourth transistor, and a fifth transistor;

[0015] The source of the first transistor is connected to the power supply voltage, the gate is connected to the first bias voltage, and the drain is connected to the source of the second transistor and the source of the third transistor respectively; the gate of the second transistor is connected to the reference voltage, the drain of the second transistor is connected to the drain and gate of the fourth transistor, and the source of the fourth transistor is grounded; the gate of the third transistor is connected to the feedback voltage, the drain of the third transistor is connected to the drain of the fifth transistor and forms a first node, the gate of the fifth transistor is connected to the gate of the fourth transistor, and the source of the fifth transistor is grounded.

[0016] In one embodiment of the present invention, the second amplifier circuit includes: a seventh transistor, an eighth transistor, and a ninth transistor;

[0017] The source of the ninth transistor is connected to the power supply voltage, the gate is connected to the third bias voltage, the drain is connected to the source of the eighth transistor, the drain of the eighth transistor is respectively connected to the gate of the eighth transistor and the drain of the seventh transistor, the gate of the eighth transistor is connected to the gate of the power adjustment tube, the source of the seventh transistor is grounded, and the gate of the seventh transistor is connected to the first node.

[0018] In one embodiment of the present invention, the transient enhancement circuit includes: a tenth transistor, an eleventh transistor, and a sampling module;

[0019] The source of the tenth transistor is connected to the power supply voltage, the gate is connected to the output end of the sampling module, the drain is connected to the source of the eighth transistor, the gate of the eleventh transistor is connected to the gate of the eighth transistor, the source of the eleventh transistor is connected to the power supply voltage, the drain of the eleventh transistor is connected to the sampling module, and the input end of the sampling module is connected to the output voltage.

[0020] In one embodiment of the present invention, the sampling module includes: a twelfth transistor, a thirteenth transistor, a fourteenth transistor, a fifteenth transistor, a sixteenth transistor, a seventeenth transistor, an eighteenth transistor, a twentieth transistor, and a twenty-first transistor;

[0021] The source of the twelfth transistor is connected to the drain of the eleventh transistor, the gate of the twelfth transistor is connected to the drain of the twelfth transistor and the gate of the twentieth transistor respectively, the drain of the twelfth transistor is connected to the drain of the fourteenth transistor, the source of the fourteenth transistor is grounded, the gate of the fourteenth transistor is connected to the gate of the thirteenth transistor, the drain of the thirteenth transistor is connected to the gate of the thirteenth transistor and connected to a bias current, the source of the thirteenth transistor is grounded, the source of the fifteenth transistor is connected to the source of the twelfth transistor, the drain of the fifteenth transistor is connected to the drain and gate of the sixteenth transistor, the source of the sixteenth transistor is grounded, the gate of the sixteenth transistor is connected to the gate of the seventeenth transistor, the source of the seventeenth transistor is grounded, the drain of the seventeenth transistor is connected to the drain and gate of the eighteenth transistor, and the source of the eighteenth transistor is connected to the power supply voltage; the gate of the fifteenth transistor is connected to the drain of the twentieth transistor and the drain of the twenty-first transistor, the source of the twenty-first transistor is grounded, the gate of the twenty-first transistor is connected to the gate of the fourteenth transistor, and the source of the twentieth transistor is connected to the drain of the power adjustment tube.

[0022] In one embodiment of the present invention, the feedback circuit includes: a first resistor, a second resistor, and a trimming resistor network, wherein one end of the second resistor is connected to the drain of the power regulating tube, the other end of the second resistor is connected to one end of the first resistor, the other end of the first resistor is connected to one end of the trimming resistor network, and the other end of the trimming resistor network is connected to one input end of the error amplifier to input a feedback voltage to the error amplifier.

[0023] In one embodiment of the present invention, the LDO circuit further includes:

[0024] The output circuit includes an output resistor and an output capacitor, one end of the output resistor is connected to the drain of the power adjustment tube, and the other end of the output resistor is grounded. One end of the output capacitor is connected to the drain of the power adjustment tube, and the other end of the output capacitor is grounded.

[0025] In one embodiment of the present invention, the LDO circuit further includes an overcurrent protection circuit; the overcurrent protection circuit includes: a sixth transistor, a twenty-sixth transistor, a twenty-second transistor, a twenty-third transistor, a twenty-fourth transistor, and a twenty-fifth transistor; the sampling module further includes a nineteenth transistor and a third resistor;

[0026] The source of the twenty-sixth transistor is connected to the power supply voltage, the gate of the twenty-sixth transistor is connected to the second bias voltage, the drain of the twenty-sixth transistor is connected to the source of the twenty-second transistor and the source of the twenty-third transistor respectively, the drain of the twenty-second transistor is connected to the drain of the twenty-fourth transistor, the source of the twenty-fourth transistor is grounded, the gate of the twenty-fourth transistor is connected to the drain, the drain of the twenty-third transistor is connected to the drain of the twenty-fifth transistor and forms a second node, the source of the twenty-fifth transistor is grounded, the gate of the twenty-fifth transistor is connected to the gate of the twenty-fourth transistor, the second node is connected to the gate of the sixth transistor, the source of the sixth transistor is grounded, and the drain of the sixth transistor is connected to the source of the seventh transistor; the source of the nineteenth transistor is connected to the power supply voltage, the gate of the nineteenth transistor is connected to the gate of the eighteenth transistor, and the drain of the nineteenth transistor is grounded via the third resistor; the gate of the twenty-second transistor is connected to the reference voltage, and the gate of the twenty-third transistor is connected to the drain of the nineteenth transistor.

[0027] In one embodiment of the present invention, the first amplifier circuit further includes: a first capacitor, one end of the first capacitor is connected to the gate of the third transistor, and the other end of the first capacitor is grounded.

[0028] Beneficial effects of this application:

[0029] The present invention discloses a fast transient response LDO circuit, comprising: an error amplifier for amplifying the difference between a reference voltage and a feedback voltage to obtain an error amplification voltage; a power adjustment tube connected to the output terminal of the error amplifier and outputting the output voltage through the output terminal; a feedback circuit connected to the power adjustment tube and performing voltage division processing on the output voltage to obtain a feedback voltage and coupling the feedback voltage to the error amplifier; and a transient enhancement circuit connected to the power adjustment tube and adjusting the gate voltage of the power adjustment tube to restore the output voltage to a stable value when a sudden change occurs in the output voltage. The present invention proposes a fast transient response LDO circuit for providing power to a digital module in a high-speed, high-precision analog-to-digital converter. A fast transient response enhancement circuit is designed in a traditional off-chip capacitor LDO to effectively improve the stability and transient response capability of the LDO circuit.

[0030] It should be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] The accompanying drawings are incorporated into and constitute a part of the specification, illustrating embodiments consistent with the present application and, together with the specification, serving to explain the principles of the present application. It is obvious that the drawings described below are merely some embodiments of the present application, and a person of ordinary skill in the art can derive other drawings based on these drawings without inventive effort. In the drawings:

[0032] Figure 1 This is a typical circuit structure diagram of an existing LDO;

[0033] Figure 2 This is the AC characteristic diagram when the LDO load resistance changes;

[0034] Figure 3 A circuit diagram of a fast transient response LDO circuit according to an embodiment of the present application;

[0035] Figure 4 This is a diagram of an overcurrent protection circuit according to an embodiment of the present application. DETAILED DESCRIPTION

[0036] The following describes the embodiments of the present application through specific examples. Those skilled in the art can easily understand the other advantages and effects of the present application from the content disclosed in this specification. The present application can also be implemented or applied through other different specific embodiments. The details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present application. It should be noted that the following embodiments and features in the embodiments can be combined with each other unless they conflict.

[0037] It should be noted that the illustrations provided in the following embodiments are only schematic illustrations of the basic concept of the present application. Therefore, the illustrations only show components related to the present application and are not drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component can be changed at will, and the component layout type may also be more complicated.

[0038] Although the terms "first," "second," "A," and "B," etc. may be used herein to describe various elements, these elements should not be limited by these terms and are merely used to distinguish one element from another. For example, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element without departing from the scope of the technology described below. The term "and / or" includes a combination of a plurality of related items or any of the plurality of related items.

[0039] As used herein, unless the context indicates otherwise, the singular form is intended to include the plural form, and it will be understood that the term "comprising" means the presence of stated features, quantities, steps, operations, elements, or combinations thereof, but does not preclude the presence or addition of one or more other features, quantities, steps, operations, elements, components, or combinations thereof.

[0040] Before describing the components in detail, it is intended to clarify that the components in this specification are divided only by the primary function of each component. That is, two or more components described below may be combined into one component, or may be divided into two or more components based on more detailed functions. In addition to the primary function of the component, each component described below may also perform some or all of the functions of other components, and some of the primary functions of each component may be exclusively performed by other components.

[0041] Figure 1 It is a traditional typical LDO circuit, including a bandgap reference circuit, an error amplifier, a power regulator Mp, a feedback resistor network and an auxiliary circuit. LDO is a negative feedback closed loop system that connects the error amplifier and the power regulator Mp through a resistor feedback network. When the voltage at the output of the LDO changes, the feedback resistor network inputs the feedback signal to the non-inverting input of the error amplifier, which is inversely proportional to the reference voltage V at the inverting input. REF The error amplifier amplifies the difference and controls the gate voltage of the power regulator, thereby driving the power regulator to provide different load currents and stabilize the output voltage. OUT for:

[0042]

[0043] Where V REF is the reference voltage of the reference circuit, A O,EA is the open-loop gain of the error amplifier, A O,POW is the open-loop gain of the power regulator, R FB1 With R FB2 are the resistance values ​​of the feedback resistors respectively. If the gain of the difference amplifier is infinite, the output voltage is:

[0044] In traditional LDO circuits, since the error amplifier directly drives the power regulator, the power regulator needs to provide a large load current, so there is a large parasitic capacitance at the input end of the power regulator. Figure 2 As shown, under load R L When φ increases, the main pole P1 will change accordingly. It is possible that the secondary pole P2 is within the GBW and the zero Z1 is outside the GBW, which will cause the LDO circuit to be unstable. Therefore, an intermediate-stage adaptive bias buffer is added to the LDO circuit.

[0045] In an LDO circuit, a sudden change in load current causes a change in output voltage. This change then requires a negative feedback system to return the output voltage to a stable value. Two key indicators of transient response are overshoot voltage and recovery time. Excessive overshoot voltage can affect the normal operation of other modules and even cause MOSFET breakdown in digital modules, leading to chip failure. Therefore, improving the transient response capability of LDO circuits is crucial.

[0046] See also Figure 3 , Figure 3 This is a circuit diagram of a fast transient response LDO circuit according to an embodiment of the present application. Figure 3 As shown, a fast transient response LDO circuit includes:

[0047] An error amplifier, used to amplify the difference between the reference voltage and the feedback voltage to obtain an error amplified voltage;

[0048] a power adjustment tube, connected to the output end of the error amplifier, and outputting the output voltage through the output end;

[0049] a feedback circuit connected to the power adjustment tube, performing voltage division processing on the output voltage to obtain a feedback voltage and coupling the feedback voltage to the error amplifier;

[0050] The transient enhancement circuit is connected to the power adjustment tube and adjusts the gate voltage of the power adjustment tube when the output voltage suddenly changes so that the output voltage returns to a stable value.

[0051] The present invention proposes a fast transient response LDO circuit for providing power to digital modules in high-speed and high-precision analog-to-digital converters. A fast transient response enhancement circuit is designed in a traditional off-chip capacitor LDO, which can effectively improve the stability and transient response capability of the LDO circuit.

[0052] In an embodiment of the present application, the error amplifier includes:

[0053] The first amplifier circuit includes a first input terminal and a second input terminal, wherein the first input terminal is connected to a reference voltage V REF The second input terminal is connected to the feedback voltage V FB , the first amplifier circuit is used to amplify the reference voltage V REF With the feedback voltage V FB The difference is amplified for the first time to obtain a first amplified voltage;

[0054] The second amplifier circuit is connected to the output end of the first amplifier circuit and is used to amplify the first amplified voltage for a second time to obtain a second amplified voltage, namely the error amplified voltage.

[0055] In the embodiment of the present application, the first amplifying circuit includes: a first transistor M1, a second transistor M2, a third transistor M3, a fourth transistor M4, and a fifth transistor M5;

[0056] The source of the first transistor M1 is connected to the power supply voltage, and the gate is connected to the first bias voltage V b1 The drain is connected to the source of the second transistor M2 and the source of the third transistor M3 respectively; the gate of the second transistor M2 is connected to the reference voltage R EF The drain of the second transistor M2 is connected to the drain and gate of the fourth transistor M4, and the source of the fourth transistor M4 is grounded; the gate of the third transistor M3 is connected to the feedback voltage V FB The drain of the third transistor M3 is connected to the drain of the fifth transistor M5 and forms a first node. The gate of the fifth transistor M5 is connected to the gate of the fourth transistor M4. The source of the fifth transistor M5 is grounded.

[0057] In the embodiment of the present application, the first transistor M1 is a tail current source of the first amplifier circuit, and its bias voltage V b1 Provided by the bias circuit, the second transistor M2 and the third transistor M3 are PMOS input differential pair transistors, and the fourth transistor M4 and the fifth transistor M5 are current mirror loads.

[0058] In the embodiment of the present application, the second amplifying circuit includes: a seventh transistor M7, an eighth transistor M8, and a ninth transistor M9;

[0059] The source of the ninth transistor M9 is connected to the power supply voltage, and the gate is connected to the third bias voltage V b3 The drain of the eighth transistor M8 is connected to the source of the eighth transistor M8, the drain of the eighth transistor M8 is connected to the gate of the eighth transistor M8 and the drain of the seventh transistor M7, and the gate of the eighth transistor M8 is connected to the power adjustment tube M8. P The gate of the seventh transistor M7 is connected to the first node, the source of the seventh transistor M7 is grounded, and the gate of the seventh transistor M7 is connected to the first node.

[0060] The seventh transistor M7 and the eighth transistor M8 are the second stage circuit of the error amplifier, the ninth transistor M9 is a current source working in the linear region, and the eighth transistor M8 is a load connected in a diode manner. In this way, the low frequency gain A of the error amplifier is V for:

[0061]

[0062] Among them, 1 / gm8 The error amplifier has a low output impedance. Reducing the output impedance of the error amplifier can increase the secondary pole P2 of the LDO circuit and improve the stability of the LDO circuit.

[0063] In the present application, the second-stage amplification circuit of the error amplifier is designed to have low output impedance. This structure is similar to adding a buffer, which can improve the stability of the circuit.

[0064] In the embodiment of the present application, the transient enhancement circuit includes: a tenth transistor M 10 , the eleventh transistor M 11 , sampling module;

[0065] tenth transistor M 10 The source of the transistor M is connected to the power supply voltage, the gate is connected to the output end of the sampling module, the drain is connected to the source of the eighth transistor M8, and the eleventh transistor M 11 The gate of the eleventh transistor M is connected to the gate of the eighth transistor M8. 11 The source of the eleventh transistor M is connected to the power supply voltage. 11 The drain is connected to the sampling module, and the input end of the sampling module is connected to the output voltage.

[0066] Furthermore, the sampling module includes: a twelfth transistor M 12 , the thirteenth transistor M 13 , the fourteenth transistor M 14 , the fifteenth transistor M 15 , the sixteenth transistor M 16 , the seventeenth transistor M 17 , the eighteenth transistor M 18 , the twentieth transistor M 20 , the twenty-first transistor M 21 ;

[0067] The twelfth transistor M 12 The source of the eleventh transistor M 11 The drain of the twelfth transistor M 12 The gates of the twelfth transistor M are connected to 12 The drain of the twentieth transistor M 20 The gate of the twelfth transistor M 12 The drain of the fourteenth transistor M 14 The drain of the fourteenth transistor M 14 The source of the fourteenth transistor M is grounded. 14 The gate of the thirteenth transistor M 13 The gate of the thirteenth transistor M is connected 13 The drain of the thirteenth transistor M 13The gate of the thirteenth transistor M is connected in parallel with the bias current. 13 The source of the fifteenth transistor M is grounded. 15 The source of the twelfth transistor M 12 The source of the fifteenth transistor M is connected 15 The drain of the sixteenth transistor M 16 The drain and gate of the sixteenth transistor M are connected 16 The source of the sixteenth transistor M is grounded. 16 The gate of the seventeenth transistor M 17 The gate of the seventeenth transistor M is connected 17 The source of the seventeenth transistor M is grounded. 17 The drain of the eighteenth transistor M 18 The drain and gate of the eighteenth transistor M 18 The source of the fifteenth transistor M is connected to the power supply voltage; 15 The gate of the twentieth transistor M 20 The drain of the twenty-first transistor M 21 The drain of the twenty-first transistor M is connected 21 The source of the twenty-first transistor M is grounded. 21 The gate of the fourteenth transistor M 14 The gate of the twentieth transistor M is connected 20 The source and power adjustment tube M P Drain connection.

[0068] Among them, the twelfth transistor M 12 With the twentieth transistor M 20 The same size as the voltage mirror, the fourteenth transistor M 14 With the twenty-first transistor M 21 The tail current source is provided for the voltage mirror. The bias voltage of the current mirror is provided by the thirteenth transistor M 13 Provided. The twelfth transistor M 12 With the twentieth transistor M 20 The voltage can be clamped so that the eleventh transistor M 11 The drain voltage V M Follower power adjustment tube M P The change of the drain voltage causes the eleventh transistor M 11 The current can be mirrored in equal proportion to the power adjustment tube M. P The load current has a current ratio of 1:100. The fifteenth transistor M 15 ~Eighteenth transistor M 18 Convert the load current signal into a sampling voltage signal V CS1 The tenth transistor M 10 The gate voltage is the sampling voltage signal V CS1, when the sampling voltage signal V CS1 When following the load current change, the tenth transistor M 10 The current flowing into the eighth transistor M8 will also increase or decrease. Specifically, when the load current jumps from light load to heavy load, the power adjustment transistor M8 will P The current of the fifteenth transistor M 15 The current increases, and the sampling voltage V CS1 Decreases, then the tenth transistor M 10 The drain current of the eighth transistor M8 increases, which in turn causes the gate voltage of the eighth transistor M8 to decrease. P The gate voltage is connected to the power regulator M P The current increases, responding to the load current jump faster. When the load current jumps from heavy load to light load, the change process is reversed, and the sampling voltage V CS1 will increase, thus causing the gate voltage of the eighth transistor M8 to increase. Since the gate voltage of the eighth transistor M8 is closely related to the power adjustment tube M P The gate voltage is connected to the power regulator M P The current is reduced, so it responds faster to the jump of load current.

[0069] In the embodiment of the present application, the feedback circuit includes: a first resistor R1, a second resistor R2, and a trimming resistor network, wherein one end of the second resistor R2 is connected to the power adjustment tube M1. P The other end of the second resistor R2 is connected to one end of the first resistor R1, the other end of the first resistor R1 is connected to one end of the trimming resistor network, and the other end of the trimming resistor network is connected to one input end of the error amplifier to input a feedback voltage to the error amplifier.

[0070] In an embodiment of the present application, the LDO circuit further includes:

[0071] Output circuit, including output resistor R L and output capacitor C L , the output resistance R L One end of the power adjustment tube M P The drain connection, output resistor R L The other end of the output capacitor C L One end of the power adjustment tube M P The drain connection, output capacitor C L The other end is grounded.

[0072] In an embodiment of the present application, the LDO circuit further includes an overcurrent protection circuit.

[0073] Specifically, the overcurrent protection circuit includes: a sixth transistor M6, a twenty-sixth transistor M0, a twenty-second transistor M 22 , the twenty-third transistor M 23 , the twenty-fourth transistor M 24 25th transistor M 25 , the sampling module further includes a nineteenth transistor M19 and a third resistor;

[0074] The source of the twenty-sixth transistor M0 is connected to the power supply voltage, the gate of the twenty-sixth transistor M0 is connected to the second bias voltage, and the drain of the twenty-sixth transistor M0 is connected to the second bias voltage. 22 The source of the twenty-third transistor M 23 The source of the twenty-second transistor M is connected 22 The drain of the twenty-fourth transistor M 24 The drain of the twenty-fourth transistor M is connected 24 The source of the twenty-fourth transistor M is grounded. 24 The gate and drain of the twenty-third transistor M are connected. 23 The drain of the twenty-fifth transistor M 25 The drain of the twenty-fifth transistor M is connected to form a second node. 25 The source of the twenty-fifth transistor M is grounded. 25 The gate of the twenty-fourth transistor M 24 The second node is connected to the gate of the sixth transistor M6, the source of the sixth transistor M6 is grounded, and the drain of the sixth transistor M6 is connected to the source of the seventh transistor M7; the nineteenth transistor M 19 The source of the nineteenth transistor M is connected to the power supply voltage. 19 The gate of the eighteenth transistor M 18 The gate of the nineteenth transistor M is connected 19 The drain of the 22nd transistor M is grounded via the third resistor; 22 The gate of the twenty-third transistor M is connected to the reference voltage. 23 The gate of the nineteenth transistor M 19 of the drain.

[0075] When the LDO circuit is overloaded or short-circuited, the output current increases rapidly, resulting in unstable output voltage and even chip overheating. In order to protect the LDO circuit, the present invention adds an overcurrent protection circuit. The comparator in the overcurrent protection circuit is composed of Figure 3 The twenty-sixth transistor M0 and the twenty-second transistor M 22 ~25th transistor M 25 The overcurrent protection principle is as follows: Figure 4 As shown, the sampling voltage V CS2The reference input voltage is connected to the input port of the comparator respectively. The output of the comparator controls the gate voltage of the sixth transistor M6. When the load current is less than the current upper limit set by the LDO circuit, the sampling current is very small and the sampling voltage V CS2 <V FEF , the comparator output is high level, so that the sixth transistor M6 is turned on and the circuit works normally; when the load current is larger than the current upper limit set by the LDO circuit, the sampling current increases and the sampling voltage V CS2 >V FEF , the comparator output is low level, so that the sixth transistor M6 is turned off to perform overcurrent protection.

[0076] In the embodiment of the present application, the first amplifier circuit further includes: a first capacitor Cm, one end of the first capacitor Cm is connected to the gate of the third transistor M3, and the other end of the first capacitor is grounded. FB The addition of a frequency compensation capacitor, namely the first capacitor, further improves stability.

[0077] It should be noted that the first transistor M1, the second transistor M2, the third transistor M3, the eighth transistor M8, the ninth transistor M9, the tenth transistor M 10 , the eleventh transistor M 11 , the twelfth transistor M 12 , the fifteenth transistor M 15 , the eighteenth transistor M 18 , the nineteenth transistor M 19 , the twentieth transistor M 20 , the twenty-second transistor M 22 , the twenty-third transistor M 23 The twenty-sixth transistor M0 is a PMOS transistor, the fourth transistor M4, the fifth transistor M5, the sixth transistor M6, the thirteenth transistor M 13 , the fourteenth transistor M 14 , the sixteenth transistor M 16 , the seventeenth transistor M 17 , the twenty-first transistor M 21 , the twenty-fourth transistor M 24 25th transistor M 25 It is an NMOS tube.

[0078] The above embodiments are merely illustrative of the principles and effects of this application and are not intended to limit this application. Anyone skilled in the art may modify or alter the above embodiments without departing from the spirit and scope of this application. Therefore, any equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical concepts disclosed in this application shall be covered by the claims of this application.

Claims

1. A fast transient response LDO circuit, characterized in that: The LDO circuit includes: An error amplifier, used to amplify the difference between the reference voltage and the feedback voltage to obtain an error amplified voltage; a power adjustment tube connected to the output terminal of the error amplifier and outputting an output voltage through the output terminal; a feedback circuit connected to the power adjustment tube, performing voltage division processing on the output voltage to obtain a feedback voltage and coupling the feedback voltage to the error amplifier; a transient enhancement circuit connected to the power adjustment tube, for adjusting the gate voltage of the power adjustment tube to restore the output voltage to a stable value when the output voltage suddenly changes; The error amplifier includes a first amplifying circuit and a second amplifying circuit, and the second amplifying circuit includes: a seventh transistor, an eighth transistor, and a ninth transistor; The source of the ninth transistor is connected to the power supply voltage, the gate is connected to the third bias voltage, the drain is connected to the source of the eighth transistor, the drain of the eighth transistor is connected to the gate of the eighth transistor and the drain of the seventh transistor respectively, the gate of the eighth transistor is connected to the gate of the power adjustment tube, the source of the seventh transistor is grounded, and the gate of the seventh transistor is connected to the output of the first amplifier circuit; The transient enhancement circuit includes: a tenth transistor, an eleventh transistor, and a sampling module; The source of the tenth transistor is connected to the power supply voltage, the gate is connected to the output terminal of the sampling module, the drain is connected to the source of the eighth transistor, the gate of the eleventh transistor is connected to the gate of the eighth transistor, the source of the eleventh transistor is connected to the power supply voltage, the drain of the eleventh transistor is connected to the sampling module, and the input terminal of the sampling module is connected to the output voltage; The sampling module includes: a twelfth transistor, a thirteenth transistor, a fourteenth transistor, a fifteenth transistor, a sixteenth transistor, a seventeenth transistor, an eighteenth transistor, a twentieth transistor, and a twenty-first transistor; The source of the twelfth transistor is connected to the drain of the eleventh transistor, the gate of the twelfth transistor is connected to the drain of the twelfth transistor and the gate of the twentieth transistor respectively, the drain of the twelfth transistor is connected to the drain of the fourteenth transistor, the source of the fourteenth transistor is grounded, the gate of the fourteenth transistor is connected to the gate of the thirteenth transistor, the drain of the thirteenth transistor is connected to the gate of the thirteenth transistor and connected to a bias current, the source of the thirteenth transistor is grounded, the source of the fifteenth transistor is connected to the source of the twelfth transistor, the drain of the fifteenth transistor is connected to the drain and gate of the sixteenth transistor, the source of the sixteenth transistor is grounded, the gate of the sixteenth transistor is connected to the gate of the seventeenth transistor, the source of the seventeenth transistor is grounded, the drain of the seventeenth transistor is connected to the drain and gate of the eighteenth transistor, and the source of the eighteenth transistor is connected to the power supply voltage; the gate of the fifteenth transistor is connected to the drain of the twentieth transistor and the drain of the twenty-first transistor, the source of the twenty-first transistor is grounded, the gate of the twenty-first transistor is connected to the gate of the fourteenth transistor, and the source of the twentieth transistor is connected to the drain of the power adjustment tube.

2. The fast transient response LDO circuit according to claim 1, characterized in that: The error amplifier comprises: a first amplifier circuit comprising a first input terminal and a second input terminal, wherein the first input terminal is connected to a reference voltage, and the second input terminal is connected to a feedback voltage, and the first amplifier circuit is configured to amplify a difference between the reference voltage and the feedback voltage for the first time to obtain a first amplified voltage; The second amplifier circuit is connected to the output end of the first amplifier circuit and is used to amplify the first amplified voltage for a second time to obtain a second amplified voltage, namely the error amplified voltage.

3. The fast transient response LDO circuit according to claim 2, characterized in that: The first amplifying circuit includes: a first transistor, a second transistor, a third transistor, a fourth transistor, and a fifth transistor; The source of the first transistor is connected to the power supply voltage, the gate is connected to the first bias voltage, and the drain is connected to the source of the second transistor and the source of the third transistor respectively; the gate of the second transistor is connected to the reference voltage, the drain of the second transistor is connected to the drain and gate of the fourth transistor, and the source of the fourth transistor is grounded; the gate of the third transistor is connected to the feedback voltage, the drain of the third transistor is connected to the drain of the fifth transistor and forms a first node, the gate of the fifth transistor is connected to the gate of the fourth transistor, and the source of the fifth transistor is grounded.

4. The fast transient response LDO circuit according to claim 1, wherein: The feedback circuit includes: a first resistor, a second resistor, and a trimming resistor network, one end of the second resistor is connected to the drain of the power adjustment tube, the other end of the second resistor is connected to one end of the first resistor, the other end of the first resistor is connected to one end of the trimming resistor network, one end of the first resistor is connected to one input end of the error amplifier to input a feedback voltage to the error amplifier, and the other end of the trimming resistor network is grounded.

5. The fast transient response LDO circuit according to claim 1, wherein: The LDO circuit further includes: The output circuit includes an output resistor and an output capacitor, one end of the output resistor is connected to the drain of the power adjustment tube, and the other end of the output resistor is grounded. One end of the output capacitor is connected to the drain of the power adjustment tube, and the other end of the output capacitor is grounded.

6. The fast transient response LDO circuit according to claim 1, wherein: The LDO circuit further includes an overcurrent protection circuit, which includes: a sixth transistor, a twenty-sixth transistor, a twenty-second transistor, a twenty-third transistor, a twenty-fourth transistor, and a twenty-fifth transistor. The sampling module further includes a nineteenth transistor and a third resistor. The source of the twenty-sixth transistor is connected to the power supply voltage, the gate of the twenty-sixth transistor is connected to the second bias voltage, the drain of the twenty-sixth transistor is connected to the source of the twenty-second transistor and the source of the twenty-third transistor respectively, the drain of the twenty-second transistor is connected to the drain of the twenty-fourth transistor, the source of the twenty-fourth transistor is grounded, the gate of the twenty-fourth transistor is connected to the drain, the drain of the twenty-third transistor is connected to the drain of the twenty-fifth transistor and forms a second node, the source of the twenty-fifth transistor is grounded, the gate of the twenty-fifth transistor is connected to the gate of the twenty-fourth transistor, the second node is connected to the gate of the sixth transistor, the source of the sixth transistor is grounded, and the drain of the sixth transistor is connected to the source of the seventh transistor; the source of the nineteenth transistor is connected to the power supply voltage, the gate of the nineteenth transistor is connected to the gate of the eighteenth transistor, and the drain of the nineteenth transistor is grounded via the third resistor; the gate of the twenty-second transistor is connected to the reference voltage, and the gate of the twenty-third transistor is connected to the drain of the nineteenth transistor.

7. The fast transient response LDO circuit according to claim 3, wherein: The first amplifying circuit further includes: a first capacitor, one end of the first capacitor is connected to the gate of the third transistor, and the other end of the first capacitor is grounded.

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