Semiconductor packaging structure

Abstract

The present invention provides a semiconductor packaging structure, which includes: a packaging shell having a first cavity, the packaging shell including a substrate; a semiconductor chip connected to the substrate; a terminal portion electrically connected to the electrode of the semiconductor chip; wherein the packaging shell is provided with a first inlet and a first outlet, the first inlet and the first outlet are both connected to the first cavity so that an insulating heat dissipation medium can enter the first cavity through the first inlet and flow out to the outside of the first cavity through the first outlet, and the semiconductor chip is immersed in the insulating heat dissipation medium. The technical solution of the present application can effectively solve the problem of unsatisfactory heat dissipation effect of power semiconductor devices in related technologies.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a semiconductor packaging structure. Background Art

[0002] Power semiconductor devices are a type of semiconductor devices that can handle and control higher voltages and currents. Unlike small signal semiconductor devices used for signal processing, power semiconductor devices can be used for the conversion, distribution and control of electrical energy. They play a vital role in the field of power electronics, such as power management, motor drive, renewable energy systems, power transmission and distribution, and power quality control.

[0003] In this field, a power semiconductor device generally includes a housing, a substrate and a power semiconductor chip (such as a silicon carbide chip). The housing and the substrate form an inner cavity. The power semiconductor chip is arranged in the inner cavity and connected to the substrate. Generally, the power semiconductor chip generates more heat when working. If the power semiconductor chip is not effectively dissipated, it will have an adverse effect on the reliability of the power semiconductor device. Usually, heat dissipation fins are arranged on the housing, and the heat generated by the power semiconductor chip can be transferred to the heat dissipation fins through the housing and dissipated, but the heat dissipation effect of this heat dissipation method is not ideal. In addition, in order to ensure the insulation performance of the power semiconductor device, an insulating colloid layer is usually arranged in the inner cavity. The arrangement of the insulating colloid layer is also not conducive to heat dissipation. Summary of the invention

[0004] The main purpose of the present invention is to provide a semiconductor device to solve the problem of unsatisfactory heat dissipation effect of power semiconductor devices in the related art.

[0005] In order to achieve the above-mentioned purpose, the present invention provides a semiconductor packaging structure, comprising: a packaging shell having a first cavity, the packaging shell comprising a substrate; a semiconductor chip connected to the substrate; a terminal portion, electrically connected to the electrode of the semiconductor chip; wherein a first inlet and a first outlet are provided on the packaging shell, the first inlet and the first outlet are both connected to the first cavity so that an insulating heat dissipation medium can enter the first cavity through the first inlet and flow out to the outside of the first cavity through the first outlet, and the semiconductor chip is immersed in the insulating heat dissipation medium.

[0006] Furthermore, the packaging shell also includes a first cover plate and a first enclosure plate, the first enclosure plate is arranged between the first cover plate and the substrate to form a first cavity, the first enclosure plate includes a first plate body and a second plate body, the first plate body and the second plate body are arranged opposite to each other, the first inlet is arranged on the first plate body, and the first outlet is arranged on the second plate body.

[0007] Furthermore, the first enclosure is a rectangular frame structure, the first enclosure has a vertical symmetry plane, the vertical symmetry plane passes through the first plate body and the second plate body, and the first inlet and the first outlet are respectively located on both sides of the vertical symmetry plane.

[0008] Furthermore, the semiconductor packaging structure also includes a heat sink connected to the substrate, and the heat sink and the semiconductor chip are located on both sides of the substrate.

[0009] Furthermore, the packaging shell also includes a second cover plate and a second enclosure plate, the second enclosure plate is arranged between the second cover plate and the substrate to form a second cavity, the heat sink is located in the second cavity, and the second enclosure plate is provided with a second inlet and a second outlet connected to the second cavity, so that the flowing heat dissipation medium can enter the second cavity through the second inlet and flow out to the outside of the second cavity through the second outlet.

[0010] Furthermore, the second enclosure plate includes a third plate body and a fourth plate body that are arranged opposite to each other, the second inlet is arranged on the third plate body, and the second outlet is arranged on the fourth plate body.

[0011] Furthermore, the semiconductor packaging structure also includes a first connecting plate, a second connecting plate and an insulating block arranged at intervals, the first connecting plate is electrically connected to the first pole of the semiconductor chip, the second connecting plate is electrically connected to the second pole of the semiconductor chip, the terminal portion includes a first connecting terminal connected to the first connecting plate and a second connecting terminal connected to the second connecting plate, and the semiconductor packaging structure also includes an insulating block arranged between the first connecting plate and the second connecting plate.

[0012] Furthermore, the semiconductor packaging structure also includes a first insulating bump and a second insulating bump connected to the substrate, the first insulating bump and the second insulating bump are spaced apart along the length direction of the first enclosure, the semiconductor chip includes a first chip and a second chip, the first chip is located on a side of the first insulating bump away from the second insulating bump, and the second chip is located on a side of the second insulating bump away from the first insulating bump.

[0013] Furthermore, the terminal portion includes a first terminal, the first terminal is located between the first insulating bump and the second insulating bump, and the first terminal is electrically connected to the first electrode of the first chip and the first electrode of the second chip.

[0014] Furthermore, the terminal portion also includes a second terminal and a third terminal, the second terminal is electrically connected to the third pole of the first chip, and the third terminal is electrically connected to the third pole of the second chip, and the second terminal and the third terminal are both located between the first insulating bump and the second insulating bump and on both sides of the first terminal.

[0015] Furthermore, the terminal portion also includes a fourth terminal and a fifth terminal, the fourth terminal is electrically connected to the second pole of the first chip, the fifth terminal is electrically connected to the second pole of the second chip, the fourth terminal is located on the side of the first insulating bump away from the second insulating bump, and the fifth terminal is located on the side of the second insulating bump away from the first insulating bump.

[0016] Furthermore, the semiconductor packaging structure also includes a sealing sleeve, which is arranged between the first terminal and the packaging shell.

[0017] Furthermore, the semiconductor packaging structure also includes a metal connecting piece, the semiconductor chip is connected to the substrate through the metal connecting piece, and the terminal portion is electrically connected to the electrode of the semiconductor chip through the metal connecting piece.

[0018] According to the technical solution of the present invention, the packaging shell has a first cavity, the packaging shell includes a substrate, the first cavity is used to accommodate various components of the semiconductor packaging structure and to allow the insulating heat dissipation medium to circulate, and the packaging shell provides an installation basis for the various components of the semiconductor packaging structure. Specifically, the semiconductor chip is arranged in the first cavity, and the semiconductor chip is connected to the substrate; the terminal portion is electrically connected to the electrode of the semiconductor chip to realize the electrical connection between the semiconductor chip and the external device, thereby forming a current loop and enabling the semiconductor chip to realize its function. By providing a first inlet and a first outlet connected to the first cavity, the insulating heat dissipation medium can enter the first cavity through the first inlet and flow out to the outside of the first cavity through the first outlet. The flowing insulating heat dissipation medium can directly contact the semiconductor chip and directly take away part of the heat generated by the semiconductor chip during operation, thereby realizing the effect of further heat dissipation of the semiconductor chip; the insulating heat dissipation medium directly takes away the heat generated by the semiconductor chip, so that the semiconductor chip can work at a suitable temperature, and then the semiconductor chip can continuously and stably perform its function, thereby ensuring the reliability of the semiconductor packaging structure. In addition, the insulating heat dissipation medium has an insulating property, so that the semiconductor chip is immersed in the insulating heat dissipation medium, so that the semiconductor chip is insulated, thereby taking into account the heat dissipation effect and safety of the semiconductor packaging structure. Therefore, the technical solution of the present application can effectively solve the problem of unsatisfactory heat dissipation effect of power semiconductor devices in the related art. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] The drawings constituting a part of the present application are used to provide a further understanding of the present invention. The exemplary embodiments of the present invention and their descriptions are used to explain the present invention and do not constitute an improper limitation of the present invention. In the drawings:

[0020] Figure 1 A schematic diagram of a three-dimensional structure of a first embodiment of a semiconductor packaging structure according to the present invention is shown;

[0021] Figure 2 Shows Figure 1A schematic top view of a semiconductor package structure;

[0022] Figure 3 Shows Figure 1 A schematic diagram of the split structure of a semiconductor packaging structure;

[0023] Figure 4 Shows Figure 1 A schematic diagram of a split structure of a semiconductor package structure from another angle;

[0024] Figure 5 Shows Figure 1 A schematic diagram of a flow channel plate in a first cavity of a semiconductor packaging structure;

[0025] Figure 6 A schematic diagram of the three-dimensional structure of a substrate and a first enclosure according to a second embodiment of a semiconductor package structure of the present invention is shown;

[0026] Figure 7 A schematic diagram of the split structure of a third embodiment of a semiconductor packaging structure according to the present invention is shown;

[0027] Figure 8 Shows Figure 7 A three-dimensional structural schematic diagram of a partial structure of a semiconductor packaging structure;

[0028] Fig. 9 Shows Figure 7 A three-dimensional structural schematic diagram of a partial structure of a semiconductor packaging structure;

[0029] Fig.10 Shows Figure 7 Schematic diagram of a first partition and a second partition in a second cavity of a semiconductor package structure.

[0030] The above drawings include the following reference numerals:

[0031] 10. Encapsulation shell; 11. Inner cavity; 111. First cavity; 112. Second cavity; 12. First inlet; 13. First outlet; 14. Second inlet; 15. Second outlet; 16. First cover plate; 17. Second cover plate; 18. First enclosure; 181. First plate body; 182. Second plate body; 19. Second enclosure; 191. Third plate body; 192. Fourth plate body; 155. First baffle plate; 156. Second baffle plate;

[0032] 20. Substrate;

[0033] 30. semiconductor chip; 31. first chip; 32. second chip;

[0034] 40. terminal portion; 41. first terminal; 42. second terminal; 43. third terminal; 44. fourth terminal; 45. fifth terminal;

[0035] 50. Heat dissipation components;

[0036] 60. Runner plate;

[0037] 71. a first insulating protrusion; 72. a second insulating protrusion;

[0038] 80, metal connecting sheet; 81, first sheet; 82, second sheet; 83, third sheet; 84, fourth sheet; 85, fifth sheet;

[0039] 90. Sealing sleeve;

[0040] 1001. First connecting plate; 1002. Second connecting plate; 1003. Insulating block. DETAILED DESCRIPTION

[0041] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, rather than all the embodiments. The following description of at least one exemplary embodiment is actually only illustrative and is by no means intended to limit the present invention and its application or use. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0042] It should be noted that the terms used herein are only for describing specific embodiments and are not intended to limit the exemplary embodiments according to the present application. As used herein, unless the context clearly indicates otherwise, the singular form is also intended to include the plural form. In addition, it should be understood that when the terms "comprise" and / or "include" are used in this specification, it indicates the presence of features, steps, operations, devices, components and / or combinations thereof.

[0043] Unless otherwise specifically stated, the relative arrangement, numerical expressions and numerical values ​​of the parts and steps set forth in these embodiments do not limit the scope of the present invention. Meanwhile, it should be understood that, for ease of description, the sizes of the various parts shown in the accompanying drawings are not drawn according to the actual proportional relationship. The technology, method and equipment known to those of ordinary skill in the relevant art may not be discussed in detail, but in appropriate cases, the technology, method and equipment should be considered as a part of the specification. In all examples shown and discussed here, any specific value should be interpreted as being merely exemplary, rather than as a limitation. Therefore, other examples of exemplary embodiments may have different values. It should be noted that similar reference numerals and letters represent similar items in the following drawings, and therefore, once a certain item is defined in an accompanying drawing, it does not need to be further discussed in subsequent drawings.

[0044] like Figures 1 to 4 As shown, the present application provides a semiconductor packaging structure, and a first embodiment of the semiconductor packaging structure of the present application includes: a packaging shell 10, a semiconductor chip 30, and a terminal portion 40; the packaging shell 10 has a first cavity 111, and the packaging shell 10 includes a substrate 20; the semiconductor chip 30 is connected to the substrate 20; the terminal portion 40 is electrically connected to the electrode of the semiconductor chip 30; wherein, a first inlet 12 and a first outlet 13 are provided on the packaging shell 10, and the first inlet 12 and the first outlet 13 are both connected to the first cavity 111 so that an insulating heat dissipation medium can enter the first cavity 111 through the first inlet 12 and flow out to the outside of the first cavity 111 through the first outlet 13, and the semiconductor chip 30 is immersed in the insulating heat dissipation medium.

[0045] According to the technical solution of the present embodiment, the package shell 10 has a first cavity 111, and the package shell 10 includes a substrate 20. The first cavity 111 is used to accommodate various components of the semiconductor package structure and to allow the insulating heat dissipation medium to circulate. The package shell 10 provides an installation basis for various components of the semiconductor package structure. Specifically, the semiconductor chip 30 is arranged in the first cavity 111, and the semiconductor chip 30 is connected to the substrate 20; the terminal portion 40 is electrically connected to the electrode of the semiconductor chip 30 to realize the electrical connection between the semiconductor chip 30 and the external device, thereby forming a current loop and enabling the semiconductor chip 30 to realize its function. By providing a first inlet 12 and a first outlet 13 connected to the first cavity 111, the insulating heat dissipation medium can enter the first cavity through the first inlet 12. The insulating heat dissipation medium flows into the body 111 and flows out to the outside of the first cavity 111 through the first outlet 13. The flowing insulating heat dissipation medium can directly contact the semiconductor chip 30 and directly take away part of the heat generated by the semiconductor chip 30 during operation, thereby achieving the effect of further heat dissipation of the semiconductor chip 30; the insulating heat dissipation medium directly takes away the heat generated by the semiconductor chip 30, so that the semiconductor chip 30 can work at a suitable temperature, and then the semiconductor chip 30 can continuously and stably perform its function, thereby ensuring the reliability of the semiconductor packaging structure. In addition, the insulating heat dissipation medium has insulating properties, so that the semiconductor chip 30 is immersed in the insulating heat dissipation medium, so that the semiconductor chip 30 is insulated, thereby taking into account the heat dissipation effect and safety of the semiconductor packaging structure. Therefore, the technical solution of this embodiment can effectively solve the problem of unsatisfactory heat dissipation effect of power semiconductor devices in related technologies.

[0046] It should be noted that the insulating heat dissipation medium (with insulating properties) and the overflow heat dissipation medium (mentioned later, it may or may not have insulating properties) can be heat transfer oils. The insulating heat dissipation medium and the overflow heat dissipation medium can be composed of the same substance or different substances. The heat transfer oil can be mineral heat transfer oil, alkylbenzene heat transfer oil, alkylnaphthalene heat transfer oil, alkylbiphenyl heat transfer oil, biphenyl and biphenyl ether low-melting mixture type heat transfer oil or alkylbiphenyl ether type heat transfer oil. Mineral heat transfer oil is a product of a certain distillation range in the petroleum refining process, and its main component is a mixture of long-chain alkanes and cycloalkanes. This type of heat transfer oil usually has good thermal conductivity and cost-effectiveness, and is suitable for medium and low temperature ranges; alkylbenzene type heat transfer oil is a compound with alkane side chains attached to the benzene ring, has a low vapor pressure, and does not vaporize under normal operation; it has good thermal stability and is suitable for applications below 300°C; the structure of alkylnaphthalene type heat transfer oil is a compound with alkane side chains attached to the benzene ring, and is suitable for gas phase heating systems in the range of 240~280°C; alkylbiphenyl type heat transfer oil is composed of a short-chain alkyl group combined with a biphenyl ring, has high thermal stability, and is suitable for use in the range of 300~340°C; biphenyl and biphenyl ether low-melting mixture type heat transfer oil is composed of 26.5% biphenyl and 73.5% biphenyl ether, has good thermal stability and high operating temperature (400°C), and is suitable for use in the range of 256~258°C; alkylbiphenyl ether type heat transfer oil is linked by an ether group in the middle of two benzene rings, has low viscosity and good fluidity, is suitable for use in low temperature environments, and the recommended maximum operating temperature does not exceed 330°C. In addition, the heat dissipation medium may also be electronic fluoride liquid.

[0047] Specifically, in the present embodiment, the packaging shell 10 has an inner cavity 11, the substrate 20 is arranged in the inner cavity 11 and divides the inner cavity 11 into a first cavity 111 and a second cavity 112 isolated from each other, one end of the terminal portion 40 is electrically connected to the electrode of the semiconductor chip 30, and the other end of the terminal portion 40 extends to the outside of the inner cavity 11; the semiconductor chip 30 is connected to the first side of the substrate 20, and in addition, a heat sink 50 is also arranged on the second side of the substrate 20, and part of the heat generated when the semiconductor chip 30 is working will be directly transferred to the substrate 20 through the connection between the semiconductor chip 30 and the substrate 20, the heat sink 50 is located in the second cavity 112 and connected to the second side of the substrate 20, and the packaging shell 10 is provided with a second inlet 14 and a second outlet 15 connected to the second cavity 112 so that The heat dissipation medium can enter the second cavity 112 from the second inlet 14 and flow out from the second outlet 15 to the outside of the second cavity 112. Part of the heat generated by the semiconductor chip 30 during operation is transferred to the substrate 20 and then transferred to the heat sink 50 through the substrate 20. The overflow heat dissipation medium can flow in the second cavity 112 to take away the heat on the heat sink 50, thereby playing a role in dissipating heat for the semiconductor chip 30; the insulating heat dissipation medium directly takes away the heat generated by the semiconductor chip 30, and the overflow heat dissipation medium takes away the heat transferred from the semiconductor chip 30 to the heat sink 50. The two work together to enable the semiconductor chip 30 to work at a suitable temperature, and then enable the semiconductor chip 30 to continuously and stably perform its functions, thereby ensuring the reliability of the semiconductor packaging structure. The number of heat sinks 50 is greater than 2, the heat sink 50 is a cylindrical structure, and a plurality of heat sinks 50 are arranged in an array. In other embodiments, the heat sink may be a heat sink fin. In the present embodiment, the semiconductor chip 30 is a power semiconductor chip. The semiconductor chip 30 is a sheet structure and has a first surface and a second surface. The source electrode (that is, the first electrode of the semiconductor chip 30) and the gate electrode (that is, the third electrode of the semiconductor chip 30) of the semiconductor chip 30 are arranged on the first surface, and the drain electrode (that is, the second electrode of the semiconductor chip 30) of the semiconductor chip 30 is arranged on the second surface. The second surface of the semiconductor chip 30 is connected to the substrate 20. When the semiconductor chip 30 is working, the heat generated by the first surface of the semiconductor chip 30 will be greater than the heat generated by the second surface of the semiconductor chip 30. Therefore, in the related art, insulating glue is usually poured into the first cavity, and the insulating glue layer formed by curing the insulating glue will directly contact the first surface of the semiconductor chip 30. When the semiconductor chip 30 is working, the heat generated by the first surface is difficult to dissipate through the insulating glue layer, thereby resulting in an unsatisfactory heat dissipation effect of the semiconductor packaging structure.

[0048] In addition, it should be noted that “the semiconductor chip 30 is immersed in the insulating heat dissipation medium” means that the upper surface of the insulating heat dissipation medium is located above the upper surface of the semiconductor chip 30. In this embodiment, the distance between the upper surface of the insulating heat dissipation medium and the upper surface of the semiconductor chip 30 is between 3 mm and 10 mm.

[0049] like Figures 1 to 4 As shown, the packaging shell 10 includes a first cover plate 16, a second cover plate 17, a first enclosure plate 18 and a second enclosure plate 19, the first enclosure plate 18 is arranged between the first cover plate 16 and the substrate 20, the second enclosure plate 19 is arranged between the second cover plate 17 and the substrate 20, the substrate 20 is connected to the first enclosure plate 18, the first inlet 12 and the first outlet 13 are formed on the first enclosure plate 18, and the second inlet 14 and the second outlet 15 are formed on the second enclosure plate 19. Specifically, in this embodiment, the second enclosure 19 includes a plurality of vertical plate segments and a plurality of transverse plate segments, and a mounting port is formed between the transverse plate segments for mounting the substrate 20. The second inlet 14 is multiple, and the plurality of second inlets 14 are arranged on the transverse plate segments. The second outlet 15 is also multiple, and the plurality of second outlets 15 are arranged on the vertical plate segments. The substrate 20 and the first enclosure 18 are an integral structure, and the first cover plate 16 is detachably connected to the first enclosure 18. The substrate 20, the first enclosure 18, and the first cover plate 16 are all made of ceramics, such as aluminum oxide, aluminum nitride, silicon nitride, zirconium oxide, silicon carbide, etc., so that the first enclosure 18, the first cover plate 16, the substrate 20, and the heat sink 50 have the advantages of high temperature resistance, corrosion resistance, good thermal conductivity, and high structural strength. Aluminum oxide has excellent structural strength and chemical corrosion resistance, and is suitable for applications with high durability requirements. Zirconia is known for its excellent toughness and high temperature resistance, and performs well in high temperature and high stress environments. Aluminum nitride has high thermal conductivity and low expansion coefficient, can effectively dissipate heat, and is suitable for high-power electronic devices. Silicon carbide not only has high hardness and high wear resistance, but also can remain stable at extremely high temperatures, making it very popular in high-temperature electronic devices and high-frequency applications. The diversity and excellent properties of these ceramic materials provide a wide range of choices and significant performance improvements for the design and application of semiconductor packaging structures; the second enclosure 19 and the second cover 17 are made of polymer insulating materials.

[0050] like Figures 1 to 4As shown, the first enclosure 18 includes a first plate body 181 and a second plate body 182, the first plate body 181 and the second plate body 182 are arranged opposite to each other, the first inlet 12 is arranged on the first plate body 181, and the first outlet 13 is arranged on the second plate body 182. Specifically, compared with the solution in which the inlet and the outlet are arranged adjacent to each other, with such an arrangement, the semiconductor packaging structure of this embodiment can allow the insulating heat dissipation medium to flow out of the first cavity 111 through a longer flow path after entering the first cavity 111, so that the insulating heat dissipation medium can fully exchange heat with the semiconductor chip 30 and take away the heat on the semiconductor chip 30, thereby ensuring the heat dissipation effect on the semiconductor chip 30.

[0051] like Figures 1 to 4 As shown, the first enclosure 18 is a rectangular frame structure, and the first enclosure 18 has a vertical symmetry plane, which passes through the first plate body 181 and the second plate body 182, and the first inlet 12 and the first outlet 13 are respectively located on both sides of the vertical symmetry plane. Compared with the solution in which the inlet and the outlet are arranged at the same end of the first plate body and the second plate body, the semiconductor packaging structure of this embodiment can make the insulating heat dissipation medium enter the first cavity 111 and then be discharged after at least a diagonal distance, so that the flow path of the insulating heat dissipation medium is increased, so that the insulating heat dissipation medium can fully exchange heat with the semiconductor chip 30 and take away the heat on the semiconductor chip 30, thereby ensuring the heat dissipation effect of the semiconductor chip 30.

[0052] like Figure 5 As shown, the semiconductor packaging structure includes a plurality of flow channel plates 60, and the flow channel plates 60 are connected to the first cover plate 16. The plurality of flow channel plates 60 extend along the width direction of the first enclosure plate 18 and are spaced apart along the length direction of the first enclosure plate 18. In two adjacent flow channel plates 60, the first end of the first flow channel plate 60 abuts against the first plate body 181, and the second end of the first flow channel plate 60 is spaced apart from the second plate body 182. The first end of the second flow channel plate 60 abuts against the second plate body 182, and the second end of the second flow channel plate 60 is spaced apart from the first plate body 181. Specifically, the arrangement of the plurality of flow channel plates 60 forms a multi-tortuous flow path in the first cavity 111, thereby further increasing the flow path of the insulating heat dissipation medium, so that the insulating heat dissipation medium can fully exchange heat with the semiconductor chip 30 and take away the heat from the semiconductor chip 30, thereby ensuring the heat dissipation effect on the semiconductor chip 30. It should be noted that, Figure 5 As shown, the width direction of the first enclosure 18 is the direction from the first plate body 181 to the second plate body 182 , and the length direction of the first enclosure 18 is the extension direction of the first plate body 181 or the second plate body 182 .

[0053] like Figure 3 as well as Figure 4 As shown, the semiconductor package structure further includes a first insulating bump 71 and a second insulating bump 72, and the first insulating bump 71 and the second insulating bump 72 are arranged at intervals along the length direction of the first enclosure 18, and the semiconductor chip 30 includes a first chip 31 and a second chip 32, and the first chip 31 is located on a side of the first insulating bump 71 away from the second insulating bump 72, and the second chip 32 is located on a side of the second insulating bump 72 away from the first insulating bump 71. Specifically, the first insulating bump 71 and the second insulating bump 72 divide the substrate 20 into a first mounting area, a second mounting area, and a third mounting area that are isolated from each other, wherein the third mounting area is located between the first insulating bump 71 and the second insulating bump 72, the first mounting area is located on a side of the first insulating bump 71 away from the second insulating bump 72, and the second mounting area is located on a side of the second insulating bump 72 away from the first insulating bump 71, the first chip 31 is arranged in the first mounting area, and the second chip 32 is arranged in the second mounting area, thereby ensuring that there is a large surface distance between the first chip 31 and the second chip 32, thereby ensuring the insulation performance of the semiconductor package structure.

[0054] like Figure 3 as well as Figure 4 As shown, the terminal portion 40 includes a first terminal 41, one end of which is located between the first insulating bump 71 and the second insulating bump 72, and the first terminal 41 is electrically connected to the source of the first chip 31 and the source of the second chip 32. Specifically, the first terminal 41 is electrically connected to the source of the first chip 31 and the source of the second chip 32, so that the source of the first chip 31 and the source of the second chip 32 share the first terminal 41, thereby forming a 10,000-volt high-voltage half-bridge module, which can determine the number of power semiconductor chips in the first mounting area or the second mounting area according to the current requirements of the semiconductor package structure; and can also determine the number, thickness and height of the insulating bumps according to the voltage level requirements of the semiconductor package structure and the voltage level of the power semiconductor chip used.

[0055] like Figure 3 as well as Figure 4 As shown, the terminal portion 40 further includes a second terminal 42 and a third terminal 43, the second terminal 42 is electrically connected to the gate of the first chip 31, the third terminal 43 is electrically connected to the gate of the second chip 32, and one end of the second terminal 42 and one end of the third terminal 43 are both located between the first insulating bump 71 and the second insulating bump 72 and located on both sides of the first terminal 41. Specifically, as Figure 3As shown, the second terminal 42 and the third terminal 43 are located on both sides of the first terminal 41 in the width direction of the first enclosure 18. Such an arrangement can make the layout of each terminal more reasonable; in addition, in the semiconductor packaging structure, the gate of the semiconductor chip 30 controls the current to flow from the source of the semiconductor chip 30 to the drain of the semiconductor chip 30 by applying voltage. The change in the voltage of the gate of the semiconductor chip 30 can accurately control the current passing through the drain and source of the semiconductor chip 30. Since the voltage difference between the gate and the source of the semiconductor chip 30 is much smaller than the voltage difference between the drain and the source of the semiconductor chip 30, the first terminal 41, the second terminal 42 and the third terminal 43 are all located in the third mounting area, which can meet the insulation requirements of the semiconductor packaging structure.

[0056] like Figures 1 to 4 As shown, the terminal portion 40 further includes a fourth terminal 44 and a fifth terminal 45, the fourth terminal 44 is electrically connected to the drain of the first chip 31, the fifth terminal 45 is electrically connected to the drain of the second chip 32, one end of the fourth terminal 44 is located on a side of the first insulating bump 71 away from the second insulating bump 72, and the other end of the fourth terminal 44 passes through the first enclosure 18, one end of the fifth terminal 45 is located on a side of the second insulating bump 72 away from the first insulating bump 71, and the other end of the fifth terminal 45 passes through the first enclosure 18. Specifically, such an arrangement can make the distance between the fourth terminal 44 and the fifth terminal 45 relatively far, thereby ensuring the insulation performance of the semiconductor package structure.

[0057] like Figure 3 as well as Figure 4As shown, the semiconductor package structure further includes a metal connecting sheet 80, which is connected between the semiconductor chip 30 and the substrate 20, and the terminal portion 40 is electrically connected to the electrode of the semiconductor chip 30 through the metal connecting sheet 80. Specifically, the semiconductor chip 30 is directly connected to the substrate 20 through the metal connecting sheet 80. Compared with the solution in the related art that the package shell and the power semiconductor chip are connected through the liner and the connecting portion between the liner and the shell, this embodiment simplifies the heat dissipation path between the semiconductor chip 30 and the substrate 20, reduces the thermal resistance on the heat dissipation path, so that the heat generated by the semiconductor chip 30 during operation can be better transferred to the substrate 20, which is more conducive to the heat dissipation of the semiconductor chip 30; the metal connecting sheets 80 are mutually isolated. A sheet 81, a second sheet 82, a third sheet 83, a fourth sheet 84, and a fifth sheet 85; the first sheet 81, the second sheet 82, and the third sheet 83 are located in the third installation area, the fourth sheet 84 is located in the first installation area, and the fifth sheet 85 is located in the second installation area. The first sheet 81 is electrically connected to the first terminal 41, the second sheet 82 is electrically connected to the second terminal 42, the third sheet 83 is electrically connected to the third terminal 43, the fourth sheet 84 is electrically connected to the fourth terminal 44, and the fifth sheet 85 is electrically connected to the fifth terminal 45.

[0058] like Figure 3 As shown, the semiconductor package structure further includes a sealing sleeve 90, which is disposed between the first terminal 41 and the package shell 10. Specifically, the sealing sleeve 90 can prevent the insulating heat dissipation medium from leaking out of the first cavity 111 through the gap between the first terminal 41 and the package shell 10. Sealing sleeves are also disposed between other terminals and the package shell 10.

[0059] In addition, if Figure 6 As shown, the semiconductor packaging structure of the present application also provides a second embodiment. Different from the first embodiment, the first inlet 12 and the first outlet 13 are both arranged in multiple and one-to-one correspondence. Such an arrangement can shorten the flow path between the corresponding first inlet 12 and the first outlet 13, and increase the flow rate of the insulating heat dissipation medium, thereby increasing the updating frequency of the insulating heat dissipation medium, thereby also ensuring the heat dissipation effect of the semiconductor packaging structure.

[0060] like Figures 7 to 10As shown, the semiconductor packaging structure of the present application also provides a third embodiment, which is different from the first embodiment in that the second enclosure 19 includes a third plate body 191 and a fourth plate body 192 arranged opposite to each other, the second inlet 14 is arranged on the third plate body 191, and the second outlet 15 is arranged on the fourth plate body 192. Specifically, compared with the solution in which the inlet and the outlet are arranged adjacent to each other, with such an arrangement, the semiconductor packaging structure of this embodiment can allow the overflow heat dissipation medium to flow out of the second cavity 112 through a longer flow path after entering the second cavity 112, so that the overflow heat dissipation medium can fully exchange heat with the heat dissipation element 50 and take away the heat on the heat dissipation element 50, thereby ensuring the heat dissipation effect on the semiconductor chip 30.

[0061] like Figure 7 As shown, the semiconductor packaging structure also includes a first connecting plate 1001, a second connecting plate 1002 and an insulating block 1003 which are spaced apart from each other, the first connecting plate 1001 is electrically connected to the first pole of the semiconductor chip 30, the second connecting plate 1002 is electrically connected to the second pole of the semiconductor chip 30, the terminal portion 40 includes a first connecting terminal connected to the first connecting plate 1001 and a second connecting terminal connected to the second connecting plate 1002, and the semiconductor packaging structure also includes an insulating block 1003 which is arranged between the first connecting plate 1001 and the second connecting plate 1002. Specifically, the two ends of the insulating block 1003 are respectively connected to the two opposite inner surfaces of the second enclosure 19, so that the substrate 20 is divided into two mutually isolated areas by the insulating block 1003, namely the first divided area and the second divided area. The first connecting board 1001 is located in the first divided area, and the second connecting board 1002 is located in the second divided area. Since the first connecting board 1001 is electrically connected to the source of the semiconductor chip 30, and the second connecting board 1002 is electrically connected to the drain of the semiconductor chip 30, the voltage difference between the first connecting board 1001 and the second connecting board 1002 is large. The insulating block 1003 makes the first connecting board 1001 and the second connecting board 1002 have a large surface distance. The insulating block 1003 has a suitable length to ensure the insulation between the first connecting board 1001 and the second connecting board 1002, thereby ensuring the insulation performance of the semiconductor packaging structure.

[0062] It should be noted that "creepage distance" refers to the shortest path along the surface of the insulating material between two conductive parts. Creepage distance / creepage distance design is a necessary measure taken by electrical equipment at different voltage levels to prevent tracking and creepage discharge.

[0063] It should be noted that the semiconductor chip 30 and the second connecting plate 1002 are connected by a sintering process. The sintering process may be a nanosilver sintering process. The semiconductor chip 30 and the second connecting plate 1002 are made by the nanosilver sintering process so that the semiconductor packaging structure can withstand an operating temperature of more than 300°C, which is higher than the operating temperature of the semiconductor chip and the second connecting plate made by the traditional welding process. The nanosilver sintering process is an innovative material connection technology, which is particularly suitable for the manufacture of electronic packaging and high-power devices. This process forms a connection layer with high conductivity and high thermal conductivity by sintering nano-scale silver particles at low temperature, and has significant technical advantages and wide application potential. The nanosilver sintering process has become an important technology in the manufacture of electronic packaging and high-power devices with its low-temperature sintering, high conductivity, high thermal conductivity, structural strength and environmental protection characteristics. The nanosilver sintering process not only improves the performance and reliability of the semiconductor packaging structure, but also provides a green and environmentally friendly solution. The benefits of using the nanosilver sintering process are as follows: 1. Low-temperature sintering: One of the main advantages of the nanosilver sintering process is its low-temperature sintering characteristics. Traditional metal sintering processes usually require high temperatures (over 800°C) to achieve effective sintering, while nanosilver sintering can be completed between 200°C and 300°C. This low-temperature sintering feature makes the process particularly suitable for temperature-sensitive electronic components and materials, such as certain semiconductors and organic materials, thereby avoiding thermal damage and material degradation that may be caused by high temperatures. 2. High conductivity: The connection layer formed by nanosilver particles after sintering has excellent conductive properties. As a metal, silver has the highest conductivity among all metals. The nanosilver sintering process can achieve close connection between silver particles at a lower temperature, thereby forming a low-resistance connection layer. This can significantly improve performance and efficiency for electronic devices and circuit boards that require efficient electrical transmission. 3. High thermal conductivity: In addition to high conductivity, the nanosilver sintered layer also has high thermal conductivity. This means that it can effectively dissipate heat and avoid failure or performance degradation of electronic devices due to overheating. In high-power devices such as power semiconductors, LEDs, and high-frequency communication equipment, good thermal management is a key factor in ensuring their stability and long life. 4. Structural strength and stability: The nanosilver sintering process can achieve close bonding of silver particles at a lower temperature to form a connection layer with high structural strength and stability. Compared with traditional welding methods, the nanosilver sintered layer has higher reliability and durability, and can better resist fatigue and damage caused by stress and thermal cycles. 5. Environmental protection characteristics: The nanosilver sintering process is lead-free and meets environmental protection requirements. Traditional welding processes often use lead-containing solder, which is harmful to the environment and health despite its superior performance. Nanosilver sintering provides a green alternative that is in line with the future environmental protection development trend in the field of electronic packaging and manufacturing. 6. Process flexibility: Nanosilver sintering materials are usually in the form of paste and can be coated and printed by a variety of methods such as screen printing, spraying or dispensing.This flexibility enables the process to be adapted to different manufacturing needs and design requirements, providing greater design freedom and manufacturing efficiency.

[0064] In addition, the second connecting plate 1002 can be made of copper, and the substrate 20 can be made of ceramic, that is, the second connecting plate 1002 and the substrate 20 can be made of copper clad on a ceramic substrate. The above copper-clad ceramic structure can be made in the following ways: DBC (Direct Bonded Copper): Through the hot melt bonding method, copper foil is directly sintered to the surface of Al2O3 and AlN ceramics at high temperature to form a composite substrate. Thanks to the high eutectic bonding strength between copper foil and ceramic, the copper thickness of the DBC substrate can generally be 100μm-600μm. At the same time, ceramics and copper have good thermal conductivity, and the thermal stability of the DBC substrate is also good. AMB (Active Metal Brazing): AMB is developed on the basis of DBC technology. At high temperature, AgCu solder containing active elements Ti and Zr wets and reacts at the interface between ceramic and metal, thereby realizing heterogeneous bonding between ceramic and metal.

[0065] In the present embodiment, the second connecting plate 1002 is connected between the semiconductor chip 30 and the substrate 20. Specifically, in the present embodiment, the semiconductor chip 30 is directly connected to the substrate 20 through the second connecting plate 1002. That is to say, the semiconductor chip 30 is directly connected to the substrate 20 through the second connecting plate 1002. Compared with the solution in the related art of connecting the packaging shell and the power semiconductor chip through the lining plate and the connecting part between the lining plate and the shell, the present embodiment simplifies the heat dissipation path between the semiconductor chip 30 and the substrate 20, and reduces the thermal resistance on the heat dissipation path, so that the heat generated by the semiconductor chip 30 during operation can be better transferred to the substrate 20, which is more conducive to the heat dissipation of the semiconductor chip 30. It should be noted that the semiconductor chip 30 will generate more heat when working, so the heat in the second divided area is obviously higher than the heat in the first divided area.

[0066] like Fig.10As shown, the semiconductor packaging structure also includes a first partition 155 arranged in the second cavity 112 and connected to the substrate 20, the first partition 155 divides the substrate 20 into a first area corresponding to the first connecting plate 1001 and a second area corresponding to the second connecting plate 1002, the first end of the first partition 155 is spaced apart from the third plate body 191, the second end of the first partition 155 is connected to the fourth plate body 192, the second inlet 14 is arranged corresponding to the second area, the second outlet 15 is arranged corresponding to the first area, the first partition 155 is abutted against the second cover plate 17, and a plurality of flow holes are arranged on the first partition 155. The semiconductor packaging structure also includes a plurality of second partitions 156 arranged in the second cavity 112 and connected to the substrate 20. The second partitions 156 are located in the second area and are spaced apart along the direction from the third plate body 191 to the fourth plate body 192. The second partitions 156 are abutted against the second cover plate 17. Among two adjacent second partitions 156, the first second partition 156 is abutted against the first partition 155 and is spaced apart from the second enclosure 19, and the second second partition 156 is spaced apart from the first partition 155 and is abutted against the second enclosure 19. In this way, the first dividing area is set corresponding to the first area, and the second dividing area is set corresponding to the second area. The first partition 155 and the second partition 156 can form two flow channels in the second cavity 112, namely the first flow channel and the second flow channel. The first flow channel is set corresponding to the first area, and the second flow channel is set corresponding to the second area. The heat generated by the semiconductor chip 30 when working makes the heat on the heat sink 50 in the second area more than the heat on the heat sink 50 in the first area, so that the path of the second flow channel is longer than the path of the first flow channel, which can make the heat exchange between the flowing heat dissipation medium in the second flow channel and the corresponding heat sink 50 more sufficient, thereby improving the heat dissipation effect of the semiconductor packaging structure.

[0067] In the description of the present invention, it is necessary to understand that the directions or positional relationships indicated by directional words such as "front, back, up, down, left, right", "lateral, vertical, perpendicular, horizontal" and "top, bottom" are usually based on the directions or positional relationships shown in the drawings. They are only for the convenience of describing the present invention and simplifying the description. Unless otherwise specified, these directional words do not indicate or imply that the devices or elements referred to must have a specific direction or be constructed and operated in a specific direction. Therefore, they cannot be understood as limiting the scope of protection of the present invention. The directional words "inside and outside" refer to the inside and outside relative to the contours of each component itself.

[0068] For ease of description, spatially relative terms such as "above", "above", "on the upper surface of", "above", etc. may be used herein to describe the spatial positional relationship between a device or feature and other devices or features as shown in the figure. It should be understood that spatially relative terms are intended to include different orientations of the device in use or operation in addition to the orientation described in the figure. For example, if the device in the accompanying drawings is inverted, the device described as "above other devices or structures" or "above other devices or structures" will be positioned as "below other devices or structures" or "below other devices or structures". Thus, the exemplary term "above" may include both "above" and "below". The device may also be positioned in other different ways (rotated 90 degrees or in other orientations), and the spatially relative descriptions used herein are interpreted accordingly.

[0069] In addition, it should be noted that the use of terms such as "first" and "second" to limit components is only for the convenience of distinguishing the corresponding components. If not otherwise stated, the above terms have no special meaning and therefore cannot be understood as limiting the scope of protection of the present invention.

[0070] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. For those skilled in the art, the present invention may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

Claims

1. A semiconductor packaging structure, characterized in that: include: A packaging shell (10) having a first cavity (111), wherein the packaging shell (10) comprises a substrate (20); A semiconductor chip (30) connected to the substrate (20); A terminal portion (40) electrically connected to an electrode of the semiconductor chip (30); The packaging shell (10) is provided with a first inlet (12) and a first outlet (13), and the first inlet (12) and the first outlet (13) are both connected to the first cavity (111) so that an insulating heat dissipation medium can enter the first cavity (111) through the first inlet (12) and flow out to the outside of the first cavity (111) through the first outlet (13), and the semiconductor chip (30) is immersed in the insulating heat dissipation medium; The semiconductor packaging structure further comprises a heat sink (50) connected to the substrate (20), wherein the heat sink (50) and the semiconductor chip (30) are located on both sides of the substrate (20); The packaging shell (10) further comprises a second cover plate (17) and a second enclosure plate (19); the second enclosure plate (19) is arranged between the second cover plate (17) and the substrate (20) to form a second cavity (112); the heat sink (50) is located in the second cavity (112); and the second enclosure plate (19) is provided with a second inlet (14) and a second outlet (15) which are in communication with the second cavity (112), so that a heat dissipation medium can enter the second cavity (112) through the second inlet (14) and flow out to the outside of the second cavity (112) through the second outlet (15).

2. The semiconductor package structure according to claim 1, wherein: The packaging shell (10) further comprises a first cover plate (16) and a first enclosure plate (18); the first enclosure plate (18) is arranged between the first cover plate (16) and the substrate (20) to form the first cavity (111); the first enclosure plate (18) comprises a first plate body (181) and a second plate body (182); the first plate body (181) and the second plate body (182) are arranged opposite to each other; the first inlet (12) is arranged on the first plate body (181); and the first outlet (13) is arranged on the second plate body (182).

3. The semiconductor package structure according to claim 2, characterized in that: The first enclosure (18) is a rectangular frame structure, the first enclosure (18) having a vertical symmetry plane, the vertical symmetry plane passing through the first plate body (181) and the second plate body (182), the first inlet (12) and the first outlet (13) being respectively located on both sides of the vertical symmetry plane.

4. The semiconductor package structure according to claim 1, wherein: The second enclosure plate (19) comprises a third plate body (191) and a fourth plate body (192) which are arranged opposite to each other, the second inlet (14) is arranged on the third plate body (191), and the second outlet (15) is arranged on the fourth plate body (192).

5. The semiconductor package structure according to claim 4, characterized in that: The semiconductor packaging structure further comprises a first connecting plate (1001), a second connecting plate (1002) and an insulating block (1003) which are arranged at intervals, wherein the first connecting plate (1001) is electrically connected to a first pole of the semiconductor chip (30), and the second connecting plate (1002) is electrically connected to a second pole of the semiconductor chip (30), the terminal portion (40) comprises a first connecting terminal connected to the first connecting plate (1001) and a second connecting terminal connected to the second connecting plate (1002), and the semiconductor packaging structure further comprises an insulating block (1003) arranged between the first connecting plate (1001) and the second connecting plate (1002).

6. The semiconductor package structure according to claim 3, characterized in that: The semiconductor packaging structure further comprises a first insulating bump (71) and a second insulating bump (72) connected to the substrate (20), the first insulating bump (71) and the second insulating bump (72) being arranged at intervals along the length direction of the first enclosure (18), the semiconductor chip (30) comprising a first chip (31) and a second chip (32), the first chip (31) being located on a side of the first insulating bump (71) away from the second insulating bump (72), and the second chip (32) being located on a side of the second insulating bump (72) away from the first insulating bump (71).

7. The semiconductor package structure according to claim 6, characterized in that: The terminal portion (40) comprises a first terminal (41), the first terminal (41) being located between the first insulating protrusion (71) and the second insulating protrusion (72), the first terminal (41) being electrically connected to a first pole of the first chip (31) and a first pole of the second chip (32).

8. The semiconductor package structure according to claim 7, characterized in that: The terminal portion (40) further comprises a second terminal (42) and a third terminal (43), wherein the second terminal (42) is electrically connected to the third pole of the first chip (31), and the third terminal (43) is electrically connected to the third pole of the second chip (32), and the second terminal (42) and the third terminal (43) are both located between the first insulating protrusion (71) and the second insulating protrusion (72) and on both sides of the first terminal (41).

9. The semiconductor package structure according to claim 7, wherein: The terminal portion (40) further includes a fourth terminal (44) and a fifth terminal (45), wherein the fourth terminal (44) is electrically connected to the second pole of the first chip (31), and the fifth terminal (45) is electrically connected to the second pole of the second chip (32), and the fourth terminal (44) is located on a side of the first insulating protrusion (71) away from the second insulating protrusion (72), and the fifth terminal (45) is located on a side of the second insulating protrusion (72) away from the first insulating protrusion (71).

10. The semiconductor package structure according to claim 7, wherein: The semiconductor packaging structure further comprises a sealing sleeve (90), wherein the sealing sleeve (90) is arranged between the first terminal (41) and the packaging shell (10).

11. The semiconductor package structure according to any one of claims 1 to 3, characterized in that: The semiconductor packaging structure further comprises a metal connecting sheet (80), the semiconductor chip (30) is connected to the substrate (20) via the metal connecting sheet (80), and the terminal portion (40) is electrically connected to an electrode of the semiconductor chip (30) via the metal connecting sheet (80).

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