Semiconductor devices and electronic devices

Abstract

This application provides a semiconductor device and an electronic device. The semiconductor device, in a second direction, makes the ratio of the dielectric constant to the thickness of the portion of the gate insulating layer located in the middle region of the channel greater than the ratio of the dielectric constant to the thickness of the edge region of the gate insulating layer located in the channel. This results in the capacitance between the gate and the channel in the middle region of the semiconductor device being greater than the capacitance between the gate and the channel in the edge region. This allows the middle region of the channel to turn on before the edge region of the channel, eliminating peak current, reducing the subthreshold swing of the semiconductor device, improving the performance of the semiconductor device, and thereby improving display uniformity.

Description

Technical Field

[0001] This application relates to the field of display technology, and in particular to a semiconductor device and an electronic device. Background Technology

[0002] With the development of display devices, the requirements for thin-film transistors (TFTs) in existing display devices are becoming increasingly stringent. Low-temperature polycrystalline silicon (LTPS) TFTs are widely used due to their advantages of fast switching speed and low power consumption. However, during the use of LTPS, a "hump" characteristic has been found, leading to uneven brightness in display devices at low grayscale levels. This is because, along the edge of the channel width, under gate bias, geometric effects result in a higher electric field at the channel edge. More charge carriers are trapped at the width edge, forming parasitic transistors, thus creating a hump current at the edge. This causes the edge region of the LTPS to turn on earlier than the central region, increasing the subthreshold swing of the LTPS, leading to uneven pixel charging and consequently, uneven display performance.

[0003] Therefore, existing display devices suffer from a technical problem where the edge regions of thin-film transistors turn on earlier than the central regions, resulting in uneven display. Summary of the Invention

[0004] This application provides a semiconductor device and an electronic device to solve the technical problem of uneven display caused by the edge region of the thin-film transistor turning on earlier than the middle region in existing display devices.

[0005] This application provides a semiconductor device, which includes:

[0006] Substrate;

[0007] An active layer is disposed on one side of the substrate, the active layer including a channel portion and doped portions located on both sides of the channel portion;

[0008] A gate layer is disposed on one side of the substrate;

[0009] A gate insulating layer is disposed between the active layer and the gate layer;

[0010] The active layer has a first direction and a second direction that are perpendicular to each other on the plane. The direction in which the channel portion points to the doped portion is the first direction. In the second direction, the ratio of the dielectric constant to the thickness of the portion of the gate insulating layer located in the middle region of the channel portion is greater than the ratio of the dielectric constant to the thickness of the portion of the gate insulating layer located in the edge region of the channel portion.

[0011] In some embodiments, in the second direction, the thickness of the portion of the gate insulating layer located in the middle region of the channel is less than or equal to the thickness of the portion of the gate insulating layer located in the edge region of the channel, and the dielectric constant of the portion of the gate insulating layer located in the middle region of the channel is greater than the dielectric constant of the portion of the gate insulating layer located in the edge region of the channel.

[0012] In some embodiments, in the second direction, the thickness of the portion of the gate insulating layer located in the middle region of the channel is greater than the thickness of the portion of the gate insulating layer located in the edge region of the channel, and the dielectric constant of the portion of the gate insulating layer located in the middle region of the channel is greater than the dielectric constant of the portion of the gate insulating layer located in the edge region of the channel.

[0013] In some embodiments, the material of the portion of the gate insulating layer located in the middle region of the channel portion is different from the material of the portion of the gate insulating layer located in the edge region of the channel portion.

[0014] In some embodiments, the gate layer is disposed on the side of the active layer away from the substrate, the gate insulating layer includes at least a first gate insulating layer and a second gate insulating layer, the dielectric constant of the second gate insulating layer is greater than the dielectric constant of the first gate insulating layer, in a second direction, the projection of the second gate insulating layer on the substrate does not overlap with the projection of the channel portion in the edge region on the substrate, and the thickness of the portion of the first gate insulating layer located in the middle region is less than the thickness of the portion of the first gate insulating layer located in the edge region.

[0015] In some embodiments, the first gate insulating layer is disposed between the second gate insulating layer and the active layer; or the second gate insulating layer is disposed between the first gate insulating layer and the active layer.

[0016] In some embodiments, the semiconductor device further includes a source-drain layer, the source-drain layer including a source and a drain, the source and the drain being connected to the doped portions located on both sides of the channel portion; wherein, the second gate insulating layer is disposed in the disposed regions of the source and the drain, and the source and the drain are connected to the doped portions through vias in the second gate insulating layer.

[0017] In some embodiments, the pattern of the second gate insulating layer is the same as the pattern of the active layer.

[0018] In some embodiments, the gate layer is disposed between the active layer and the substrate; or the gate layer is disposed on the side of the active layer away from the substrate.

[0019] Meanwhile, this application provides an electronic device, which includes a semiconductor device as described in any of the above embodiments.

[0020] Beneficial effects: This application provides a semiconductor device and an electronic device; the semiconductor device, by making the ratio of the dielectric constant to the thickness of the portion of the gate insulating layer located in the middle region of the channel portion greater than the ratio of the dielectric constant to the thickness of the edge region of the gate insulating layer located in the channel portion in a second direction, makes the capacitance of the gate and channel portion in the middle region of the semiconductor device greater than the capacitance of the gate and channel portion in the edge region, so that the middle region of the channel portion can turn on before the edge region of the channel portion, eliminating the peak current, reducing the subthreshold swing of the semiconductor device, improving the performance of the semiconductor device, and thereby improving display uniformity. Attached Figure Description

[0021] The technical solution and other beneficial effects of this application will become apparent from the following detailed description of specific embodiments in conjunction with the accompanying drawings.

[0022] Figure 1 Perspective view for comparison of semiconductor devices.

[0023] Figure 2 for Figure 1 A cross-sectional view of a semiconductor device.

[0024] Figure 3 A perspective view of a semiconductor device provided in an embodiment of this application.

[0025] Figure 4 for Figure 3 The first cross-sectional view of a semiconductor device.

[0026] Figure 5 for Figure 3 The second cross-sectional view of the semiconductor device.

[0027] Figure 6 for Figure 4 The diagram shows the structure of a semiconductor device corresponding to some steps in the fabrication method of the semiconductor device.

[0028] Figure 7 for Figure 4 The schematic diagram of the semiconductor device structure corresponds to some other steps in the semiconductor device fabrication method.

[0029] Figure 8 for Figure 5 The diagram shows the structure of a semiconductor device corresponding to some steps in the fabrication method of the semiconductor device.

[0030] Figure 9for Figure 5 The schematic diagram of the semiconductor device structure corresponds to some other steps in the semiconductor device fabrication method.

[0031] Figure 10 A cross-sectional view of a semiconductor device provided in an embodiment of this application.

[0032] Figure 11 for Figure 10 TCAD simulation diagram of electric field distribution of semiconductor devices.

[0033] Figure 12 This is a graph showing the gate voltage versus drain current for different semiconductor devices.

[0034] Figure 13 for Figure 3 The third cross-sectional view of the semiconductor device. Detailed Implementation

[0035] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.

[0036] In the description of this application, it should be understood that the terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," and "counterclockwise," etc., indicating orientation or positional relationships based on the orientation or positional relationships shown in the accompanying drawings, are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this application. Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, features defined with "first" and "second" may explicitly or implicitly include one or more of the stated features. In the description of this application, "a plurality of" means two or more, unless otherwise explicitly specified.

[0037] In the description of this application, it should be noted that, unless otherwise expressly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection, an electrical connection, or a connection that allows communication between them; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication between two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this application according to the specific circumstances.

[0038] In this application, unless otherwise expressly specified and limited, "above" or "below" the second feature can include direct contact between the first and second features, or contact between the first and second features through another feature between them. Furthermore, "above," "over," and "on top" of the second feature includes the first feature being directly above or diagonally above the second feature, or simply indicates that the first feature is at a higher horizontal level than the second feature. "Below," "below," and "under" the second feature includes the first feature being directly below or diagonally below the second feature, or simply indicates that the first feature is at a lower horizontal level than the second feature.

[0039] The following disclosure provides many different embodiments or examples for implementing different structures of this application. To simplify the disclosure, specific examples of components and arrangements are described below. Of course, these are merely examples and are not intended to limit the scope of this application. Furthermore, reference numerals and / or letters may be repeated in different examples; such repetition is for simplification and clarity and does not in itself indicate a relationship between the various embodiments and / or arrangements discussed. In addition, various specific examples of processes and materials are provided in this application, but those skilled in the art will recognize the application of other processes and / or the use of other materials.

[0040] Figure 1 To compare the perspective views of semiconductor devices, Figure 2 (a) is Figure 1 A cross-sectional view of the semiconductor device in the diagram. Figure 2 (b) in the middle is Figure 1 BB cross-sectional view of semiconductor devices in the image.

[0041] As an introduction to the embodiments of this application, a comparative semiconductor device is provided to illustrate the principle behind the technical problem to be solved by the embodiments of this application. Figure 1 , Figure 2As shown, the comparative semiconductor device includes a substrate 11, a light-shielding film 12, a first insulating film 13, an active film 14, a second insulating film 15, a gate film 16, a third insulating film 17, and a source / drain film 18. The active film 14 includes a channel region 143, a lightly doped region 142, and a heavily doped region 141. During the use of the comparative semiconductor device, it was found that under gate bias, due to geometric effects (specifically, an angle at the edge region), the electric field at the edge of the channel region 143 is higher. More charge carriers are trapped at the wide edge, forming parasitic transistors, resulting in a peak current at the edge. This causes the edge region of the low-temperature polycrystalline silicon thin-film transistor to turn on earlier than the middle region, increasing the subthreshold swing of the low-temperature polycrystalline silicon thin-film transistor, leading to uneven pixel charging and consequently, uneven display. Therefore, existing display devices suffer from the technical problem of uneven display caused by the edge region of the thin-film transistor turning on earlier than the middle region.

[0042] This application provides a semiconductor device and an electronic device to address the aforementioned technical problems.

[0043] Figure 3 A perspective view of a semiconductor device provided in an embodiment of this application. Figure 4 for Figure 3 The first cross-sectional view of a semiconductor device in a photograph; Figure 4 (a) in the middle is Figure 3 The first AA cross-sectional view of the semiconductor device in the diagram. Figure 4 (b) in the middle is Figure 3 The first BB cross-sectional view of a semiconductor device in the image. Figure 5 for Figure 3 A second cross-sectional view of a semiconductor device in a photograph; Figure 5 (a) in the middle is Figure 3 The second type of AA cross-sectional view of the semiconductor device in the diagram. Figure 5 (b) in the middle is Figure 3 The second type of BB cross-section diagram of the semiconductor device.

[0044] Figure 6 for Figure 4 The diagram shows the structure of a semiconductor device corresponding to some steps in the fabrication method of the semiconductor device. Figure 7 for Figure 4 The schematic diagram of the semiconductor device structure corresponds to some other steps in the semiconductor device fabrication method. Figure 8 for Figure 5 The diagram shows the structure of a semiconductor device corresponding to some steps in the fabrication method of the semiconductor device. Figure 9 for Figure 5 The schematic diagram of the semiconductor device structure corresponds to some other steps in the semiconductor device fabrication method. Figure 10A cross-sectional view of a semiconductor device provided in an embodiment of this application. Figure 11 for Figure 10 TCAD simulation diagram of electric field distribution of semiconductor devices. Figure 12 This is a graph showing the gate voltage versus drain current for different semiconductor devices. Figure 13 for Figure 3 A third cross-sectional view of a semiconductor device in a photograph; Figure 13 (a) in the middle is Figure 3 The third type of AA cross-sectional view of the semiconductor device in the diagram. Figure 13 (b) in the middle is Figure 3 The third type of BB cross-section diagram of semiconductor devices.

[0045] Specifically, it is understood that, due to the embodiments of this application Figure 3 Only the light-shielding layer, active layer, and gate layer are shown in the image; therefore, Figure 4 and Figure 5 The perspective views of the corresponding semiconductor devices are the same, all of which are Figure 3 A perspective view of the semiconductor device shown. But... Figure 4 and Figure 5 The film layer structures in the diagrams are not the same, and when the perspective view of the corresponding semiconductor device includes all film layers, Figure 4 and Figure 5 The perspective views of the corresponding semiconductor devices are different.

[0046] like Figures 3 to 5 As shown, this application provides a semiconductor device 2, which includes a substrate 21, an active layer 25, a gate layer 27, and a gate insulating layer 26. The active layer 25 is disposed on one side of the substrate 21 and includes a channel portion 251 and doped portions 253 located on both sides of the channel portion 251. The gate layer 27 is disposed on one side of the substrate 21, and the gate insulating layer 26 is disposed between the active layer 25 and the gate layer 27.

[0047] Specifically, the active layer 25 has a first direction X and a second direction Y that are perpendicular to each other on the plane. The direction of the channel portion 251 pointing to the doped portion 253 is the first direction X. In the second direction Y, the ratio of the dielectric constant to the thickness of the portion of the gate insulating layer 26 located in the middle region 251a of the channel portion 251 is greater than the ratio of the dielectric constant to the thickness of the portion of the gate insulating layer 26 located in the edge region 251b of the channel portion 251.

[0048] This application provides a semiconductor device and an electronic device. The semiconductor device, in a second direction, makes the ratio of the dielectric constant to the thickness of the portion of the gate insulating layer located in the middle region of the channel greater than the ratio of the dielectric constant to the thickness of the edge region of the gate insulating layer located in the channel. This results in the capacitance between the gate and the channel in the middle region of the semiconductor device being greater than the capacitance between the gate and the channel in the edge region. This allows the middle region of the channel to turn on before the edge region of the channel, eliminating peak current, reducing the subthreshold swing of the semiconductor device, improving the performance of the semiconductor device, and thereby improving display uniformity.

[0049] Specifically, the plane where the active layer is located can be understood as the plane of the active layer from a top-down angle.

[0050] Specifically, it is understood that the middle region and edge region defined in the embodiments of this application are for the purpose of describing the relative positions of the middle region and the edge region. The edge region refers to the region that is opened earlier than other regions when the technical solution described in the embodiments of this application is not adopted. The size of the middle region and the edge region is determined according to the actual situation. For example, in the comparison semiconductor device, if the left side region with a width of 1 micrometer and the right side region with a width of 1 micrometer of the channel are opened earlier than the middle region, then the left side region with a width of 1 micrometer and the right side region with a width of 1 micrometer of the channel can be defined as the edge region.

[0051] Specifically, it is understood that in the embodiments of this application... Figure 1 , Figure 3 In this diagram, to illustrate the specific design of the active layer, the structure of the active layer is shown while the structure of the gate is obscured. However, the relative positions of the active and gate layers can actually be as follows: Figure 2 , Figure 4 and Figure 5 As shown, in actual top-view angles, when the semiconductor device includes a top-gate thin-film transistor, the gate layer covers the active layer; in actual top-view angles, when the semiconductor device includes a bottom-gate thin-film transistor, the active layer covers the gate layer. Therefore, the perspective view in the embodiments of this application does not limit the relative positions of the gate and the active layer, and their relative positions can be determined according to different designs. In the embodiments of this application, different embodiments are described using thin-film transistors with top-gate and bottom-gate structures as examples.

[0052] Specifically, the semiconductor device can be an array substrate, and the semiconductor device can include a thin-film transistor.

[0053] Specifically, compared to other semiconductor devices, for top-gate thin-film transistors, the edge region of the channel is thinner than the middle region during fabrication, resulting in a larger capacitance in the edge region. Furthermore, for both top-gate and bottom-gate thin-film transistors, the edge of the channel experiences a concentrated electric field due to the slope, leading to premature turn-on of the edge region and resulting in a peak current. In this embodiment, the capacitance between the gate and the channel in the middle region of the semiconductor device is made greater than that between the gate and the channel in the edge region, allowing the middle region of the channel to turn on before the edge region, thus eliminating the peak current.

[0054] Specifically, when the portion of the gate insulating layer located in the middle region of the channel is formed using a single material, the dielectric constant of this portion is the dielectric constant of that material. For example, if the portion of the gate insulating layer located in the middle region of the channel is formed using silicon nitride, the dielectric constant of this portion is the dielectric constant of silicon nitride. When the portion of the gate insulating layer located in the middle region of the channel is formed using at least two materials, the dielectric constant of this portion can be determined based on the dielectric constants of the two materials, as detailed in the following embodiments. Similarly, the dielectric constant of the portion of the gate insulating layer located in the edge region can also be determined as described above.

[0055] Specifically, when there is only one layer in the middle region of the gate insulating layer located in the channel portion, the thickness of this portion is equal to the thickness of the film layer. When there are at least two layers in the middle region of the gate insulating layer located in the channel portion, the thickness of this portion is the sum of the thicknesses of the at least two film layers. Similarly, the thickness of the portion of the gate insulating layer located in the edge region can also be determined according to the above description.

[0056] Specifically, the capacitor described in the embodiments of this application is a capacitor formed by the gate and the channel.

[0057] In some embodiments, in the second direction Y, the dielectric constant of the portion of the gate insulating layer 26 located in the middle region 251a of the channel portion 251 is greater than the dielectric constant of the portion of the gate insulating layer 26 located in the edge region 251b of the channel portion 251. By making the dielectric constant of the portion of the gate insulating layer located in the middle region of the channel portion greater than the dielectric constant of the portion of the gate insulating layer located in the edge region of the channel portion, the capacitance of the middle region of the channel portion of the semiconductor device can be increased by increasing the dielectric constant of the portion of the gate insulating layer located in the middle region of the channel portion. This allows the middle region of the channel portion to turn on before the edge region of the channel portion, eliminating peak current, reducing the subthreshold swing of the semiconductor device, improving the performance of the semiconductor device, and thus improving display uniformity.

[0058] In some embodiments, in the second direction Y, the thickness of the portion of the gate insulating layer 26 located in the middle region 251a of the channel portion 251 is less than or equal to the thickness of the portion of the gate insulating layer 26 located in the edge region 251b of the channel portion 251, and the dielectric constant of the portion of the gate insulating layer 26 located in the middle region 251a of the channel portion 251 is greater than the dielectric constant of the portion of the gate insulating layer 26 located in the edge region 251b of the channel portion 251. By making the thickness of the portion of the gate insulating layer located in the middle region of the channel portion less than or equal to the thickness of the portion of the gate insulating layer located in the edge region of the channel portion, and by making the dielectric constant of the portion of the gate insulating layer located in the middle region of the channel portion greater than the dielectric constant of the portion of the gate insulating layer located in the edge region of the channel portion, the capacitance between the gate and the channel portion in the middle region of the semiconductor device can be made greater than the capacitance between the gate and the channel portion in the edge region. This allows the middle region of the channel portion to turn on before the edge region of the channel portion, eliminating peak current, reducing the subthreshold swing of the semiconductor device, improving the performance of the semiconductor device, and thus improving display uniformity.

[0059] In some embodiments, in the second direction Y, the thickness of the portion of the gate insulating layer 26 located in the middle region 251a of the channel portion 251 is greater than the thickness of the portion of the gate insulating layer 26 located in the edge region 251b of the channel portion 251, and the dielectric constant of the portion of the gate insulating layer 26 located in the middle region 251a of the channel portion 251 is greater than the dielectric constant of the portion of the gate insulating layer 26 located in the edge region 251b of the channel portion 251. By making the thickness of the portion of the gate insulating layer located in the middle region of the channel greater than the thickness of the portion of the gate insulating layer located in the edge region of the channel, and the dielectric constant of the portion of the gate insulating layer located in the middle region of the channel greater than the dielectric constant of the portion of the gate insulating layer located in the edge region of the channel, and the ratio of the dielectric constant to the thickness of the portion of the gate insulating layer located in the middle region of the channel greater than the ratio of the dielectric constant to the thickness of the portion of the gate insulating layer located in the edge region of the channel, the capacitance of the gate and channel in the middle region of the semiconductor device can be made greater than the capacitance of the gate and channel in the edge region. This allows the middle region of the channel to turn on before the edge region of the channel, eliminating peak current, reducing the subthreshold swing of the semiconductor device, improving the performance of the semiconductor device, and thus improving display uniformity.

[0060] In some embodiments, the material of the portion of the gate insulating layer 26 located in the middle region 251a of the channel portion 251 is different from the material of the portion of the gate insulating layer 26 located in the edge region 251b of the channel portion 251. By making the material of the portion of the gate insulating layer located in the middle region of the channel portion different from the material of the portion of the gate insulating layer located in the edge region of the channel portion, the capacitance of the gate and channel portion in the middle region of the semiconductor device can be made greater than that in the edge region by the difference in dielectric constant of the different materials. This eliminates peak current, reduces the subthreshold swing of the semiconductor device, improves the performance of the semiconductor device, and thus improves display uniformity.

[0061] Specifically, for example, the portion of the gate insulating layer located in the middle region of the channel has only one film layer made of silicon nitride, and the portion of the gate insulating layer located in the edge region of the channel has only one film layer made of silicon oxide. Under the same conditions, the dielectric constant of silicon nitride is measured to be 7, and the dielectric constant of silicon oxide is 3. The capacitance formula is: C = εS / 4πkd, where C is the capacitance, ε is the dielectric constant of the material, S is the area of ​​the two plates facing each other, k is the electrostatic constant, and d is the distance between the two plates. In the embodiments of this application, S is the area of ​​the gate and the channel facing each other, and d is the area of ​​the gate and the channel facing each other. The thickness of the gate insulating layer between channels, with other parameters remaining constant, is such that the material of the middle region of the gate insulating layer in the channel is silicon nitride, and the material of the edge region of the gate insulating layer in the channel is silicon oxide. This results in the dielectric constant of the middle region of the gate insulating layer being greater than that of the edge region. Furthermore, the thickness of the edge region of the gate insulating layer and the thickness of the middle region of the channel can vary in several ways, as follows: First: Gate insulating layer... In the first scenario, the thickness of the portion of the gate insulating layer located in the middle region of the channel is less than the thickness of the portion located in the edge region of the channel. In this case, the ratio of the dielectric constant to the thickness of the portion of the gate insulating layer located in the middle region of the channel is necessarily greater than the ratio of the dielectric constant to the thickness of the portion of the gate insulating layer located in the edge region of the channel. In the second scenario, the thickness of the portion of the gate insulating layer located in the middle region of the channel is equal to the thickness of the portion of the gate insulating layer located in the edge region of the channel. In this case, the ratio of the dielectric constant to the thickness of the portion of the gate insulating layer located in the middle region of the channel is necessarily greater than the ratio of the dielectric constant to the thickness of the portion of the gate insulating layer located in the edge region of the channel. The ratio of the dielectric constant to the thickness of the edge region of the channel in the layer; the third type: the thickness of the portion of the gate insulating layer located in the middle region of the channel is greater than the thickness of the portion of the gate insulating layer located in the edge region of the channel. In this case, the thickness can be adjusted so that the ratio of the dielectric constant to the thickness of the portion of the gate insulating layer located in the middle region of the channel is greater than the ratio of the dielectric constant to the thickness of the portion of the gate insulating layer located in the edge region of the channel, thereby making the capacitance of the gate and channel in the middle region of the semiconductor device greater than the capacitance of the gate and channel in the edge region.

[0062] Specifically, for example, the thickness of the portion of the gate insulating layer located in the middle region of the channel is 1000, and the thickness of the portion of the gate insulating layer located in the middle region of the channel can be 900, 1000, or 1100. In this case, the ratio of the dielectric constant to the thickness of the portion of the gate insulating layer located in the middle region of the channel is 0.007, and the ratios are 0.0033, 0.003, and 0.0027, respectively. It can be seen that when the dielectric constant of the portion of the gate insulating layer located in the middle region of the channel is greater than the dielectric constant of the portion of the gate insulating layer located in the edge region of the channel, and when the thickness of the portion of the gate insulating layer located in the middle region of the channel is less than, equal to, or greater than the thickness of the portion of the gate insulating layer located in the edge region of the channel, the ratio of the dielectric constant to the thickness of the portion of the gate insulating layer located in the middle region of the channel can be greater than the ratio of the dielectric constant to the thickness of the portion of the gate insulating layer located in the edge region of the channel.

[0063] In some embodiments, such as Figures 3 to 5 , Figure 13 As shown, the gate insulating layer 26 includes at least a first gate insulating layer 261 and a second gate insulating layer 262. The dielectric constant of the second gate insulating layer 262 is greater than that of the first gate insulating layer 261. In the second direction Y, the projection of the second gate insulating layer 262 onto the substrate 21 does not overlap with the projection of the channel portion 251 in the edge region 251b onto the substrate 21. Furthermore, the thickness of the portion of the first gate insulating layer 261 located in the intermediate region 251a is less than the thickness of the portion of the first gate insulating layer 261 located in the edge region 251b. By including a first gate insulating layer and a second gate insulating layer, and ensuring that the dielectric constant of the second gate insulating layer is greater than that of the first gate insulating layer, and that the projection of the second gate insulating layer onto the substrate does not overlap with the projection of the channel portion in the edge region onto the substrate, the dielectric constant of the portion of the gate insulating layer located in the intermediate region of the channel can be increased by the second gate insulating layer. This results in the dielectric constant of the portion of the gate insulating layer located in the intermediate region of the channel being greater than that of the portion of the gate insulating layer located in the edge region of the channel.

[0064] Specifically, taking a first gate insulating layer made of silicon oxide and a second gate insulating layer made of silicon nitride, with the dielectric constant of silicon nitride measured to be 7 and the dielectric constant of silicon oxide to be 3 under the same conditions, and assuming the thickness of the portion of the first gate insulating layer located in the middle region of the channel is 1000 mm, the thickness of the portion of the first gate insulating layer located in the edge region of the channel is 1200 mm, and the thickness of the second gate insulating layer is 200 mm, then the thickness is the distance between the gate and the channel. The thickness H1 of the portion of the gate insulating layer located in the middle region of the channel is equal to the thickness H2 of the portion of the gate insulating layer located in the edge region of the channel. Therefore, the dielectric constant ε of the portion of the gate insulating layer located in the middle region of the channel can be determined using the capacitance formula. Specifically, when the insulating medium is the gate insulating layer, the capacitance C0 of the gate and channel located in the middle region can be determined by the following formula: 1 / C0 = 1 / C1 + 1 / C2, where C1 is the dielectric constant of the first gate insulating layer. When the gate insulating layer is in the middle region, the capacitance of the gate and channel is in the middle region. When C2 is the insulating medium and the second gate insulating layer is in the middle region, the capacitance of the gate and channel is in the middle region. When the facing area of ​​the gate and channel and the electrostatic constant are unchanged, we can get the following from the above formula: 1200 / ε=1000 / 3+200 / 7. Then we can calculate that ε is about 3.3. The material of the edge region of the channel in the gate insulating layer is silicon oxide, which has a dielectric constant of 3. The thickness H1 of the middle region of the channel in the gate insulating layer is equal to the thickness H2 of the edge region of the channel in the gate insulating layer. Therefore, we can determine that the capacitance of the gate and channel in the middle region of the semiconductor device is greater than that of the gate and channel in the edge region. This allows the middle region of the channel to turn on before the edge region of the channel, eliminating the peak current, reducing the subthreshold swing of the semiconductor device, improving the performance of the semiconductor device, and thus improving the uniformity of the display.

[0065] Specifically, taking the same example where the material of the first gate insulating layer is silicon oxide and the material of the second gate insulating layer is silicon nitride, and under the same conditions, the dielectric constant of silicon nitride is measured to be 7, the dielectric constant of silicon oxide is 3, and the thickness of the portion of the first gate insulating layer located in the middle region of the channel is 1000, the thickness of the portion of the first gate insulating layer located in the edge region of the channel is 1200, and the thickness of the second gate insulating layer is 100, then the thickness H1 of the portion of the gate insulating layer located in the middle region of the channel is less than the thickness H2 of the portion of the gate insulating layer located in the edge region of the channel. Therefore, the thickness H2 of the portion of the gate insulating layer located in the channel can be determined using the capacitance formula. The dielectric constant ε of the middle region is approximately 3.45, while the material of the edge region of the gate insulating layer located in the channel is silicon oxide, which has a dielectric constant of 3. Furthermore, the thickness H1 of the middle region of the gate insulating layer located in the channel is less than the thickness H2 of the edge region of the gate insulating layer located in the channel. Therefore, it can be determined that the capacitance between the gate and the channel in the middle region of the semiconductor device is greater than that between the gate and the channel in the edge region. This allows the middle region of the channel to turn on before the edge region of the channel, eliminating peak current, reducing the subthreshold swing of the semiconductor device, improving the performance of the semiconductor device, and thus improving display uniformity.

[0066] Specifically, taking the first gate insulating layer as silicon oxide and the second gate insulating layer as silicon nitride, and under the same conditions, the dielectric constant of silicon nitride is measured to be 7, and the dielectric constant of silicon oxide is 3. Furthermore, the thickness of the portion of the first gate insulating layer located in the middle region of the channel is 100 mm, the thickness of the portion of the first gate insulating layer located in the edge region of the channel is 1200 mm, and the thickness of the second gate insulating layer is 1200 mm. Taking this example, the thickness H1 of the portion of the gate insulating layer located in the middle region of the channel is greater than the thickness H2 of the portion of the gate insulating layer located in the edge region of the channel. Therefore, the dielectric constant ε of the portion of the gate insulating layer located in the middle region of the channel can be determined using the capacitance formula to be approximately 6.34. Thus, the gate dielectric constant ε can be calculated. The ratio of the dielectric constant to the thickness of the portion of the polar insulating layer located in the middle region of the channel is approximately 0.0048, while the ratio of the dielectric constant to the thickness of the portion of the gate insulating layer located in the edge region of the channel is 0.003. Therefore, the ratio of the dielectric constant to the thickness of the portion of the gate insulating layer located in the middle region of the channel is greater than that of the portion of the polar insulating layer located in the edge region of the channel. Consequently, the capacitance of the gate and channel located in the middle region of the semiconductor device is greater than that of the gate and channel located in the edge region. This allows the middle region of the channel to turn on before the edge region of the channel, eliminating peak current, reducing the subthreshold swing of the semiconductor device, improving the performance of the semiconductor device, and thus improving display uniformity.

[0067] In some embodiments, such as Figure 4As shown, the first gate insulating layer 261 is disposed between the second gate insulating layer 262 and the active layer 25. By disposing the first gate insulating layer between the second gate insulating layer and the active layer, the second gate insulating layer can be formed without changing the original process, thereby increasing the capacitance of the gate and channel in the middle region of the semiconductor device, eliminating peak current, reducing the subthreshold swing of the semiconductor device, improving the performance of the semiconductor device, and thus improving display uniformity.

[0068] In some embodiments, such as Figure 5 As shown, the second gate insulating layer 262 is disposed between the first gate insulating layer 261 and the active layer 25. By disposing the second gate insulating layer between the first gate insulating layer and the active layer, the capacitance of the gate and channel portions in the middle region of the semiconductor device can be increased, eliminating peak current, reducing the subthreshold swing of the semiconductor device, improving the performance of the semiconductor device, and thus improving display uniformity.

[0069] Specifically, the above embodiments are illustrated using the example of a gate insulating layer including a first gate insulating layer and a second gate insulating layer. However, the embodiments of this application are not limited to this. The gate insulating layer may also include a third gate insulating layer, such that the dielectric constant of the third gate insulating layer is greater than that of the first gate insulating layer. The second and third gate insulating layers are disposed on both sides or on the same side of the first gate insulating layer. The disposed area and thickness of the second and third gate insulating layers can be set according to requirements, ensuring that the ratio of the dielectric constant to the thickness of the portion of the gate insulating layer located in the middle region of the channel is greater than the ratio of the dielectric constant to the thickness of the portion of the gate insulating layer located in the edge region of the channel.

[0070] In some embodiments, such as Figure 4 (a) and Figure 5 As shown in (a), the semiconductor device 2 further includes a source-drain layer 31, which includes a source 311 and a drain 312. The source 311 and the drain 312 are respectively connected to the doped portions 253 located on both sides of the channel portion 251. A second gate insulating layer 262 is disposed in the area where the source 311 and the drain 312 are disposed. The source 311 and the drain 312 are respectively connected to the doped portions 253 through vias in the second gate insulating layer 262. When the second gate insulating layer is disposed, vias can be formed simultaneously with the first gate insulating layer, allowing the source and drain to connect to the doped portions through the vias.

[0071] Specifically, the above embodiment is illustrated by taking the connection between the source and drain through the vias of the second gate insulating layer and the doped portion as an example. However, the embodiments of this application are not limited to this. The second gate insulating layer may not be disposed in the location of the source and drain, thereby reducing vias and improving the yield of semiconductor devices.

[0072] In some embodiments, the pattern of the second gate insulating layer is the same as the pattern of the active layer. By making the pattern of the second gate insulating layer the same as the pattern of the active layer, the same mask can be used to form the second gate insulating layer and the active layer, thereby eliminating the peak current and reducing the subthreshold swing of the semiconductor device without the need for additional masks, reducing process complexity and lowering costs.

[0073] Specifically, in the embodiments of this application, the meaning that the pattern of the second gate insulating layer is the same as the pattern of the active layer is that the pattern of the second gate insulating layer is basically the same as the pattern of the active layer. However, considering the process error and the need to prevent the second gate insulating layer from being disposed in the edge region of the channel, there may be some differences between the two. In this case, it can still be considered that the pattern of the second gate insulating layer is the same as the pattern of the active layer. For example, the pattern of the second gate insulating layer is basically the same as the pattern of the active layer, but when etching the two film layers, due to certain process errors, the shape of a certain edge of the second gate insulating layer is somewhat different from the shape of the corresponding edge of the active layer. In this case, it is still considered that the pattern of the second gate insulating layer is the same as the pattern of the active layer.

[0074] Specifically, the second gate insulating layer and the active layer can be formed using the same mask, so that when forming a semiconductor device, the dielectric constant of the portion of the gate insulating layer located in the middle region of the channel can be increased by the second gate insulating layer without increasing the number of masks required to form the semiconductor device.

[0075] Specifically, when forming the second gate insulating layer and the active layer using the same mask, in order to prevent the second gate insulating layer from being located in the edge region of the channel, the pattern of the second gate insulating layer is slightly smaller than the pattern of the active layer. A large amount of etching material or a gas with a higher etching ratio to the second gate insulating layer can be used to etch the second active layer, such as pentafluoroethane (C2F5H).

[0076] In some embodiments, such as Figure 13 As shown, the gate layer 27 is disposed between the active layer 25 and the substrate 21; or as... Figure 4As shown, the gate layer 27 is disposed on the side of the active layer 25 away from the substrate 21. In this embodiment, for a top-gate thin-film transistor, there is a problem that the edge region of the channel is thinner than the middle region of the channel during fabrication, resulting in a larger capacitance in the edge region. Furthermore, the edge of the channel experiences a slope that causes a concentrated electric field at the tip, leading to premature turn-on in the edge region. Similarly, for a bottom-gate thin-film transistor, the same problem exists where the edge of the channel experiences a slope that causes a concentrated electric field at the tip, also leading to premature turn-on in the edge region. The design of this embodiment can be used to eliminate the peak current.

[0077] Specifically, whether it is a bottom-gate or top-gate thin-film transistor, the ratio of the dielectric constant to the thickness of the portion of the gate insulating layer located in the middle region of the channel can be made greater than the ratio of the dielectric constant to the thickness of the portion of the gate insulating layer located in the edge region of the channel. This allows the middle region of the channel to turn on before the edge region of the channel, eliminating peak current, reducing the subthreshold swing of the semiconductor device, improving the performance of the semiconductor device, and thus improving display uniformity. Therefore, for each embodiment in this application, when there is no conflict in the technical features, it can be applied in both bottom-gate and top-gate thin-film transistors. For example, the gate insulating layer includes at least a first gate insulating layer and a second gate insulating layer, the dielectric constant of the second gate insulating layer is greater than that of the first gate insulating layer, and in the second direction, the projection of the second gate insulating layer on the substrate does not overlap with the projection of the channel portion in the edge region on the substrate, and the thickness of the portion of the first gate insulating layer located in the middle region is less than the thickness of the portion of the first gate insulating layer located in the edge region. This solution can be applied in both bottom-gate and top-gate thin-film transistors. For other embodiments, please refer to the above description, which will not be repeated here.

[0078] In some embodiments, the material of the first gate insulating layer includes silicon oxide, and the material of the second gate insulating layer includes one of silicon nitride, hafnium oxide, zirconium oxide, and titanium oxide. By making the material of the first gate insulating layer silicon oxide and the material of the second gate insulating layer one of silicon nitride, hafnium oxide, zirconium oxide, and titanium oxide, the dielectric constant of the portion of the gate insulating layer located in the middle region can be increased. This results in the capacitance between the gate and the channel in the middle region of the semiconductor device being greater than the capacitance between the gate and the channel in the edge region. Consequently, the middle region of the channel can turn on before the edge region of the channel, eliminating peak current, reducing the subthreshold swing of the semiconductor device, improving the performance of the semiconductor device, and thereby improving display uniformity.

[0079] In some embodiments, such as Figure 4 , Figure 5 As shown, the active layer 25 further includes an electrical adjustment section 252, which is disposed between the channel portion 251 and the doped portion 253. The electrical adjustment section 252 connects the channel portion 251 and the doped portion 253. The ion doping concentration of the electrical adjustment section 252 is lower than that of the doped portion 253, and the ion doping concentration of the electrical adjustment section 252 is greater than that of the channel portion 251. By including an electrical adjustment section in the active layer, the leakage current of the semiconductor device can be reduced, and the performance of the semiconductor device can be improved.

[0080] Specifically, compared to the problem that an active layer consisting only of a channel portion and a doped portion may lead to a large leakage current in semiconductor devices, the embodiments of this application reduce the leakage current of semiconductor devices by providing an electrical adjustment portion, such that the ion doping concentration of the electrical adjustment portion is between the ion doping concentration of the channel portion and the ion doping concentration of the doped portion. However, the embodiments of this application are not limited to this; the active layer may also consist only of a channel portion and a doped portion.

[0081] Specifically, the dopant ions in the electrical conditioning section can be the same as those in the dopant section, and the electrical conditioning section and the dopant section can be formed by two doping processes.

[0082] Specifically, the active layer is trapezoidal in shape, with the angle between its base and side ranging from 60 to 70 degrees. Similarly, the angle at the ramp points of other membrane layers can also range from 60 to 70 degrees.

[0083] Specifically, such as Figure 4 , Figure 5 As shown, the semiconductor device 2 further includes a light-shielding layer 22, a barrier layer 23, a buffer layer 24, a gate layer 27, a first interlayer insulating layer 28, and a second interlayer insulating layer 29. It is understood that only the gate of the gate layer 27 is shown in the accompanying drawings of this embodiment.

[0084] Specifically, the barrier layer 23 is made of silicon nitride and the buffer layer 24 is made of silicon oxide. The barrier layer and the buffer layer can be formed simultaneously and can be stacked as a single film layer.

[0085] Specifically, the active layer material includes polycrystalline silicon.

[0086] Specifically, the gate layer includes a gate, and the material of the gate layer includes molybdenum.

[0087] Specifically, the material of the first interlayer insulating layer includes silicon nitride, and the material of the second interlayer insulating layer includes silicon oxide. The first and second interlayer insulating layers can be formed simultaneously and can be stacked as a film layer.

[0088] Meanwhile, this application provides a method for fabricating a semiconductor device, which fabricates a semiconductor device as described in any of the above embodiments.

[0089] In some embodiments, the method for fabricating the semiconductor device includes:

[0090] Provide a substrate and a light-shielding layer; the structure of the semiconductor device corresponding to this step is as follows: Figure 6 As shown in (a) in the text;

[0091] A barrier layer, a buffer layer, and an active layer are formed on the substrate and the light-shielding layer, and the active layer is patterned; the structure of the semiconductor device corresponding to this step is as follows. Figure 6 As shown in (b) in the image;

[0092] The active layer undergoes its first doping process to form a doped portion; the corresponding semiconductor device structure is as follows. Figure 6 As shown in (c);

[0093] A first gate insulating layer and a second gate insulating layer are sequentially formed on the active layer, and the second gate insulating layer is patterned; the structure of the semiconductor device corresponding to this step is as follows. Figure 6 As shown in (d);

[0094] Specifically, a mask for forming the active layer can be used to pattern the second gate insulating layer, and a large amount of etching material can be used to etch the second gate insulating layer so that the pattern of the second gate insulating layer is slightly smaller than the pattern of the active layer.

[0095] A gate layer is formed on the second gate insulating layer, and the gate layer is patterned; the structure of the semiconductor device corresponding to this step is as follows. Figure 6 As shown in (e);

[0096] The active layer is doped a second time to form an electrically modulated section; the structure of the semiconductor device corresponding to this step is as follows: Figure 7 As shown in (a) in the text;

[0097] A first interlayer insulating layer and a second interlayer insulating layer are formed on the gate layer; the structure of the semiconductor device corresponding to this step is as follows: Figure 7 As shown in (b) in the image;

[0098] Vias are formed by etching the gate insulating layer, the first interlayer insulating layer, and the second interlayer insulating layer, and source / drain layers are formed on the second interlayer insulating layer; the structure of the semiconductor device corresponding to this step is as follows. Figure 4 As shown.

[0099] In some embodiments, the method for fabricating the semiconductor device includes:

[0100] Provide a substrate and a light-shielding layer; the structure of the semiconductor device corresponding to this step is as follows: Figure 8 As shown in (a) in the text;

[0101] A barrier layer, a buffer layer, an active layer, and a second gate insulating layer are formed on a substrate and a light-shielding layer, and the active layer and the second gate insulating layer are patterned; the structure of the semiconductor device corresponding to this step is as follows. Figure 8 As shown in (b) in the image;

[0102] Specifically, a mask for forming the active layer can be used to simultaneously pattern the active layer and the second gate insulating layer, and a gas with a high etching ratio can be used to etch the second gate insulating layer, so that the pattern of the second gate insulating layer is slightly smaller than the pattern of the active layer.

[0103] The active layer undergoes its first doping process to form a doped portion; the corresponding semiconductor device structure is as follows. Figure 8 As shown in (c);

[0104] A first gate insulating layer is formed on the second gate insulating layer; the structure of the semiconductor device corresponding to this step is as follows: Figure 8 As shown in (d);

[0105] A gate layer is formed on the second gate insulating layer, and the gate layer is patterned; the structure of the semiconductor device corresponding to this step is as follows. Figure 8 As shown in (e);

[0106] The active layer is doped a second time to form an electrically modulated section; the structure of the semiconductor device corresponding to this step is as follows: Figure 9 As shown in (a) in the text;

[0107] A first interlayer insulating layer and a second interlayer insulating layer are formed on the gate layer; the structure of the semiconductor device corresponding to this step is as follows: Figure 9 As shown in (b) in the image;

[0108] Vias are formed by etching the gate insulating layer, the first interlayer insulating layer, and the second interlayer insulating layer, and source / drain layers are formed on the second interlayer insulating layer; the structure of the semiconductor device corresponding to this step is as follows. Figure 5 As shown.

[0109] Specifically, Figure 10 A cross-sectional view of a semiconductor device provided in an embodiment of this application. Figure 11 for Figure 10 The electric field distribution of semiconductor devices is simulated using TCAD (Technology Computer Aided Design, a tool for semiconductor process simulation and device simulation). Figure 10 and Figure 11The horizontal axis represents width in micrometers, and the vertical axis represents thickness in micrometers. Figure 11 The unit for the electric field distribution in V is V / cm, which is volts per centimeter. Figure 11 The simulation results are obtained under the condition of a gate voltage of 10 volts. Figure 10 , Figure 11 As shown, taking a substrate 21, buffer layer 24, first gate insulating layer 261, and second interlayer insulating layer 29 as materials of silicon dioxide, barrier layer 23, second gate insulating layer 262, and first interlayer insulating layer 28 as materials of silicon nitride, active layer as material of polysilicon, and gate layer as material of molybdenum as an example, from... Figure 11 As can be seen, the electric field strength in the middle region of the channel is larger, while the electric field strength in the edge region of the channel is smaller. This allows the middle region of the channel to turn on before the edge region of the channel, eliminating the peak current, reducing the subthreshold swing of the semiconductor device, improving the performance of the semiconductor device, and thus improving the uniformity of the display.

[0110] Specifically, Figure 12 The graphs show the gate voltage versus drain current of different semiconductor devices, such as... Figure 12 As shown, the horizontal axis represents the gate voltage in volts, and the vertical axis represents the drain current in amperes. Figure 12 (a) in the middle is Figure 1 The curves showing the gate voltage versus drain current of the comparative semiconductor devices are shown. Figure 12 (b) in the middle is Figure 10 The figures show the gate voltage versus drain current curves of a semiconductor device. Curve 1 shows the gate voltage versus drain current when the drain voltage is 10 volts, and curve 2 shows the gate voltage versus drain current when the drain voltage is 0.1 volts. Figure 12 As can be seen in (a), the gate and drain voltages of the semiconductor device turn on prematurely at the edge of the subthreshold region, resulting in a peak phenomenon after the semiconductor device turns on; while from Figure 12 As can be seen in (b) of the diagram, the hump phenomenon has disappeared.

[0111] Specifically, the above embodiments have provided a detailed description of the semiconductor device from the design of film structure, materials, etc. It is understood that when there is no conflict between the embodiments, the embodiments can be combined. For example, the pattern of the second gate insulating layer is the same as the pattern of the active layer. The material of the first gate insulating layer includes silicon oxide, and the material of the second gate insulating layer includes one of silicon nitride, hafnium oxide, zirconium oxide, and titanium oxide.

[0112] Meanwhile, this application provides an electronic device, which includes a semiconductor device as described in any of the above embodiments.

[0113] Specifically, the electronic device can be a display panel, which can be a liquid crystal display panel or an organic light-emitting diode display panel.

[0114] In the above embodiments, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions in other embodiments.

[0115] The above provides a detailed description of a semiconductor device and an electronic device provided in the embodiments of this application. Specific examples have been used to illustrate the principles and implementation methods of this application. The description of the above embodiments is only for the purpose of helping to understand the technical solutions and core ideas of this application. Those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. These modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.

Claims

1. A semiconductor device, characterized in that, include: Substrate; An active layer is disposed on one side of the substrate, the active layer including a channel portion and doped portions located on both sides of the channel portion; A gate layer is disposed on one side of the substrate; A gate insulating layer is disposed between the active layer and the gate layer; Wherein, the active layer has a first direction and a second direction that are perpendicular to each other on the plane where the active layer is located. The direction in which the channel portion points to the doped portion is the first direction. In the second direction, the ratio of the dielectric constant to the thickness of the portion of the gate insulating layer located in the middle region of the channel portion is greater than the ratio of the dielectric constant to the thickness of the portion of the gate insulating layer located in the edge region of the channel portion. In the second direction, the thickness of the portion of the gate insulating layer located in the middle region of the channel is greater than the thickness of the portion of the gate insulating layer located in the edge region of the channel, and the dielectric constant of the portion of the gate insulating layer located in the middle region of the channel is greater than the dielectric constant of the portion of the gate insulating layer located in the edge region of the channel.

2. The semiconductor device as claimed in claim 1, characterized in that, The material of the portion of the gate insulating layer located in the middle region of the channel is different from the material of the portion of the gate insulating layer located in the edge region of the channel.

3. The semiconductor device as described in claim 1, characterized in that, The gate insulating layer includes at least a first gate insulating layer and a second gate insulating layer, wherein the dielectric constant of the second gate insulating layer is greater than that of the first gate insulating layer, and in a second direction, the projection of the second gate insulating layer on the substrate does not overlap with the projection of the channel portion in the edge region on the substrate, and the thickness of the portion of the first gate insulating layer located in the middle region is less than the thickness of the portion of the first gate insulating layer located in the edge region.

4. The semiconductor device as described in claim 3, characterized in that, The first gate insulating layer is disposed between the second gate insulating layer and the active layer; or the second gate insulating layer is disposed between the first gate insulating layer and the active layer.

5. The semiconductor device as described in claim 3, characterized in that, The semiconductor device further includes a source-drain layer, which includes a source and a drain. The source and the drain are respectively connected to the doped portions located on both sides of the channel portion. The second gate insulating layer is disposed in the disposed regions of the source and the drain. The source and the drain are respectively connected to the doped portions through vias in the second gate insulating layer.

6. The semiconductor device as claimed in claim 3, characterized in that, The second gate insulating layer and the active layer are formed using the same photomask, and the pattern of the second gate insulating layer is slightly smaller than the pattern of the active layer.

7. The semiconductor device as claimed in claim 1, characterized in that, The gate layer is disposed between the active layer and the substrate; or the gate layer is disposed on the side of the active layer away from the substrate.

8. An electronic device, characterized in that, Includes the semiconductor device as described in any one of claims 1 to 7.

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