Semiconductor devices and electronic devices

Abstract

The application provides a semiconductor device and an electronic device; the semiconductor device is characterized in that: by making the effective length of the part of the middle region corresponding to the channel part of the gate smaller than the effective length of the part of the edge region corresponding to the channel part of the gate in the second direction, the channel length of the middle region corresponding to the channel part of the semiconductor device is smaller than the channel length of the edge region corresponding to the channel part of the semiconductor device; thus, under the short channel effect, the middle region of the semiconductor device is opened prior to the edge region of the semiconductor device, thereby eliminating the hump current, reducing the sub-threshold swing of the semiconductor device, improving the performance of the semiconductor device, and improving the display uniformity.

Description

Technical Field

[0001] This application relates to the field of display technology, and in particular to a semiconductor device and an electronic device. Background Technology

[0002] With the development of display devices, the requirements for thin-film transistors (TFTs) in existing display devices are becoming increasingly stringent. Low-temperature polycrystalline silicon (LTPS) TFTs are widely used due to their advantages of fast switching speed and low power consumption. However, during the use of LTPS, a "hump" characteristic has been found, leading to uneven brightness in display devices at low grayscale levels. This is because, along the edge of the channel width, under gate bias, geometric effects result in a higher electric field at the channel edge. More charge carriers are trapped at the width edge, forming parasitic transistors, thus creating a hump current at the edge. This causes the edge region of the LTPS to turn on earlier than the central region, increasing the subthreshold swing of the LTPS, leading to uneven pixel charging and consequently, uneven display performance.

[0003] Therefore, existing display devices suffer from a technical problem where the edge regions of thin-film transistors turn on earlier than the central regions, resulting in uneven display. Summary of the Invention

[0004] This application provides a semiconductor device and an electronic device to solve the technical problem of uneven display caused by the edge region of the thin-film transistor turning on earlier than the middle region in existing display devices.

[0005] This application provides a semiconductor device, which includes:

[0006] Substrate;

[0007] An active layer is disposed on one side of the substrate, the active layer including a channel portion and doped portions located on both sides of the channel portion;

[0008] A gate is disposed on one side of the substrate;

[0009] The active layer has a first direction and a second direction that are perpendicular to each other on the plane. The direction in which the channel portion points to the doped portion is the first direction. In the second direction, the effective length of the portion of the gate corresponding to the middle region of the channel portion is less than the effective length of the portion of the gate corresponding to the edge region of the channel portion.

[0010] In some embodiments, in the edge region of the channel portion, in the thickness direction of the semiconductor device, the gate includes a first portion and a second portion, wherein the thickness of the first portion is less than the thickness of the second portion.

[0011] In some embodiments, the semiconductor device further includes a buffer layer and a gate insulating layer, the buffer layer being disposed between the substrate and the active layer, the gate being disposed on the side of the active layer away from the buffer layer, and the gate insulating layer being disposed between the active layer and the gate;

[0012] In the edge region of the channel portion, the buffer layer includes a first protrusion, the channel portion includes a second protrusion, the second protrusion is disposed corresponding to the first protrusion, the gate insulating layer includes a third protrusion, the third protrusion is disposed corresponding to the second protrusion, and the first portion is disposed corresponding to the third protrusion.

[0013] In some embodiments, in the middle region of the channel portion, the side of the channel portion near the gate is a plane, and the side of the gate near the channel portion is a plane.

[0014] In some embodiments, the thickness of the portion of the gate corresponding to the middle region of the channel is equal to the thickness of the first portion, and the width of the portion of the gate corresponding to the middle region of the channel in the first direction is equal to the sum of the widths of the first portion and the second portion in the first direction.

[0015] In some embodiments, in the second direction, the first protrusion is disposed outside the disposed area of ​​the channel portion.

[0016] In some embodiments, the thickness of the portion of the gate corresponding to the middle region of the channel is equal to the thickness of the portion of the gate corresponding to the edge region of the channel, and the width of the portion of the gate corresponding to the middle region of the channel in the first direction is less than the width of the portion of the gate corresponding to the edge region of the channel in the first direction.

[0017] In some embodiments, in the second direction, the width of the gate decreases along the edge region of the channel portion to the middle region of the channel portion.

[0018] In some embodiments, in the second direction, the width of the portion of the gate corresponding to the region outside the channel portion in the first direction is greater than or equal to the width of the portion of the gate corresponding to the edge region of the channel portion in the first direction.

[0019] Meanwhile, this application provides an electronic device, which includes a semiconductor device as described in any of the above embodiments.

[0020] Beneficial effects: This application provides a semiconductor device and an electronic device; the semiconductor device, by making the effective length of the middle region of the gate corresponding to the channel portion smaller than the effective length of the edge region of the gate corresponding to the channel portion in a second direction, and making the channel length of the middle region of the semiconductor device corresponding to the channel portion smaller than the channel length of the edge region of the semiconductor device corresponding to the channel portion, under the short channel effect, the middle region of the semiconductor device will turn on preferentially over the edge region of the semiconductor device, thereby eliminating the peak current, reducing the subthreshold swing of the semiconductor device, improving the performance of the semiconductor device, and thus improving the display uniformity. Attached Figure Description

[0021] The technical solution and other beneficial effects of this application will become apparent from the following detailed description of specific embodiments in conjunction with the accompanying drawings.

[0022] Figure 1 Perspective view for comparison of semiconductor devices.

[0023] Figure 2 for Figure 1 A cross-sectional view of a semiconductor device.

[0024] Figure 3 This is a first perspective view of a semiconductor device provided in an embodiment of this application.

[0025] Figure 4 for Figure 3 A cross-sectional view of a semiconductor device.

[0026] Figure 5 This is a second perspective view of a semiconductor device provided in an embodiment of this application.

[0027] Figure 6 for Figure 5 A cross-sectional view of a semiconductor device.

[0028] Figure 7 for Figure 3 The diagram shows the structure of a semiconductor device corresponding to some steps in the fabrication method of the semiconductor device.

[0029] Figure 8 A plan view and simulation diagram of a semiconductor device provided for embodiments of this application.

[0030] Figure 9 A plan view and simulation diagram of another semiconductor device provided in the embodiments of this application.

[0031] Figure 10 To compare the curves of gate voltage versus drain current in semiconductor devices.

[0032] Figure 11A cross-sectional view of a semiconductor device provided in the embodiments of this application and a graph showing its gate voltage versus drain current. Detailed Implementation

[0033] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.

[0034] In the description of this application, it should be understood that the terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," and "counterclockwise," etc., indicating orientation or positional relationships based on the orientation or positional relationships shown in the accompanying drawings, are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this application. Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, features defined with "first" and "second" may explicitly or implicitly include one or more of the stated features. In the description of this application, "a plurality of" means two or more, unless otherwise explicitly specified.

[0035] In the description of this application, it should be noted that, unless otherwise expressly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection, an electrical connection, or a connection that allows communication between them; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication between two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this application according to the specific circumstances.

[0036] In this application, unless otherwise expressly specified and limited, "above" or "below" the second feature can include direct contact between the first and second features, or contact between the first and second features through another feature between them. Furthermore, "above," "over," and "on top" of the second feature includes the first feature being directly above or diagonally above the second feature, or simply indicates that the first feature is at a higher horizontal level than the second feature. "Below," "below," and "under" the second feature includes the first feature being directly below or diagonally below the second feature, or simply indicates that the first feature is at a lower horizontal level than the second feature.

[0037] The following disclosure provides many different embodiments or examples for implementing different structures of this application. To simplify the disclosure, specific examples of components and arrangements are described below. Of course, these are merely examples and are not intended to limit the scope of this application. Furthermore, reference numerals and / or letters may be repeated in different examples; such repetition is for simplification and clarity and does not in itself indicate a relationship between the various embodiments and / or arrangements discussed. In addition, various specific examples of processes and materials are provided in this application, but those skilled in the art will recognize the application of other processes and / or the use of other materials.

[0038] Figure 1 To compare the perspective views of semiconductor devices, Figure 2 (a) is Figure 1 A cross-sectional view of the semiconductor device in the diagram. Figure 2 (b) in the middle is Figure 1 BB cross-sectional view of semiconductor devices in the image.

[0039] As an introduction to the embodiments of this application, a comparative semiconductor device is provided to illustrate the principle behind the technical problem to be solved by the embodiments of this application. Figure 1 , Figure 2 As shown, the comparative semiconductor device includes a substrate 11, a light-shielding film 12, a first insulating film 13, an active film 14, a second insulating film 15, a gate film 16, a third insulating film 17, and a source / drain film 18. The active film 14 includes a channel region 143, a lightly doped region 142, and a heavily doped region 141. During the use of the comparative semiconductor device, it was found that under gate bias, due to geometric effects, the electric field at the edge of the channel region 143 is higher. More charge carriers are trapped at the wide edge, forming parasitic transistors, resulting in a peak current at the edge. This causes the edge region of the low-temperature polycrystalline silicon thin-film transistor to turn on earlier than the middle region, increasing the subthreshold swing of the low-temperature polycrystalline silicon thin-film transistor, leading to uneven pixel charging and consequently, uneven display. Therefore, existing display devices suffer from the technical problem of uneven display caused by the edge region of the thin-film transistor turning on earlier than the middle region.

[0040] This application provides a semiconductor device and an electronic device to address the aforementioned technical problems.

[0041] Figure 3 This is a first perspective view of a semiconductor device provided in an embodiment of this application. Figure 4 for Figure 3 A cross-sectional view of a semiconductor device in a semiconductor device; Figure 4 (a) in the middle is Figure 3 A cross-sectional view of the semiconductor device in the diagram. Figure 4 (b) in the middle is Figure 3 BB cross-sectional view of semiconductor devices in the image. Figure 4 (c) in the middle is Figure 3 CC cross-section of a semiconductor device. Figure 5 This is a second perspective view of a semiconductor device provided in an embodiment of this application. Figure 6 for Figure 5 A cross-sectional view of a semiconductor device in a semiconductor device; Figure 6 (a) in the middle is Figure 5 A cross-sectional view of the semiconductor device in the diagram. Figure 6 (b) in the middle is Figure 5 BB cross-sectional view of semiconductor devices in the image.

[0042] Figure 7 for Figure 3 The diagram shows the structure of a semiconductor device corresponding to some steps in the fabrication method of the semiconductor device. Figure 8 A plan view and simulation diagram of a semiconductor device provided for embodiments of this application. Figure 9 A plan view and simulation diagram of another semiconductor device provided in the embodiments of this application. Figure 10 To compare the curves of gate voltage versus drain current in semiconductor devices. Figure 11 A cross-sectional view of a semiconductor device provided in the embodiments of this application and a graph showing its gate voltage versus drain current.

[0043] like Figures 3 to 6 As shown, this application provides a semiconductor device 2, which includes a substrate 21, an active layer 25 and a gate 27. The active layer 25 is disposed on one side of the substrate 21 and includes a channel portion 251 and doped portions 253 located on both sides of the channel portion 251. The gate 27 is disposed on one side of the substrate 21.

[0044] The active layer 25 has a first direction X and a second direction Y that are perpendicular to each other on the plane. The direction of the channel portion 251 pointing to the doped portion 253 is the first direction X. In the second direction Y, the effective length of the gate 27 corresponding to the middle region 251a of the channel portion 251 is less than the effective length of the gate 27 corresponding to the edge region 251b of the channel portion 251.

[0045] This application provides a semiconductor device in which, in a second direction, the effective length of the middle region of the gate corresponding to the channel is less than the effective length of the edge region of the gate corresponding to the channel, and the channel length of the middle region of the channel is less than the channel length of the edge region of the channel. Under the short-channel effect, the middle region of the semiconductor device will turn on preferentially over the edge region of the semiconductor device, thereby eliminating the peak current, reducing the subthreshold swing of the semiconductor device, improving the performance of the semiconductor device, and thus improving display uniformity.

[0046] Specifically, the plane where the active layer is located can be understood as the plane of the active layer from a top-down angle.

[0047] Specifically, it is understood that the middle region and edge region defined in the embodiments of this application are for the purpose of describing the relative positions of the middle region and the edge region. The edge region refers to the region that is opened earlier than other regions when the technical solution described in the embodiments of this application is not adopted. The size of the middle region and the edge region is determined according to the actual situation. For example, in the comparison semiconductor device, if the left side region with a width of 1 micrometer and the right side region with a width of 1 micrometer of the channel are opened earlier than the middle region, then the left side region with a width of 1 micrometer and the right side region with a width of 1 micrometer of the channel can be defined as the edge region.

[0048] Specifically, it is understood that in the embodiments of this application... Figure 1 In this diagram, to illustrate the specific design of the active layer, the structure of the active layer is shown while the structure of the gate is obscured. Figure 3 and Figure 5 In this diagram, to illustrate the specific design of the gate, the structure of the gate is shown while the structure of the active layer is obscured. However, the relative positions of the active layer and the gate can actually be determined according to the design of different thin-film transistors. For example, in thin-film transistors where the semiconductor device includes a top-gate structure, such as... Figure 2 , Figure 4 , Figure 6As shown, in the actual top view, the gate will cover the active layer. When the semiconductor device includes a thin-film transistor with a bottom gate structure, the active layer will cover the gate in the actual top view. Therefore, the perspective view in the embodiments of this application does not limit the relative position of the gate and the active layer. Their relative position can be determined according to different designs. In the embodiments of this application, a thin-film transistor with a top gate structure is used as an example for illustration.

[0049] Specifically, it is understood that the embodiments of this application use a thin-film transistor with a top-gate structure as an example for illustration. For thin-film transistors with a bottom-gate structure, the design can be carried out by referring to the design of a thin-film transistor with a top-gate structure, and will not be described in detail here.

[0050] Specifically, the semiconductor device can be an array substrate, and the semiconductor device can include a thin-film transistor.

[0051] Specifically, the effective length of the gate refers to the length of the portion of the thin-film transistor in the semiconductor device that controls it. The effective length of the gate can be the channel length of the semiconductor device. Correspondingly, the effective length of the portion of the gate corresponding to the middle region of the channel is less than the effective length of the portion of the gate corresponding to the edge region of the channel. This makes the channel length of the middle region of the semiconductor device less than the channel length of the edge region of the semiconductor device. Thus, through the short-channel effect, the middle region of the semiconductor device turns on before the edge region, eliminating peak current, reducing the subthreshold swing of the semiconductor device, improving the performance of the semiconductor device, and thereby improving display uniformity.

[0052] In some embodiments, such as Figure 3 , Figure 4 As shown, within the edge region 251b of the channel portion 251, along the thickness direction Z of the semiconductor device 2, the gate 27 includes a first portion 271 and a second portion 272, where the thickness H1 of the first portion 271 is less than the thickness H2 of the second portion 272. By including a first portion and a second portion within the gate located in the edge region of the channel portion, and making the thickness of the first portion less than the thickness of the second portion, the effective length of the gate can be increased by increasing the gate thickness, thereby increasing the channel length of the edge region of the semiconductor device. This allows the middle region of the semiconductor device to turn on before the edge region, thereby eliminating peak current, reducing the subthreshold swing of the semiconductor device, improving the performance of the semiconductor device, and thus improving display uniformity.

[0053] In some embodiments, such as Figure 3 , Figure 4As shown, the semiconductor device 2 further includes a buffer layer 24 and a gate insulating layer 26. The buffer layer 24 is disposed between the substrate 21 and the active layer 25. The gate 27 is disposed on the side of the active layer 25 away from the buffer layer 24. The gate insulating layer 26 is disposed between the active layer 25 and the gate 27. In the edge region 251b of the channel portion 251, the buffer layer 24 includes a first protrusion 241, the channel portion 251 includes a second protrusion 254, the second protrusion 254 is correspondingly disposed to the first protrusion 241, the gate insulating layer 26 includes a third protrusion 261, the third protrusion 261 is correspondingly disposed to the second protrusion 254, and the first portion 271 is correspondingly disposed to the third protrusion 261. By providing a first protrusion in the buffer layer, and having the first protrusion corresponding to the channel portion, a second protrusion is formed in the channel portion when the active layer is formed on the buffer layer. Correspondingly, a third protrusion is formed in the gate insulating layer, resulting in different thicknesses for the first and second portions of the gate. This allows the channel length of the edge region of the semiconductor device to be increased by making the edge of the channel portion and the edge of the gate corresponding to the channel portion protrude, thereby suppressing the edge effect of the semiconductor device, eliminating the peak current, reducing the subthreshold swing of the semiconductor device, and improving the performance of the semiconductor device. This improves display uniformity without reducing the aperture ratio of the semiconductor device.

[0054] Specifically, such as Figure 4 As shown in (c), by providing a first protrusion in the buffer layer, the channel portion, the gate insulating layer, and the gate will correspondingly form a second, third, and fourth protrusion, which increases the channel length in the edge region of the semiconductor device. This allows the middle region of the semiconductor device to turn on preferentially over the edge region under the short-channel effect, eliminating peak current, reducing the subthreshold swing of the semiconductor device, improving the performance of the semiconductor device, and thus improving display uniformity.

[0055] Specifically, such as Figure 4 As shown in (c), the effective length of the portion of the edge region of the gate corresponding to the channel is twice the difference between the thickness of the second portion and the thickness of the first portion plus the sum of the widths of the first portion and the second portion in the first direction, i.e., 2(H2-H1)+L2, thereby increasing the effective length of the portion of the edge region of the gate corresponding to the channel.

[0056] Specifically, the above embodiment is illustrated by taking the side of the active layer away from the substrate as an example. It can be understood that when the gate is disposed on the side of the active layer close to the substrate, the effective length of the edge region of the gate corresponding to the channel portion can be increased by setting a protrusion or a groove.

[0057] In some embodiments, such as Figure 3, Figure 4 As shown in (a), within the intermediate region 251a of the channel portion 251, the side of the channel portion 251 near the gate 27 is planar, and the side of the gate 27 near the channel portion 251 is planar. By making the side of the channel portion near the gate planar and the side of the gate near the channel portion planar within the intermediate region of the channel portion, the effective length of the gate is relatively small in the intermediate region of the channel portion. The effective length of the portion of the gate corresponding to the intermediate region of the channel portion is smaller than the effective length of the portion of the gate corresponding to the edge region of the channel portion. Therefore, under the short-channel effect, the intermediate region of the semiconductor device will turn on preferentially over the edge region of the semiconductor device, eliminating peak current, reducing the subthreshold swing of the semiconductor device, improving the performance of the semiconductor device, and thus improving display uniformity.

[0058] Specifically, the above embodiment is illustrated by taking the middle region of the channel portion, where the side of the channel portion near the gate is a plane and the side of the gate portion near the channel portion is a plane. This is based on the fact that the design of the channel portion and the gate portion meets the requirements and has been verified. This design can improve the performance of the semiconductor device without requiring additional design and avoiding additional process steps. However, the embodiments of this application are not limited to this. Without considering the addition of process steps or changes in performance (which may improve or worsen performance), the design of the middle region of the channel portion can be changed. For example, the design of the middle region of the channel portion can also adopt the same approach as... Figure 4 The design shown in (c) is similar to or the same as that shown in the example. Figure 4 The design shown in (c) is the same as the design shown in the figure, but the effective length of the portion of the gate corresponding to the middle region of the channel is less than the effective length of the portion of the gate corresponding to the edge region of the channel.

[0059] In some embodiments, such as Figure 4As shown, the thickness H3 of the portion of the gate 27 corresponding to the middle region 251a of the channel portion 251 is equal to the thickness H1 of the first portion 271. The width L1 of the portion of the gate 27 corresponding to the middle region 251a of the channel portion 251 in the first direction X is equal to the sum of the widths L2 of the first portion 271 and the second portion 272 in the first direction. By making the thickness of the portion of the gate corresponding to the middle region of the channel portion equal to the thickness of the first portion, and the width of the portion of the gate corresponding to the middle region of the channel portion in the first direction equal to the sum of the widths of the first portion and the second portion in the first direction, the channel portion and the gate can form a protrusion through the first protrusion of the buffer layer. At the same time, the effective length of the portion of the gate corresponding to the middle region of the channel portion can be less than the effective length of the portion of the gate corresponding to the edge region of the channel portion. Thus, under the short channel effect, the middle region of the semiconductor device will turn on preferentially over the edge region of the semiconductor device, eliminating the peak current, reducing the subthreshold swing of the semiconductor device, improving the performance of the semiconductor device, and thus improving the display uniformity.

[0060] Specifically, it can be seen that the effective length of the portion of the gate corresponding to the middle region of the channel is the width L1 of the portion of the gate 27 corresponding to the middle region 251a of the channel 251 in the first direction X. The effective length of the portion of the gate corresponding to the edge region of the channel is twice the difference between the thickness of the second part and the thickness of the first part plus the sum of the widths of the first part and the second part in the first direction, i.e., 2(H2-H1)+L2. Since L1 equals L2, the effective length of the portion of the gate corresponding to the middle region of the channel can be less than the effective length of the portion of the gate corresponding to the edge region of the channel.

[0061] Specifically, the above embodiments are illustrated by taking the example that the thickness of the portion of the middle region of the gate corresponding to the channel is equal to the thickness of the first portion, and the width of the portion of the middle region of the gate corresponding to the channel in the first direction is equal to the sum of the widths of the first portion and the second portion in the first direction. This is based on the fact that the design of the channel and the gate meets the requirements and has been verified. Using this design can make the semiconductor device perform better without additional design and avoid adding process steps. However, the embodiments of this application are not limited to this. Without considering adding process or changes in performance (which may improve or worsen performance), the design of the middle region of the gate can be changed. For example, the thickness of the portion of the middle region of the gate corresponding to the channel can be less than or greater than the thickness of the first portion.

[0062] In some embodiments, such as Figure 3 , Figure 4As shown in (b), in the second direction Y, the first protrusion 241 is disposed outside the disposed area of ​​the channel portion 251. By disposing the first protrusion outside the disposed area of ​​the channel portion, it is ensured that the edges of the channel portion and the gate can form protrusions when the channel portion and the gate are formed, thereby increasing the channel length of the edge region of the semiconductor device. Furthermore, the presence of the first protrusion in the region outside the channel portion can further prevent the formation of parasitic transistors in the region outside the channel, thereby improving the performance of the semiconductor device.

[0063] Specifically, when setting the first protrusion, the first protrusion can be positioned in the second direction at the edge region of the channel portion and outside the channel portion, so that the first protrusion can ensure that the edge region of the subsequently formed channel portion can protrude and the edge region of the gate corresponding to the channel portion can protrude, thereby increasing the channel length of the edge region of the semiconductor device, which can eliminate the peak current, reduce the subthreshold swing of the semiconductor device, improve the performance of the semiconductor device, and thus improve the display uniformity.

[0064] In some embodiments, such as Figure 5 , Figure 6 As shown, the thickness of the portion of the gate 27 corresponding to the middle region 251a of the channel portion 251 is equal to the thickness of the portion of the gate 27 corresponding to the edge region 251b of the channel portion 251. The width L3 of the portion of the gate 27 corresponding to the middle region 251a of the channel portion 251 in the first direction X is smaller than the width L4 of the portion of the gate 27 corresponding to the edge region 251b of the channel portion 251 in the first direction X. By making the width of the portion of the gate corresponding to the middle region of the channel portion in the corresponding direction smaller than the width of the portion of the gate corresponding to the edge region of the channel portion in the first direction, the width of the portion of the middle region of the channel portion in the first direction is smaller than the width of the portion of the edge region of the channel portion in the first direction. This allows the channel length of the edge region of the semiconductor device to be greater than the channel length of the middle region of the semiconductor device. Under the short-channel effect, the middle region of the semiconductor device will turn on preferentially over the edge region of the semiconductor device, thereby eliminating the peak current, reducing the subthreshold swing of the semiconductor device, improving the performance of the semiconductor device, and thus improving display uniformity.

[0065] Specifically, this application embodiment takes the example of the gate width decreasing in the first direction from the edge region of the channel to the middle region of the channel. The widths of the gate corresponding to the middle region of the channel are not equal, and the widths of the gate corresponding to the edge region of the channel are not equal. The width of the gate corresponding to the middle region of the channel in the first direction being less than the width of the gate corresponding to the edge region of the channel in the first direction means that the maximum width of the gate corresponding to the middle region of the channel in the first direction is less than the minimum width of the gate corresponding to the edge region of the channel in the first direction.

[0066] Specifically, by making the thickness of the middle region of the gate corresponding to the channel equal to the thickness of the edge region of the gate corresponding to the channel, without changing the design of other film layers, the width in the first direction of the middle region of the gate corresponding to the channel is less than the width in the first direction of the edge region of the gate corresponding to the channel, thus making the channel length of the edge region of the semiconductor device greater than the channel length of the middle region of the semiconductor device.

[0067] In some embodiments, such as Figure 5 As shown, in the second direction Y, from the edge region 251b of the channel portion 251 to the middle region 251a of the channel portion 251, the width of the gate 27 decreases in the first direction X. By decreasing the width of the gate in the first direction along the direction from the edge region to the middle region of the channel portion, the channel length of the middle region of the semiconductor device decreases sequentially compared to the channel length of the edge region of the semiconductor device. Therefore, under the short-channel effect, the middle region of the semiconductor device can turn on before the edge region of the semiconductor device, thereby eliminating peak current, reducing the subthreshold swing of the semiconductor device, improving the performance of the semiconductor device, and thus improving display uniformity.

[0068] Specifically, the above embodiment is illustrated by taking the example of the width of the gate decreasing in the first direction from the edge region of the channel to the middle region of the channel. However, the embodiments of this application are not limited to this. The width of each part of the middle region of the channel corresponding to the gate can be equal, the width of each part of the edge region of the channel corresponding to the gate can be equal, and the width of the part of the middle region of the channel corresponding to the gate in the first direction is smaller than the width of the part of the edge region of the channel corresponding to the gate in the first direction.

[0069] In some embodiments, such as Figure 5 , Figure 6As shown, in the second direction Y, the width L5 of the portion of the gate 27 corresponding to the area outside the channel portion 251 in the first direction X is greater than or equal to the width L4 of the portion of the gate 27 corresponding to the edge region 251b of the channel portion 251 in the first direction X. By making the width of the portion of the gate corresponding to the area outside the channel portion in the first direction greater than or equal to the width of the portion of the gate corresponding to the edge region of the channel portion in the first direction, it is ensured that when setting the width of each portion of the gate, the width of the portion of the gate corresponding to the edge region of the channel portion in the first direction is greater than the width of the portion of the gate corresponding to the middle region of the channel portion in the first direction.

[0070] In some embodiments, such as Figure 4 , Figure 6 As shown, the active layer 25 further includes an electrical adjustment section 252, which is disposed between the channel portion 251 and the doped portion 253. The electrical adjustment section 252 connects the channel portion 251 and the doped portion 253. The ion doping concentration of the electrical adjustment section 252 is lower than that of the doped portion 253, and the ion doping concentration of the electrical adjustment section 252 is greater than that of the channel portion 251. By including an electrical adjustment section in the active layer, the leakage current of the semiconductor device can be reduced, and the performance of the semiconductor device can be improved.

[0071] Specifically, compared to the problem that an active layer consisting only of a channel portion and a doped portion may lead to a large leakage current in semiconductor devices, the embodiments of this application reduce the leakage current of semiconductor devices by providing an electrical adjustment portion, such that the ion doping concentration of the electrical adjustment portion is between the ion doping concentration of the channel portion and the ion doping concentration of the doped portion. However, the embodiments of this application are not limited to this; the active layer may also consist only of a channel portion and a doped portion.

[0072] Specifically, the dopant ions in the electrical conditioning section can be the same as those in the dopant section, and the electrical conditioning section and the dopant section can be formed by two doping processes.

[0073] Specifically, the active layer is trapezoidal in shape, with the angle between its base and side ranging from 60 to 70 degrees. Similarly, the angle at the ramp points of other membrane layers can also range from 60 to 70 degrees.

[0074] Specifically, such as Figure 4 , Figure 6 As shown, the semiconductor device 2 also includes a light-shielding layer 22, a blocking layer 23, a buffer layer 24, a first interlayer insulating layer 28, a second interlayer insulating layer 29, and a source-drain layer 31, wherein the source-drain layer 31 includes a source 311 and a drain 312.

[0075] Specifically, it is understood that only the gate 27 is shown in the accompanying drawings of the embodiments of this application. The gate 27 may also be disposed on the same layer as other traces to form a gate layer.

[0076] Specifically, the barrier layer 23 is made of silicon nitride and the buffer layer 24 is made of silicon oxide. The barrier layer and the buffer layer can be formed simultaneously and can be stacked as a single film layer.

[0077] Specifically, the active layer material includes polycrystalline silicon.

[0078] Specifically, the gate material includes molybdenum.

[0079] Specifically, the material of the first interlayer insulating layer includes silicon nitride, and the material of the second interlayer insulating layer includes silicon oxide. The first and second interlayer insulating layers can be formed simultaneously and can be stacked as a film layer.

[0080] Meanwhile, this application provides a method for fabricating a semiconductor device, which fabricates a semiconductor device as described in any of the above embodiments.

[0081] In some embodiments, the method for fabricating a semiconductor device includes:

[0082] Provide a substrate and a light-shielding layer; the structure of the semiconductor device corresponding to this step is as follows: Figure 7 As shown in (a) in the middle;

[0083] A blocking layer and a buffer layer are sequentially formed on the light-shielding layer, and the buffer layer is patterned; the structure of the semiconductor device corresponding to this step is as follows. Figure 7 As shown in (b);

[0084] An active layer is formed on the buffer layer, and the active layer is patterned; the structure of the semiconductor device corresponding to this step is as follows. Figure 7 As shown in (c);

[0085] A gate insulating layer is formed on the active layer; the structure of the semiconductor device corresponding to this step is as follows: Figure 7 As shown in (d);

[0086] A gate is formed on the gate insulating layer; the structure of the semiconductor device corresponding to this step is as follows: Figure 7 As shown in (e);

[0087] A first interlayer insulating layer, a second interlayer insulating layer, and source / drain layers are formed on the gate; the corresponding semiconductor device is as follows: Figure 4 As shown.

[0088] Specifically, Figure 8 This application provides a plan view and simulation diagram of a semiconductor device. Figure 8(a) is a plan view of a semiconductor device provided in an embodiment of this application. Figure 8 (b) in the middle is Figure 8 The electric field distribution of the semiconductor device in (a) is a simulation diagram from TCAD (Technology Computer Aided Design, a semiconductor process simulation and device simulation tool). Figure 8 The horizontal axis represents the width in micrometers, and the vertical axis represents the length in micrometers. Figure 8 The unit of the electric field distribution in (b) is V / cm, i.e., volts per centimeter. For example... Figure 8 As shown, Figure 8 Image (a) shows the connection hole 32 connecting the source and drain to the doped portion and the photomask 33 of the doped portion. Figure 8 (b) shows the simulation results obtained under the condition of a gate voltage of 10 volts. Figure 8 As can be seen, the electric field strength in the middle region of the semiconductor device is larger, while the electric field strength in the edge regions on both sides of the semiconductor device is smaller. This can eliminate the peak current, reduce the subthreshold swing of the semiconductor device, improve the performance of the semiconductor device, and thus improve the uniformity of the display.

[0089] Specifically, Figure 9 A plan view and simulation diagram of another semiconductor device provided in the embodiments of this application. Figure 9 (a) is a plan view of a semiconductor device provided in an embodiment of this application. Figure 9 (b) in the middle is Figure 8 The electric field distribution of the semiconductor device in (a) is a simulation diagram from TCAD (Technology Computer Aided Design, a semiconductor process simulation and device simulation tool). Figure 9 In (a), the horizontal axis represents the width in micrometers, and the vertical axis represents the length in micrometers. Figure 9 In (b), the horizontal axis represents the width in micrometers, and the vertical axis represents the thickness in micrometers. Figure 9 The unit of the electric field distribution in (b) is V / cm, which is volts per centimeter. Figure 9 (a) shows the connection hole 32 connecting the source and drain to the doped portion and the photomask 33 of the doped portion. Figure 9 (b) shows the simulation results obtained under the condition of a gate voltage of 10 volts. Figure 9 As can be seen, the electric field strength in the middle region of the semiconductor device is larger, while the electric field strength in the edge regions on both sides of the semiconductor device is smaller. This can eliminate the peak current, reduce the subthreshold swing of the semiconductor device, improve the performance of the semiconductor device, and thus improve the uniformity of the display.

[0090] Specifically, Figure 10 To compare the gate voltage versus drain current curves of semiconductor devices. Figure 11 A cross-sectional view of the semiconductor device provided in the embodiments of this application and a graph showing its gate voltage versus drain current. Figure 11 (a) is a cross-sectional view of the semiconductor device provided in an embodiment of this application, with the horizontal axis representing the width in micrometers and the vertical axis representing the thickness in micrometers. Figure 11 (b) in the middle is Figure 11 The graph in (a) shows the gate voltage versus drain current of the semiconductor device. Figure 10 and Figure 11 The horizontal axis represents the gate voltage in volts, and the vertical axis represents the drain current in amperes. Curve 1 shows the gate voltage versus drain current when the drain voltage is 10 volts, and curve 2 shows the gate voltage versus drain current when the drain voltage is 0.1 volts. Figure 10 As can be seen, the gate and drain voltages of the semiconductor device turn on prematurely at the edge of the subthreshold region, resulting in a peak phenomenon after the semiconductor device turns on; while from Figure 11 As can be seen in (b) of the diagram, the hump phenomenon has disappeared.

[0091] Specifically, the above embodiments have provided a detailed description of the semiconductor device in terms of film structure, width, thickness, and other designs. It is understood that when there is no conflict between the embodiments, the embodiments can be combined. For example, in the second direction, from the edge region of the channel portion to the middle region of the channel portion, the width of the gate in the first direction decreases; and in the second direction, the width of the portion of the gate corresponding to the region outside the channel portion in the first direction is greater than or equal to the width of the portion of the gate corresponding to the edge region of the channel portion in the first direction.

[0092] Meanwhile, this application provides an electronic device, which includes a semiconductor device as described in any of the above embodiments.

[0093] Specifically, the electronic device can be a display panel, which can be a liquid crystal display panel or an organic light-emitting diode display panel.

[0094] In the above embodiments, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions in other embodiments.

[0095] The above provides a detailed description of a semiconductor device and an electronic device provided in the embodiments of this application. Specific examples have been used to illustrate the principles and implementation methods of this application. The description of the above embodiments is only for the purpose of helping to understand the technical solutions and core ideas of this application. Those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. These modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.

Claims

1. A semiconductor device, characterized in that, include: Substrate; An active layer is disposed on one side of the substrate. The active layer includes a channel portion and doped portions located on both sides of the channel portion. The active layer has a first direction and a second direction that are perpendicular to each other on the plane where the active layer is located. The direction from the channel portion to the doped portion is the first direction. A gate is disposed on one side of the substrate; the thickness of the portion of the gate corresponding to the middle region of the channel is equal to the thickness of the portion of the gate corresponding to the edge region of the channel; the width of the portion of the gate corresponding to the middle region of the channel in the first direction is less than the width of the portion of the gate corresponding to the edge region of the channel in the first direction; in the second direction, the width of the gate decreases from the edge region of the channel to the middle region of the channel. In the second direction, the effective length of the portion of the gate corresponding to the middle region of the channel is less than the effective length of the portion of the gate corresponding to the edge region of the channel. Under the short-channel effect, the middle region turns on before the edge region.

2. The semiconductor device as claimed in claim 1, characterized in that, The active layer further includes an electrical conditioning section disposed between the channel section and the doped section, the electrical conditioning section connecting the channel section and the doped section, the ion doping concentration of the electrical conditioning section being less than the ion doping concentration of the doped section, and the ion doping concentration of the electrical conditioning section being greater than the ion doping concentration of the channel section.

3. The semiconductor device as described in claim 2, characterized in that, The semiconductor device further includes a buffer layer and a gate insulating layer. The buffer layer is disposed between the substrate and the active layer. The gate is disposed on the side of the active layer away from the buffer layer. The gate insulating layer is disposed between the active layer and the gate.

4. The semiconductor device as described in claim 3, characterized in that, In the middle region of the channel portion, the side of the channel portion near the gate is a plane, and the side of the gate near the channel portion is a plane.

5. The semiconductor device as claimed in claim 4, characterized in that, The dopant ions in the electrical adjustment section are the same as those in the doped section, and the electrical adjustment section and the doped section are formed by two doping processes.

6. The semiconductor device as claimed in claim 3, characterized in that, The semiconductor device further includes a light-shielding layer, a blocking layer, a first interlayer insulating layer, a second interlayer insulating layer, and a source-drain layer, wherein the source-drain layer includes a source and a drain.

7. The semiconductor device as claimed in claim 1, characterized in that, In the second direction, the width of the portion of the gate corresponding to the area outside the channel portion in the first direction is greater than or equal to the width of the portion of the gate corresponding to the edge region of the channel portion in the first direction.

8. An electronic device, characterized in that, Includes the semiconductor device as described in any one of claims 1 to 7.

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