Light emitting diode epitaxial wafer and preparation method thereof, LED

Abstract

The present invention relates to the field of optoelectronic technology, and discloses a light-emitting diode epitaxial wafer and a preparation method thereof, and an LED. The light-emitting diode epitaxial wafer comprises a substrate, on which a buffer layer, an undoped GaN layer, an N-type GaN layer, a stress release layer, a multi-quantum well light-emitting layer, an electron blocking layer, and a P-type GaN layer are sequentially arranged; the stress release layer comprises a Si-doped porous GaN layer, a porous InGaN / GaN superlattice layer with a low In component, a low Si-doped GaN merged layer, a porous InGaN / GaN superlattice layer with a high In component, and a Si-doped GaN merged layer, which are sequentially stacked. The light-emitting diode epitaxial wafer provided by the present invention can reduce the stress and defect density of the multi-quantum well light-emitting layer material, significantly improve the quality of the multi-quantum well light-emitting layer, and enhance the radiation recombination efficiency in the multi-quantum well light-emitting layer, thereby improving the luminous efficiency of the LED device.

Description

Technical Field

[0001] The invention relates to the field of optoelectronic technology, and in particular to a light emitting diode epitaxial wafer and a preparation method thereof, and an LED. Background Art

[0002] At present, GaN-based LED devices with InGaN quantum wells as active layers are widely used in various fields. However, due to the lack of suitable homogeneous epitaxial substrates, GaN is usually grown on sapphire, silicon carbide or silicon substrates with large lattice mismatches. The lattice mismatch between GaN and the substrate will undoubtedly form a large number of dislocation defects, thereby affecting its epitaxial quality. In addition, long-wavelength InGaN-based LEDs also have a large lattice mismatch between InGaN and GaN in the multi-quantum well light-emitting layer, and the InGaN quantum well will be subject to compressive stress from GaN. Both dislocation defects and compressive stress will have an adverse effect on the performance of LED devices. Therefore, in order to improve the luminous efficiency and performance of long-wavelength InGaN-based LEDs, it is very necessary to reduce the stress on the epitaxial layer material and reduce the defect density of the epitaxial layer material. Summary of the invention

[0003] The technical problem to be solved by the present invention is to provide a light-emitting diode epitaxial wafer, which can reduce the stress and defect density of the multi-quantum well light-emitting layer material, significantly improve the quality of the multi-quantum well light-emitting layer, and enhance the radiation recombination efficiency in the multi-quantum well light-emitting layer, thereby improving the luminous efficiency of the LED device.

[0004] The technical problem to be solved by the present invention is to provide a method for preparing a light emitting diode epitaxial wafer, which has a simple process and can stably prepare a light emitting diode epitaxial wafer with good luminous efficiency.

[0005] In order to solve the above technical problems, the present invention provides a light-emitting diode epitaxial wafer, comprising a substrate, on which a buffer layer, a non-doped GaN layer, an N-type GaN layer, a stress release layer, a multi-quantum well light-emitting layer, an electron blocking layer, and a P-type GaN layer are sequentially arranged;

[0006] The stress release layer includes a Si-doped porous GaN layer, a porous InGaN / GaN superlattice layer with a low In content, a low Si-doped GaN merged layer, a porous InGaN / GaN superlattice layer with a high In content, and a Si-doped GaN merged layer, which are stacked in sequence.

[0007] In some embodiments, the thickness of the Si-doped porous GaN layer is 16 nm to 520 nm;

[0008] The Si doping concentration of the Si-doped porous GaN layer is 3.6×10 17 atoms / cm 3~2.8×10 19 atoms / cm 3 ;

[0009] The Si-doped porous GaN layer is provided with a first V-shaped hole penetrating through the Si-doped porous GaN layer;

[0010] The first V-shaped holes are uniformly distributed in the Si-doped porous GaN layer, and the density of the first V-shaped holes is 1.2×10 8 Pieces / cm 2 ~5.6×10 11 Pieces / cm 2 .

[0011] In some embodiments, the porous InGaN / GaN superlattice layer with a low In content includes a first InGaN layer and a first GaN layer alternately stacked, and the number of periods is 2 to 5;

[0012] The thickness of the first InGaN layer is 1.2 nm to 5 nm;

[0013] The In composition of the first InGaN layer is 0.01-0.15;

[0014] The Si doping concentration of the first GaN layer is 1.2×10 17 atoms / cm 3 ~5.6×10 18 atoms / cm 3 ;

[0015] The thickness of the first GaN layer is 2nm~13.6nm;

[0016] The porous InGaN / GaN superlattice layer with low In content is provided with a third V-shaped hole penetrating through the porous InGaN / GaN superlattice layer with low In content, and the third V-shaped hole is stacked on the first V-shaped hole;

[0017] The third V-shaped holes are uniformly distributed in the porous InGaN / GaN superlattice layer with low In content, and the density of the third V-shaped holes is 1.2×10 8 Pieces / cm 2 ~5.6×10 11 Pieces / cm 2 ;

[0018] The porous InGaN / GaN superlattice layer with low In content is provided with a second V-shaped hole penetrating the porous InGaN / GaN superlattice layer with low In content, and the second V-shaped hole is not stacked on the first V-shaped hole;

[0019] The second V-shaped holes are uniformly distributed in the porous InGaN / GaN superlattice layer with low In content, and the density of the second V-shaped holes is 2.6×10 8 Pieces / cm 2 ~1.8×10 12 Pieces / cm 2 ;

[0020] An opening size of the third V-shaped hole is larger than an opening size of the second V-shaped hole.

[0021] In some embodiments, the thickness of the low Si-doped GaN combined layer is 10 nm to 180 nm;

[0022] The Si doping concentration of the low Si-doped GaN combined layer is 1.2×10 17 atoms / cm 3 ~5.6×10 18 atoms / cm 3 ;

[0023] The low Si-doped GaN merged layer completely fills the second V-shaped hole, and does not completely fill the third V-shaped hole;

[0024] The low Si-doped GaN merged layer is provided with a fifth V-shaped hole penetrating the low Si-doped GaN merged layer, and the fifth V-shaped hole is stacked on the third V-shaped hole.

[0025] In some embodiments, the porous InGaN / GaN superlattice layer with a high In content includes a second InGaN layer and a second GaN layer alternately stacked, and the number of periods is 2 to 8;

[0026] The thickness of the second InGaN layer is 1.2 nm to 5 nm;

[0027] The In composition of the second InGaN layer is 0.03-0.3;

[0028] The Si doping concentration of the second GaN layer is 1.2×10 17 atoms / cm 3 ~5.6×10 18 atoms / cm 3 ;

[0029] The thickness of the second GaN layer is 2nm~13.6nm;

[0030] The porous InGaN / GaN superlattice layer with a high In content is provided with a sixth V-shaped hole penetrating the porous InGaN / GaN superlattice layer with a high In content, and the sixth V-shaped hole is stacked on the fifth V-shaped hole;

[0031] The sixth V-shaped holes are uniformly distributed in the porous InGaN / GaN superlattice layer with a high In content, and the density of the sixth V-shaped holes is 1.2×10 8 Pieces / cm 2 ~5.6×10 11 Pieces / cm 2 ;

[0032] The porous InGaN / GaN superlattice layer with a high In content is provided with a fourth V-shaped hole penetrating the porous InGaN / GaN superlattice layer with a high In content, and the fourth V-shaped hole is not stacked on the fifth V-shaped hole;

[0033] The fourth V-shaped holes are uniformly distributed in the porous InGaN / GaN superlattice layer with a high In content, and the density of the fourth V-shaped holes is 2.6×10 8 Pieces / cm 2 ~1.8×10 12 Pieces / cm 2 ;

[0034] An opening size of the sixth V-shaped hole is larger than an opening size of the fourth V-shaped hole.

[0035] In some embodiments, the thickness of the Si-doped GaN merged layer is 12 nm to 250 nm;

[0036] The Si doping concentration of the Si-doped GaN combined layer is 3.6×10 17 atoms / cm 3 ~2.8×10 19 atoms / cm 3 ;

[0037] The Si-doped GaN merged layer completely fills the fourth V-shaped hole, and does not completely fill the sixth V-shaped hole;

[0038] The Si-doped GaN merged layer is provided with a seventh V-shaped hole penetrating the Si-doped GaN merged layer, and the seventh V-shaped hole is stacked on the sixth V-shaped hole.

[0039] To solve the above problems, the present invention also provides a method for preparing a light emitting diode epitaxial wafer, comprising the following steps:

[0040] S1. providing a substrate;

[0041] S2, depositing a buffer layer, an undoped GaN layer, an N-type GaN layer, a stress release layer, a multi-quantum well light-emitting layer, an electron blocking layer, and a P-type GaN layer on the substrate in sequence;

[0042] The stress release layer includes a Si-doped porous GaN layer, a porous InGaN / GaN superlattice layer with a low In content, a low Si-doped GaN merged layer, a porous InGaN / GaN superlattice layer with a high In content, and a Si-doped GaN merged layer, which are stacked in sequence.

[0043] In some embodiments, before depositing the Si-doped porous GaN layer, the surface of the epitaxial layer material is subjected to a first high temperature H 2 Gas treatment, before depositing the porous InGaN / GaN superlattice layer with low In content, the surface of the epitaxial layer material is subjected to a second high temperature H 2 Gas treatment, before depositing the porous InGaN / GaN superlattice layer with a high In content, a third high temperature H 2 Gas treatment;

[0044] High temperature H 2 Gas treatment includes:

[0045] Step 1: Under the conditions of a reaction chamber temperature of 920°C to 1200°C and a pressure of 50 torr to 500 torr, introduce H into the reaction chamber. 2 and N 2 Mix the gas and keep it for 3s~180s;

[0046] Step 2: Stop feeding H 2 and N 2 Mixed gas;

[0047] Cycle the steps 1 and 2 to complete the high temperature H 2 Gas treatment.

[0048] In some embodiments, the first high temperature H 2 Gas treatment time ≥ the second high temperature H 2 Gas treatment time ≥ the third high temperature H 2 Processing time of gas treatment;

[0049] The first high temperature H 2 Gas treatment H 2 Inlet flow ≥ the second high temperature H 2 Gas treatment H 2 Inlet flow ≥ the third high temperature H 2 Gas treatment H 2 Incoming traffic.

[0050] Correspondingly, the present invention further provides an LED, which includes the light-emitting diode epitaxial wafer as described above, or includes the light-emitting diode epitaxial wafer manufactured by the method for manufacturing the light-emitting diode epitaxial wafer as described above.

[0051] The implementation of the present invention has the following beneficial effects:

[0052] In the light-emitting diode epitaxial wafer provided by the present invention, the stress release layer comprises a Si-doped porous GaN layer, a porous InGaN / GaN superlattice layer with a low In component, a low Si-doped GaN merged layer, a porous InGaN / GaN superlattice layer with a high In component and a Si-doped GaN merged layer which are stacked in sequence.

[0053] Among them, the three sublayers of Si-doped porous GaN layer, low-In component porous InGaN / GaN superlattice layer, and high-In component porous InGaN / GaN superlattice layer are all porous structures. The design of this structure is conducive to fully releasing the stress of the epitaxial layer material, and can effectively reduce the defects caused by large stress in the subsequent epitaxial layer material, thereby improving the quality of the multi-quantum well light-emitting layer material.

[0054] Furthermore, the porous InGaN / GaN superlattice layer with low In component and the porous InGaN / GaN superlattice layer with high In component are both porous InGaN / GaN superlattice materials, and there are differences in In components. This structural design is not only conducive to fully releasing the stress of the epitaxial layer material, but also can reduce the sidewall quantum well light-emitting area sacrificed to enhance hole injection, effectively increase the light-emitting area of ​​the platform quantum well required for the light-emitting diode, thereby improving the luminescence efficiency of the light-emitting diode.

[0055] Furthermore, since the stress release layer is provided with a V-shaped hole of a specific structure, a V-pit exists in the multi-quantum well light-emitting layer. The V-pit is generated in the stress release layer of the multi-layer structure and runs through the entire light-emitting unit. The quantum well grows in the V-pit to form a sidewall quantum well, which is thinner than the platform quantum well and has a smaller bandgap width. When carriers are injected into the active area, the quantum well at the sidewall of the V-pit has a smaller bandgap width and a thinner thickness. Through tunneling, carriers are more easily injected into the sidewall of the V-pit, thereby improving the matching degree of electrons and holes in the quantum well, promoting the light emission of the quantum well close to the N surface, and thus improving the luminescence efficiency of the InGaN-based LED.

[0056] In the method for preparing the light-emitting diode epitaxial wafer provided by the present invention, before depositing the Si-doped porous GaN layer, the porous InGaN / GaN superlattice layer with a low In component, and the porous InGaN / GaN superlattice layer with a high In component, the surface of the epitaxial layer material needs to be subjected to high temperature H 2 Gas treatment, after high temperature H 2The material with poor crystallization quality on the surface of the gas-treated epitaxial layer material will be decomposed, which is beneficial to reduce the defect density of the epitaxial layer material and improve the crystal quality of the epitaxial layer material. At the same time, an uneven rough surface is formed, which is beneficial for the subsequently deposited epitaxial layer material to more easily obtain large V-shaped holes and small V-shaped holes of the same size and uniform distribution, further fully release the stress of the epitaxial layer material and improve the quality of the epitaxial layer material.

[0057] Combining the above processes, the LED chip prepared by the present invention can reduce the stress and defect density of the multi-quantum well light-emitting layer material, significantly improve the quality of the multi-quantum well light-emitting layer, and effectively enhance the injection of holes in the active area to improve the matching degree of the electron-hole concentration in the quantum well, while increasing the light-emitting area of ​​the platform quantum well required for the light-emitting diode, thereby improving the radiation recombination efficiency in the multi-quantum well light-emitting layer, thereby improving the luminous efficiency of the LED chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0058] Figure 1 This is a schematic structural diagram of the light emitting diode epitaxial wafer provided by the present invention. DETAILED DESCRIPTION

[0059] In order to make the purpose, technical scheme and advantages of the present invention clearer, the present invention is further described in detail below in conjunction with the accompanying drawings and embodiments. Examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements with the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present invention, and should not be construed as limiting the present invention. In addition, it should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention.

[0060] In the description of the present invention, it is necessary to understand that the terms "length", "width", "up", "down", "left", "right", "horizontal", "top", "bottom", etc. indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present invention.

[0061] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features. In the description of the present invention, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.

[0062] In the description of the present invention, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, an electrical connection, or mutual communication; it can be a direct connection, or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0063] In the present invention, unless otherwise clearly specified and limited, a first feature being "above" or "below" a second feature may include that the first and second features are in direct contact, or may include that the first and second features are not in direct contact but are in contact through another feature between them. Moreover, a first feature being "above", "above" and "above" a second feature includes that the first feature is directly above and obliquely above the second feature, or simply indicates that the first feature is higher in level than the second feature. A first feature being "below", "below" and "below" a second feature includes that the first feature is directly below and obliquely below the second feature, or simply indicates that the first feature is lower in level than the second feature.

[0064] The disclosure below provides many different embodiments or examples to realize different structures of the present invention. In order to simplify the disclosure of the present invention, the parts and settings of specific examples are described below. Of course, they are only examples, and the purpose is not to limit the present invention. In addition, the present invention can repeat reference numbers and / or reference letters in different examples, and this repetition is for the purpose of simplification and clarity, which itself does not indicate the relationship between the various embodiments and / or settings discussed. In addition, the examples of various specific processes and materials provided by the present invention, but those of ordinary skill in the art can be aware of the application of other processes and / or the use of other materials.

[0065] In the present invention, "preferred" and "better" are only used to describe implementation methods or embodiments with better effects, and it should be understood that they do not constitute a limitation on the scope of protection of the present invention. In the present invention, the technical features described in an open manner include closed technical solutions composed of the listed features, and also include open technical solutions containing the listed features. In the present invention, when involving numerical ranges, unless otherwise specified, the two endpoints of the numerical range are included.

[0066] To solve the above problems, the present invention provides a light emitting diode epitaxial wafer, such as Figure 1 As shown, it includes a substrate 100, on which a buffer layer 200, a non-doped GaN layer 300, an N-type GaN layer 400, a stress release layer 500, a multi-quantum well light-emitting layer 600, an electron blocking layer 700, and a P-type GaN layer 800 are sequentially arranged;

[0067] The stress release layer 500 includes a Si-doped porous GaN layer 510, a porous InGaN / GaN superlattice layer 520 with a low In content, a low Si-doped GaN merged layer 530, a porous InGaN / GaN superlattice layer 540 with a high In content, and a Si-doped GaN merged layer 550 which are stacked in sequence.

[0068] The specific structure of the stress release layer 500 provided by the present invention is as follows:

[0069] In some embodiments, the thickness of the Si-doped porous GaN layer 510 is 16 nm to 520 nm. Exemplary thicknesses of the Si-doped porous GaN layer 510 are 50 nm, 100 nm, 150 nm, 200 nm, 250 nm, 300 nm, 350 nm, 400 nm, 450 nm, and 500 nm, but are not limited to the above. The Si doping concentration of the Si-doped porous GaN layer 510 is 3.6×10 17 atoms / cm 3 ~2.8×10 19 atoms / cm 3 The Si doping concentration of the Si-doped porous GaN layer 510 is 5×10 17 atoms / cm 3 , 1×10 18 atoms / cm 3 , 5×10 18 atoms / cm 3 , 1×10 19 atoms / cm 3 , but not limited to the above. The Si-doped porous GaN layer 510 is provided with a first V-shaped hole 511 penetrating the Si-doped porous GaN layer 510; the first V-shaped holes 511 are uniformly distributed in the Si-doped porous GaN layer 510, and the density of the first V-shaped holes 511 is 1.2×10 8 Pieces / cm 2 ~5.6×10 11 Pieces / cm 2 The first V-shaped holes 511 have a plurality of uniform sizes and are evenly arranged in the Si-doped porous GaN layer 510. The exemplary density of the first V-shaped holes 511 is 5×10 8 Pieces / cm 2 , 1×10 9 Pieces / cm 2 , 5×10 9 Pieces / cm 2 , 1×10 10 Pieces / cm 2, 5×10 10 Pieces / cm 2 , 1×10 11 Pieces / cm 2 , 5×10 11 Pieces / cm 2 , but not limited to the above.

[0070] In some embodiments, the low In component porous InGaN / GaN superlattice layer 520 includes a first InGaN layer and a first GaN layer alternately stacked, with a period number of 2 to 5. The thickness of the first InGaN layer is 1.2nm to 5nm; the exemplary thickness of the first InGaN layer is 2nm, 3nm, 4nm, but not limited to the above. The In component of the first InGaN layer is 0.01 to 0.15; preferably, the In component of the first InGaN layer is 0.05 to 0.10. The thickness of the first GaN layer is 2nm to 13.6nm; the exemplary thickness of the first GaN layer is 4nm, 6nm, 8nm, 10nm, 12nm, but not limited to the above. The Si doping concentration of the first GaN layer is 1.2×10 17 atoms / cm 3 ~5.6×10 18 atoms / cm 3 ; The exemplary Si doping concentration of the first GaN layer is 2×10 17 atoms / cm 3 , 4×10 17 atoms / cm 3 , 6×10 17 atoms / cm 3 , 8×10 17 atoms / cm 3 , 1×10 18 atoms / cm 3 , 3×10 18 atoms / cm 3 , 5×10 18 atoms / cm 3 , but not limited to the above.

[0071] In some embodiments, the low-In-content porous InGaN / GaN superlattice layer 520 is provided with a third V-shaped hole 521 penetrating the low-In-content porous InGaN / GaN superlattice layer 520 , and the third V-shaped hole 521 is stacked on the first V-shaped hole 511 ;

[0072] The third V-shaped holes 521 are uniformly distributed in the porous InGaN / GaN superlattice layer 520 with a low In content, and the density of the third V-shaped holes 521 is 1.2×10 8 Pieces / cm 2 ~5.6×10 11 Pieces / cm 2 The exemplary density of the third V-shaped holes 521 is 5×10 8 Pieces / cm 2 , 1×10 9 Pieces / cm 2 , 5×10 9 Pieces / cm 2 , 1×10 10 Pieces / cm 2 , 5×10 10 Pieces / cm 2 , 1×10 11 Pieces / cm 2 , 5×10 11 Pieces / cm 2 , but not limited to the above.

[0073] Meanwhile, the porous InGaN / GaN superlattice layer 520 with low In content is provided with a second V-shaped hole 522 penetrating the porous InGaN / GaN superlattice layer 520 with low In content, and the second V-shaped hole 522 is not stacked on the first V-shaped hole 511;

[0074] The second V-shaped holes 522 are uniformly distributed in the porous InGaN / GaN superlattice layer 520 with a low In content, and the density of the second V-shaped holes 522 is 2.6×10 8 Pieces / cm 2 ~1.8×10 12 Pieces / cm 2 The exemplary density of the second V-shaped holes 522 is 5×10 8 Pieces / cm 2 , 1×10 9 Pieces / cm 2 , 5×10 9 Pieces / cm 2 , 1×10 10 Pieces / cm 2 , 5×10 10 Pieces / cm 2 , 1×10 11 Pieces / cm 2 , 5×10 11 Pieces / cm 2 , 1×10 12 Pieces / cm 2 , but not limited to the above.

[0075] The porous InGaN / GaN superlattice layer 520 with low In content is deposited on the second high temperature H 2 A porous structure with two hole sizes is formed on the gas-treated Si-doped porous GaN layer 510, and the opening size of the third V-shaped hole is larger than the opening size of the second V-shaped hole, namely the large V-shaped hole - the third V-shaped hole 521 and the small V-shaped hole - the second V-shaped hole 522. The third V-shaped hole 521 is stacked on the first V-shaped hole 511, and the second V-shaped hole 522 is not stacked on the first V-shaped hole 511.

[0076] In some embodiments, the thickness of the low Si-doped GaN merged layer 530 is 10 nm to 180 nm; exemplary thicknesses of the low Si-doped GaN merged layer 530 are 20 nm, 40 nm, 60 nm, 80 nm, 100 nm, 120 nm, 140 nm, and 160 nm, but are not limited to the above. The Si doping concentration of the low Si-doped GaN merged layer 530 is 1.2×10 17 atoms / cm 3 ~5.6×10 18 atoms / cm 3 The exemplary Si doping concentration of the low Si-doped GaN merged layer 530 is 2×10 17 atoms / cm 3 , 4×10 17 atoms / cm 3 , 6×10 17 atoms / cm 3 , 8×10 17 atoms / cm 3 , 1×10 18 atoms / cm 3 , 2×10 18 atoms / cm 3 , 3×10 18 atoms / cm 3 , 4×10 18 atoms / cm 3 , 5×10 18 atoms / cm 3 , but not limited to the above.

[0077] In some embodiments, the low Si-doped GaN merged layer 530 completely fills the second V-shaped hole 522 and does not completely fill the third V-shaped hole 521; the low Si-doped GaN merged layer 530 is provided with a fifth V-shaped hole 531 that penetrates the low Si-doped GaN merged layer 530, and the fifth V-shaped hole 531 is stacked on the third V-shaped hole 521.

[0078] In some embodiments, the porous InGaN / GaN superlattice layer 540 with a high In component includes a second InGaN layer and a second GaN layer alternately stacked, with a period number of 2 to 8. The thickness of the second InGaN layer is 1.2nm to 5nm; the exemplary thickness of the second InGaN layer is 2nm, 3nm, 4nm, but not limited to the above. The In component of the second InGaN layer is 0.03 to 0.3; preferably, the In component of the second InGaN layer is 0.05 to 0.25. The thickness of the second GaN layer is 2nm to 13.6nm; the exemplary thickness of the second GaN layer is 4nm, 6nm, 8nm, 10nm, 11nm, 12nm, 13nm, but not limited to the above. The Si doping concentration of the second GaN layer is 1.2×10 17 atoms / cm 3 ~5.6×10 18 atoms / cm 3 ; The exemplary Si doping concentration of the second GaN layer is 2×10 17 atoms / cm 3 , 4×10 17 atoms / cm 3 , 6×10 17 atoms / cm 3 , 8×10 17 atoms / cm 3 , 1×10 18 atoms / cm 3 , 2×10 18 atoms / cm 3 , 3×10 18 atoms / cm 3 , 4×10 18 atoms / cm 3 , 5×10 18 atoms / cm 3 , but not limited to the above.

[0079] In some embodiments, the porous InGaN / GaN superlattice layer 540 with a high In content is provided with a sixth V-shaped hole 541 penetrating the porous InGaN / GaN superlattice layer 540 with a high In content, and the sixth V-shaped hole 541 is stacked on the fifth V-shaped hole 531;

[0080] The sixth V-shaped holes 541 are uniformly distributed in the porous InGaN / GaN superlattice layer 540 with a high In content, and the density of the sixth V-shaped holes 541 is 1.2×10 8 Pieces / cm 2 ~5.6×10 11 Pieces / cm 2 The exemplary density of the sixth V-shaped holes 541 is 5×10 8 Pieces / cm 2 , 1×10 9 Pieces / cm 2 , 5×10 9 Pieces / cm 2 , 1×10 10 Pieces / cm 2 , 5×10 10 Pieces / cm 2 , 1×10 11 Pieces / cm 2 , 5×10 11 Pieces / cm 2 , but not limited to the above.

[0081] Meanwhile, the porous InGaN / GaN superlattice layer 540 with a high In content is provided with a fourth V-shaped hole 542 penetrating the porous InGaN / GaN superlattice layer 540 with a high In content, and the fourth V-shaped hole 542 is not stacked on the fifth V-shaped hole 531;

[0082] The fourth V-shaped holes 542 are uniformly distributed in the porous InGaN / GaN superlattice layer 540 with a high In content, and the density of the fourth V-shaped holes 542 is 2.6×10 8 Pieces / cm 2 ~1.8×10 12 Pieces / cm 2 The exemplary density of the fourth V-shaped holes 542 is 5×10 8 Pieces / cm 2 , 1×10 9 Pieces / cm 2 , 5×10 9 Pieces / cm 2 , 1×10 10 Pieces / cm 2 , 5×10 10 Pieces / cm2 , 1×10 11 Pieces / cm 2 , 5×10 11 Pieces / cm 2 , 1×10 12 Pieces / cm 2 , but not limited to the above.

[0083] The porous InGaN / GaN superlattice layer 540 with a high In content is deposited on the substrate after the third high temperature H 2 A porous structure with two hole sizes is formed on the gas-treated low Si-doped GaN merged layer 530, and the opening size of the sixth V-shaped hole is larger than the opening size of the fourth V-shaped hole, namely the large V-shaped hole - the sixth V-shaped hole 541 and the small V-shaped hole - the fourth V-shaped hole 542. The sixth V-shaped hole 541 is stacked on the fifth V-shaped hole 531, and the fourth V-shaped hole 542 is not stacked on the fifth V-shaped hole 531.

[0084] In some embodiments, the thickness of the Si-doped GaN merged layer 550 is 12 nm to 250 nm; exemplary thicknesses of the Si-doped GaN merged layer 550 are 20 nm, 40 nm, 60 nm, 80 nm, 100 nm, 120 nm, 140 nm, 160 nm, 180 nm, 200 nm, 220 nm, and 240 nm, but are not limited to the above. The Si doping concentration of the Si-doped GaN merged layer 550 is 3.6×10 17 atoms / cm 3 ~2.8×10 19 atoms / cm 3 The exemplary Si doping concentration of the Si-doped GaN merged layer 550 is 4×10 17 atoms / cm 3 , 6×10 17 atoms / cm 3 , 8×10 17 atoms / cm 3 , 1×10 18 atoms / cm 3 , 3×10 18 atoms / cm 3 , 5×10 18 atoms / cm 3 ,7×10 18 atoms / cm 3 ,9×10 18 atoms / cm 3 , 1.1×10 19 atoms / cm3 , but not limited to the above.

[0085] In some embodiments, the Si-doped GaN merged layer 550 completely fills the fourth V-shaped hole 542 , and does not completely fill the sixth V-shaped hole 541 ;

[0086] The Si-doped GaN merged layer 550 is provided with a seventh V-shaped hole 551 penetrating the Si-doped GaN merged layer 550 , and the seventh V-shaped hole 551 is stacked on the sixth V-shaped hole 541 .

[0087] In summary, in the light-emitting diode epitaxial wafer provided by the present invention, the stress release layer 500 includes a Si-doped porous GaN layer 510, a porous InGaN / GaN superlattice layer 520 with a low In component, a low Si-doped GaN merged layer 530, a porous InGaN / GaN superlattice layer 540 with a high In component, and a Si-doped GaN merged layer 550 stacked in sequence.

[0088] Among them, the three sub-layers of Si-doped porous GaN layer 510, low-In component porous InGaN / GaN superlattice layer 520, and high-In component porous InGaN / GaN superlattice layer 540 are all porous structures. The design of this structure is conducive to fully releasing the stress of the epitaxial layer material, and can effectively reduce the defects caused by the subsequent epitaxial layer material being subjected to large stress, thereby improving the quality of the multi-quantum well light-emitting layer material.

[0089] Furthermore, the porous InGaN / GaN superlattice layer 520 with a low In component and the porous InGaN / GaN superlattice layer 540 with a high In component are both porous InGaN / GaN superlattice materials, and there are differences in the In components. This structural design is not only conducive to fully releasing the stress of the epitaxial layer material, but also can reduce the sidewall quantum well light-emitting area sacrificed to enhance hole injection, effectively increase the light-emitting area of ​​the platform quantum well required for the light-emitting diode, thereby improving the light-emitting efficiency of the light-emitting diode.

[0090] Furthermore, since the stress release layer 500 is provided with a V-shaped hole of a specific structure, a V-pit exists in the multi-quantum well light-emitting layer 600. The V-pit is generated in the stress release layer of the multi-layer structure and runs through the entire light-emitting unit. The quantum well grows in the V-pit to form a sidewall quantum well, which is thinner than the platform quantum well and has a smaller bandgap width. When carriers are injected into the active area, the quantum well at the sidewall of the V-pit has a smaller bandgap width and a thinner thickness. Through tunneling, carriers are more easily injected into the sidewall of the V-pit, thereby improving the matching degree of electrons and holes in the quantum well, promoting the light emission of the quantum well close to the N surface, and thus improving the luminescence efficiency of the InGaN-based LED.

[0091] Accordingly, the present invention provides a method for preparing a light emitting diode epitaxial wafer, comprising the following steps:

[0092] S1, providing a substrate 100;

[0093] In some embodiments, the substrate 100 may be a sapphire substrate, a SiO 2 One of sapphire composite substrate, silicon substrate, silicon carbide substrate, gallium nitride substrate, and zinc oxide substrate. Preferably, the substrate 100 is a sapphire substrate, which is a commonly used GaN-based LED substrate material. The sapphire substrate has a mature preparation process, a low price, is easy to clean and handle, and has good stability at high temperatures.

[0094] S2, sequentially depositing a buffer layer 200, a non-doped GaN layer 300, an N-type GaN layer 400, a stress release layer 500, a multi-quantum well light-emitting layer 600, an electron blocking layer 700, and a P-type GaN layer 800 on the substrate 100;

[0095] The stress release layer 500 includes a Si-doped porous GaN layer 510, a porous InGaN / GaN superlattice layer 520 with a low In content, a low Si-doped GaN merged layer 530, a porous InGaN / GaN superlattice layer 540 with a high In content, and a Si-doped GaN merged layer 550 which are stacked in sequence.

[0096] Specifically, the above step S2 specifically includes the following steps:

[0097] S21 , depositing the buffer layer 200 on the substrate 100 .

[0098] In some embodiments, the buffer layer 200 is an AlN buffer layer.

[0099] S22 , depositing the undoped GaN layer 300 on the buffer layer 200 .

[0100] In some embodiments, the temperature of the reaction chamber is controlled at 1050° C. to 1200° C., the pressure is controlled at 100 torr to 600 torr, N source and Ga source are introduced, and a non-doped GaN layer with a thickness of 1 μm to 5 μm is grown.

[0101] S23 , depositing the N-type GaN layer 400 on the undoped GaN layer 300 .

[0102] In some embodiments, the temperature of the reaction chamber is controlled at 1050° C. to 1200° C., the pressure is controlled at 100 torr to 600 torr, and an N source, a Ga source, and a Si source are introduced to grow the N-type GaN layer.

[0103] S24 , depositing the stress release layer 500 on the N-type GaN layer 400 .

[0104] In some embodiments, before depositing the Si-doped porous GaN layer 510, the surface of the epitaxial layer material is subjected to a first high temperature H 2 Gas treatment, before depositing the porous InGaN / GaN superlattice layer 520 with a low In content, a second high temperature H 2 Gas treatment, before depositing the porous InGaN / GaN superlattice layer 540 with a high In content, a third high temperature H 2 Gas treatment;

[0105] The first high temperature H 2 Gas treatment, second high temperature H 2 Gas treatment, third high temperature H 2 Gas treatment includes:

[0106] Step 1: Under the conditions of a reaction chamber temperature of 920°C to 1200°C and a pressure of 50 torr to 500 torr, introduce H into the reaction chamber. 2 and N 2 Mix the gas and keep it for 3s~180s;

[0107] Step 2: Stop feeding H 2 and N 2 Mixed gas;

[0108] Cycle the steps 1 and 2 to complete the high temperature H 2 Gas treatment.

[0109] Preferably, the first high temperature H 2 Gas treatment time ≥ the second high temperature H 2 Gas treatment time ≥ the third high temperature H 2 Processing time of gas treatment;

[0110] The first high temperature H 2 Gas treatment H 2 Inlet flow ≥ the second high temperature H 2 Gas treatment H 2 Inlet flow ≥ the third high temperature H 2 Gas treatment H 2 Incoming traffic.

[0111] More preferably, the first high temperature H 2 The processing time of gas treatment is 10s~180s, H 2 The inlet flow rate is 50slm~360slm; the second high temperature H 2 The processing time of gas treatment is 5s~120s, H2 The flow rate is 30slm~300slm; the third high temperature H 2 The processing time of gas treatment is 3s~60s, H 2 The inlet flow rate is 20slm~250slm.

[0112] In the method for preparing the light-emitting diode epitaxial wafer provided in the above embodiment, before depositing the Si-doped porous GaN layer, the porous InGaN / GaN superlattice layer with a low In content, and the porous InGaN / GaN superlattice layer with a high In content, the surface of the epitaxial layer material needs to be subjected to high temperature H 2 Gas treatment, after high temperature H 2 The material with poor crystallization quality on the surface of the gas-treated epitaxial layer material will be decomposed, which is beneficial to reduce the defect density of the epitaxial layer material and improve the crystal quality of the epitaxial layer material. At the same time, an uneven rough surface is formed, which is beneficial for the subsequently deposited epitaxial layer material to more easily obtain large V-shaped holes and small V-shaped holes of the same size and uniform distribution, further fully release the stress of the epitaxial layer material and improve the quality of the epitaxial layer material.

[0113] S25 , depositing the multi-quantum well light-emitting layer 600 on the stress release layer 500 .

[0114] In some embodiments, the multi-quantum well light-emitting layer is an alternately stacked InGaN quantum well layer and an AlGaN quantum barrier layer, with a stacking period number of 1 to 20. The growth temperature of the InGaN quantum well layer is 790°C to 810°C, the thickness is 2nm to 5nm, and the growth pressure is 50torr to 300torr; the growth temperature of the AlGaN quantum barrier layer is 800°C to 900°C, the thickness is 5nm to 15nm, and the growth pressure is 50torr to 300torr.

[0115] S26, depositing the electron blocking layer 700 on the multi-quantum well light-emitting layer 600;

[0116] In some embodiments, the temperature of the reaction chamber is controlled at 900° C. to 1000° C., the pressure is controlled at 100 torr to 300 torr, N source, Al source, Ga source, and In source are introduced, and an AlInGaN electron blocking layer with a thickness of 10 nm to 40 nm is grown.

[0117] S27 , depositing the P-type GaN layer 800 on the electron blocking layer 700 .

[0118] In some embodiments, the temperature of the reaction chamber is controlled at 900° C. to 1050° C., the pressure is controlled at 100 torr to 600 torr, and an N source, a Mg source, and a Ga source are introduced to grow the P-type GaN layer.

[0119] Combining the above processes, the LED chip prepared by the present invention can reduce the stress and defect density of the multi-quantum well light-emitting layer material, significantly improve the quality of the multi-quantum well light-emitting layer, and effectively enhance the injection of holes in the active area to improve the matching degree of the electron-hole concentration in the quantum well, while increasing the light-emitting area of ​​the platform quantum well required for the light-emitting diode, thereby improving the radiation recombination efficiency in the multi-quantum well light-emitting layer, thereby improving the luminous efficiency of the LED chip.

[0120] Accordingly, the present invention further provides an LED, which comprises the above-mentioned light-emitting diode epitaxial wafer, wherein the photoelectric efficiency of the LED is effectively improved and other electrical properties are good.

[0121] The present invention is further described below with specific embodiments:

[0122] Example 1

[0123] This embodiment provides a light-emitting diode epitaxial wafer, comprising a substrate, on which a buffer layer, a non-doped GaN layer, an N-type GaN layer, a stress release layer, a multi-quantum well light-emitting layer, an electron blocking layer, and a P-type GaN layer are sequentially provided;

[0124] The stress release layer includes a Si-doped porous GaN layer, a porous InGaN / GaN superlattice layer with a low In content, a low Si-doped GaN merged layer, a porous InGaN / GaN superlattice layer with a high In content, and a Si-doped GaN merged layer, which are stacked in sequence.

[0125] The thickness of the Si-doped porous GaN layer is 50 nm, and the Si doping concentration is 5×10 18 atoms / cm 3 The Si-doped porous GaN layer is provided with first V-shaped holes penetrating the Si-doped porous GaN layer, and the density of the first V-shaped holes is 1×10 10 Pieces / cm 2 .

[0126] The porous InGaN / GaN superlattice layer with low In content includes a first InGaN layer and a first GaN layer alternately stacked, with a period number of 3; the thickness of the first InGaN layer is 3 nm; the In content of the first InGaN layer is 0.1; the Si doping concentration of the first GaN layer is 5×10 17 atoms / cm 3 ; The thickness of the first GaN layer is 10 nm;

[0127] The porous InGaN / GaN superlattice layer with low In component is provided with a third V-shaped hole penetrating the porous InGaN / GaN superlattice layer with low In component, and the third V-shaped hole is stacked on the first V-shaped hole; the porous InGaN / GaN superlattice layer with low In component is provided with a second V-shaped hole penetrating the porous InGaN / GaN superlattice layer with low In component, and the second V-shaped hole is not stacked on the first V-shaped hole; the density of the third V-shaped hole is 1×10 10 Pieces / cm 2 , the density of the second V-shaped holes is 1×10 11 Pieces / cm 2 .

[0128] The thickness of the low Si-doped GaN combined layer is 50 nm, and the Si doping concentration is 2×10 17 atoms / cm 3 The low Si-doped GaN merged layer completely fills the second V-shaped hole, and does not completely fill the third V-shaped hole; the low Si-doped GaN merged layer is provided with a fifth V-shaped hole penetrating the low Si-doped GaN merged layer, and the fifth V-shaped hole is stacked on the third V-shaped hole.

[0129] The porous InGaN / GaN superlattice layer with a high In content comprises a second InGaN layer and a second GaN layer alternately stacked, with a period number of 5; the thickness of the second InGaN layer is 3 nm; the In content of the second InGaN layer is 0.2; the Si doping concentration of the second GaN layer is 5×10 17 atoms / cm 3 ; The thickness of the second GaN layer is 10 nm; the porous InGaN / GaN superlattice layer with a high In component is provided with a sixth V-shaped hole penetrating the porous InGaN / GaN superlattice layer with a high In component, and the sixth V-shaped hole is stacked on the fifth V-shaped hole; the porous InGaN / GaN superlattice layer with a high In component is provided with a fourth V-shaped hole penetrating the porous InGaN / GaN superlattice layer with a high In component, and the fourth V-shaped hole is not stacked on the fifth V-shaped hole; the density of the sixth V-shaped hole is 1×10 10 Pieces / cm 2 The density of the fourth V-shaped holes is 1×10 11 Pieces / cm 2 .

[0130] The thickness of the Si-doped GaN merged layer is 100 nm, the Si-doped GaN merged layer completely fills the fourth V-shaped hole, and does not completely fill the sixth V-shaped hole; the Si-doped GaN merged layer is provided with a seventh V-shaped hole penetrating the Si-doped GaN merged layer, and the seventh V-shaped hole is stacked on the sixth V-shaped hole.

[0131] Example 2

[0132] This embodiment provides a light-emitting diode epitaxial wafer, comprising a substrate, on which a buffer layer, a non-doped GaN layer, an N-type GaN layer, a stress release layer, a multi-quantum well light-emitting layer, an electron blocking layer, and a P-type GaN layer are sequentially provided;

[0133] The stress release layer includes a Si-doped porous GaN layer, a porous InGaN / GaN superlattice layer with a low In content, a low Si-doped GaN merged layer, a porous InGaN / GaN superlattice layer with a high In content, and a Si-doped GaN merged layer, which are stacked in sequence.

[0134] The thickness of the Si-doped porous GaN layer is 100 nm, and the Si doping concentration is 1×10 19 atoms / cm 3 The Si-doped porous GaN layer is provided with first V-shaped holes penetrating the Si-doped porous GaN layer, and the density of the first V-shaped holes is 1×10 10 Pieces / cm 2 .

[0135] The porous InGaN / GaN superlattice layer with low In content includes a first InGaN layer and a first GaN layer alternately stacked, with a period number of 3; the thickness of the first InGaN layer is 3 nm; the In content of the first InGaN layer is 0.1; the Si doping concentration of the first GaN layer is 5×10 18 atoms / cm 3 ; The thickness of the first GaN layer is 10 nm;

[0136] The porous InGaN / GaN superlattice layer with low In component is provided with a third V-shaped hole penetrating the porous InGaN / GaN superlattice layer with low In component, and the third V-shaped hole is stacked on the first V-shaped hole; the porous InGaN / GaN superlattice layer with low In component is provided with a second V-shaped hole penetrating the porous InGaN / GaN superlattice layer with low In component, and the second V-shaped hole is not stacked on the first V-shaped hole; the density of the third V-shaped hole is 1×10 10 Pieces / cm 2 , the density of the second V-shaped holes is 1×10 11Pieces / cm 2 .

[0137] The thickness of the low Si-doped GaN combined layer is 150 nm, and the Si doping concentration is 5×10 18 atoms / cm 3 The low Si-doped GaN merged layer completely fills the second V-shaped hole, and does not completely fill the third V-shaped hole; the low Si-doped GaN merged layer is provided with a fifth V-shaped hole penetrating the low Si-doped GaN merged layer, and the fifth V-shaped hole is stacked on the third V-shaped hole.

[0138] The porous InGaN / GaN superlattice layer with a high In content comprises a second InGaN layer and a second GaN layer alternately stacked, with a period number of 5; the thickness of the second InGaN layer is 3 nm; the In content of the second InGaN layer is 0.2; the Si doping concentration of the second GaN layer is 5×10 17 atoms / cm 3 ; The thickness of the second GaN layer is 10 nm;

[0139] The porous InGaN / GaN superlattice layer with a high In component is provided with a sixth V-shaped hole penetrating the porous InGaN / GaN superlattice layer with a high In component, and the sixth V-shaped hole is stacked on the fifth V-shaped hole; the porous InGaN / GaN superlattice layer with a high In component is provided with a fourth V-shaped hole penetrating the porous InGaN / GaN superlattice layer with a high In component, and the fourth V-shaped hole is not stacked on the fifth V-shaped hole; the density of the sixth V-shaped hole is 1×10 10 Pieces / cm 2 The density of the fourth V-shaped holes is 1×10 11 Pieces / cm 2 .

[0140] The thickness of the Si-doped GaN merged layer is 200 nm, the Si-doped GaN merged layer completely fills the fourth V-shaped hole, and does not completely fill the sixth V-shaped hole; the Si-doped GaN merged layer is provided with a seventh V-shaped hole penetrating the Si-doped GaN merged layer, and the seventh V-shaped hole is stacked on the sixth V-shaped hole.

[0141] Example 3

[0142] This embodiment provides a light-emitting diode epitaxial wafer, comprising a substrate, on which a buffer layer, a non-doped GaN layer, an N-type GaN layer, a stress release layer, a multi-quantum well light-emitting layer, an electron blocking layer, and a P-type GaN layer are sequentially provided;

[0143] The stress release layer includes a Si-doped porous GaN layer, a porous InGaN / GaN superlattice layer with a low In content, a low Si-doped GaN merged layer, a porous InGaN / GaN superlattice layer with a high In content, and a Si-doped GaN merged layer, which are stacked in sequence.

[0144] The thickness of the Si-doped porous GaN layer is 30 nm, and the Si doping concentration is 5×10 17 atoms / cm 3 The Si-doped porous GaN layer is provided with first V-shaped holes penetrating the Si-doped porous GaN layer, and the density of the first V-shaped holes is 1×10 10 Pieces / cm 2 .

[0145] The porous InGaN / GaN superlattice layer with low In content includes a first InGaN layer and a first GaN layer alternately stacked, with a period number of 3; the thickness of the first InGaN layer is 3 nm; the In content of the first InGaN layer is 0.1; the Si doping concentration of the first GaN layer is 3×10 17 atoms / cm 3 ; The thickness of the first GaN layer is 10 nm;

[0146] The porous InGaN / GaN superlattice layer with low In component is provided with a third V-shaped hole penetrating the porous InGaN / GaN superlattice layer with low In component, and the third V-shaped hole is stacked on the first V-shaped hole; the porous InGaN / GaN superlattice layer with low In component is provided with a second V-shaped hole penetrating the porous InGaN / GaN superlattice layer with low In component, and the second V-shaped hole is not stacked on the first V-shaped hole; the density of the third V-shaped hole is 1×10 10 Pieces / cm 2 , the density of the second V-shaped holes is 1×10 11 Pieces / cm 2 .

[0147] The thickness of the low Si-doped GaN combined layer is 20 nm, and the Si doping concentration is 1×10 18 atoms / cm 3 The low Si-doped GaN merged layer completely fills the second V-shaped hole, and does not completely fill the third V-shaped hole; the low Si-doped GaN merged layer is provided with a fifth V-shaped hole penetrating the low Si-doped GaN merged layer, and the fifth V-shaped hole is stacked on the third V-shaped hole.

[0148] The porous InGaN / GaN superlattice layer with a high In content includes a second InGaN layer and a second GaN layer alternately stacked, with a period number of 5; the thickness of the second InGaN layer is 3 nm; the In content of the second InGaN layer is 0.2; the Si doping concentration of the second GaN layer is 2×10 17 atoms / cm 3 ; The thickness of the second GaN layer is 10 nm;

[0149] The porous InGaN / GaN superlattice layer with a high In component is provided with a sixth V-shaped hole penetrating the porous InGaN / GaN superlattice layer with a high In component, and the sixth V-shaped hole is stacked on the fifth V-shaped hole; the porous InGaN / GaN superlattice layer with a high In component is provided with a fourth V-shaped hole penetrating the porous InGaN / GaN superlattice layer with a high In component, and the fourth V-shaped hole is not stacked on the fifth V-shaped hole; the density of the sixth V-shaped hole is 1×10 10 Pieces / cm 2 The density of the fourth V-shaped holes is 1×10 11 Pieces / cm 2 .

[0150] The thickness of the Si-doped GaN merged layer is 20 nm, the Si-doped GaN merged layer completely fills the fourth V-shaped hole, and does not completely fill the sixth V-shaped hole; the Si-doped GaN merged layer is provided with a seventh V-shaped hole penetrating the Si-doped GaN merged layer, and the seventh V-shaped hole is stacked on the sixth V-shaped hole.

[0151] Comparative Example 1

[0152] This comparative example provides a light emitting diode epitaxial wafer, which is different from the other embodiment 1 in that its stress release layer is alternately stacked GaN layers and InGaN layers, and the rest is the same as the embodiment 1.

[0153] The light-emitting diode epitaxial wafers prepared in Examples 1 to 3 and Comparative Example 1 were used to prepare 10 mil×24 mil LED chips using the same chip process conditions. 300 LED chips were respectively extracted and tested at a current of 120 mA. Compared with the LED chip prepared in Comparative Example 1, the luminous efficiency improvement rate of each example was calculated. The specific test results are shown in Table 1.

[0154] Table 1 Performance test results of LEDs obtained from Examples 1 to 3 and Comparative Example 1

[0155]

[0156] From the above results, it can be seen that the light-emitting diode epitaxial wafer provided by the present invention can reduce the stress and defect density of the multi-quantum well light-emitting layer material, significantly improve the quality of the multi-quantum well light-emitting layer, and enhance the radiation recombination efficiency in the multi-quantum well light-emitting layer, thereby improving the luminous efficiency of the LED device.

[0157] In the description of this specification, the description with reference to the terms "some embodiments", "illustrative embodiments", "examples", "specific examples", or "some examples" means that the specific features, structures, materials or characteristics described in conjunction with the embodiments or examples are included in at least one embodiment or example of the present application. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner.

[0158] The above is a preferred embodiment of the invention. It should be pointed out that a person skilled in the art can make several improvements and modifications without departing from the principle of the invention. These improvements and modifications are also considered to be within the scope of protection of the invention.

Claims

1. A light emitting diode epitaxial wafer, characterized in that: It comprises a substrate, on which a buffer layer, a non-doped GaN layer, an N-type GaN layer, a stress release layer, a multi-quantum well light-emitting layer, an electron blocking layer, and a P-type GaN layer are sequentially arranged; The stress release layer comprises a Si-doped porous GaN layer, a porous InGaN / GaN superlattice layer with a low In component, a low Si-doped GaN merged layer, a porous InGaN / GaN superlattice layer with a high In component, and a Si-doped GaN merged layer, which are stacked in sequence; The porous InGaN / GaN superlattice layer with low In content comprises a first InGaN layer and a first GaN layer alternately stacked, wherein the In content of the first InGaN layer is 0.01-0.15; The Si doping concentration of the low Si-doped GaN combined layer is 1.2×10 17 atoms / cm 3 ~5.6×10 18 atoms / cm 3 ; The porous InGaN / GaN superlattice layer with a high In composition includes a second InGaN layer and a second GaN layer stacked alternately, and the In composition of the second InGaN layer is 0.03-0.

3.

2. The light emitting diode epitaxial wafer according to claim 1, characterized in that: The thickness of the Si-doped porous GaN layer is 16 nm to 520 nm; The Si doping concentration of the Si-doped porous GaN layer is 3.6×10 17 atoms / cm 3 ~2.8×10 19 atoms / cm 3 ; The Si-doped porous GaN layer is provided with a first V-shaped hole penetrating through the Si-doped porous GaN layer; The first V-shaped holes are uniformly distributed in the Si-doped porous GaN layer, and the density of the first V-shaped holes is 1.2×10 8 Pieces / cm 2 ~5.6×10 11 Pieces / cm 2 .

3. The light emitting diode epitaxial wafer according to claim 2, characterized in that: The porous InGaN / GaN superlattice layer with low In content comprises first InGaN layers and first GaN layers alternately stacked, and the number of periods is 2 to 5; The thickness of the first InGaN layer is 1.2 nm to 5 nm; The Si doping concentration of the first GaN layer is 1.2×10 17 atoms / cm 3 ~5.6×10 18 atoms / cm 3 ; The thickness of the first GaN layer is 2nm~13.6nm; The porous InGaN / GaN superlattice layer with low In content is provided with a third V-shaped hole penetrating through the porous InGaN / GaN superlattice layer with low In content, and the third V-shaped hole is stacked on the first V-shaped hole; The third V-shaped holes are uniformly distributed in the porous InGaN / GaN superlattice layer with low In content, and the density of the third V-shaped holes is 1.2×10 8 Pieces / cm 2 ~5.6×10 11 Pieces / cm 2 ; The porous InGaN / GaN superlattice layer with low In content is provided with a second V-shaped hole penetrating the porous InGaN / GaN superlattice layer with low In content, and the second V-shaped hole is not stacked on the first V-shaped hole; The second V-shaped holes are uniformly distributed in the porous InGaN / GaN superlattice layer with low In content, and the density of the second V-shaped holes is 2.6×10 8 Pieces / cm 2 ~1.8×10 12 Pieces / cm 2 ; An opening size of the third V-shaped hole is larger than an opening size of the second V-shaped hole.

4. The light emitting diode epitaxial wafer according to claim 3, characterized in that: The thickness of the low Si-doped GaN combined layer is 10nm~180nm; The low Si-doped GaN merged layer completely fills the second V-shaped hole, and does not completely fill the third V-shaped hole; The low Si-doped GaN merged layer is provided with a fifth V-shaped hole penetrating the low Si-doped GaN merged layer, and the fifth V-shaped hole is stacked on the third V-shaped hole.

5. The light emitting diode epitaxial wafer according to claim 4, characterized in that: The porous InGaN / GaN superlattice layer with a high In component comprises a second InGaN layer and a second GaN layer alternately stacked, and the number of periods is 2 to 8; The thickness of the second InGaN layer is 1.2 nm to 5 nm; The Si doping concentration of the second GaN layer is 1.2×10 17 atoms / cm 3 ~5.6×10 18 atoms / cm 3 ; The thickness of the second GaN layer is 2nm~13.6nm; The porous InGaN / GaN superlattice layer with a high In content is provided with a sixth V-shaped hole penetrating the porous InGaN / GaN superlattice layer with a high In content, and the sixth V-shaped hole is stacked on the fifth V-shaped hole; The sixth V-shaped holes are uniformly distributed in the porous InGaN / GaN superlattice layer with a high In content, and the density of the sixth V-shaped holes is 1.2×10 8 Pieces / cm 2 ~5.6×10 11 Pieces / cm 2 ; The porous InGaN / GaN superlattice layer with a high In content is provided with a fourth V-shaped hole penetrating the porous InGaN / GaN superlattice layer with a high In content, and the fourth V-shaped hole is not stacked on the fifth V-shaped hole; The fourth V-shaped holes are uniformly distributed in the porous InGaN / GaN superlattice layer with a high In content, and the density of the fourth V-shaped holes is 2.6×10 8 Pieces / cm 2 ~1.8×10 12 Pieces / cm 2 ; An opening size of the sixth V-shaped hole is larger than an opening size of the fourth V-shaped hole.

6. The light emitting diode epitaxial wafer according to claim 5, characterized in that: The thickness of the Si-doped GaN combined layer is 12nm~250nm; The Si doping concentration of the Si-doped GaN combined layer is 3.6×10 17 atoms / cm 3 ~2.8×10 19 atoms / cm 3 ; The Si-doped GaN merged layer completely fills the fourth V-shaped hole, and does not completely fill the sixth V-shaped hole; The Si-doped GaN merged layer is provided with a seventh V-shaped hole penetrating the Si-doped GaN merged layer, and the seventh V-shaped hole is stacked on the sixth V-shaped hole.

7. A method for preparing a light emitting diode epitaxial wafer according to any one of claims 1 to 6, characterized in that: The following steps are involved: S1. providing a substrate; S2, depositing a buffer layer, an undoped GaN layer, an N-type GaN layer, a stress release layer, a multi-quantum well light-emitting layer, an electron blocking layer, and a P-type GaN layer on the substrate in sequence; The stress release layer comprises a Si-doped porous GaN layer, a porous InGaN / GaN superlattice layer with a low In component, a low Si-doped GaN merged layer, a porous InGaN / GaN superlattice layer with a high In component, and a Si-doped GaN merged layer, which are stacked in sequence; The porous InGaN / GaN superlattice layer with low In content comprises a first InGaN layer and a first GaN layer alternately stacked, wherein the In content of the first InGaN layer is 0.01-0.15; The Si doping concentration of the low Si-doped GaN combined layer is 1.2×10 17 atoms / cm 3 ~5.6×10 18 atoms / cm 3 ; The porous InGaN / GaN superlattice layer with a high In composition includes a second InGaN layer and a second GaN layer stacked alternately, and the In composition of the second InGaN layer is 0.03-0.

3.

8. The method for preparing a light emitting diode epitaxial wafer according to claim 7, characterized in that: Before depositing the Si-doped porous GaN layer, the surface of the epitaxial layer material is subjected to a first high-temperature H2 gas treatment, before depositing the low-In component porous InGaN / GaN superlattice layer, the surface of the epitaxial layer material is subjected to a second high-temperature H2 gas treatment, and before depositing the high-In component porous InGaN / GaN superlattice layer, the surface of the epitaxial layer material is subjected to a third high-temperature H2 gas treatment; High temperature H2 gas treatment includes: Step 1: Under the conditions of a reaction chamber temperature of 920°C to 1200°C and a pressure of 50 torr to 500 torr, a mixture of H2 and N2 is introduced into the reaction chamber and maintained for 3s to 180s; Step 2: Stop introducing the H2 and N2 mixed gas; The steps 1 and 2 are repeated to complete the high temperature H2 gas treatment.

9. The method for preparing a light emitting diode epitaxial wafer according to claim 8, characterized in that: The processing time of the first high temperature H2 gas treatment ≥ the processing time of the second high temperature H2 gas treatment ≥ the processing time of the third high temperature H2 gas treatment; The H2 input flow rate of the first high temperature H2 gas treatment ≥ the H2 input flow rate of the second high temperature H2 gas treatment ≥ the H2 input flow rate of the third high temperature H2 gas treatment.

10. An LED, characterized in that: The LED comprises the light-emitting diode epitaxial wafer as described in any one of claims 1 to 6 or comprises a light-emitting diode epitaxial wafer prepared by the method for preparing a light-emitting diode epitaxial wafer as described in any one of claims 7 to 9.

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