An Intermediate Frequency Digital Omnidirectional Range Monitoring Method

Abstract

The present invention discloses an intermediate frequency digital omnidirectional beacon monitor and a monitoring method, which relates to the field of monitoring. The intermediate frequency digital omnidirectional beacon monitor includes: a band-pass filter, which is used to receive the radio frequency analog signal of the external field signal and mix it to the intermediate frequency through analog mixing. The beneficial effects of the present invention are as follows: First, the radio frequency analog signal of the external field signal is mixed to the intermediate frequency through analog mixing, and then band-pass filtering, attenuation, amplification, and low-pass filtering are performed in sequence. The DFT digital processing technology is used to collect data of the monitoring signal; the monitor digitizes the analog signal at the intermediate frequency, and then performs digital signal processing and analysis. Using the digital intermediate frequency technology, digital IQ demodulation is realized to calculate the signal; when calculating in the adjacent field, considering that the distances between the monitoring antenna and the antenna elements are different and the phase difference cannot be ignored, phase compensation needs to be performed on different elements, and then IQ demodulation is carried out, so that the modulation degree can be accurately calculated and the algorithm is simple.

Description

Technical Field

[0001] The present invention relates to the field of surveillance, and more particularly to a method for monitoring an intermediate frequency digital omnidirectional beacon. Background Art

[0002] Foreign devices for surveillance systems are implemented using a large number of analog circuits. Their adjacent field monitoring methods require adding hardware circuits, hardware interfaces, and data sampling, and need to change carrier antennas (adding circuits such as directional couplers), monitors (adding sampling circuits), sideband synchronization signals, etc. The algorithms are complex and need to be improved. Summary of the Invention

[0003] An object of the present invention is to provide a method for monitoring an intermediate frequency digital omnidirectional beacon to solve the problems raised in the above background art.

[0004] To achieve the above object, the present invention provides the following technical solutions:

[0005] An intermediate frequency digital omnidirectional beacon monitor, comprising:

[0006] A band-pass filter for receiving an external field signal radio frequency analog signal, mixing it to an intermediate frequency through analog mixing, intercepting non-intermediate frequency signals, and only allowing intermediate frequency signals (300 KHz to 3000 KHz) to be input;

[0007] An attenuation module for attenuating the input intermediate frequency signal and outputting it to an amplification module;

[0008] An amplification module for amplifying the attenuated intermediate frequency signal and outputting it so that the power of the attenuated and amplified intermediate frequency signal meets the measurement accuracy requirements of the A / D module;

[0009] A low-pass filter for filtering out interference signals existing in the attenuated and amplified intermediate frequency signal;

[0010] An analog switch module for controlling the connection or disconnection of the intermediate frequency signal transmission;

[0011] An A / D module for converting the intermediate frequency signal from an analog signal to a digital signal and transmitting it to an FPGA chip;

[0012] An FPGA chip for sampling the intermediate frequency signal at 64.5 M, and performing low-pass filtering, NCO digital phase-locked loop processing, and low-pass filtering on the data, finally reducing the sampling frequency to 120 kHz, reducing the frequency to 30 kHz, and communicating with an ARM chip;

[0013] An ARM chip for completing the monitoring data calculation of the intermediate frequency signal, controlling the transmitter to turn on and off, communicating with the upper computer, and completing the monitoring data warning and warning record;

[0014] The band-pass filter is connected to an attenuation module, the attenuation module is connected to an amplification module, the amplification module is connected to a low-pass filter, the low-pass filter is connected to an analog switch module, the analog switch module is connected to an A / D module through an operational amplifier circuit, the A / D module is connected to an FPGA chip, and the FPGA chip is connected to an ARM chip.

[0015] As a further solution of the present invention: The attenuation module includes chip N2, the model of chip N2 is HMC759, the 8th pin of chip N2 is connected to the band-pass filter through capacitor C10, and the 13th pin of chip N2 is connected to the amplification module.

[0016] As a further solution of the present invention: The amplification module includes chip N5, the model is GALI-74+, the 1st pin of chip N5 is connected to the attenuation module through capacitor C19, the 3rd pin of chip N5 is connected to capacitor C20 and inductor L4, the other end of capacitor C20 is connected to the low-pass filter, the other end of inductor L4 is connected to one end of resistor R12, the other end of resistor R12 is connected to one end of capacitor C16, one end of capacitor C17, one end of capacitor C18, and one end of inductor L3, the other end of capacitor C16 is grounded, the other end of capacitor C17 is grounded, the other end of capacitor C18 is grounded, and the other end of inductor L3 is connected to 5V voltage.

[0017] As a further solution of the present invention: The analog switch module includes a radio frequency switch circuit and a radio frequency transformer circuit.

[0018] The radio frequency switch circuit includes chips D4, D5, and D6. The model of chip D4 is HMC194A, and the models of chips D5 and D6 are 74LVC1G14DBVR. The 8th pin of chip D4 is connected to the low-pass filter through capacitor C65, the 5th pin of chip D4 is connected to the ARM chip through capacitor C67, the 4th pin of chip D4 is connected to the FPGA chip, the 1st pin of chip D4 is connected to the 2nd pin of chip D5, the 2nd pin of chip D4 is connected to the 4th pin of chip D6, and the 4th pin of chip D5 is connected to the 2nd pin of chip D6.

[0019] The radio frequency transformer circuit includes chip D9, the model of chip D9 is ADT1-1WT. The 1st pin of chip D9 is connected through capacitor C70, the other end of capacitor C70 is connected to one end of capacitor C66, the other end of capacitor C66 is connected to the 3rd pin of chip D4, the 4th pin of chip D9 is connected to one end of resistor R32, the 6th pin of chip D9 is connected to one end of resistor R30, the other end of resistor R32 is connected to one end of capacitor C72, the other end of resistor R30 is connected to the other end of capacitor C72, and a voltage signal is formed at capacitor C72 and output to the A / D module through an operational amplifier circuit.

[0020] As a further solution of the present invention: The A / D module includes a chip D12, the model of the chip D12 is AD9245BCP-80M. The 29th and 30th pins of the chip D12 are connected to the analog switch module through an operational amplifier circuit. The 5th, 6th, 7th, and 8th pins of the chip D12 are connected to the FPGA chip through an interface RN4. The 9th, 10th, 11th, and 12th pins of the chip D12 are connected to the FPGA chip through an interface RN3. The 13th, 14th, and 17th pins of the chip D12 are connected to the FPGA chip through an interface RN2. The 18th, 19th, 20th, and 21st pins of the chip D12 are connected to the FPGA chip through an interface RN1.

[0021] An intermediate frequency digitalized omnidirectional beacon monitoring method includes the following steps:

[0022] Step 1, the adjacent field monitoring algorithm calculates or measures the relative correction coefficient according to the relative position relationship between the receiving monitoring antenna and the sideband antenna; during the signal processing, the amplitude and phase correction coefficients of the upper and lower sidebands should be multiplied by the signals transmitted by each sideband antenna one by one to correct the path difference from each sideband antenna to the monitoring antenna in turn.

[0023] Step 2, after the adjacent field waveform is compensated, it is equivalent to the far field waveform, and then the modulation and demodulation algorithms are used to demodulate the waveform (the DVOR outer field monitoring antenna is built in the far field, and the received field pattern is the far field waveform; the outer field antenna is built in the adjacent field, and the received field pattern is the adjacent field waveform).

[0024] As a further solution of the present invention: In step 1, the moment of updating the correction coefficient is 1 / 4 cycle and 3 / 4 cycle after each sideband antenna is turned on, and the continuous implementation of the compensation coefficient can cover the maximum moment when each sideband antenna transmits a signal; the carrier signal is an AM signal with 30% amplitude modulation, the modulation period is 30Hz, and the waveform function of the carrier is as follows:

[0025] ; where is the carrier frequency;

[0026] The upper and lower sideband signals are cosine or sine square modulation, the modulation depth is 100%, and the frequency of the modulation signal is 720Hz; the amplitudes of the upper and lower sideband signals are 30% of the carrier signal, and the waveform functions of the upper and lower sidebands are as follows:

[0027] ;

[0028] ;

[0029] ;

[0030] ;

[0031] Wherein, 9960 Hz is the upper and lower sideband frequencies;

[0032] The upper and lower sideband signals and the carrier signal are synthesized into the total VOR signal in space according to the distance attenuation and amplitude delay;

[0033] For the simulation waveform of the far-field signal:

[0034] fup = 0.15.*sin(2*pi*30000*t+2*pi*9960*t);

[0035] fdown = 0.15.*sin(2*pi*30000*t-2*pi*9960*t);

[0036] For the simulation waveform of the near-field signal:

[0037] fup1 = power_up.*sin(2*pi*30000*t+2*pi*9960*t -deta_up);

[0038] fdown1 = power_down.*sin(2*pi*30000*t-2*pi*9960*t- deta_down);

[0039] Wherein, power_up is the amplitude of the upper sideband of the near field, power_down is the amplitude of the lower sideband of the near field; deta_up is the phase to be corrected for the upper sideband of the near field, and deta_up is the phase to be corrected for the lower sideband of the near field;

[0040] power_up, power_down, deta_up, and deta_down need to be compensated using the correction values;

[0041] Represents the field pattern of the odd antenna elements in the lower sideband, Represents the field pattern of the even antenna elements in the lower sideband, Represents the field pattern of the odd antenna elements in the upper sideband, Represents the field pattern of the even antenna elements in the upper sideband;

[0042] fup represents the field pattern of the upper sideband in the far field, fdown represents the field pattern of the lower sideband in the far field, fup1 represents the field pattern of the upper sideband in the near field, and fdown1 represents the field pattern of the lower sideband in the near field.

[0043] As a further solution of the present invention: Step 2 specifically includes:

[0044] Step 21, using the principle of digital mixing and orthogonal transformation, demodulate and filter the 9960 Hz signal to obtain the I-channel and Q-channel signals after demodulation of 9960 Hz;

[0045] Step 22, obtain the amplitude of the AM30 modulation wave, obtain the amplitude of the FM30 modulation wave, and obtain the amplitude of the carrier wave;

[0046] Step 23, use the DFT algorithm to obtain the real part and the imaginary part of the AM30 signal, and obtain the amplitude of the AM30 modulation wave;

[0047] Step 24, use the DFT algorithm to obtain the real part and the imaginary part of the FM30 signal, and obtain the amplitude of the FM30 modulation wave;

[0048] Step 25, obtain the angle of AM30, obtain the angle of FM30, and the azimuth angle is equal to the difference between the two;

[0049] Step 26, calculate the radio frequency level by summing the AM30 signals;

[0050] Step 27, calculate the AM30 modulation degree and the FM30 modulation degree. AM30 is a 30 Hz amplitude modulation signal, and FM30 is a 30 Hz phase modulation signal.

[0051] Compared with the prior art, the beneficial effects of the present invention are as follows: the present invention first mixes the radio frequency analog signal of the external field signal to the intermediate frequency through analog mixing, and then performs band-pass filtering, attenuation, amplification, and low-pass filtering in sequence to filter out high-frequency noise and ensure that the signal is within the measurable range, and uses the DFT digital processing technology to collect data of the monitoring signal;

[0052] The monitor digitizes the analog signal at the intermediate frequency, and then performs digital signal processing and analysis. Using digital intermediate frequency technology, it realizes digital IQ demodulation and calculates the signal;

[0053] When calculating in the adjacent field, considering that the distances between the monitoring antenna and the antenna elements are different and the phase difference cannot be ignored, it is necessary to perform phase compensation on different elements and then perform IQ demodulation, which can accurately calculate the modulation degree and the algorithm is simple. Description of the Drawings

[0054] Figure 1 It is a schematic diagram of an intermediate frequency digital omnidirectional beacon monitor.

[0055] Figure 2 It is the spectrum diagram before sampling the band-pass signal.

[0056] Figure 3 It is the spectrum diagram after sampling the band-pass signal.

[0057] Figure 4 It is the circuit diagram of the band-pass filter and the attenuation module.

[0058] Figure 5 It is the circuit diagram of the amplification module and the low-pass filter.

[0059] Figure 6 Circuit diagram of the RF switch circuit of the analog switch module.

[0060] Figure 7 Circuit diagram of the RF transformer circuit of the analog switch module.

[0061] Figure 8 Circuit diagram of the A / D module.

[0062] Figure 9 Timing diagram of the correction coefficient update iteration.

[0063] Figure 10 Diagram of the uncompensated overall envelope signal.

[0064] Figure 11 Diagram of the uncompensated envelope of the lower sideband signal component.

[0065] Figure 12 Diagram of the uncompensated envelope of the upper sideband signal component.

[0066] Figure 13 Diagram of the compensated overall envelope signal.

[0067] Figure 14 Diagram of the compensated envelope of the lower sideband signal component.

[0068] Figure 15 Diagram of the compensated envelope of the upper sideband signal component. Specific implementation mode

[0069] Next, the technical solutions in the embodiments of the present invention will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention.

[0070] Please refer to Figure 1 , an intermediate frequency digital omnidirectional beacon monitor, comprising:

[0071] A band-pass filter for receiving an external field signal RF analog signal, mixing it to an intermediate frequency through analog mixing, intercepting non-intermediate frequency signals, and only allowing intermediate frequency signals (300 KHz to 3000 KHz) to be input;

[0072] An attenuation module for attenuating the input intermediate frequency signal and outputting it to the amplification module;

[0073] An amplification module for amplifying the attenuated intermediate frequency signal and outputting it, so that the power of the intermediate frequency signal after attenuation and amplification meets the measurement accuracy requirements of the A / D module;

[0074] A low-pass filter for filtering out interference signals existing in the intermediate-frequency signal after attenuation and amplification;

[0075] An analog switch module for controlling the connection or disconnection of the intermediate-frequency signal transmission;

[0076] An A / D module for converting the intermediate-frequency signal from an analog signal to a digital signal and transmitting it to the FPGA chip;

[0077] An FPGA chip for sampling the intermediate-frequency signal at 64.5M, performing low-pass filtering, NCO digital phase-locked loop processing, and low-pass filtering on the data, finally reducing the sampling frequency to 120kHz, reducing the frequency to 30kHz, and communicating with the ARM chip;

[0078] An ARM chip for completing the monitoring data calculation of the intermediate-frequency signal, controlling the power-on and power-off of the transmitter, communicating with the upper computer, and completing the monitoring data warning and warning record;

[0079] The band-pass filter is connected to the attenuation module, the attenuation module is connected to the amplification module, the amplification module is connected to the low-pass filter, the low-pass filter is connected to the analog switch module, the analog switch module is connected to the A / D module through an operational amplifier circuit, the A / D module is connected to the FPGA chip, and the FPGA chip is connected to the ARM chip.

[0080] In a specific embodiment: The ARM+FPGA architecture is used to achieve intermediate-frequency digitization, taking advantage of the real-time processing of the FPGA and the computing power and data processing ability of the ARM chip.

[0081] Analysis of the filter selected for the RF link. In order to reduce the volume, the RF band-pass technology is adopted in this system;

[0082] Band-pass signal sampling theorem: For a band-pass signal with a center frequency of and a bandwidth of , denoting its upper and lower cut-off frequencies as and respectively, the necessary and sufficient condition for reconstructing the signal from the sampled values without distortion is that the sampling rate satisfies:

[0083] ;

[0084] where , , denotes the largest integer not greater than ;

[0085] The proof of the band-pass signal sampling theorem can be obtained from the frequency spectrum diagrams before and after signal sampling. Figure 2 is the band-pass signal The spectrum diagram before sampling, sampled at the sampling rate of , the spectrum of the sampled signal is the extension of the spectrum of the original signal with a period of , as shown in Figure 3 .

[0086] It can be seen from the above figure that what may be aliased with the original signal is the spectrum of the periodic extension of its mirror spectrum M1. On the low-frequency side of the original signal frequency band , the overlapping frequency band may be the upper sideband of the spectrum M2 of the mirror spectrum after secondary extension; on the high-frequency side , the overlapping frequency band may be the lower sideband of the spectrum M3 of the mirror spectrum after secondary extension.

[0087] In order not to have frequency band overlap, the sampling frequency should satisfy the following conditions:

[0088] ;

[0089] Rearranging the above formula gives:

[0090] ;

[0091] The sampling theorem for bandpass signals shows that for bandpass signals, sampling can be performed at a sampling rate much lower than twice the highest signal frequency. At the same time, it shows that the two concepts of "undersampling" and "oversampling" are not completely opposite. Generally speaking, for narrowband signals, if , it becomes "oversampling"; for bandpass signals, , it becomes "undersampling". Therefore, for narrowband bandpass signals, if , then relative to the carrier frequency, it is undersampled, and relative to the bandwidth, it is oversampled.

[0092] Bandpass sampling reduces the ADC sampling frequency, greatly reducing the requirements for ADC devices and digital signal processor devices, and by appropriately selecting the sampling frequency and intermediate frequency, it is possible to avoid mixing out-of-band harmonics and spurs into the band.

[0093] Please refer to Figure 4 . Therefore, a bandpass filter (chip N3, model BL-113A / U10-7C can be selected) is added before the AD sampling chip. The signal bandwidth is 108 MHz - 118 MHz, and the sampling frequency is selected as 64.5 MHz. According to the above analysis, its image interference frequencies are less than 85.5 MHz and greater than 140 MHz.

[0094] RF link power dynamic analysis. The monitoring antenna is 80 meters away, and the received signal is -16 dBm. When the device works in the near field, the signal is attenuated to below -10 dBm by a fixed attenuator, and the maximum amplitude of the AD-acquired signal is +3 dBm;

[0095] In order to ensure that the signal amplitude does not exceed the AD range when the signal enters the AD chip and to meet a certain quantization bit number, due to on-site factors such as the installation position and distance of the external field antenna being affected by the site conditions, the amplitude of the input signal will also change. Therefore, a power adjustment circuit is needed to adjust the power of the input signal so that the AD-acquired signal has a sampling accuracy of 12 bits.

[0096] The system adjusts the signal gain through an adjustable 31.25 dB attenuator and an amplifier with a fixed gain of 25 dB. The input signal can be adjusted to -16 dBm for AD digital processing. The effective bit number of the AD is about 12 bits, which can ensure the measurement accuracy and provide a digital dynamic range of 20 dB.

[0097] Analysis of the 1 dB compression point of the RF link. First, ensure that the input signal amplitude does not exceed -10 dBm by adding a fixed attenuator. Considering signal linear distortionlessness, the 1 dB compression point of the required device needs to be backed off by more than 6 dB. Therefore, the P1F of the link devices through which the signal passes needs to be more than 6 dB higher than the actual power.

[0098] In this embodiment: Please refer to Figure 4 , the attenuation module includes chip N2, the model of chip N2 is HMC759. The 8th pin of chip N2 is connected to the band-pass filter through capacitor C10, and the 13th pin of chip N2 is connected to the amplification module.

[0099] Select the HMC759 chip for the digital control attenuator: HMC759 is a digital step attenuator of ADI Corporation. The operating frequency range is (10~300M) Hz, which meets the frequency requirements. It steps from 0.25 dB LSB to 31.75 dB with a step accuracy of 0.25 dB. The P1F of this chip is 21 dBm, which meets the usage requirements.

[0100] In this embodiment: Please refer to Figure 5, the amplification module includes chip N5, with the model number GALI-74+. The 1st pin of chip N5 is connected to the attenuation module through capacitor C19. The 3rd pin of chip N5 is connected to capacitor C20 and inductor L4. The other end of capacitor C20 is connected to the low-pass filter. The other end of inductor L4 is connected to one end of resistor R12. The other end of resistor R12 is connected to one end of capacitor C16, one end of capacitor C17, one end of capacitor C18, and one end of inductor L3. The other end of capacitor C16 is grounded. The other end of capacitor C17 is grounded. The other end of capacitor C18 is grounded. The other end of inductor L3 is connected to the 5V voltage.

[0101] The amplifier selects GALI-74+. The P1F of this chip is 25dBm. The gain is 25dBm, and the operating frequency is 0 - 1GHz, meeting the usage requirements. Chip N4 is a low-pass filter.

[0102] In this embodiment: Please refer to Figure 6 and Figure 7 , the analog switch module includes a radio frequency switch circuit and a radio frequency voltage transformation circuit.

[0103] The radio frequency switch circuit includes chips D4, D5, and D6. The model of chip D4 is HMC194A. The models of chips D5 and D6 are 74LVC1G14DBVR. The 8th pin of chip D4 is connected to the low-pass filter through capacitor C65. The 5th pin of chip D4 is connected to the ARM chip through capacitor C67. The 4th pin of chip D4 is connected to the FPGA chip. The 1st pin of chip D4 is connected to the 2nd pin of chip D5. The 2nd pin of chip D4 is connected to the 4th pin of chip D6. The 4th pin of chip D5 is connected to the 2nd pin of chip D6.

[0104] The radio frequency voltage transformation circuit includes chip D9, with the model number ADT1-1WT. The 1st pin of chip D9 is connected through capacitor C70. The other end of capacitor C70 is connected to one end of capacitor C66. The other end of capacitor C66 is connected to the 3rd pin of chip D4. The 4th pin of chip D9 is connected to one end of resistor R32. The 6th pin of chip D9 is connected to one end of resistor R30. The other end of resistor R32 is connected to one end of capacitor C72. The other end of resistor R30 is connected to the other end of capacitor C72. A voltage signal is formed at capacitor C72 and is output to the A / D module through an operational amplifier circuit.

[0105] The HMC194A is a low-cost SPDT switch in an 8-pin MSOP package, suitable for applications that require high isolation performance between two RF (radio frequency signal) paths. This device can control signals in the DC to 3 GHz range and is optimized to provide extremely high isolation and minimum insertion loss required for medium- and low-power applications. The VOR signal frequency range is 108 MHz - 117.975 MHz, and the sine wave frequency of the ARM self-test signal is 10 MHz. The selection of this chip meets the usage requirements. The ADT1-1WT is an RF converter that converts single-ended to differential (converts the RF-TEDT signal to the A-VIN+ and A-VIN- signals), with a frequency range of 0.4 to 800 MHz, meeting the usage requirements.

[0106] In this embodiment: Please refer to Figure 8 , the A / D module includes chip D12, the model of chip D12 is AD9245BCP-80M. The 29th and 30th pins of chip D12 are connected to the analog switch module through an operational amplifier circuit. The 5th, 6th, 7th, and 8th pins of chip D12 are connected to the FPGA chip through interface RN4. The 9th, 10th, 11th, and 12th pins of chip D12 are connected to the FPGA chip through interface RN3. The 13th, 14th, and 17th pins of chip D12 are connected to the FPGA chip through interface RN2. The 18th, 19th, 20th, and 21st pins of chip D12 are connected to the FPGA chip through interface RN1.

[0107] Select one of the self-test signal and the RF detection signal for A / D conversion, which is read and processed by the FPGA chip. The analog signal enters the A / D module for sampling through the multiplexer. The chip used in the A / D module is AD9245BCP-80M, which is a single-chip, 14-bit, 20MSPS / 40MSPS / 65MSPS / 80MSPS analog-to-digital converter. It is powered by a 3V single power supply and has a built-in high-performance sample-and-hold amplifier (SHA) and reference power supply. It adopts a multi-stage differential pipelined architecture and built-in output error correction logic, which can provide 14-bit accuracy, meet the sampling accuracy requirement of 12 bits, and ensure no missing codes within the entire operating temperature range. The OTR output bit can indicate signals exceeding the specified input range. It meets the sampling accuracy of 64.5 MHz of the system.

[0108] The power supply circuit, CAN communication circuit, RS232 communication circuit, operational amplifier circuit, buzzer circuit, FRAM storage circuit, reset circuit, temperature-compensated crystal oscillator circuit, etc. of the intermediate frequency digitalized VOR monitor are all conventional circuits and will not be elaborated here.

[0109] The ARM chip completes functions such as monitoring data calculation, controlling the transmitter to turn on and off, and communicating with the host computer, and also completes monitoring data warning and warning record. The ARM chip selects a domestic ARM chip, which uses a Cortex™-M4 processor and meets the usage requirements.

[0110] The FPGA chip samples the radio frequency signal at 64.5M, and performs low-pass filtering, NCO digital phase-locked loop processing, and low-pass filtering on the data. Finally, the sampling frequency is reduced to 120kHz, and the frequency is reduced to 30kHz.

[0111] The domestic chip JFM7K325T device is selected for the FPGA. It has 326k logic units. Through simulation calculation, the usage rate is within 60%, meeting the usage requirements.

[0112] An intermediate frequency digital omnidirectional beacon monitoring method includes the following steps:

[0113] Step 1, the adjacent field monitoring algorithm calculates or measures the relative correction coefficient based on the relative position relationship between the receiving monitoring antenna and the sideband antenna; during the signal processing, the amplitude and phase correction coefficients of the upper and lower sidebands need to be multiplied by the signals emitted by each sideband antenna one by one to correct the path difference from each sideband antenna to the monitoring antenna in turn.

[0114] Step 2, after the adjacent field waveform is compensated, it is equivalent to the far field waveform, and then the modulation and demodulation algorithms are used to demodulate the waveform (the DVOR outer field monitoring antenna is built in the far field, and the received field pattern is the far field waveform; the outer field antenna is built in the adjacent field, and the received field pattern is the adjacent field waveform).

[0115] In this embodiment: Please refer to Figure 9 , in Step 1, the update timing of the correction coefficient is as Figure 9 shown, and the update moments are the 1 / 4 cycle and 3 / 4 cycle after each sideband antenna is turned on. The update moments of the correction coefficient are the 1 / 4 cycle and 3 / 4 cycle after each sideband antenna is turned on, and the continuous implementation of the compensation coefficient can cover the maximum moment when each sideband antenna emits a signal; the carrier signal is an AM signal with 30% amplitude modulation, the modulation period is 30Hz, and the waveform function of the carrier is as follows:

[0116] ; where is the carrier frequency;

[0117] The upper and lower sideband signals are cosine or sine square modulated, the modulation depth is 100%, and the frequency of the modulation signal is 720Hz; the amplitudes of the upper and lower sideband signals are 30% of the carrier signal, and the waveform functions of the upper and lower sidebands are as follows:

[0118] ;

[0119] ;

[0120] ;

[0121] ;

[0122] where 9960 Hz is the upper and lower sideband frequencies;

[0123] The upper and lower sideband signals and the carrier signal are combined in space according to distance attenuation and amplitude delay to form the total VOR signal;

[0124] For the far-field signal simulation waveform:

[0125] fup = 0.15.*sin(2*pi*30000*t + 2*pi*9960*t);

[0126] fdown = 0.15.*sin(2*pi*30000*t - 2*pi*9960*t);

[0127] For the near-field signal simulation waveform:

[0128] fup1 = power_up.*sin(2*pi*30000*t + 2*pi*9960*t - deta_up);

[0129] fdown1 = power_down.*sin(2*pi*30000*t - 2*pi*9960*t - deta_down);

[0130] where power_up is the amplitude of the upper sideband in the near field, power_down is the amplitude of the lower sideband in the near field; deta_up is the phase to be corrected for the upper sideband in the near field, deta_up is the phase to be corrected for the lower sideband in the near field;

[0131] power_up, power_down, deta_up, deta_down need to be compensated using the correction values;

[0132] represents the field pattern of the odd antenna elements in the lower sideband, represents the field pattern of the even antenna elements in the lower sideband, represents the field pattern of the odd antenna elements in the upper sideband, represents the field pattern of the even antenna elements in the upper sideband;

[0133] fup represents the far-field upper sideband field pattern, fdown represents the far-field lower sideband field pattern, fup1 represents the near-field upper sideband field pattern, and fdown1 represents the near-field lower sideband field pattern.

[0134] The overall before compensation includes the signal, the lower sideband signal, the upper sideband signal as Figure 10 , Figure 11 , Figure 12As shown, the amplitudes and phases of the upper and lower sideband signals are compensated respectively. The compensated upper and lower sideband signals are superimposed on the carrier signal, and then output after taking the modulus. The overall envelope signal, the lower sideband signal, and the upper sideband signal after compensation are as Figure 13 , Figure 14 , Figure 15 shown. It can be seen that the envelope signal after compensation is consistent with the far-field waveform. The modulation degrees of 30 Hz and 9960 Hz are calculated by using intermediate frequency digitization technology and IQ demodulation technology.

[0135] In this embodiment: Step 2 specifically includes:

[0136] Step 21, using the principle of digital mixing orthogonal transformation, demodulating and filtering the 9960 Hz signal to obtain the I-channel and Q-channel signals after demodulating the 9960 Hz signal;

[0137] Step 22, obtaining the amplitude of the AM30 modulation wave, obtaining the amplitude of the FM30 modulation wave, and obtaining the amplitude of the carrier;

[0138] Step 23, using the DFT algorithm to obtain the real part and the imaginary part of the AM30 signal, and obtaining the amplitude of the modulation wave of AM30;

[0139] Step 24, using the DFT algorithm to obtain the real part and the imaginary part of the FM30 signal, and obtaining the amplitude of the modulation wave of FM30;

[0140] Step 25, obtaining the angle of AM30, obtaining the angle of FM30, and the azimuth angle is equal to the difference between the two;

[0141] Step 26, using the summation of the AM30 signal to calculate the RF level;

[0142] Step 27, calculating the modulation degree of AM30 and the modulation degree of FM30. AM30 is a 30 Hz amplitude modulation signal, and FM30 is a 30 Hz phase modulation signal.

[0143] In the present invention, the RF analog signal of the external field signal is first mixed to the intermediate frequency through analog mixing, and then band-pass filtering, attenuation, amplification, and low-pass filtering are sequentially performed to filter out high-frequency noise and ensure that the signal is within the measurable range. The DFT digital processing technology is used to collect data of the monitoring signal;

[0144] The monitor digitizes the analog signal at the intermediate frequency, and then performs digital signal processing and analysis. Using digital intermediate frequency technology, digital IQ demodulation is realized, and the signal is solved;

[0145] When calculating in the adjacent field, considering that the distances between the monitoring antenna and the antenna elements are different and the phase difference cannot be ignored, phase compensation needs to be performed on different elements, and then IQ demodulation is performed to accurately calculate the modulation degree.

[0146] Calculations are performed without compensating the signal during adjacent field monitoring, and the change in modulation index cannot be promptly reflected when the azimuth information changes. After signal compensation, the modulation index information can be promptly fed back.

[0147] For those skilled in the art, it is obvious that the present invention is not limited to the details of the above-described exemplary embodiments, and the present invention can be implemented in other specific forms without departing from the spirit or basic characteristics of the present invention. Therefore, in any aspect, the embodiments should be regarded as exemplary and non-restrictive.

[0148] In addition, it should be understood that although this specification is described according to the embodiments, not every embodiment only contains an independent technical solution. This narrative way of the specification is only for clarity. Those skilled in the art should regard the specification as a whole, and the technical solutions in each embodiment can also be appropriately combined to form other embodiments that can be understood by those skilled in the art.

Claims

1. A method for monitoring an intermediate frequency digital omnidirectional range, characterized in that, The intermediate frequency digital omnidirectional beacon monitoring method includes the following steps: Step 1, the adjacent field monitoring algorithm calculates or measures the relative correction coefficient according to the relative position relationship between the receiving monitoring antenna and the sideband antenna; during the signal processing, the amplitude-phase correction coefficients of the upper and lower sidebands should be multiplied by the signals transmitted by each sideband antenna one by one to correct the path difference from each sideband antenna to the monitoring antenna in turn; Step 2, after the adjacent field waveform is compensated, it is equivalent to the far field waveform, and then the modulation and demodulation algorithms are used to demodulate the waveform; In Step 1, the update time of the correction coefficient is 1 / 4 cycle and 3 / 4 cycle after each sideband antenna is turned on, and the continuous implementation of the compensation coefficient can cover the maximum moment of the signal transmitted by each sideband antenna; the carrier signal is an AM signal with 30% amplitude modulation, the modulation period is 30 Hz, and the waveform function of the carrier is as follows: ; wherein, is the carrier frequency; The upper and lower sideband signals are cosine or sine square modulation, the modulation depth is 100%, and the frequency of the modulation signal is 720 Hz; the amplitudes of the upper and lower sideband signals are 30% of the carrier signal, and the waveform functions of the upper and lower sidebands are as follows: ； ； ； ； In the formula, 9960 Hz is the upper and lower sideband frequencies; The upper and lower sideband signals and the carrier signal are synthesized into the total VOR signal in space according to the distance attenuation and amplitude delay; For the far field signal simulation waveform: fup = 0.15.*sin(2*pi*30000*t+2*pi*9960*t); fdown = 0.15.*sin(2*pi*30000*t-2*pi*9960*t); For the adjacent field signal simulation waveform: fup1 = power_up.*sin(2*pi*30000*t+2*pi*9960*t -deta_up); fdown1 = power_down.*sin(2*pi*30000*t-2*pi*9960*t- deta_down); Among them, power_up is the amplitude of the upper sideband of the adjacent field, power_down is the amplitude of the lower sideband of the adjacent field; deta_up is the phase to be corrected for the upper sideband of the adjacent field, and deta_up is the phase to be corrected for the lower sideband of the adjacent field; power_up, power_down, deta_up, deta_down need to be compensated using the correction values; Indicates the field pattern of the odd antenna element in the lower sideband, Indicates the field pattern of the even antenna element in the lower sideband, Indicates the field pattern of the odd antenna element in the upper sideband, Indicates the field pattern of the even antenna element in the upper sideband; fup represents the far field upper sideband field pattern, fdown represents the far field lower sideband field pattern, fup1 represents the adjacent field upper sideband field pattern, and fdown1 represents the adjacent field lower sideband field pattern.

2. The intermediate frequency digital omnidirectional beacon monitoring method according to claim 1, characterized in that, Step 2 specifically includes: Step 21, using the principle of digital mixing orthogonal transformation, demodulate and filter the 9960 Hz signal to obtain the I-channel and Q-channel signals after demodulation of 9960 Hz; Step 22, obtain the amplitude of the AM30 modulation wave, obtain the amplitude of the FM30 modulation wave, and obtain the amplitude of the carrier; Step 23, use the DFT algorithm to obtain the real and imaginary parts of the AM30 signal and obtain the amplitude of the modulation wave of AM30; Step 24, use the DFT algorithm to obtain the real and imaginary parts of the FM30 signal and obtain the amplitude of the modulation wave of FM30; Step 25, obtain the angle of AM30, obtain the angle of FM30, and the azimuth angle is equal to the difference between the two; Step 26, calculate the RF level by summing the AM30 signals; Step 27, calculate the modulation index of AM30 and FM30. AM30 is a 30 Hz amplitude modulation signal, and FM30 is a 30 Hz phase modulation signal.

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