A time synchronization method, apparatus and system

Abstract

The present application discloses a time synchronization method, apparatus and system, which solves the problem that the prior art cannot support locking more TSN devices. A time synchronization method for a generalized clock synchronization protocol includes the steps of: determining the node with the largest closeness centrality in the link as the best master clock; the closeness centrality is the reciprocal of the sum of the shortest path lengths from a certain node to other nodes; the best master clock synchronizes time with each node in the link through messages. The present application is responsible for GM election and clock failure detection, replacing the traditional mechanism that relies on Announce messages, so that nodes in the network do not need to send and interact with Announce messages and can synchronize more TSN devices.

Description

Technical Field

[0001] This application relates to the field of communication technologies, and in particular, to a time synchronization method, apparatus, and system. Background Art

[0002] Time-Sensitive Networking (TSN) is a set of IEEE 802.1 standards designed to provide deterministic services by enhancing Ethernet. Many mechanisms in TSN are based on time synchronization, and the implementation of these mechanisms depends on the support of the generalized precision time protocol (gPTP). TSN uses gPTP to ensure that the clocks of all devices in the network are synchronized, so as to ensure that the end-to-end delay and jitter of data streams are within a predictable range, which is crucial for those application scenarios that require high real-time performance and low latency. gPTP usually uses the Best Master Clock algorithm (BMCA) to determine the Best Master Clock (GM) node. Nodes exchange GM selection information by sending Announce messages, and determine the master clock in the system by comparing the message content. Moreover, gPTP stipulates the use of the Peer-to-Peer delay measurement method, uses Sync, Pdelay_Req, and Pdelay_Resp messages to measure the link delay, and uses the correctionField field in the Follow_UP message to correct the offset. Finally, the global clock achieves precise time synchronization at the sub-microsecond level, and reduces the frequency ratio between adjacent two nodes (Neighbor Rate Ratio, NRR) to within ±0.1ppm specified by the standard, realizing high-precision frequency synchronization. The gPTP time synchronization process is as Figure 1 shown. After synchronization is completed, nodes still periodically exchange messages. When the network topology changes, the Pdelay message can quickly obtain the new path delay, the Announce message can re-elect the GM, and the Sync and Pdelay messages continue to correct the clocks of each node and the GM.

[0003] The gPTP standard stipulates that TSN nodes need to maintain high precision within 7 hops, with a maximum clock deviation not exceeding 1 microsecond. However, the standard does not specify time synchronization for more than 7 hops because the synchronization accuracy will decrease significantly after more than 7 hops, and it is difficult to lock the clock when there are too many hops. For example, in a highway camera monitoring system, multiple cameras usually work in series, forming a network architecture with more than 7 hops. In this environment, accurate time synchronization of each camera can ensure that events are recorded and analyzed in a timely and accurate manner; in a multi-hop communication environment of smart grids, precise time synchronization can ensure coordinated operations between power equipment, reduce losses during power transmission, and improve the operating efficiency and security of the power grid. In addition, in the existing gPTP synchronization and delay measurement mechanisms, the message types and the transmission frequencies of each message are usually fixed and cannot be adaptively adjusted and optimized according to the time synchronization situation in the network. This results in difficulties in ensuring the accuracy and stability of time synchronization when the network load changes greatly, leading to problems such as excessive system clock deviation and inability to lock. Summary of the Invention

[0004] The embodiments of the present application provide a time synchronization method, device, and system, which solve the problem that the prior art cannot support synchronizing more TSN devices.

[0005] In a first aspect, the embodiments of the present application provide a time synchronization method for the generalized clock synchronization protocol, including the steps of:

[0006] Determine the node with the largest closeness centrality in the link as the best master clock; the closeness centrality is the reciprocal of the sum of the shortest path lengths from a certain node to other nodes;

[0007] The best master clock synchronizes time with each node in the link through messages.

[0008] In one embodiment, determining the transmission frequency of each node for time synchronization includes the steps of:

[0009] Collect historical data on clock synchronization lock time, time synchronization accuracy, and frequency synchronization accuracy under different network topologies;

[0010] Establish a machine learning model through the historical data to predict the best message transmission frequency for different network states;

[0011] Determine the best master clock and select the corresponding best message transmission frequency according to the current network state.

[0012] Furthermore, it further includes the steps of:

[0013] In response to a change in the topological relationship, add new network state data to the historical data set and retrain the machine learning model.

[0014] In one embodiment, it further includes the steps of:

[0015] Set the message acceleration factor n;

[0016] In response to at least one of the clock locking time, time synchronization accuracy, and frequency synchronization accuracy in the network exceeding a set threshold, set the message sending frequency to (1 + k × n) times the original frequency; where k starts from 1 and steps by 1 until the clock synchronization locking time, time synchronization accuracy, and frequency synchronization accuracy all do not exceed the set threshold.

[0017] In one embodiment, it further includes the steps of:

[0018] In response to a topology change, re-determine the best master clock.

[0019] In one embodiment, time synchronization is performed, specifically including the steps of:

[0020] Each node in the link performs message interaction to measure the initial link delay;

[0021] The best master clock performs periodic message interaction with each node in the link.

[0022] In a second aspect, an embodiment of the present application further provides a time synchronization device for implementing the time synchronization method described in any one of the embodiments of the first aspect, including: a determination module for determining the best master clock; a monitoring module for monitoring the synchronization situation in the network.

[0023] In a third aspect, an embodiment of the present application further provides a time synchronization system, including the time synchronization device described in the embodiment of the second aspect; it further includes terminal devices, and each terminal device corresponds to a network node.

[0024] In a fourth aspect, an embodiment of the present application further provides a computer-readable storage medium, on which a computer program is stored, and when the program is executed by a processor, it implements the method described in any one of the embodiments in the first aspect.

[0025] In a fifth aspect, an embodiment of the present application further provides an electronic device, including a memory, a processor, and a computer program stored on the memory and executable on the processor. When the processor executes the computer program, it implements the method described in any one of the embodiments in the first aspect.

[0026] The above at least one technical solution adopted in the embodiments of the present application can achieve the following beneficial effects:

[0027] This application is responsible for GM election and clock failure detection, replacing the traditional mechanism that relies on Announce messages. As a result, nodes in the network do not need to send and interact with Announce messages, and can lock more TSN devices. During the clock election phase before synchronization, the Centralized Network Controller (CNC) selects the tight central node as the GM node. By designating the node with the fewest hops to other nodes in the network as the GM, the maximum number of hops for sync message transmission is reduced, avoiding the limitations of the traditional BMCA algorithm. During the synchronization process, the Centralized Network Controller (CNC) monitors the network topology in real time, recalculates the tight centrality of each node when the topology changes, and re-designates the GM node to ensure the stability of synchronization and the selection of the optimal GM.

[0028] This application dynamically adjusts the transmission frequencies of Sync and Pdelay_Req messages by setting clock synchronization lock time thresholds, time synchronization accuracy thresholds, and frequency synchronization accuracy thresholds, improving the clock synchronization lock speed and synchronization accuracy, enabling it to synchronize more hop devices and perform self-adjustment of configurations according to the number of hops.

[0029] This application introduces a machine learning algorithm, trains a model using historical data, predicts the optimal transmission frequency strategy when the network topology changes, thereby optimizing the initial configuration and the parameter adjustment process during topology changes, and accelerating the efficiency and speed of configuration adjustment. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] The drawings described herein are used to provide a further understanding of the present application, and constitute a part of the present application. The illustrative embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation to the present application. In the drawings:

[0031] Figure 1 is a flowchart of a time synchronization method according to an embodiment of the present application;

[0032] Figure 2 is a flowchart of determining the transmission frequency according to an embodiment of the present application;

[0033] Figure 3 is a flowchart of message acceleration accuracy correction according to an embodiment of the present application;

[0034] Figure 4 is a structural diagram of a time synchronization device according to an embodiment of the present application;

[0035] Figure 5 The embodiment of the present application also provides a schematic structural diagram of a time synchronization system;

[0036] Figure 6 is a schematic structural diagram of an electronic device provided by an embodiment of the present application. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0037] To make the objectives, technical solutions, and advantages of this application clearer, the following will clearly and completely describe the technical solutions of this application in conjunction with specific embodiments of this application and the corresponding drawings. Obviously, the described embodiments are only a part of the embodiments of this application, rather than all of the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments in this application without creative efforts belong to the scope of protection of this application.

[0038] The following will, in conjunction with the drawings, elaborate on the technical solutions provided by each embodiment of this application.

[0039] Figure 1 This is a flowchart of a time synchronization method for an embodiment of this application, which is used for the generalized clock synchronization protocol and includes steps: 110 to 120.

[0040] Step 110: Determine the node with the maximum closeness centrality in the link as the best master clock; the closeness centrality is the reciprocal of the sum of the shortest path lengths from a certain node to other nodes.

[0041] For example, in the election stage of the best master clock (hereinafter referred to as GM) before time synchronization, this application uses a centralized network controller (CNC) to coordinate and control the GM election process, and designates the node with the highest closeness centrality in the link as the GM to replace the traditional election that relies on Announce messages. The closeness centrality reflects the position of a node in the network. A node with a high closeness centrality means that the average distance between this node and other nodes in the network is shorter, that is, this node is more central. The specific calculation steps are as follows:

[0042] Establish the current network topology in the form of a network graph G(V, E), where V is the set of nodes and E is the set of edges, and the graph is an undirected graph.

[0043] For each node u, use a shortest path algorithm (such as the Floyd-Warshall, Dijkstra algorithm, etc.) to calculate the shortest path length d(u, v) from node u to all other nodes v.

[0044] For each node u, calculate its closeness centrality C(u).

[0045]

[0046] Among them, d(u, v) represents the shortest path length from node u to node v, and the closeness centrality C(u) is defined as the reciprocal of the sum of the shortest path lengths from node u to all other nodes.

[0047] Find the node with the maximum closeness centrality C(u), which is the node with the fewest hops to other nodes in the network, also known as the close central node.

[0048] After determining the GM, the Centralized Network Controller (CNC) determines the packet transmission frequencies for pre-configuring each node according to the current network status.

[0049] Step 120: The Best Master Clock synchronizes time with each node in the link through messages.

[0050] In one embodiment, step 120 for time synchronization specifically includes the steps of:

[0051] Each node in the link performs message interaction to measure the initial link delay;

[0052] Enable the time synchronization function of all TSN nodes. Each node will first perform the interaction of Pdelay_Req and Pdelay_Resp messages to measure the initial link delay.

[0053] The Best Master Clock performs periodic message interaction with each node in the link.

[0054] Then the designated GM starts to periodically perform the interaction of Sync, Follow_Up, Pdelay_Req, Pdelay_Resp, and Pdelay_Resp_Follow_Up messages with other nodes in the network.

[0055] During the time synchronization process, the Centralized Network Controller (CNC) continuously monitors the synchronization situation in the network.

[0056] Figure 2 This is the flowchart for determining the packet transmission frequency in the embodiment of the present application.

[0057] In one embodiment, determining the packet transmission frequencies for each node to perform time synchronization includes the steps: 210 to 240.

[0058] Step 210: Collect historical data on clock synchronization locking time, time synchronization accuracy, and frequency synchronization accuracy under different network topologies;

[0059] Before starting time synchronization, the Centralized Network Controller (CNC) collects historical data on clock synchronization locking time, time synchronization accuracy, and frequency synchronization accuracy under different network topologies.

[0060] The clock synchronization locking refers to that the devices in the network successfully find the correct GM and synchronize with the GM.

[0061] When a device reaches the synchronization lock state, it indicates that it has started interacting with the correct GM for synchronization messages and can maintain accurate timekeeping internally. This state usually requires a period of stable convergence. During this process, the device continuously receives synchronization information and adjusts its internal clock until the time error between it and the GM is reduced to an acceptable range. The stage from finding the correct GM to completing the stable convergence is called clock synchronization lock, and the clock synchronization lock time threshold is the time required to complete this entire process. It usually takes several seconds for the entire network to reach the lock state.

[0062] The time synchronization accuracy refers to the accuracy of time synchronization between the clocks of each device in the network and the GM, that is, after stable convergence, the difference between the converged time and the GM time. This error is measured in nanoseconds and microseconds.

[0063] The frequency synchronization accuracy, that is, NRR (Neighbor Rate Ratio), represents the accuracy of frequency synchronization between adjacent devices. NRR is used to describe the clock frequency ratio between adjacent devices to ensure that the clock frequency of the device is consistent with that of the GM. The frequency synchronization accuracy is usually expressed in ppm (parts per million). The higher the frequency synchronization, the smaller the frequency difference between devices, ensuring the synchronization stability during long-term operation.

[0064] Step 220: Establish a machine learning model through the historical data to predict the optimal packet sending frequency for different network states;

[0065] Use this data to train machine learning models, such as neural networks, decision trees, or support vector machines, etc., to predict the optimal packet sending frequencies of Sync and Pdelay_Req messages in different network states.

[0066] Step 230: Determine the optimal master clock and select the corresponding optimal packet sending frequency according to the current network state.

[0067] After determining the GM, the centralized network controller (CNC) pre-configures the packet sending frequencies of each node according to the current network state and the prediction results of the model.

[0068] For example, according to the model prediction, the initial configuration of the existing network topology may be: Sync: 10 per second, Pdelay_Req: 2 per second.

[0069] Furthermore, it further includes the step:

[0070] Step 240: In response to the change in the topology relationship, add the new network state data to the historical data set and retrain the machine learning model.

[0071] Each node continuously exchanges and synchronizes messages to maintain time synchronization of the existing network topology under the existing locking conditions and accuracy. During the synchronization process, the Central Network Controller (CNC) replaces the clock failure detection function of the Announce message by monitoring the network topology nodes in real time.

[0072] If the Central Network Controller (CNC) detects topology changes such as node addition, departure, link failure, link recovery, etc., as well as GM clock failure, the Central Network Controller (CNC) re-performs the calculation of the tight centrality of all nodes. If the original GM node becomes a non-tight central node, the Central Network Controller (CNC) re-performs the election strategy and designates the node with the highest tight centrality in the current topology as the GM node. Moreover, the Central Network Controller (CNC) also adds the latest network state data to the historical data set and retrains the machine learning model with the updated data to ensure that the model can reflect the latest network state. According to the retrained model, the Central Network Controller (CNC) predicts the optimal packet sending frequency strategy for each node under the new network topology and reconfigures the sending frequencies of the Sync and Pdelay messages of each node according to the prediction results.

[0073] For example, if the optimal configuration predicted for a certain node under the new topology is: Sync: 12 per second, Pdelay_Req: 3 per second, then the Central Network Controller (CNC) will reissue this configuration to the node.

[0074] In one embodiment, it further includes the steps of:

[0075] In response to the topology change, re-determine the optimal master clock.

[0076] Figure 3 This is the flow chart for correcting the message acceleration accuracy in the embodiments of this application.

[0077] In one embodiment, it further includes the steps of:

[0078] Step 310: Set the message acceleration factor n;

[0079] Set the message acceleration factors n for Sync and Pdelay_Req messages.

[0080] Step 320: In response to at least one of the clock locking time, time synchronization accuracy, and frequency synchronization accuracy in the network exceeding the set threshold, set the message sending frequency to (1 + k × n) times the original frequency; where k starts from 1 and steps by 1 until the clock locking time, time synchronization accuracy, and frequency synchronization accuracy all do not exceed the set threshold.

[0081] For example, set the clock locking time threshold x (seconds), the time synchronization accuracy threshold y (nanoseconds), and the frequency synchronization accuracy threshold z (ppm).

[0082] If it is detected that the clock locking time in the network exceeds the threshold x, or the time synchronization accuracy exceeds the accuracy threshold y, or the frequency synchronization accuracy exceeds the threshold z, the centralized network controller (CNC) will set the packet sending frequencies of the Sync and Pdelay_Req messages of all nodes to (1 + k * n) times the original (k = 1, 2, 3..., representing the number of acceleration times).

[0083] After the configuration is sent down, the system will continue to lock the clock and correct the synchronization accuracy according to the accelerated packet sending frequencies. The Sync, Follow_Up, and Pdelay messages measure the link delay more frequently and correct the clock offset error, so as to achieve the effect of accelerating clock locking and improving synchronization accuracy.

[0084] At the same time, since the gPTP standard multiplexes the ratio of the time stamps of two ports in the same time interval for the sending and receiving time measurements of the Pdelay_Resp, accelerating the packet sending speed of the Pdelay_Req message will accelerate the measurement frequency of the Rdelay_Resp message, thereby reducing the time interval for NRR measurement and correction, and improving the frequency synchronization accuracy as well. If the corrected clock locking time is still greater than x, or the time synchronization accuracy is still greater than y, or the frequency synchronization accuracy is still greater than z, then increment k by 1 and continue to accelerate the packet sending frequencies of the Sync and Pdelay_Req messages until all three parameters are reduced below the thresholds.

[0085] This application proposes a multi-hop adaptive time synchronization method based on the gPTP protocol. By using the centralized network controller (CNC) defined in the IEEE802.1Qcc protocol to select the GM method to replace the traditional method that relies on Announce messages for GM election and clock failure detection mechanism, nodes in the network do not need to send and interact with Announce messages, and dynamically adjust the packet sending frequencies of the Sync and Pdelay_Req messages according to the network state, so as to achieve high-precision and fast-locking time synchronization in a network environment with more than 7 hops. To further improve the accuracy and efficiency of time synchronization configuration, the present invention also introduces a machine learning algorithm, trains a model using historical data, and predicts the packet sending frequency strategy when the network topology changes. In the initial configuration stage, the centralized network controller (CNC) selects the master clock GM and pre-configures the Sync and Pdelay_Req message frequencies according to the prediction results. When the network topology changes, re-configure the packet sending frequencies again according to the training results of the historical data.

[0086] Figure 4This is a structural diagram of a time synchronization device according to an embodiment of the present application, which is used to implement the time synchronization method described in any embodiment of the first aspect, and includes:

[0087] A determination module 11, configured to determine the best master clock.

[0088] A monitoring module 12, configured to monitor the synchronization status in the monitoring network.

[0089] The time synchronization device is a centralized controller defined by using the IEEE 802.1Qcc protocol.

[0090] Further, it further includes a receiving module 13, configured to receive historical data such as synchronization locking status, time synchronization accuracy, and frequency synchronization accuracy under different network topologies.

[0091] Further, it further includes an adjustment module 14, configured to adjust the packet sending frequency of the message.

[0092] Figure 5 An embodiment of the present application further provides a schematic structural diagram of a time synchronization system, which includes the time synchronization device described in the embodiment of the second aspect; it further includes terminal devices, and each terminal device corresponds to a network node.

[0093] Those skilled in the art should understand that the embodiments of the present invention can be provided as a method, a system, or a computer program product. Therefore, the present invention can take the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware aspects. Moreover, the present invention can take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk memory, CD-ROM, optical memory, etc.) containing computer-usable program code.

[0094] Therefore, the present application also proposes a computer-readable storage medium, on which a computer program is stored, and when the program is executed by a processor, it implements the method described in any embodiment of the present application.

[0095] Further, the present application also proposes an electronic device, including a memory, a processor, and a computer program stored on the memory and executable on the processor. When the processor executes the computer program, it implements the method described in any embodiment of the present application.

[0096] The present invention is described with reference to the flowcharts and / or block diagrams of methods, apparatuses (systems), and computer program products according to embodiments of the present invention. It should be understood that each flow and / or block in the flowchart and / or block diagram, and the combination of flows and / or blocks in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to the processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing devices to generate a machine, such that the instructions executed by the processor of the computer or other programmable data processing devices generate means for implementing the functions specified in one process Figure 1 one process or multiple processes and / or blocks Figure 1 or means for implementing the functions specified in one block or multiple blocks.

[0097] These computer program instructions can also be stored in a computer-readable memory capable of guiding a computer or other programmable data processing devices to work in a specific manner, such that the instructions stored in the computer-readable memory generate a manufactured article including instruction means, and the instruction means implement the functions specified in one process Figure 1 one process or multiple processes and / or blocks Figure 1 or means for implementing the functions specified in one block or multiple blocks.

[0098] These computer program instructions can also be loaded onto a computer or other programmable data processing devices, such that a series of operation steps are executed on the computer or other programmable devices to generate a computer-implemented process, and thus the instructions executed on the computer or other programmable devices provide steps for implementing the functions specified in one process Figure 1 one process or multiple processes and / or blocks Figure 1 or means for implementing the functions specified in one block or multiple blocks.

[0099] In a typical configuration, a computing device includes one or more processors (CPUs), an input / output interface, a network interface, and a memory. The memory may include non-permanent memory in the form of computer-readable media, random access memory (RAM), and / or non-volatile memory, such as read-only memory (ROM) or flash memory (flash RAM). The memory is an example of computer-readable media.

[0100] Figure 6 is a schematic structural diagram of an electronic device provided by an embodiment of the present application. The displayed electronic device 600 is only an example and should not impose any limitation on the functions and usage scope of the embodiments of the present application. It includes: one or more processors 620; a storage device 610 for storing one or more programs, and when the one or more programs are run by the one or more processors 620, the one or more processors 620 implement the time synchronization method provided by the embodiments of the present application. The method includes:

[0101] Determine the node with the maximum closeness centrality in the link as the best master clock; the closeness centrality is the reciprocal of the sum of the shortest path lengths from a certain node to other nodes.

[0102] The best master clock synchronizes time with each node in the link through messages.

[0103] The electronic device 600 further includes an input device 630 and an output device 640; the processor 620, the storage device 610, the input device 630, and the output device 640 in the electronic device can be connected through a bus or other means, and in the figure, it is taken as an example of being connected through the bus 650.

[0104] The storage device 610, as a computer-readable storage medium, can be used to store software programs, computer-executable programs, and module units, such as the program instructions corresponding to the method for determining the cloud base height in the embodiments of the present application. The storage device 610 mainly includes a program storage area and a data storage area. Among them, the program storage area can store an operating system and application programs required for at least one function; the data storage area can store data created according to the use of the terminal, etc. In addition, the storage device 610 can include a high-speed random access memory, and can also include a non-volatile memory, such as at least one magnetic disk storage device, a flash memory device, or other non-volatile solid-state storage devices. In some instances, the storage device 610 can further include a memory remotely set relative to the processor 620, and these remote memories can be connected through a network. Examples of the above network include but are not limited to the Internet, an enterprise internal network, a local area network, a mobile communication network, and combinations thereof.

[0105] The input device 630 can be used to receive input digital, character information, or voice information, and generate key signal inputs related to the user settings and function control of the electronic device. The output device 640 can include electronic devices such as a display screen and a speaker.

[0106] It should also be noted that the term "including", "comprising", or any other variant thereof is intended to cover non-exclusive inclusion, so that a process, method, commodity, or device including a series of elements not only includes those elements, but also includes other elements not explicitly listed, or further includes elements inherent to such process, method, commodity, or device. Without further limitations, the element defined by the statement "including one..." does not exclude the existence of additional identical elements in the process, method, commodity, or device including the said element.

[0107] The above are only the embodiments of the present application and are not used to limit the present application. For those skilled in the art, the present application can have various changes and modifications. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included within the scope of the claims of the present application.

Claims

1. A time synchronization method for a generalized clock synchronization protocol, characterized in that: Includes steps: Determine the node with the largest close centrality in the link as the best master clock; the close centrality is the reciprocal of the sum of the shortest path lengths from a node to other nodes; Select the corresponding optimal packet sending frequency according to the current network status; Selecting the best packet sending frequency includes the following steps: Set the message acceleration factor n; In response to at least one of the clock synchronization lock time, time synchronization accuracy and frequency synchronization accuracy in the network exceeding a set threshold, the message packet sending frequency is set to (1+k×n) times the original frequency; where k starts from 1 and is incremented by 1 until the clock lock time, time synchronization accuracy and frequency synchronization accuracy do not exceed the set threshold; The best master clock synchronizes time with each node in the link through messages.

2. The time synchronization method according to claim 1, characterized in that: Determine the packet sending frequency of each node for time synchronization, including the following steps: Collect historical data on clock synchronization lock time, time synchronization accuracy, and frequency synchronization accuracy under different network topologies; A machine learning model is established through the historical data to predict the optimal packet sending frequency for different network states.

3. The time synchronization method according to claim 1, characterized in that: During the time synchronization process, the Centralized Network Controller (CNC) continuously monitors the network synchronization.

4. The time synchronization method according to claim 1, characterized in that: Also includes the steps: In response to topology changes, the best master clock is re-determined.

5. The time synchronization method according to claim 1, characterized in that: Time synchronization includes the following steps: Each node in the link exchanges messages and measures the initial link delay; The best master clock exchanges periodic messages with each node in the link.

6. The time synchronization method according to claim 2, characterized in that: Also includes the steps: In response to changes in topological relationships, new network status data is added to the historical data set and the machine learning model is retrained.

7. A time synchronization device, characterized in that: The method for implementing the time synchronization described in any one of claims 1 to 6 comprises: A determination module, used for determining the best master clock; The monitoring module is used to monitor the synchronization status in the network.

8. A time synchronization system, characterized in that: Comprising the time synchronization device as claimed in claim 7; It also includes terminal devices, each of which corresponds to a network node.

9. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the program is executed by a processor, the method according to any one of claims 1 to 6 is implemented.

10. An electronic device comprising a memory, a processor and a computer program stored in the memory and executable on the processor, characterized in that: When the processor executes the computer program, the method according to any one of claims 1 to 6 is implemented.

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