A high dynamic range CMOS image sensor and a control method thereof

Abstract

This application discloses a high dynamic range CMOS image sensor and its control method. The image sensor circuit includes a pixel circuit array, a row control circuit, and a quantization circuit. The method includes: acquiring a row control signal; performing exposure and readout processing on the current row pixels using the row control signal to obtain the dynamic electrical signal of the current row pixels; performing quantization processing on the current row pixels based on the dynamic electrical signal of the current row pixels to output a digital code containing brightness information; shifting all shift registers in the row control circuit based on the highest bit of the digital code to obtain a shifted row control signal for exposing, reading out, and quantizing the next row pixels, while a counter counts from 0 until all row pixels have been exposed, read out, and quantized. This application embodiment can significantly improve the dynamic range of the image sensor without sacrificing the pixel fill factor. This application can be widely applied in the field of imaging system technology.

Description

Technical Field

[0001] This application relates to the field of imaging system technology, and in particular to a high dynamic range CMOS image sensor and its control method. Background Technology

[0002] Dynamic range (DR) is one of the important performance indicators of image sensors, representing the range of the maximum and minimum light intensity signals that a CMOS image sensor can simultaneously detect in the same frame. In fields such as security monitoring, machine vision, and autonomous driving, there is a great demand for high dynamic range (HDR) image sensors with a dynamic range exceeding 100dB. Existing methods for realizing high dynamic range image sensors include multiple exposure and multi-frame fusion methods, local exposure control methods, and pixel methods using high dynamic range. However, existing technologies have disadvantages such as low frame rate, high power consumption, complex circuitry, low fill factor, poor low light performance, and low signal-to-noise ratio under low light intensity.

[0003] In summary, the technical problems existing in the relevant technologies need to be improved. Summary of the Invention

[0004] The main objective of this application is to propose a high dynamic range CMOS image sensor and its control method, which can significantly improve the dynamic range of the image sensor without sacrificing the pixel fill factor.

[0005] To achieve the above objectives, one aspect of this application proposes a high dynamic range CMOS image sensor. The image sensor circuit includes a pixel circuit array, a row control circuit, and a quantization circuit. The pixel circuit array is connected to the quantization circuit via several columns of signal buses. The pixel circuit array is connected to the row control circuit via several row control lines. The row control circuit is connected to the quantization circuit via a quantization end signal line, wherein:

[0006] The pixel circuit array is used to receive optical signals and convert the optical signals into dynamic electrical signals;

[0007] The row control circuit is used to generate row control signals and control the operation of the pixel circuit array;

[0008] The quantization circuit is used to quantize the dynamic electrical signal into a digital code.

[0009] In some embodiments, the pixel circuit array includes a plurality of pixel circuits, each pixel circuit including a photodiode, a reset transistor, an amplifying transistor, and a row gating transistor. The anode of the photodiode is grounded, the cathode of the photodiode is connected to the drain of the reset transistor and the gate of the amplifying transistor, respectively. The gate of the reset transistor is connected to the gate of the row gating transistor and acquires the row control signal. The source of the reset transistor is connected to the drain of the amplifying transistor and connected to a power supply. The source of the amplifying transistor is connected to the drain of the row gating transistor, and the source of the row gating transistor is connected to the column signal bus.

[0010] In some embodiments, the pixel circuit array further includes a photodiode parasitic capacitance, a first terminal of which is connected to the cathode of the photodiode, and a second terminal of which is connected to the anode of the photodiode. The photodiode parasitic capacitance is used to drive the output of the dynamic electrical signal.

[0011] In some embodiments, the row control circuit includes a plurality of shift registers and a plurality of boost buffers. The D input terminals of the plurality of shift registers are connected to the Q output terminal of the preceding shift register in the row control circuit. The clock signal input terminals of the plurality of shift registers are interconnected to acquire a clock input signal. The reset signal input terminal of the first shift register of the row control circuit is connected to a reset input signal. The Q output terminal of the shift registers is connected to the input terminal of the boost buffer. The output terminal of the boost buffer outputs the row control signal, wherein:

[0012] The shift register is used to generate shift pulse signals;

[0013] The boost buffer is used to drive the gate capacitance of the reset transistor and the gate capacitance of the row select transistor.

[0014] In some embodiments, the quantization circuit includes a counter, a plurality of latches, a ramp voltage generation circuit, a plurality of comparators, and a multiplexer. The first output of the counter is connected to the input of the ramp voltage generation circuit; the second output of the counter is connected to the input of the plurality of latches; the third output of the counter is connected to the first input of the multiplexer; the output of the ramp voltage generation circuit is connected to the positive input of the comparators; the negative input of the comparators is connected to the column signal bus; the output of the comparators is connected to the input of the latches; and the outputs of the plurality of latches are connected to a plurality of the inputs of the multiplexer, wherein:

[0015] The counter is used to count the current clock cycle;

[0016] The latch is used to latch the current counter value;

[0017] The ramp voltage generation circuit is used to generate ramp voltage;

[0018] The comparator is used to compare the magnitude of the input signal and control the latch to complete the latching operation;

[0019] The multiplexer is used to serially output the quantization result.

[0020] To achieve the above objectives, another aspect of this application proposes a control method for a high dynamic range CMOS image sensor, the method comprising:

[0021] Acquire the row control signal as the current control signal;

[0022] The current row of pixels is exposed and read out using the current control signal to obtain the dynamic electrical signal of the current row of pixels.

[0023] Based on the dynamic electrical signal of the current row pixel, the current row pixel is quantized and a digital code with brightness information is output. The highest bit of the digital code changes from high level to low level to indicate that the quantization of the current row is complete.

[0024] Based on the highest bit of the digital code, all shift registers in the row control circuit are shifted to obtain the shifted row control signal as the control signal for the next row. Then, the pixels of the next row are exposed, read out, and quantized according to the control signal of the next row. At the same time, the counter digital code counts from 0 until all row pixels are exposed, read out, and quantized.

[0025] In some embodiments, the row control signal includes several row sequential pulse trains, and the several row sequential pulse trains correspond one-to-one with several rows of pixel circuits in the pixel circuit array. When the nth row sequential pulse train is high, pixel exposure and readout processing are performed on the corresponding nth row pixel circuit.

[0026] In some embodiments, the step of performing exposure and readout processing on the current row pixels using the current control signal to obtain the dynamic electrical signal of the current row pixels includes:

[0027] According to the current control signal, the reset transistor is turned off, the photodiode acquires the optical signal and discharges the parasitic capacitance of the photodiode to obtain the potential value at the parasitic capacitance of the photodiode.

[0028] The potential value at the parasitic capacitance of the photodiode is amplified by an amplifying transistor to obtain the potential value at the parasitic capacitance of the photodiode after amplification by a source follower.

[0029] The row selection transistor is turned on according to the current control signal, and the potential value at the parasitic capacitance of the photodiode after amplification by the source follower is transmitted to the column signal bus to obtain the dynamic electrical signal of the current row pixel.

[0030] In some embodiments, the step of quantizing the current row pixels based on the dynamic electrical signal of the current row pixels and outputting a digital code includes:

[0031] A ramp voltage is generated by a ramp voltage generation circuit.

[0032] The ramp voltage is compared with the dynamic electrical signal of the current row pixel. The output signal of the comparator is flipped when the potential at the positive input terminal is greater than the potential at the negative input terminal to obtain a high-level signal.

[0033] The high-level signal controls the latch to latch the current counter value, quantize the current row pixels, and output the digital code.

[0034] In some embodiments, the expression for the ramp voltage is as follows:

[0035] V ramp =(VDD-V th ) / T×t

[0036] In the above formula, V ramp V represents the ramp voltage, VDD represents the power supply voltage, and V th The threshold voltage of the amplifying transistor is represented by T, the row period is represented by T, and t is represented by the current time when the rising edge of the row strobe signal is 0.

[0037] The embodiments of this application include at least the following beneficial effects: This application provides a high dynamic range CMOS image sensor and its control method. This scheme generates a row control signal and controls the operation of a pixel circuit array. The pixel circuit array receives an optical signal and converts the optical signal into a dynamic electrical signal and performs quantization processing. It adopts a pixel output signal dynamic readout structure, which greatly improves the dynamic range of the image sensor without losing the pixel fill factor. Attached Figure Description

[0038] Figure 1 This is a schematic diagram of the structure of a high dynamic range CMOS image sensor provided in an embodiment of this application;

[0039] Figure 2 This is a schematic diagram of the steps of a control method for a high dynamic range CMOS image sensor provided in an embodiment of this application;

[0040] Figure 3This is a schematic diagram of the structure of a single pixel circuit in the pixel circuit array provided in the embodiments of this application;

[0041] Figure 4 This is a schematic diagram of the row control circuit provided in an embodiment of this application;

[0042] Figure 5 This is a schematic diagram of the quantization circuit provided in an embodiment of this application;

[0043] Figure 6 This is a schematic diagram of the voltage signal curves of an important node in an image sensor system within a line exposure period T, provided in an embodiment of this application.

[0044] Figure 7 This is a schematic diagram of the timing waveform of the image sensor provided in the embodiments of this application. Detailed Implementation

[0045] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of this application and are not intended to limit it. In the following description, when referring to the accompanying drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with those of this application; they are merely examples of systems and methods consistent with some aspects of the embodiments of this application as detailed in the appended claims.

[0046] It is understood that the terms “first,” “second,” etc., used in this application may be used herein to describe various concepts, but unless otherwise stated, these concepts are not limited by these terms. These terms are only used to distinguish one concept from another. For example, without departing from the scope of the embodiments of this application, first information may also be referred to as second information, and similarly, second information may also be referred to as first information. Depending on the context, the words “if,” “when,” or “in response to a determination” as used herein may be interpreted as “when…” or “when…” or “in response to a determination.”

[0047] As used in this application, the terms "at least one", "multiple", "each", "any", etc., "at least one" includes one, two or more, "multiple" includes two or more, "each" refers to each of the corresponding multiples, and "any" refers to any one of the multiples.

[0048] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing embodiments of this application only and is not intended to limit this application.

[0049] Before providing a detailed description of the embodiments of this application, some of the nouns and terms involved in the embodiments of this application will be explained first. The nouns and terms involved in the embodiments of this application are subject to the following interpretations.

[0050] CMOS image sensors, due to their advantages of low power consumption, low cost, and high integration, are widely used in consumer electronics, intelligent transportation, security monitoring, machine vision, virtual reality, and other fields. Image sensors play a vital role in both military and civilian applications, as well as in production and daily life. With continuous technological advancements, the applications of image sensors will further expand and deepen. Meanwhile, higher resolution, smaller pixel size, wider dynamic range, better noise performance, and improved optical performance are all directions pursued by image sensor manufacturers and researchers.

[0051] Dynamic range (DR) is one of the important performance indicators of image sensors. It represents the range of maximum and minimum light intensity signals that a CMOS image sensor can simultaneously detect in the same frame. The larger the dynamic range, the higher the grayscale detail level of the acquired image. The human eye has a dynamic range of over 120 dB, however, current commercial image sensors typically only have a dynamic range of 60–80 dB.

[0052] In fields such as security monitoring, machine vision, and autonomous driving, there is a high demand for high dynamic range (HDR) image sensors with a dynamic range exceeding 100dB. Examples include license plate recognition under high beams at night in traffic monitoring and scenes with drastic changes in brightness when vehicles enter or exit tunnels in autonomous driving.

[0053] There are several methods to achieve high dynamic range (HDR) image sensors. The first is multi-exposure and multi-frame fusion. This method involves capturing multiple images at different exposure times, quantizing and storing them, and then combining these images into a single image with a higher dynamic range in the image ISP (Image Signal Processor). This method significantly reduces the image sensor's frame rate, and the large amount of storage and computation results in extremely high power consumption. The second method is local exposure control. This method applies different exposure times or gains to different areas or even different pixels on the image sensor to capture details within different brightness ranges. This method does not sacrifice the image sensor's frame rate but typically requires complex pixel circuits, sensor control circuits, and algorithms. The third method uses high dynamic range pixels. This method uses pixel circuits that exhibit non-linear responses to light intensity, typically logarithmic response characteristics, to achieve non-linear compression of the light intensity range within the pixel circuitry. This method may result in a low signal-to-noise ratio under low light intensity.

[0054] Some shortcomings exist in related technologies, such as low frame rate, high power consumption, complex circuitry, low fill factor, and poor low-light performance.

[0055] In view of this, this application provides a high dynamic range CMOS image sensor. Based on the different light intensity response curves of the human eye and silicon-based photoelectric effect, and simulating the characteristic that the human eye's perception of brightness follows an approximate power function, a high dynamic range light intensity inverse proportional response image sensor with low illumination stretching and high illumination compression is designed. Without losing the pixel fill factor, the image sensor output has an inverse proportional response to light intensity, which greatly improves the dynamic range of the image sensor.

[0056] Reference Figure 1 , Figure 1 A structural diagram of a high dynamic range CMOS image sensor provided in an embodiment of the present invention is shown below. Figure 1 The image sensor circuit includes a pixel circuit array, a row control circuit, and a quantization circuit. The pixel circuit array is connected to the quantization circuit via several column signal buses, and the pixel circuit array is connected to the row control circuit via several row control lines. The row control circuit is connected to the quantization circuit via a quantization end signal line. In this CMOS image sensor, which is an inverse proportional image sensor, the pixel circuit array is connected to the quantization circuit via several column signal buses, and the pixel circuit array is connected to the row control circuit via several row control lines. The row control circuit is connected to the quantization circuit via a quantization end signal line. These three parts of the inverse proportional image sensor are interconnected in pairs. The row control signal generated by the row control circuit is transmitted to each pixel circuit in each row via the row control lines. Each column of pixels shares a column signal bus, and the pixel output result selected by the row strobe signal is transmitted to the quantization circuit via the column signal bus.

[0057] Pixel circuit arrays are used to receive optical signals and convert them into dynamic electrical signals;

[0058] In embodiments of the present invention, such as Figure 3 As shown, the pixel circuit array includes several pixel circuits, each including a photodiode, a reset transistor, an amplifying transistor, and a row gating transistor. The anode of the photodiode is grounded, and the cathode of the photodiode is connected to the drain of the reset transistor and the gate of the amplifying transistor, respectively. The gate of the reset transistor is connected to the gate of the row gating transistor to obtain the row control signal. The source of the reset transistor is connected to the drain of the amplifying transistor and connected to the power supply. The source of the amplifying transistor is connected to the drain of the row gating transistor, and the source of the row gating transistor is connected to the column signal bus.

[0059] Furthermore, the pixel circuit array also includes a photodiode parasitic capacitance. The first end of the photodiode parasitic capacitance is connected to the cathode of the photodiode, and the second end of the photodiode parasitic capacitance is connected to the anode of the photodiode. The photodiode parasitic capacitance converts the weak photocurrent into voltage, and after the amplifying transistor increases the driving capability, it is transmitted to the column signal bus through the row selector.

[0060] Specifically, the pixel circuit array module consists of several pixel circuits arranged in a rectangular pattern to form an array. The structure of a single pixel circuit is as follows: Figure 3 As shown, the system consists of one photodiode (PD) and three MOSFETs. The reset transistor (RST) is a PMOS transistor, the amplifying transistor (SF) is an NMOS transistor used as a source follower, and the row select transistor (SEL) is an NMOS transistor. The gates of both the reset transistor (RST) and the row select transistor (SEL) are connected to the row control signal (SIG). When the row control signal (SIG) is low, the reset transistor (RST) turns on, resetting the parasitic capacitance Cpd of the photodiode, and the row select transistor (SEL) turns off. When the row control signal (SIG) is high, the reset transistor (RST) turns off, and the photodiode (PD) generates a current from cathode to anode under the photoelectric effect, allowing the pixel to be exposed. Simultaneously, the row select transistor (SEL) turns on, connecting the output of the source follower amplifying transistor (SF) to the column signal bus. The voltage level on the signal bus decreases as the voltage Vpd across the parasitic capacitance Cpd of the photodiode decreases, and the pixel output level is dynamically read onto the column signal bus. The amplifier transistor SF is used to convert the weak charge on the parasitic capacitance Cpd of the photodiode into a voltage signal and then into a more powerful output signal to drive the parasitic capacitance on the column signal bus.

[0061] The row control circuit is used to generate row control signals and control the operation of the pixel circuit array;

[0062] In this embodiment of the invention, the row control circuit includes several shift registers and several boost buffers. The D input terminals of the several shift registers are connected to the Q output terminal of the previous shift register in the row control circuit. The clock signal input terminals of the several shift registers are interconnected to obtain clock input signals. The reset signal input terminal of the first shift register of the row control circuit is connected to a reset input signal. The Q output terminal of the shift register is connected to the input terminal of the boost buffer. The output terminal of the boost buffer outputs a row control signal. The shift register is used to generate a shift pulse signal. The boost buffer is used to drive the gate capacitor of the reset transistor and the gate capacitor of the row selection transistor.

[0063] Specifically, the structure of the line control circuit module is as follows: Figure 4As shown, the signal generation section consists of shift registers connected end-to-end, used to generate shift pulse signals. Each shift register output is connected to a boost buffer, used to drive the gate capacitances of all reset transistors (rst) and row select transistors (sell) in a row of the pixel array. The boost operation causes the row select transistors (sell) to operate in the linear region, reducing the source-drain voltage drop of the row select transistors (sell), thereby reducing unnecessary dynamic range loss and improving the dynamic range of the pixel output signal.

[0064] Quantization circuits are used to quantize dynamic electrical signals into digital codes.

[0065] In this embodiment of the invention, the quantization circuit includes a counter, several latches, a ramp voltage generation circuit, several comparators, and a multiplexer. The first output terminal of the counter is connected to the input terminal of the ramp voltage generation circuit, the second output terminal of the counter is connected to the input terminals of the several latches, the third output terminal of the counter is connected to the first input terminal of the multiplexer, the output terminal of the ramp voltage generation circuit is connected to the positive input terminal of the comparator, the negative input terminal of the comparator is connected to the column signal bus, the output terminal of the comparator is connected to the input terminal of the latches, and the output terminals of the several latches are connected to several input terminals of the multiplexer. The counter is used to count the current clock cycle; the latches are used to latch the current counter value; the ramp voltage generation circuit is used to generate a ramp voltage; the comparators are used to compare the magnitude of the input signals and control the latches to complete the latching operation; and the multiplexer is used to serially output the quantization result.

[0066] Specifically, the structural diagram of the quantization circuit module is as follows: Figure 5 As shown, it consists of a 10-bit counter, a 10-bit latch, a ramp voltage generation circuit, a comparator circuit, and a multiplexer. The counter and ramp voltage generation circuit are globally shared, while the 10-bit latch and comparators are column-shared. That is, the quantization circuit of an n-column pixel inverse proportional image sensor consists of one counter, one ramp voltage generation circuit, n 10-bit latches, and n comparators. The column-shared comparator inputs are connected to the column signal bus and the ramp voltage V, respectively. ramp The column signal bus level shows a decreasing trend, and the ramp voltage V ramp To maintain an upward trend, when the column-shared comparator inverts, the 10-bit column-shared latch latches the current counter value, which is then read serially through a multiplexer. After quantization of a row of pixel output is complete, the most significant bit of the counter in the quantization circuit acts as the quantization end signal and is sent to the row control circuit to control the shift operation of the shift register.

[0067] Please see Figure 2This application also provides a control method for a high dynamic range CMOS image sensor, which can realize the above-mentioned high dynamic range CMOS image sensor. The method includes:

[0068] S100: Obtain the row control signal as the current control signal;

[0069] In some specific embodiments, the row control signal includes several sequential pulse trains, and the several sequential pulse trains correspond one-to-one with several rows of pixel circuits in the pixel circuit array. When the nth sequential pulse train is high, pixel exposure and readout processing are performed on the corresponding nth row pixel circuit.

[0070] S200: The current row of pixels is exposed and read out using the current control signal to obtain the dynamic electrical signal of the current row of pixels, and then transmitted to the column signal bus.

[0071] It should be noted that in some embodiments, step S200 may include: S210, controlling the reset transistor to turn off according to the current control signal, the photodiode acquiring the light signal and discharging the parasitic capacitance of the photodiode to obtain the potential value at the parasitic capacitance of the photodiode; S220, amplifying the driving capability of the potential value at the parasitic capacitance of the photodiode through the amplification transistor to obtain the potential value at the parasitic capacitance of the photodiode after amplification by the source follower; S230, controlling the row selection transistor to be in the conducting state according to the current control signal, transmitting the potential value at the parasitic capacitance of the photodiode after amplification by the source follower to the column signal bus to obtain the dynamic electrical signal of the current row pixel.

[0072] In some specific embodiments, the image sensor of this invention employs a rolling shutter, column-parallel readout and quantization structure. The relationship between the three main circuit components is as follows: the row control circuit generates control signals to control the operating state of all pixel circuits in each row. All pixels in the controlled row are selected for exposure and readout. The output signals of all pixel circuits in the current row are read onto the column signal bus corresponding to each pixel. The quantization circuit reads and completes the quantization of the output result of each pixel in the current row within the current row's operation cycle. At this point, the current row of pixels has completed exposure and quantization. The quantization circuit then sends a signal to the row control circuit indicating that the current row's quantization is complete. The shift register in the row control circuit performs a shift operation, thereby selecting the next row of pixels for exposure, readout, and quantization. In the subsequent operation cycle of the next row of pixels, the quantization result of the previous row, latched in the quantization circuit, is serially read out through a multiplexer. The image sensor system repeats the above operations until the exposure and quantization of all rows are completed, thus generating a complete frame image.

[0073] Taking a pixel in the nth row as an example, in a complete frame, the row control circuit generates a sequential pulse train from the first row to the last row. When the rolling shutter exposes a row other than the current row, the control signal sig[n] for that row is low, the reset transistor rst in the pixel circuit is turned on, the parasitic capacitance of the photodiode is reset to the power supply voltage VDD, the row selection transistor sel is turned off, and the pixel in the current nth row is not connected to the column signal bus. When the rolling shutter exposes the nth row, the control signal sig[n] for that row is high, the reset transistor rst in the pixel circuit is turned off, the photodiode is illuminated and generates a photocurrent that discharges its own parasitic capacitance, causing the potential Vpd on the parasitic capacitance to continuously decrease. Figure 6 As shown in Vpd, the expression for Vpd is:

[0074] V pd =VDD-I pd ×t / C pd

[0075] In the above formula, V pd I represents the potential value on the parasitic capacitance. pd C represents the photocurrent generated by the photodiode under illumination. pd Let t be the equivalent parasitic capacitance of the photodiode, and t represent the current time when the rising edge of the row strobe signal is 0. The value of t is also equal to the exposure time length. If the pulse width of the row strobe signal is T, then 0 ≤ t ≤ T.

[0076] Potential V at the parasitic capacitance of the photodiode pd After being amplified by the source follower sf, the signal reaches the source of the row select transistor sel. At this time, the row select control signal sig[n] is high, and after passing through the boost buffer, it acts on the gate of the row select transistor sel to ensure that it operates in the linear region. Therefore, the output of the source follower sf is transmitted losslessly to the column signal bus through the row select transistor sel, such as... Figure 6 As shown, the voltage values ​​on the column signal bus are represented as follows:

[0077] V out =V pd -V th =VDD-I pd ×t / C pd -V th

[0078] Where V th This represents the threshold voltage of the source follower sf.

[0079] The row selection signal pulse width is T, and the time for each row of pixels to complete exposure and readout is T, therefore the row period is T. Within each row period T, the quantization circuit quantizes the output of all pixels in the selected row to obtain a digital code representing the brightness information.

[0080] S300: Based on the dynamic electrical signal of the current row of pixels, perform quantization processing on the current row of pixels and output a digital code with brightness information. The highest bit of the digital code changes from high level to low level to indicate that the quantization of the current row is complete.

[0081] It should be noted that in some embodiments, step S300 may include: S310, generating a ramp voltage through a ramp voltage generation circuit; S320, comparing the ramp voltage with the dynamic electrical signal of the current row pixel, and when the two input voltages flip, the comparator output flips from a low level signal to a high level signal; S330, controlling the latch to latch the count value of the current counter according to the high level signal, quantizing the current row pixel, and outputting a digital code.

[0082] In some specific embodiments, within each row cycle T, the output of the ramp voltage generation circuit in the quantization circuit rises from 0 to VDD-V. th The ramp voltage signal has a rise time that is exactly one row period T. For example... Figure 6 As shown, the ramp voltage is represented as:

[0083] V ramp =(VDD-V th ) / T×t

[0084] Where t represents the current time when the rising edge of the row strobe signal is 0, and 0≤t≤T.

[0085] The positive input of the column-shared comparator is connected to the globally shared ramp voltage V. ramp The negative terminal is connected to the signal bus V of the corresponding column. out During row period T, the voltage V on the column signal bus... out From VDD-V th Gradually decreasing, the globally shared ramp voltage V ramp Gradually increasing from 0 to VDD-V th Therefore, within row period T, the voltage values ​​at the positive and negative terminals of the column-shared comparator have one and only one intersection point. Before this intersection point, the signal bus V connected to the positive terminal of the column-shared comparator... out Less than the globally shared ramp voltage V at the negative terminal ramp Output result V comp The signal level is low; after this intersection, the signal bus V connected to the positive terminal of the column-shared comparator... out Greater than the globally shared ramp voltage V at the negative terminal ramp Output result Vcomp It is a high level. For example... Figure 6 As shown, the time t1 corresponding to this intersection point is V. out With V ramp At the same time, the comparator output V at time t1 is... comp The transition from low to high level is V. comp At the rising edge of time t1, the expression is:

[0086] V out =V ramp =VDD-I pd ×t / C pd -V Nh =(VDD-V th ) / T×t1

[0087] t1=(VDD-V th ) / ((VDD-V th ) / T+I pd / C pd )

[0088] In the above formula, the power supply voltage VDD and the line period T are given values. Within the same chip, the threshold voltage V of the MOS transistor used as the source follower sf in all pixel circuits is... th Parasitic capacitance C of photodiode pd It can be considered as an equal constant. It can be seen that the flip time of the column-sharing comparator exhibits an inverse proportional response characteristic with the illumination intensity, and this flip time t1 is the only rising edge of the column-sharing comparator within one row period T.

[0089] like Figure 7 As shown, the row control signal generates a sequential pulse train signal. When the nth row control signal sig[n] is high, all pixels in the nth row undergo exposure operation. During the operation time T of the nth row, the pixel output V out [n] continuously decreases, and interacts with the continuously rising V. ramp Intersection. At the moment of intersection, the comparator outputs V. comp The transition from low to high level controls the operation. Figure 4 A 10-bit latch triggered by the rising edge latches the current counter value, thereby completing the quantization of brightness information within one operation time T. When the nth row is quantized, the nth row control signal sig[n] goes back to low level, and then the (n+1)th row control signal sig[n+1] goes high level and remains high for one row period T, during which the operation process of the nth row as described above is completed.

[0090] Within each row cycle T, a globally shared 10-bit counter counts from 0 to 1023, with each digit code change interval being T / 1024. The output of the 10-bit counter is connected to a 10-bit latch shared by each column. When the column-shared comparator outputs a result V... comp When the rising edge arrives, the 10-bit latch latches the current count value of the globally shared 10-bit counter. The result latched by the 10-bit latch is the column signal bus V. out Shared ramp voltage V with the whole world ramp The quantization result at intersection point t1. At the end of a line cycle, the highest count bit of the globally shared 10-bit counter is set from high to low, i.e., from a count value of 1023 to 0, thus starting the next line cycle. The highest count bit acts as a quantization end marker. This signal is sent to the line control circuit. When the line control circuit reads the falling edge of the signal, the shift register in the line control circuit performs a shift operation, thus starting the exposure and readout of the next row of pixels in the pixel array, and the image sensor system enters the operation cycle of the next row of pixels. During the operation cycle of the next row, the readout circuit serially transmits the quantization result digital code of the previous row to outside the image sensor via a multiplexer.

[0091] For an image sensor, its dynamic range can be expressed by the maximum and minimum light intensity that can be sensed as dynamic range = 20log(maximum light intensity / minimum light intensity). The maximum light intensity is defined as the light intensity when the brightness is continuously increased to the point that the image sensor is saturated and the output remains unchanged. The minimum light intensity is defined as the light intensity when the light intensity is continuously increased from 0 to the point that the image sensor output changes by exactly one digital code.

[0092] For a traditional linear 3T pixel image sensor with a 10-bit quantizer, since the image sensor output value, pixel output voltage, photocurrent magnitude, and light intensity are linearly related, its dynamic range can be expressed as: Dynamic range of a traditional 3T image sensor = 20log(maximum light intensity / minimum light intensity) = 20log(2 10 / 1)=60.2dB.

[0093] For the high dynamic range image sensor, with a 10-bit quantization circuit, and disregarding comparator operating speed, offset voltage, and column signal bus current source load voltage drop, the image sensor proposed in this invention outputs digital code 1023 in a dark environment and outputs digital code 0 in an environment with light intensity greater than saturation. This is because the photocurrent I... pd Proportional to light intensity, the minimum detectable light intensity can be represented by an image sensor, and the minimum resolvable photocurrent I can be represented by an image sensor. pdmin This means that the photocurrent magnitude occurs precisely when the output digital code is at the boundary between 1022 and 1023, at which point the intersection time t1 = 1023T / 1024. In this case, the expression is:

[0094] t1=1023T / 1024=(VDD-V th ) / ((VDD-V th ) / T+I pdmin / C pd )

[0095] I pdmin = 1 / 1023 × (VDD - V) th )×C pd / T

[0096] This invention can sense maximum light intensity and can distinguish maximum photocurrent I using an image sensor. pdmax This indicates the magnitude of the photocurrent when the output digital code is exactly at the boundary between 0 and 1, at which point the intersection time t1 = T / 1024. In this case, the expression is:

[0097] t1 = T / 1024 = (VDD - V th ) / ((VDD-V th ) / T+I pdmax / C pd )

[0098] I pdmax =1023×(VDD-V th )×C pd / T

[0099] Therefore, the theoretical value of the dynamic range of this invention has the following expression:

[0100] Dynamic range = 20log(I) pdmax / I pdmin ) = 20log(1023) 2 )≈120.4 (dB)

[0101] The 3T high dynamic range image sensor of this invention achieves a dynamic range of 120.4dB using a 10-bit quantizer, far exceeding the maximum dynamic range of 60.2dB for traditional 10-bit quantized linear image sensors. Furthermore, the pixel circuit of this invention uses only 3 transistors and requires only 1 control signal, enabling a larger fill factor or smaller pixel area compared to traditional 3T pixel circuits.

[0102] S400: Based on the highest bit of the digital code, perform a shift operation on all shift registers in the row control circuit to obtain the shifted row control signal as the control signal for the next row. Then, based on the control signal for the next row, expose, read out, and quantize the pixels of the next row. At the same time, the counter digital code counts from 0 until all row pixels have been exposed, read out, and quantized.

[0103] Additionally, it should be noted that in this embodiment of the invention, the N / P types of the reset transistor rst and the row gating transistor sel in the pixel circuit are interchanged; the amplifying transistor sf in the pixel circuit uses a low-threshold N-type MOSFET or a complementary source follower to improve the dynamic range of the output voltage swing; the reset transistor rst and the row gating transistor sel in the pixel circuit are respectively connected to the signal line rst and the signal line sel to change the control signal to achieve two working modes: linear response or inverse proportional response; the number of bits in the quantization circuit is selected according to the imaging requirements; the column shared latch and the global shared counter in the quantization circuit are replaced by a column shared counter; the boost buffer of the control signal generation circuit can be removed or improved according to the pixel operating voltage and the controller operating voltage.

[0104] It is understood that the content of the above method embodiments is applicable to this system embodiment. The specific functions implemented in this system embodiment are the same as those in the above method embodiments, and the beneficial effects achieved are also the same as those achieved in the above method embodiments.

[0105] The preferred embodiments of the present application have been described above with reference to the accompanying drawings, but this does not limit the scope of the claims of the present application. Any modifications, equivalent substitutions, and improvements made by those skilled in the art without departing from the scope and substance of the embodiments of the present application shall be within the scope of the claims of the present application.

Claims

1. A high dynamic range CMOS image sensor, characterized in that, The image sensor circuit includes a pixel circuit array, a row control circuit, and a quantization circuit. The pixel circuit array is connected to the quantization circuit via several column signal buses. The pixel circuit array is connected to the row control circuit via several row control lines. The row control circuit is connected to the quantization circuit via a quantization end signal line. The pixel circuit array includes several pixel circuits, each of which includes a photodiode, a reset transistor, an amplifying transistor, and a row gating transistor. The pixel circuit array also includes parasitic capacitance of the photodiode. The anode of the photodiode is grounded. The cathode of the photodiode is connected to the drain of the reset transistor and the gate of the amplifying transistor. The gate of the reset transistor is connected to the gate of the row gating transistor and acquires the row control signal. The source of the reset transistor is connected to the drain of the amplifying transistor and connected to a power supply. The source of the amplifying transistor is connected to the drain of the row gating transistor. The source of the row gating transistor is connected to the column signal bus. The pixel circuit array is used to receive optical signals and convert the optical signals into dynamic electrical signals; The row control circuit is used to generate row control signals and control the operation of the pixel circuit array; The quantization circuit is used to quantize the dynamic electrical signal into a digital code; The row control circuit includes several shift registers and several boost buffers. The D input terminals of the shift registers are connected to the Q output terminal of the preceding shift register in the row control circuit. The clock signal input terminals of the shift registers are interconnected to obtain clock input signals. The reset signal input terminal of the first shift register of the row control circuit is connected to a reset input signal. The Q output terminal of the shift registers is connected to the input terminal of the boost buffer. The output terminal of the boost buffer outputs the row control signal, wherein: The shift register is used to generate shift pulse signals; The boost buffer is used to drive the gate capacitance of the reset transistor and the gate capacitance of the row select transistor; When the row control signal is low, the reset transistor turns on to reset the parasitic capacitance of the photodiode, and the row gating transistor turns off. When the row control signal is high, the reset transistor is turned off, and the photodiode generates a current from cathode to anode under the photoelectric effect, and the pixel performs an exposure operation. At the same time, the row gating transistor is turned on, and the source of the photodiode is connected to the column signal bus along with the output of the amplifying transistor. The level on the signal bus decreases as the voltage on the parasitic capacitance of the photodiode decreases, and the pixel output level is dynamically read onto the column signal bus.

2. The image sensor according to claim 1, characterized in that, The first end of the parasitic capacitance of the photodiode is connected to the cathode of the photodiode, and the second end of the parasitic capacitance of the photodiode is connected to the anode of the photodiode. The parasitic capacitance of the photodiode is used to drive the output of the dynamic electrical signal.

3. The image sensor according to claim 1, characterized in that, The quantization circuit includes a counter, several latches, a ramp voltage generation circuit, several comparators, and a multiplexer. The first output of the counter is connected to the input of the ramp voltage generation circuit; the second output of the counter is connected to the inputs of the latches; the third output of the counter is connected to the first input of the multiplexer; the output of the ramp voltage generation circuit is connected to the positive input of the comparators; the negative input of the comparators is connected to the column signal bus; the output of the comparators is connected to the input of the latches; and the outputs of the latches are connected to several inputs of the multiplexer. The counter is used to count the current clock cycle; The latch is used to latch the current counter value; The ramp voltage generation circuit is used to generate ramp voltage; The comparator is used to compare the magnitude of the input signal and control the latch to complete the latching operation; The multiplexer is used to serially output the quantization result.

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