Array substrate and display device

Abstract

An array substrate is provided. The array substrate includes a plurality of first gate lines, a plurality of second gate lines, and a plurality of pixel driving circuits. The array substrate includes a first semiconductor material layer and a second semiconductor material layer located on a side of the first semiconductor material layer away from a substrate. The first semiconductor material layer includes at least an active layer of the driving transistor and the data writing transistor. The second semiconductor material layer includes at least an active layer of the compensation transistor. A first parasitic capacitance is formed between the second semiconductor material layer and a corresponding first gate line. A second parasitic capacitance is formed between the first node connection line and a corresponding second gate line. A ratio of the first parasitic capacitance to the second parasitic capacitance is greater than 2.3.

Description

TECHNICAL FIELD

[0001] The present application relates to display technology, and in particular to an array substrate and a display device. BACKGROUND

[0002] Organic light emitting diode (OLED) displays are one of the hotspots in the field of flat panel display research today. Unlike thin film transistor-liquid crystal displays (TFT-LCD) that use a stable voltage to control brightness, OLEDs are driven by a driving current that needs to be kept constant to control brightness. An OLED display panel includes a plurality of pixel units configured with pixel driving circuits arranged in multiple rows and multiple columns. Each pixel driving circuit includes a driving transistor having a gate terminal connected to one gate line per row and a drain terminal connected to one data line per column. When the row in which the pixel unit is selected is turned on, a switch transistor connected to the driving transistor is turned on, and a data voltage is applied from the data line to the driving transistor via the switch transistor, so that the driving transistor outputs a current corresponding to the data voltage to an OLED device. The OLED device is driven to emit light of a corresponding brightness. SUMMARY

[0003] In one aspect, the present disclosure provides an array substrate, comprising a plurality of first gate lines, a plurality of second gate lines, and a plurality of pixel driving circuits; wherein each of the plurality of pixel driving circuits comprises a driving transistor, a data writing transistor, a compensation transistor, a storage capacitor, a first node connecting line connecting a gate of the driving transistor and a first electrode of the compensation transistor; each of the plurality of first gate lines is configured to provide a gate scanning signal to the data writing transistor; each of the plurality of second gate lines is configured to provide a gate scanning signal to the compensation transistor; wherein the array substrate comprises a first semiconductor material layer and a second semiconductor material layer located on a side of the first semiconductor material layer away from a substrate; the first semiconductor material layer comprises at least an active layer of the driving transistor and the data writing transistor; the second semiconductor material layer comprises at least an active layer of the compensation transistor; a first parasitic capacitance is formed between the second semiconductor material layer and the corresponding first gate line; a second parasitic capacitance is formed between the first node connecting line and the corresponding second gate line; wherein a ratio of the first parasitic capacitance to the second parasitic capacitance is greater than 2.3.

[0004] Optionally, the ratio of the first parasitic capacitance to the second parasitic capacitance is between 2.3 and 3.5.

[0005] Optionally, the first node connection line crosses the corresponding second gate line; in a region where a footprint of the first node connection line on the substrate base board overlaps with a footprint of the corresponding second gate line on the substrate base board, the array substrate does not include any other conductive component whose footprint on the substrate base board overlaps with the footprint of the first node connection line on the substrate base board; and the layer where the first node connection line is located is spaced apart from the corresponding second gate line by at least two different insulating layers and semiconductor material layers.

[0006] Optionally, each pixel driving circuit further comprises a third gate pad and a gate connection pad connecting the third gate pad with the corresponding second gate line; a footprint of the third gate pad and the corresponding second gate line on the substrate base board overlaps with a footprint of the active layer of the compensation transistor on the substrate base board; and the third gate pad, the gate connection pad, and the corresponding second gate line and the active layer of the compensation transistor are respectively located in four different layers.

[0007] Optionally, the corresponding second gate line is located in a second gate metal layer comprising a second capacitor electrode of the storage capacitor; the active layer of the compensation transistor is located in a second semiconductor material layer located on a side of the second gate metal layer away from the substrate base board; the third gate pad is located in a third gate metal layer located on a side of the second semiconductor material layer away from the second gate metal layer; and the gate connection pad is located in a first signal line layer located on a side of the third gate metal layer away from the second semiconductor material layer.

[0008] Optionally, the gate connection pad is located in a second gate metal layer comprising a second capacitor electrode of the storage capacitor; the active layer of the compensation transistor is located in a second semiconductor material layer located on a side of the second gate metal layer away from the substrate base board; the third gate pad is located in a third gate metal layer located on a side of the second semiconductor material layer away from the second gate metal layer; and the corresponding second gate line is located in a first signal line layer located on a side of the third gate metal layer away from the second semiconductor material layer.

[0009] Optionally, the respective second gate line is in a second gate metal layer including a second capacitor electrode of the storage capacitor; the first electrode of the compensation transistor is in a second semiconductor material layer, the second semiconductor material layer being on a side of the second gate metal layer distal to the substrate; and the first node connection line is in a first signal line layer, the first signal line layer being on a side of the second semiconductor material layer distal to the second gate metal layer.

[0010] Optionally, the respective second gate line is in a second gate metal layer including a second capacitor electrode of the storage capacitor; the first electrode of the compensation transistor is in a second semiconductor material layer, the second semiconductor material layer being on a side of the second gate metal layer distal to the substrate; and the first node connection line is in a first signal line layer, the first signal line layer being on a side of the second semiconductor material layer distal to the second gate metal layer.

[0011] Optionally, the first node connection line and the first capacitor electrode are part of a unitary structure.

[0012] Optionally, each pixel drive circuit further includes a node connection pad in the first signal line layer including the respective second gate line; and the node connection pad connects the first node connection line in the first gate metal layer and the first electrode of the compensation transistor in the second semiconductor material layer.

[0013] Optionally, the node connection pad is connected to the first node connection line by an eighth via and to the first electrode of the compensation transistor by a seventh via; the seventh via extends through a passivation layer and a second interlayer dielectric layer; and the eighth via extends through the passivation layer, the second interlayer dielectric layer, a first interlayer dielectric layer, and an insulating layer.

[0014] Optionally, the corresponding second gate line includes a first portion and a second portion; a footprint of the first portion on the substrate overlaps at least partially with a footprint of the active layer of the compensation transistor on the substrate and does not overlap with a footprint of the first node connection line on the substrate; a footprint of the second portion on the substrate overlaps at least partially with the footprint of the first node connection line on the substrate and does not overlap with the footprint of the active layer of the compensation transistor on the substrate; the corresponding second gate line extends along a first direction; the first portion has a first average line width along a second direction at a position where the first portion intersects with the active layer of the compensation transistor, the second direction being perpendicular to the first direction; the second portion has a second average line width along the second direction at a position where the second portion intersects with the first connection line; and the first average line width is greater than the second average line width.

[0015] Optionally, the array substrate further includes a plurality of first voltage supply lines and a plurality of light emitting control signal lines; each of the plurality of pixel driving circuits includes a first light emitting control transistor and a voltage connection pad; the voltage connection pad includes a main body portion and an extension portion extending away from the main body portion; the main body portion connects a corresponding first voltage supply line of the plurality of first voltage supply lines with a second capacitor electrode of the storage capacitor; the extension portion connects the main body portion with a first electrode of the first light emitting control transistor; and the extension portion intersects with a corresponding light emitting control signal line of the plurality of light emitting control signal lines.

[0016] Optionally, the main body portion includes a first main body portion and a second main body portion; the first main body portion connects the corresponding first voltage supply line with the second capacitor electrode; a footprint of the first main body portion on a substrate overlaps at least partially with a footprint of the second capacitor electrode on the substrate and overlaps at least partially with a footprint of the corresponding first voltage supply line on the substrate; a footprint of the second main body portion on the substrate does not overlap with the footprint of the second capacitor electrode on the substrate, does not overlap with the footprint of the corresponding first voltage supply line on the substrate, and overlaps at least partially with a footprint of the second electrode of the driving transistor on the substrate; the first main body portion has a first average pad width along a direction substantially parallel to the second direction; the second main body portion has a second average pad width along the direction substantially parallel to the second direction; and the first average pad width is greater than the second average pad width.

[0017] Optionally, each light emission control signal line is in a first gate metal layer; the body portion and the extension portion are in a first signal line layer, the first signal line layer being on a side of the first gate metal layer distal to the substrate; the respective first voltage supply line is in a second signal line layer, the second signal line layer being on a side of the first signal line layer distal to the first gate metal layer; the respective first voltage supply line is connected to the first body portion by a third via extending through a first planarization layer; and the first body portion is connected to the second capacitor electrode by a fourth via extending through a passivation layer, a second interlayer dielectric layer, and a first interlayer dielectric layer.

[0018] Optionally, a footprint of the respective first voltage supply line on the substrate covers the footprint of the first node connection line on the substrate.

[0019] Optionally, each pixel driving circuit further comprises a first reset transistor; the active layers of the compensation transistor and the first reset transistor are in a second semiconductor material layer; and a footprint of the respective first voltage supply line on the substrate covers footprints of the active layers of the compensation transistor and the first reset transistor on the substrate.

[0020] Optionally, the array substrate further comprises a plurality of second voltage supply lines, a plurality of fourth reset signal lines, and a plurality of data lines in the same layer as the plurality of first voltage supply lines; the plurality of pixel driving circuits are arranged in a plurality of columns, including a (2k-1)-th column C(2k-1) and a (2k)-th column C(2k) of K columns, K and k being positive integers, 1≤k≤K / 2; the plurality of fourth reset signal lines exist in the (2k-1)-th column C(2k-1) but not in the (2k)-th column C(2k); and the plurality of second voltage supply lines exist in the (2k)-th column C(2k) but not in the (2k-1)-th column C(2k-1).

[0021] Optionally, the array substrate further comprises a plurality of reset signal lines respectively extending along directions substantially parallel to the first direction; the plurality of first voltage supply lines, the plurality of second voltage supply lines, the plurality of fourth reset signal lines, and the plurality of data lines extend along directions substantially parallel to the second direction; the array substrate comprises: an interconnection reset signal network comprising the plurality of fourth reset signal lines and the plurality of reset signal lines; each reset signal line in the plurality of reset signal lines is connected to one or more fourth reset signal lines in the plurality of fourth reset signal lines; and each fourth reset signal line in the plurality of fourth reset signal lines is connected to one or more reset signal lines in the plurality of reset signal lines.

[0022] In another aspect, the present disclosure provides an array substrate comprising a plurality of first gate lines, a plurality of second gate lines, and a plurality of pixel driving circuits; wherein each of the plurality of pixel driving circuits comprises a driving transistor, a data writing transistor, a compensation transistor, a storage capacitor, a first node connecting line connecting a gate of the driving transistor and a first electrode of the compensation transistor; each of the plurality of first gate lines is configured to provide a gate scanning signal to the data writing transistor; each of the plurality of second gate lines is configured to provide a gate scanning signal to the compensation transistor; wherein the array substrate comprises a first semiconductor material layer and a second semiconductor material layer located on a side of the first semiconductor material layer away from a substrate; the first semiconductor material layer comprises at least an active layer of the driving transistor and the data writing transistor; the second semiconductor material layer comprises at least an active layer of the compensation transistor; a first parasitic capacitance is formed between the second semiconductor material layer and a corresponding first gate line; a second parasitic capacitance is formed between the first node connecting line and a corresponding second gate line; the corresponding first gate line comprises a corresponding first gate line first branch in a first gate metal layer and a corresponding first gate line second branch in a first signal line layer located on a side of the first gate metal layer away from the substrate; the corresponding first gate line second branch is connected to the corresponding first gate line first branch through one or more vias; the first parasitic capacitance is formed between the second semiconductor material layer and the corresponding first gate line first branch and between the second semiconductor material layer and the corresponding first gate line second branch; and the first parasitic capacitance is greater than at least twice the second parasitic capacitance.

[0023] In another aspect, the present disclosure provides a display device comprising the array substrate described herein and one or more integrated circuits connected to the array substrate. BRIEF DESCRIPTION OF DRAWINGS

[0024] According to various disclosed embodiments, the following drawings are merely examples for illustrative purposes and are not intended to limit the scope of the present disclosure.

[0025] Figure 1 is a plan view of an array substrate according to some embodiments of the present disclosure.

[0026] Figure 2A is a circuit diagram showing a structure of a pixel driving circuit according to some embodiments of the present disclosure.

[0027] Figure 2B is a timing diagram showing an operation of a pixel driving circuit according to some embodiments of the present disclosure.

[0028] Figure 3AThis is a schematic diagram illustrating the structure of a pixel driving circuit in an array substrate according to some embodiments of the present disclosure.

[0029] Figure 3B It is shown Figure 3A A schematic diagram of the structure of the first semiconductor material layer in the array substrate shown.

[0030] Figure 3C It is shown Figure 3A The diagram shows a schematic of the structure of the first gate metal layer in the array substrate.

[0031] Figure 3D It is shown Figure 3A A schematic diagram of the structure of the second gate metal layer in the array substrate shown.

[0032] Figure 3E It is shown Figure 3A A schematic diagram of the structure of the second semiconductor material layer in the array substrate shown.

[0033] Figure 3F It is shown Figure 3A The diagram shows a schematic of the structure of the third gate metal layer in the array substrate.

[0034] Figure 3G It is shown Figure 3A A schematic diagram of a via extending through the first interlayer dielectric layer in an array substrate shown.

[0035] Figure 3H It is shown Figure 3A A schematic diagram of a via extending through a passivation layer in an array substrate shown.

[0036] Figure 3I It is shown Figure 3A The diagram shows a schematic of the structure of the first signal line layer in the array substrate.

[0037] Figure 3J It is shown Figure 3A A schematic diagram of a via extending through the first planarization layer in an array substrate shown.

[0038] Figure 3K It is shown Figure 3A A schematic diagram of the structure of the second signal line layer in the array substrate shown.

[0039] Figure 4A It is along Figure 3A A cross-sectional view of line A-A' in the diagram.

[0040] Figure 4B It is along Figure 3A A cross-sectional view of line B-B' in the diagram.

[0041] Figure 5A is a schematic diagram illustrating a structure of a pixel driving circuit in an array substrate in some embodiments according to the present disclosure.

[0042] Figure 5B is a schematic diagram illustrating a structure of a first semiconductor material layer in an array substrate shown in Figure 5A

[0043] Figure 5C is a schematic diagram illustrating a structure of a first gate metal layer in an array substrate shown in Figure 5A

[0044] Figure 5D is a schematic diagram illustrating a structure of a second gate metal layer in an array substrate shown in Figure 5A

[0045] Figure 5E is a schematic diagram illustrating a structure of a second semiconductor material layer in an array substrate shown in Figure 5A

[0046] Figure 5F is a schematic diagram illustrating a structure of a third gate metal layer in an array substrate shown in Figure 5A

[0047] Figure 5G is a schematic diagram illustrating a via extending through a first interlayer dielectric layer in an array substrate shown in Figure 5A

[0048] Figure 5H is a schematic diagram illustrating a via extending through a passivation layer in an array substrate shown in Figure 5A

[0049] Figure 5I is a schematic diagram illustrating a structure of a first signal line layer in an array substrate shown in Figure 5A

[0050] Figure 5J is a schematic diagram illustrating a via extending through a first planarization layer in an array substrate shown in Figure 5A

[0051] Figure 5K is a schematic diagram illustrating a structure of a second signal line layer in an array substrate shown in Figure 5A

[0052] Figure 6A is a cross-sectional view along line C-C’ in Figure 5A

[0053] Figure 6B is a cross-sectional view along line D-D’ in Figure 5A ​​​​​​​​​​​​

[0054] Figure 7 is a schematic diagram showing the structure of a pixel drive circuit in an array substrate in some embodiments according to the present disclosure.

[0055] Figure 8 is a cross-sectional view along line E-E’ in Figure 7

[0056] Figure 9 is a cross-sectional view of the area where the first node connection line crosses the respective second gate line first branch and the respective second gate line second branch.

[0057] Figure 10 is a schematic diagram showing the structure of a second signal line layer in an array substrate in some embodiments according to the present disclosure.

[0058] Figure 11 interconnected reset signal network in some embodiments according to the present disclosure is shown.

[0059] Figure 12 interconnected reset signal network in some embodiments according to the present disclosure is shown.

[0060] Figure 13 is a schematic diagram showing the structure of a voltage connection pad in an array substrate in some embodiments according to the present disclosure.

[0061] Figure 14 is a cross-sectional view along line F-F’ in Figure 3A DETAILED DESCRIPTION

[0062] The present disclosure will now be described in greater particularity with reference to the following embodiments. It should be noted that the following description of some embodiments presented herein is merely illustrative and is in no way limiting. It is not exhaustive or limited to the precise form disclosed.

[0063] ​​The present disclosure provides, among other things, an array substrate and a display device that substantially overcome one or more problems due to limitations and disadvantages of the related art. In one aspect, the present disclosure provides an array substrate. In some embodiments, the array substrate includes a plurality of pixel driving circuits, a plurality of first voltage supply lines, and a plurality of light emission control signal lines. Optionally, each of the plurality of pixel driving circuits includes a driving transistor, a first light emission control transistor, a storage capacitor, and a voltage connection pad. Optionally, the voltage connection pad includes a body portion and an extension portion extending away from the body portion. Optionally, the body portion connects a respective first voltage supply line of the plurality of first voltage supply lines with a second capacitor electrode of the storage capacitor. Optionally, the extension portion connects the body portion with a first electrode of the first light emission control transistor. Optionally, the extension portion intersects a respective light emission control signal line of the plurality of light emission control signal lines.

[0064] Various suitable pixel driving circuits can be used in the array substrate described in the present disclosure. Examples of suitable driving circuits include 3T1C, 2T1C, 4T1C, 4T2C, 5T2C, 6T1C, 7T1C, 7T2C, 8T1C, and 8T2C. In some embodiments, each of the plurality of pixel driving circuits is an 8T1C driving circuit. Various suitable light emitting elements can be used in the array substrate described in the present disclosure. Examples of suitable light emitting elements include organic light emitting diodes, quantum dot light emitting diodes, and micro light emitting diodes. Optionally, the light emitting element is a micro light emitting diode. Optionally, the light emitting element is an organic light emitting diode including an organic light emitting layer.

[0065] Figure 1 is a plan view of an array substrate in some embodiments according to the present disclosure. Referring to Figure 1 , the array substrate includes an array of sub-pixels Sp. Each sub-pixel includes electronic components, e.g., including a light emitting element. In one example, the light emitting element is driven by a respective pixel driving circuit PDC. The array substrate includes a plurality of first gate lines GL1, a plurality of second gate lines GL2, a plurality of data lines DL, a plurality of first voltage supply lines Vdd (e.g., a respective first voltage supply line Vdd), and a plurality of second voltage supply lines (e.g., a respective second voltage supply line Vss). Light emission by each sub-pixel Sp is driven by a respective pixel driving circuit PDC. In one example, a high voltage signal (e.g., a VDD signal) is input to the respective pixel driving circuit PDC connected to an anode of the light emitting element through a respective high voltage supply line Vdd; a low voltage signal (e.g., a VSS signal) is input to a cathode of the light emitting element through a low voltage supply line. The voltage difference between the high voltage signal (e.g., a VDD signal) and the low voltage signal (e.g., a VSS signal) is a driving voltage AV, which drives the light emitting element to emit light.

[0066] Figure 2A is a circuit diagram illustrating a structure of a pixel driving circuit according to some embodiments of the present disclosure. Referring to Figure 2A In some embodiments, the pixel driving circuit includes a drive transistor Td; a storage capacitor Cst having a first capacitor electrode Ce1 and a second capacitor electrode Ce2; a first reset transistor Tr1 having a gate connected to a respective first reset control signal line rst1 of a plurality of first reset control signal lines, a first electrode connected to a respective first reset signal line Vint1 of a plurality of first reset signal lines, and a second electrode connected to the first capacitor electrode Ce1 of the storage capacitor Cst and a gate of the drive transistor Td; a second reset transistor Tr2 having a gate connected to a respective second reset control signal line rst2 of a plurality of second reset control signal lines, a first electrode connected to a respective second reset signal line Vint2 of a plurality of second reset signal lines, and a second electrode connected to a second electrode of a fourth transistor T4 and an anode of a light emitting element LE; a third reset transistor Tr3 having a gate connected to a respective second reset control signal line rst2 of the plurality of second reset control signal lines, a first electrode connected to a respective third reset signal line Vint3 of a plurality of third reset signal lines, and a second electrode connected to a first electrode of the drive transistor Td; a first transistor T1 (e.g., a data write transistor) having a gate connected to a respective first gate line GL1 of a plurality of first gate lines, a first electrode connected to a respective data line DL of a plurality of data lines, and a second electrode connected to a first electrode of the drive transistor Td; a second transistor T2 (e.g., a compensation transistor) having a gate connected to a respective second gate line GL2 of a plurality of second gate lines, a first electrode connected to the first capacitor electrode Ce1 of the storage capacitor Cst and a gate of the drive transistor Td, and a second electrode connected to a second electrode of the drive transistor Td; a third transistor T3 having a gate connected to a respective light emission control signal line em of a plurality of light emission control signal lines, a first electrode connected to a respective first voltage supply line Vdd of a plurality of first voltage supply lines, and a second electrode connected to a first electrode of the drive transistor Td and a second electrode of the first transistor T1; and a fourth transistor T4 having a gate connected to a respective light emission control signal line em of the plurality of light emission control signal lines, a first electrode connected to the second electrode of the drive transistor Td and the second transistor T2, and a second electrode connected to the anode of the light emitting element LE and a second electrode of the second reset transistor Tr2. The second capacitor electrode Ce2 is connected to a respective voltage supply line and a first electrode of the third transistor T3.

[0067] In some embodiments, the pixel driving circuit includes a driving transistor Td, a data writing transistor (e.g., a first transistor T1), a compensation transistor (e.g., a second transistor T2), two light emitting control transistors (e.g., a third transistor T3 and a fourth transistor T4), and three reset transistors (e.g., a first reset transistor Tr1, a second reset transistor Tr2, and a third reset transistor Tr3).

[0068] As used herein, a first electrode or a second electrode refers to one of a first terminal and a second terminal of a transistor, the first terminal and the second terminal being connected to an active layer of the transistor. A direction of a current flowing through the transistor can be configured to be from the first electrode to the second electrode, or from the second electrode to the first electrode. Thus, depending on the direction of the current flowing through the transistor, in one example, the first electrode is configured to receive an input signal, and the second electrode is configured to output an output signal; in another example, the second electrode is configured to receive the input signal, and the first electrode is configured to output the output signal.

[0069] The pixel driving circuit further includes a first node N1, a second node N2, a third node N3, and a fourth node N4. The first node N1 is connected to a gate of the driving transistor Td, a first capacitor electrode Ce1, a first electrode of the second transistor T2, and a second electrode of the first reset transistor Tr1. The second node N2 is connected to a second electrode of the third transistor T3, a second electrode of the first transistor T1, a second electrode of the third reset transistor Tr3, and a first electrode of the driving transistor Td. The third node N3 is connected to a second electrode of the driving transistor Td, a second electrode of the second transistor T2, and a first electrode of the fourth transistor T4. The fourth node N4 is connected to a second electrode of the fourth transistor T4, a second electrode of the second reset transistor Tr2, and an anode of the light emitting element LE.

[0070] In some embodiments, the array substrate includes a plurality of sub-pixels. In some embodiments, the plurality of sub-pixels includes a respective first sub-pixel, a respective second sub-pixel, and a respective third sub-pixel. Optionally, each pixel of the array substrate includes a respective first sub-pixel, a respective second sub-pixel, and a respective third sub-pixel. The plurality of sub-pixels in the array substrate are arranged in an array. In one example, the array of the plurality of sub-pixels includes an S1-S2-S3 format repeating array, where S1 represents a respective first sub-pixel, S2 represents a respective second sub-pixel, and S3 represents a respective third sub-pixel. In another example, the S1-S2-S3 format is a C1-C2-C3 format, where C1 represents a respective first sub-pixel of a first color, C2 represents a respective second sub-pixel of a second color, and C3 represents a respective third sub-pixel of a third color. In another example, the C1-C2-C3 format is an R-G-B format, where each first sub-pixel is a red sub-pixel, each second sub-pixel is a green sub-pixel, and each third sub-pixel is a blue sub-pixel.

[0071] In another example, the array of the plurality of sub-pixels includes an S1-S2-S3-S4 format repeating array, where S1 represents a respective first sub-pixel, S2 represents a respective second sub-pixel, S3 represents a respective third sub-pixel, and S4 represents a respective fourth sub-pixel. In another example, the S1-S2-S3-S4 format is a C1-C2-C3-C4 format, where C1 represents a respective first sub-pixel of a first color, C2 represents a respective second sub-pixel of a second color, C3 represents a respective third sub-pixel of a third color, and C4 represents a respective fourth sub-pixel of a fourth color. In another example, the S1-S2-S3-S4 format is a C1-C2-C3-C2’ format, where C1 represents a respective first sub-pixel of a first color, C2 represents a respective second sub-pixel of a second color, C3 represents a respective third sub-pixel of a third color, and C2’ represents a respective fourth sub-pixel of a second color. In another example, the C1-C2-C3-C2’ format is an R-G-B-G format, where each first sub-pixel is a red sub-pixel, each second sub-pixel is a green sub-pixel, each third sub-pixel is a blue sub-pixel, and each fourth sub-pixel is a green sub-pixel.

[0072] In some embodiments, a minimum repeating unit of the plurality of sub-pixels of the array substrate includes a respective first sub-pixel, a respective second sub-pixel, and a respective third sub-pixel. Optionally, each of the respective first sub-pixel, the respective second sub-pixel, and the respective third sub-pixel includes a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a driving transistor Td, a first reset transistor Tr1, a second reset transistor Tr2, a third reset transistor Tr3, and a storage capacitor Cst.

[0073] In alternative embodiments, the minimum repeating unit of the plurality of sub-pixels of the array substrate comprises a respective first sub-pixel, a respective second sub-pixel, a respective third sub-pixel, and a respective fourth sub-pixel. Optionally, each first sub-pixel, each second sub-pixel, each third sub-pixel, and each fourth sub-pixel comprises a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a driving transistor Td, a first reset transistor Tr1, a second reset transistor Tr2, a third reset transistor Tr3, and a storage capacitor Cst.

[0074] The present disclosure can be implemented in pixel driving circuits having various types of transistors, including pixel driving circuits having p-type transistors, pixel driving circuits having n-type transistors, and pixel driving circuits having one or more p-type transistors and one or more n-type transistors. Referring to Figure 2A , the second transistor T2 and the first reset transistor are n-type transistors, e.g., metal-oxide transistors, while the other transistors are p-type transistors, e.g., polysilicon transistors. For p-type transistors, an active control signal (e.g., an on control signal) is a low voltage signal, while an inactive control signal (e.g., an off control signal) is a high voltage signal. For n-type transistors, an active control signal (e.g., an on control signal) is a high voltage signal, while an inactive control signal (e.g., an off control signal) is a low voltage signal.

[0075] Figure 2B is a timing diagram illustrating the operation of a pixel driving circuit in accordance with some embodiments of the present disclosure. Referring to Figure 2A and Figure 2B During a frame of an image, the operation of the pixel driving circuit comprises a reset sub-phase tl, a data write sub-phase t2, and a light emission sub-phase t3. In an initial sub-phase to, the first reset transistor Trl is turned off by providing an off reset control signal to the gate of the first reset transistor Trl via a respective first reset control signal line rstl. The second reset transistor Tr2 and the third reset transistor Tr3 are turned off by providing an off reset control signal to the gate of the second reset transistor Tr2 and to the gate of the third reset transistor Tr3 via a respective second reset control signal line rst2. In the initial sub-phase to, each of the first gate lines GLl and each of the second gate lines GL2 is provided with an off signal, so the first transistor Tl and the second transistor T2 are turned off.

[0076] In the reset sub-stage t1, a turn-on reset control signal is provided to the gate of the first reset transistor Tr1 through the first reset control signal line rst1 to turn on the first reset transistor Tr1; the initialization voltage signal from the corresponding first reset signal line Vint1 is allowed to pass from the first electrode of the first reset transistor Tr1 to the second electrode of the first reset transistor Tr1, and further to the first capacitor electrode Ce1 and the gate of the driving transistor Td. The gate of the driving transistor Td is initialized. The second capacitor electrode Ce2 receives a high voltage signal from the corresponding first voltage supply line Vdd. The first capacitor electrode Ce1 is charged in the reset sub-stage t1 due to the increase of the voltage difference between the first capacitor electrode Ce1 and the second capacitor electrode Ce2. In the reset sub-stage t1, each of the first gate lines GL1 and the second gate lines GL2 is provided with a turn-off signal, so the first transistor T1 and the second transistor T2 are turned off. The corresponding light-emitting control signal line em is provided with a high voltage signal to turn off the third transistor T3 and the fourth transistor T4.

[0077] In the data write sub-stage t2, a turn-off reset control signal is provided to the gate of the first reset transistor Tr1 through the corresponding first reset control signal line rst1 to turn off the first reset transistor Tr1. Each of the first gate lines GL1 and the second gate lines GL2 is provided with a turn-on signal, so the first transistor T1 and the second transistor T2 are turned on. The second electrode of the driving transistor Td is connected to the second electrode of the second transistor T2. The gate of the driving transistor Td is electrically connected to the first electrode of the second transistor T2. Since the second transistor T2 is turned on in the data write sub-stage t2, the gate and the second electrode of the driving transistor Td are connected and short-circuited, only the PN junction between the gate and the first electrode of the driving transistor Td is effective, so that the driving transistor Td is in a diode connection mode. The first transistor T1 is turned on in the data write sub-stage t2. The data voltage signal transmitted through the corresponding data line DL is received by the first electrode of the first transistor T1, and is transmitted to the first electrode of the driving transistor Td in turn, which is connected to the second electrode of the first transistor T1. The node N2 connected to the first electrode of the driving transistor Td has a voltage level of the data voltage signal. Since only the PN junction between the gate and the first electrode of the driving transistor Td is effective, the voltage level of the N1 node gradually increases to (Vdata+Vth) in the data write sub-stage t2, where Vdata is the voltage level of the data voltage signal, and Vth is the voltage level of the threshold voltage Th of the PN junction. Since the voltage difference between the first capacitor electrode Ce1 and the second capacitor electrode Ce2 decreases to a relatively small value, the storage capacitor Cst is discharged. The corresponding light-emitting control signal line em is provided with a high voltage signal to turn off the third transistor T3 and the fourth transistor T4.

[0078] In the data writing sub-phase t2, a turn-on reset control signal is provided to the gate of the second reset transistor Tr2 through the corresponding second reset control signal line rst2 to turn on the second reset transistor Tr2; the initialization voltage signal from the corresponding second reset signal line Vint2 is allowed to pass from the first electrode of the second reset transistor Tr2 to the second electrode of the second reset transistor Tr2; and in turn to the node N4. The anode of the light emitting element LE is initialized. A turn-off reset control signal is provided to the gate of the third reset transistor Tr3 through the corresponding second reset control signal line rst2 to turn off the third reset transistor Tr3; the initialization voltage signal from the corresponding second reset signal line Vint2 is allowed to pass from the first electrode of the third reset transistor Tr3 to the second electrode of the third reset transistor Tr3; and in turn to the node N2. The node N2 is initialized.

[0079] In the light emitting sub-phase t3, a turn-off reset control signal is again provided to the gate of the first reset transistor Tr1 through the corresponding first reset control signal line rst1 to turn off the first reset transistor Tr1. The first gate lines GL1 and the second gate lines GL2 are provided with turn-off signals respectively, and the first transistor T1 and the second transistor T2 are turned off. The corresponding light emitting control signal lines em are provided with low voltage signals to turn on the third transistor T3 and the fourth transistor T4. In the light emitting sub-phase t3, the voltage level of the node N1 is maintained at (Vdata+Vth), and the driving transistor Td is turned on by the voltage level and works in the saturation region. A path is formed via the third transistor T3, the driving transistor Td, the fourth transistor T4 to the light emitting element LE. The driving transistor Td generates a driving current for driving the light emitting element LE to emit light. The voltage level at the node N3 connected to the second electrode of the driving transistor Td is equal to the light emitting voltage of the light emitting element LE.

[0080] Figure 3A FIG. 1 is a schematic diagram illustrating a structure of a pixel driving circuit in an array substrate according to some embodiments of the present disclosure. Figure 3B FIG. 2 is a schematic diagram illustrating a structure of a first semiconductor material layer in the array substrate shown in FIG. 1. Figure 3A FIG. 3 is a schematic diagram illustrating a structure of a first gate metal layer in the array substrate shown in FIG. 1. Figure 3C FIG. 4 is a schematic diagram illustrating a structure of a second gate metal layer in the array substrate shown in FIG. 1. Figure 3A FIG. 5 is a schematic diagram illustrating a structure of a second semiconductor material layer in the array substrate shown in FIG. 1. Figure 3D FIG. 6 is a schematic diagram illustrating a structure of a third gate metal layer in the array substrate shown in FIG. 1. Figure 3A FIG. 7 is a schematic diagram illustrating a structure of a third semiconductor material layer in the array substrate shown in FIG. 1. Figure 3E FIG. 8 is a schematic diagram illustrating a structure of a fourth gate metal layer in the array substrate shown in FIG. 1. Figure 3A FIG. 9 is a schematic diagram illustrating a structure of a fourth semiconductor material layer in the array substrate shown in FIG. 1. Figure 3F FIG. 10 is a schematic diagram illustrating a structure of a fifth gate metal layer in the array substrate shown in FIG. 1. Figure 3A FIG. 11 is a schematic diagram illustrating a structure of a fifth semiconductor material layer in the array substrate shown in FIG. 1. Figure 3G FIG. 12 is a schematic diagram illustrating a structure of a sixth gate metal layer in the array substrate shown in FIG. 1. Figure 3A schematic diagram of a via extending through the first interlayer dielectric layer in the array substrate shown in Figure 3H is a schematic diagram showing Figure 3A schematic diagram of a via extending through the passivation layer in the array substrate shown in Figure 3I is a schematic diagram showing Figure 3A schematic diagram of the structure of the first signal line layer in the array substrate shown in Figure 3J is a schematic diagram showing Figure 3A schematic diagram of a via extending through the first planarization layer in the array substrate shown in Figure 3K is a schematic diagram showing Figure 3A schematic diagram of the structure of the second signal line layer in the array substrate shown in Figure 4A is a cross-sectional view along Figure 3A line A-A’ in Figure 4B is a cross-sectional view along Figure 3A line B-B’ in

[0081] Reference is made to Figures 3A to 3K and Figures 4A to 4B In some embodiments, the array substrate comprises a substrate base BS; a buffer layer BUF on the substrate base BS; a first semiconductor material layer SML1 on a side of the buffer layer BUF distal from the substrate base BS; a gate insulating layer GI on a side of the first semiconductor material layer SML1 distal from the substrate base BS; a first gate metal layer Gate1 on a side of the gate insulating layer GI distal from the first semiconductor material layer SML1; an insulating layer IN on a side of the first gate metal layer Gate1 distal from the gate insulating layer GI; a second gate metal layer Gate2 on a side of the insulating layer IN distal from the first gate metal layer Gate1; a first interlayer dielectric layer ILD1 on a side of the second gate metal layer Gate2 distal from the insulating layer IN; a second semiconductor material layer SML2 on a side of the first interlayer dielectric layer ILD1 distal from the second gate metal layer Gate2; a second interlayer dielectric layer ILD2 on a side of the second semiconductor material layer SML2 distal from the first interlayer dielectric layer ILD1; a third gate metal layer Gate3 on a side of the second interlayer dielectric layer ILD2 distal from the second semiconductor material layer SML2; a passivation layer PVX on a side of the third gate metal layer Gate3 distal from the second interlayer dielectric layer ILD2; a first signal line layer SD1 on a side of the passivation layer PVX distal from the third gate metal layer Gate3; a first planarization layer PLN1 on a side of the first signal line layer SD1 distal from the passivation layer PVX; a second signal line layer SD2 on a side of the first planarization layer PLN1 distal from the first signal line layer SD1; and a second planarization layer PLN2 on a side of the second signal line layer SD2 distal from the first planarization layer PLN1.

[0082] With reference to Figure 2A , Figure 3A , Figure 3B , Figure 4A and Figure 4B In some embodiments, the first semiconductor material layer SML1 comprises at least active layers of a plurality of transistors of the pixel driving circuit, including the first transistor T1, the third transistor T3, the fourth transistor T4, the second reset transistor Tr2, the third reset transistor Tr3, and the driving transistor Td. Optionally, the first semiconductor material layer SML1 further comprises at least respective portions of first electrodes of the plurality of transistors of the pixel driving circuit, including the first transistor T1, the third transistor T3, the fourth transistor T4, the second reset transistor Tr2, the third reset transistor Tr3, and the driving transistor Td. Optionally, the first semiconductor material layer SML1 further comprises at least respective portions of second electrodes of the plurality of transistors of the pixel driving circuit, including the first transistor T1, the third transistor T3, the fourth transistor T4, the second reset transistor Tr2, the third reset transistor Tr3, and the driving transistor Td. Optionally, the first semiconductor material layer SML1 comprises the active layers, the first electrodes, and the second electrodes of the plurality of transistors of the pixel driving circuit, including the first transistor T1, the third transistor T3, the fourth transistor T4, the second reset transistor Tr2, the third reset transistor Tr3, and the driving transistor Td. Various suitable semiconductor materials can be used to fabricate the first semiconductor material layer SML1. Examples of semiconductor materials used to fabricate the first semiconductor material layer SML1 include silicon-based semiconductor materials, such as polysilicon, monocrystalline silicon, and amorphous silicon.

[0083] Figure 3B The components of each of the plurality of transistors (T1, T3, T4, Tr2, Tr3, and Td) in the pixel driving circuit are labeled with labels. For example, the first transistor T1 comprises an active layer ACT1, a first electrode S1, and a second electrode D1. The third transistor T3 comprises an active layer ACT3, a first electrode S3, and a second electrode D3. The fourth transistor T4 comprises an active layer ACT4, a first electrode S4, and a second electrode D4. The second reset transistor Tr2 comprises an active layer ACTr2, a first electrode Sr2, and a second electrode Dr2. The third reset transistor Tr3 comprises an active layer ACTr3, a first electrode Sr3, and a second electrode Dr3. The driving transistor Td comprises an active layer ACTd, a first electrode Sd, and a second electrode Dd.

[0084] Optionally, the active layers (ACT1, ACT3, ACT4, ACTr2, ACTr3, and ACTd), the first electrodes (S1, S3, S4, Sr2, Sr3, and Sd), and the second electrodes (D1, D3, D4, Dr2, Dr3, and Dd) of the respective transistors (T1, T3, T4, Tr2, Tr3, and Td) are located in the same layer.

[0085] In some embodiments, the active layers (ACT1, ACT3, ACT4, ACTr2, and ACTd) of the plurality of transistors (T1, T3, T4, Tr2, and Td), at least part of the first electrodes (S1, S3, S4, Sr2, and Sd), and at least part of the second electrodes (D1, D3, D4, Dr2, and Dd) in the pixel driving circuit are part of the monolithic structure. Optionally, in the same pixel driving circuit, a portion of the third reset transistor Tr3 (ACTr3, Sr3, Dr3) in the first semiconductor material layer is spaced apart from the monolithic structure (T1, T3, T4, Tr2, and Td).

[0086] Reference is made to Figure 2A , Figure 3A , Figure 3C , Figure 4A and Figure 4B In some embodiments, the first gate metal layer Gate1 includes a plurality of first gate lines (e.g., a respective first gate line first branch GL1-1), a plurality of light emission control signal lines (e.g., a respective light emission control signal line em), a first gate pad GEP1, a second gate pad GEP2, and at least part of a first capacitor electrode Ce1 of a storage capacitor Cst.

[0087] In some embodiments, each first gate line includes a plurality of branches respectively located at a plurality of layers. In one example, each first gate line includes a respective first gate line first branch GL1-1 in the first gate metal layer Gate1 (as shown in FIG. 1A) and a respective first gate line second branch GL1-2 in the first signal line layer SD1 (as shown in FIG. 1A). Figure 3C Figure 3I Optionally, a footprint of each first gate line first branch GL1-1 on the substrate BS at least partially (e.g., at least 80%, at least 85%, at least 90%, at least 95%, at least 98%, or at least 99%) overlaps with a footprint of the respective first gate line second branch GL1-2 on the substrate BS.

[0088] ​Various suitable electrode materials and various suitable fabrication methods can be used to fabricate the first gate metal layer Gate1. For example, the conductive material can be deposited on the substrate and patterned by a plasma-enhanced chemical vapor deposition (PECVD) process. Examples of suitable conductive materials for fabricating the first gate metal layer Gate1 include, but are not limited to, aluminum, copper, molybdenum, chromium, aluminum-copper alloy, copper-molybdenum alloy, molybdenum-aluminum alloy, aluminum-chromium alloy, copper-chromium alloy, molybdenum-chromium alloy, copper-molybdenum-aluminum alloy, etc. Optionally, at least portions of the plurality of first gate lines (e.g., respective first gate lines first branch GL1-1), the plurality of light emission control signal lines (e.g., respective light emission control signal lines em), the first gate pad GEP1, the second gate pad GEP2, and the first capacitor electrode Ce1 of the storage capacitor Cst are located in the same layer.

[0089] As used herein, the term “same layer” refers to a relationship between layers that are formed simultaneously in the same step. In one example, the plurality of light emission control signal lines and the first capacitor electrode Ce1 are located in the same layer when the plurality of light emission control signal lines and the first capacitor electrode Ce1 are formed due to one or more steps of a same patterning process performed in a same layer of material. In another example, the plurality of light emission control signal lines and the first capacitor electrode Ce1 can be formed in the same layer by simultaneously performing a step of forming the plurality of light emission control signal lines and a step of forming the first capacitor electrode Ce1. The term “same layer” does not always mean that the thickness of the layers or the height of the layers are the same in a cross-sectional view.

[0090] In some embodiments, the first gate pad GEP1 includes a gate Gr2 of a second reset transistor Tr2 in the pixel driving circuit. In some embodiments, the second gate pad GEP2 includes a gate Gr3 of a third reset transistor Tr3 in the pixel driving circuit. The first gate pad GEP1 and the second gate pad GEP2 are respectively connected to respective second reset control signal lines rst2 in the plurality of second reset control signal lines.

[0091] Reference is made to Figure 2A , Figure 3A , Figure 3D , Figure 4A and Figure 4BIn some embodiments, the second gate metal layer Gate2 includes a plurality of first reset control signal lines (e.g., respective first reset control signal line first branches rst1-1), a plurality of second gate lines (e.g., respective second gate lines GL2), a plurality of third reset signal lines (e.g., respective third reset signal lines Vint3), and at least portions of second capacitor electrodes Ce2 of storage capacitors Cst. Various suitable electrode materials and various suitable fabrication methods can be used to fabricate the second gate metal layer Gate2. For example, the conductive material can be deposited on the substrate by a plasma-enhanced chemical vapor deposition (PECVD) process and patterned. Examples of suitable conductive materials for fabricating the second gate metal layer Gate2 include, but are not limited to, aluminum, copper, molybdenum, chromium, aluminum-copper alloy, copper-molybdenum alloy, molybdenum-aluminum alloy, aluminum-chromium alloy, copper-chromium alloy, molybdenum-chromium alloy, copper-molybdenum-aluminum alloy, etc. Optionally, the plurality of first reset control signal lines (e.g., respective first reset control signal line first branches rst1-1), the plurality of second gate lines (e.g., respective second gate lines GL2), the plurality of third reset signal lines (e.g., respective third reset signal lines Vint3), and at least portions of second capacitor electrodes Ce2 of storage capacitors Cst are located in the same layer.

[0092] In some embodiments, each of the plurality of first reset control signal lines includes a plurality of branches located in a plurality of layers, respectively. In one example, each of the plurality of first reset control signal lines includes a respective first reset control signal line first branch rst1-1 in the second gate metal layer Gate2 (as shown in Figure 3D FIG. 2B) and a respective first reset control signal line second branch rst1-2 in the first signal line layer SD1 (as shown in Figure 3I FIG. 2B). Optionally, a footprint of the respective first reset control signal line first branch rst1-1 on the substrate BS at least partially (e.g., at least 80%, at least 85%, at least 90%, at least 95%, at least 98%, or at least 99%) overlaps with a footprint of the respective first reset control signal line second branch rst1-2 on the substrate BS.

[0093] Referring to Figure 2A , Figure 3A , Figure 3E , Figure 4A , and Figure 4BIn some embodiments, the second semiconductor material layer SML2 includes at least the active layer ACT2 of the second transistor T2 and the active layer ACTr1 of the first reset transistor Tr1. Optionally, the second semiconductor material layer SML2 further includes at least a portion of the first electrode S2 of the second transistor T2 and at least a portion of the first electrode Sr1 of the first reset transistor Tr1. Optionally, the second semiconductor material layer SML2 further includes at least a portion of the second electrode D2 of the second transistor T2 and at least a portion of the second electrode Dr1 of the first reset transistor Tr1. Optionally, the second semiconductor material layer SML2 includes the active layer ACT2, the first electrode S2 and the second electrode D2 of the second transistor T2; and the active layer ACTr1, the first electrode Sr1 and the second electrode Dr1 of the first reset transistor Tr1. In the present array substrate, at least the active layer ACT2 of the second transistor T2 and the active layer ACTr1 of the first reset transistor Tr1 are located in a layer different from at least the active layer of the other transistors. Various suitable semiconductor materials can be used to fabricate the second semiconductor material layer SML2. Examples of semiconductor materials used to fabricate the second semiconductor material layer SML2 include metal oxide-based semiconductor materials (e.g., indium gallium zinc oxide) and metal oxynitride-based semiconductor materials (e.g., zinc oxynitride).

[0094] Figure 3E The components of the second transistor T2 and the first reset transistor Tr1 are labeled with labels. For example, the second transistor T2 includes the active layer ACT2, the first electrode S2 and the second electrode D2; and the first reset transistor Tr1 includes the active layer ACTr1, the first electrode Sr1 and the second electrode Dr1. Optionally, the active layer ACT2, the first electrode S2 and the second electrode D2 of the second transistor T2; and the active layer ACTr1, the first electrode Sr1 and the second electrode Dr1 of the first reset transistor Tr1 are located in the same layer. Optionally, the active layer ACT2 of the second transistor T2 and the active layer ACTr1 of the first reset transistor Tr1 are part of an integral structure. Optionally, the active layer ACT2, the first electrode S2 and the second electrode D2 of the second transistor T2; and the active layer ACTr1, the first electrode Sr1 and the second electrode Dr1 of the first reset transistor Tr1 are part of an integral structure.

[0095] Referring to Figure 2A , Figure 3A , Figure 3F , Figure 4A and Figure 4BIn some embodiments, the third gate metal layer Gate3 includes a third gate pad GEP3 and a fourth gate pad GEP4. Various suitable electrode materials and various suitable fabrication methods can be used to fabricate the third gate metal layer Gate3. For example, the conductive material can be deposited on the substrate by a plasma-enhanced chemical vapor deposition (PECVD) process and patterned. Examples of suitable conductive materials for fabricating the third gate metal layer Gate3 include, but are not limited to, aluminum, copper, molybdenum, chromium, aluminum-copper alloy, copper-molybdenum alloy, molybdenum-aluminum alloy, aluminum-chromium alloy, copper-chromium alloy, molybdenum-chromium alloy, copper-molybdenum-aluminum alloy, etc. Optionally, the third gate pad GEP3 and the fourth gate pad GEP4 are located in the same layer.

[0096] In some embodiments, the third gate pad GEP3 includes a gate G2 of a second transistor T2 in the pixel driving circuit. In some embodiments, the fourth gate pad GEP4 includes a gate Gr1 of a first reset transistor Tr1 in the pixel driving circuit. The third gate pad GEP3 is connected to a respective second gate line GL2 in the plurality of second gate lines through a gate connection pad GCP. The fourth gate pad GEP4 is connected to a respective first reset control signal line rst1 in the plurality of first reset control signal lines. Figure 3I Figure 3I In some embodiments, the fourth gate pad GEP4 is connected to a respective first reset control signal line second branch rst1-2 in the plurality of first reset control signal lines.

[0097] Figure 3G A via extending through the first interlayer dielectric layer ILD1 is shown.

[0098] Figure 3H A via extending through the passivation layer PVX is shown in

[0099] Reference is made to Figure 2A , Figure 3A , Figure 3I , Figure 4A and Figure 4B In some embodiments, the first signal line layer SD1 includes a plurality of first reset signal lines (e.g., a respective first reset signal line Vint1), a plurality of second reset signal lines (e.g., a respective second reset signal line Vint2), at least part of a plurality of first reset control signal lines (e.g., a respective first reset control signal line second branch rst1-2), at least part of a plurality of first gate lines (e.g., a respective first gate line second branch GL1-2), a plurality of second reset control signal lines (e.g., a respective second reset control signal line rst2), a gate connection pad GCP, a relay electrode RE, a first node connection line Cln1, a second node connection line Cln2, a third node connection line Cln3, a voltage connection pad VCP, a data signal connection pad DCP, and a reset signal connection pad Cli. ​

[0100] Various suitable conductive materials and various suitable fabrication methods can be used to fabricate the first signal line layer SD1. For example, the conductive material can be deposited on the substrate and patterned by a plasma-enhanced chemical vapor deposition (PECVD) process. Examples of suitable conductive materials for fabricating the first signal line layer include, but are not limited to, titanium, aluminum, copper, molybdenum, chromium, aluminum-copper alloy, copper-molybdenum alloy, molybdenum-aluminum alloy, aluminum-chromium alloy, copper-chromium alloy, molybdenum-chromium alloy, copper-molybdenum-aluminum alloy, etc. In some embodiments, the first signal line layer includes multiple sub-layers stacked together. In one example, the first signal line layer includes a stacked titanium / aluminum / titanium multi-layer structure. In another example, the first signal line layer includes a stacked molybdenum / aluminum / molybdenum multi-layer structure.

[0101] Optionally, the plurality of first reset signal lines (e.g., a respective first reset signal line Vint1), the plurality of second reset signal lines (e.g., a respective second reset signal line Vint2), at least part of the plurality of first reset control signal lines (e.g., a respective first reset control signal line second branch rst1-2), at least part of the plurality of first gate lines (e.g., a respective first gate line second branch GL1-2), the plurality of second reset control signal lines (e.g., a respective second reset control signal line rst2), the gate connection pad GCP, the relay electrode RE, the first node connection line Cln1, the second node connection line Cln2, the third node connection line Cln3, the voltage connection pad VCP, the data signal connection pad DCP, and the reset signal connection pad Cli are located in the same layer.

[0102] In some embodiments, the first node connection line Cln1 in the pixel driving circuit connects multiple components of the pixel driving circuit to the node N1. Referring to Figure 4A , the first node connection line Cln1 is connected to the first capacitor electrode Ce1 through a first via v1 and to the second transistor T2 (e.g., to the first electrode S2 of the second transistor T2) through a second via v2. Optionally, the first node connection line Cln1 corresponds to the node N1 described in Figure 2A .

[0103] Referring to Figure 2A , Figure 3A , Figure 3C , Figure 3D and Figure 4AIn some embodiments, in the hole region H, a portion of the second capacitor electrode Ce2 is absent. Optionally, in addition to the hole region H in which a portion of the second capacitor electrode Ce2 is absent, the second capacitor electrode Ce2 on the substrate BS substantially (e.g., at least 80%, at least 85%, at least 90%, at least 95%, at least 98%, at least 99%, or 100%) covers and is larger than the footprint of the first capacitor electrode Cel on the substrate BS. Optionally, the first via vl extends through the passivation layer PVX, the second interlayer dielectric layer ILD2, the first interlayer dielectric layer ILD1, the hole region H, and the insulating layer IN.

[0104] In some embodiments, the first node connection line Clnl intersects with a respective second gate line GL2 of the plurality of second gate lines. As shown in Figure 3A 、 Figure 3D and Figure 4A , the first node connection line Clnl intersects with a respective second gate line of the second gate metal layer Gate2. The footprint of the first node connection line Clnl on the substrate BS at least partially overlaps with the footprint of the respective second gate line on the substrate BS.

[0105] Referring to Figure 3A 、 Figure 3I 、 Figure 3K and Figure 4A , the data signal connection pad DCP in the pixel driving circuit connects a respective data line DL to the first electrode S1 of the first transistor T1, and the data signal provided by the respective data line DL is transmitted to the first electrode S1 of the first transistor T1 through the signal connection pad DCP.

[0106] In some embodiments, each of the first gate lines comprises a plurality of branches respectively located at a plurality of layers. In one example, each of the first gate lines comprises a respective first gate line first branch GL1-1 (as shown in Figure 3C ) in the first gate metal layer Gate1 and a respective first gate line second branch GL1-2 (as shown in Figure 3I ) in the first signal line layer SD1. Optionally, the footprint of the respective first gate line first branch GL1-1 on the substrate BS at least partially (e.g., at least 80%, at least 85%, at least 90%, at least 95%, at least 98%, or at least 99%) overlaps with the footprint of the respective first gate line second branch GL1-2 on the substrate BS.

[0107] In some embodiments, each of the first reset control signal lines comprises a plurality of branches respectively located at a plurality of layers. In one example, each of the first reset control signal lines comprises a respective first reset control signal line first branch rst1-1 (as shown in Figure 3D The respective first reset control signal line first branch rst1-1 is connected to the respective first reset control signal line second branch rst1-2 in the first signal line layer SD1 (as shown in FIG. 1A). Figure 3I Optionally, the orthogonal projection of the respective first reset control signal line first branch rst1-1 onto the substrate BS at least partially (e.g., at least 80%, at least 85%, at least 90%, at least 95%, at least 98%, or at least 99%) overlaps with the orthogonal projection of the respective first reset control signal line second branch rst1-2 onto the substrate BS.

[0108] Referring to Figure 3A , Figure 3D , Figure 3F , Figure 3I , Figure 4A and Figure 4B The gate connection pad GCP connects a third gate pad GEP3 in the third gate metal layer Gate3 to a respective second gate line GL2 of a plurality of second gate lines in the second gate metal layer Gate2. The gate scan signal provided by the respective second gate line GL2 is transmitted to the gate G2 of the second transistor T2 through the gate connection pad GCP. Referring to Figure 4B The gate connection pad GCP is connected to the respective second gate line GL2 through a fifth via v5 and to the third gate pad GEP3 through a sixth via v6. In one example, the fifth via v5 extends through the passivation layer PVX, the second interlayer dielectric layer ILD2, and the first interlayer dielectric layer ILD1. In another example, the sixth via v6 extends through the passivation layer PVX.

[0109] Referring to Figure 3A , Figure 3D , Figure 3I , Figure 3K , Figure 4A and Figure 4B The voltage connection pad VCP connects the respective first voltage supply line Vdd to the second capacitor electrode Ce2 of the storage capacitor. Referring to Figure 4A The respective first voltage supply line Vdd is connected to the voltage connection pad VCP through a third via v3. The voltage connection pad VCP is connected to the second capacitor electrode Ce2 of the storage capacitor through a fourth via v4. In one example, the third via v3 extends through the first planarization layer PLN1. In another example, the fourth via v4 extends through the passivation layer PVX, the second interlayer dielectric layer ILD2, and the first interlayer dielectric layer ILD1.

[0110] Referring to Figure 3A , Figure 3B , Figure 3I , Figure 3K , Figure 4A and Figure 4BThe relay electrode RE connects the anode connection pad ACP and the second electrode D4 of the fourth transistor T4 in the pixel drive circuit. The anode connection pad ACP is also connected to the anode of the light emitting element.

[0111] Referring to Figure 3A , Figure 3B , Figure 3D , Figure 3I , Figure 4A and Figure 4B The reset signal connection line Cli connects the corresponding third reset signal line Vint3 and the first electrode Sr3 of the third reset transistor Tr3 in the pixel drive circuit, thereby providing a reset signal to the first electrode Sr3 of the third reset transistor Tr3 in the pixel drive circuit.

[0112] Referring to Figure 3A , Figure 3B , Figure 3I , Figure 4A and Figure 4B The second node connection line Cln2 in the pixel drive circuit is connected to the second electrode D3 of the third transistor T3 in the pixel drive circuit, and to the second electrode Dr3 of the third reset transistor Tr3 in the pixel drive circuit.

[0113] Referring to Figure 3A , Figure 3B , Figure 3I , Figure 4A and Figure 4B The third node connection line Cln3 in the pixel drive circuit is connected to the second electrode D2 of the second transistor T2 in the pixel drive circuit, and to the second electrode Dd of the drive transistor Td and the first electrode S4 of the fourth transistor T4 in the pixel drive circuit.

[0114] Figure 3J A via extending through the first planarization layer PLN1 is shown.

[0115] Referring to Figure 2A , Figure 3A , Figure 3K , Figure 4A and Figure 4BIn some embodiments, the second signal line layer SD2 includes a plurality of first voltage supply lines (e.g., respective first voltage supply lines Vdd), a plurality of second voltage supply lines (e.g., respective second voltage supply lines Vss), a plurality of data lines (e.g., respective data lines DL), and anode contact pads ACP. Various suitable conductive materials and various suitable fabrication methods can be used to fabricate the second signal line layer SD2. For example, the conductive material can be deposited on the substrate by a plasma-enhanced chemical vapor deposition (PECVD) process and patterned. Examples of suitable conductive materials for fabricating the second signal line layer SD2 include, but are not limited to, titanium, aluminum, copper, molybdenum, chromium, aluminum-copper alloy, copper-molybdenum alloy, molybdenum-aluminum alloy, aluminum-chromium alloy, copper-chromium alloy, molybdenum-chromium alloy, copper-molybdenum-aluminum alloy, etc. In some embodiments, the second signal line layer includes a plurality of sub-layers stacked together. In one example, the second signal line layer includes a stacked titanium / aluminum / titanium multi-layer structure. In another example, the second signal line layer includes a stacked molybdenum / aluminum / molybdenum multi-layer structure. Optionally, the plurality of first voltage supply lines (e.g., respective first voltage supply lines Vdd), the plurality of second voltage supply lines (e.g., respective second voltage supply lines Vss), the plurality of data lines (e.g., respective data lines DL), and the anode contact pads ACP are located in the same layer.

[0116] In some embodiments, the plurality of first voltage supply lines are configured to provide a first reference voltage signal. Optionally, the plurality of second voltage supply lines are configured to provide a second reference voltage signal. Optionally, the second reference voltage signal is different from the first reference voltage signal. In one example, the first reference voltage signal is a constant voltage signal, e.g., a high reference voltage signal. In another example, the second reference voltage signal is a constant voltage signal, e.g., a low reference voltage signal.

[0117] Figure 5A FIG. 1 is a schematic diagram illustrating a structure of a pixel driving circuit in an array substrate according to some embodiments of the present disclosure. Figure 5B FIG. 2 is a schematic diagram illustrating a structure of a first semiconductor material layer in the array substrate shown in FIG. 1. Figure 5A FIG. 3 is a schematic diagram illustrating a structure of a first gate metal layer in the array substrate shown in FIG. 1. Figure 5C FIG. 4 is a schematic diagram illustrating a structure of a second gate metal layer in the array substrate shown in FIG. 1. Figure 5A FIG. 5 is a schematic diagram illustrating a structure of a second semiconductor material layer in the array substrate shown in FIG. 1. Figure 5D FIG. 6 is a schematic diagram illustrating a structure of a third gate metal layer in the array substrate shown in FIG. 1. Figure 5A FIG. 7 is a schematic diagram illustrating a structure of a third semiconductor material layer in the array substrate shown in FIG. 1. Figure 5E FIG. 8 is a schematic diagram illustrating a structure of a fourth gate metal layer in the array substrate shown in FIG. 1. Figure 5A FIG. 9 is a schematic diagram illustrating a structure of a fourth semiconductor material layer in the array substrate shown in FIG. 1. Figure 5F FIG. 10 is a schematic diagram illustrating a structure of a fifth gate metal layer in the array substrate shown in FIG. 1. Figure 5A FIG. 11 is a schematic diagram illustrating a structure of a fifth semiconductor material layer in the array substrate shown in FIG. 1. Figure 5G FIG. 12 is a schematic diagram illustrating a structure of a sixth gate metal layer in the array substrate shown in FIG. 1. Figure 5AA schematic diagram of a via extending through the first interlayer dielectric layer in an array substrate shown. Figure 5H It is shown Figure 5A A schematic diagram of a via extending through a passivation layer in an array substrate shown. Figure 5I It is shown Figure 5A The diagram shows a schematic of the structure of the first signal line layer in the array substrate. Figure 5J It is shown Figure 5A A schematic diagram of a via extending through the first planarization layer in an array substrate shown. Figure 5K It is shown Figure 5A The diagram shows a schematic of the structure of the second signal line layer in the array substrate. Figure 6A It is along Figure 5A A cross-sectional view of the C-C' line in the diagram. Figure 6B It is along Figure 5A A cross-sectional view of the D-D' line in the diagram.

[0118] refer to Figures 5A to 5K as well as Figures 6A to 6B In some embodiments, the array substrate includes: a substrate BS; a buffer layer BUF located on the substrate BS; a first semiconductor material layer SML1 located on the side of the buffer layer BUF away from the substrate BS; a gate insulating layer GI located on the side of the first semiconductor material layer SML1 away from the substrate BS; a first gate metal layer Gate1 located on the side of the gate insulating layer GI away from the first semiconductor material layer SML1; an insulating layer IN located on the side of the first gate metal layer Gate1 away from the gate insulating layer GI; a second gate metal layer Gate2 located on the side of the insulating layer IN away from the first gate metal layer Gate1; a first interlayer dielectric layer ILD1 located on the side of the second gate metal layer Gate2 away from the insulating layer IN; and a second semiconductor material layer SML2 located on the side of the first interlayer dielectric layer ILD1 away from the second semiconductor material layer SML1. One side of the gate metal layer Gate2; the second interlayer dielectric layer ILD2, located on the side of the second semiconductor material layer SML2 away from the first interlayer dielectric layer ILD1; the third gate metal layer Gate3, located on the side of the second interlayer dielectric layer ILD2 away from the second semiconductor material layer SML2; the passivation layer PVX, located on the side of the third gate metal layer Gate3 away from the second interlayer dielectric layer ILD2; the first signal line layer SD1, located on the side of the passivation layer PVX away from the third gate metal layer Gate3; the first planarization layer PLN1, located on the side of the first signal line layer SD1 away from the passivation layer PVX; the second signal line layer SD2, located on the side of the first planarization layer PLN1 away from the first signal line layer SD1; and the second planarization layer PLN2, located on the side of the second signal line layer SD2 away from the first planarization layer PLN1.

[0119] Reference Figure 2A 、 Figure 5A 、 Figure 5B 、 Figure 6A and Figure 6B In some embodiments, the first semiconductor material layer SML1 includes at least active layers of a plurality of transistors of the pixel driving circuit, including the first transistor T1, the third transistor T3, the fourth transistor T4, the second reset transistor Tr2, the third reset transistor Tr3, and the driving transistor Td. Optionally, the first semiconductor material layer SML1 further includes at least respective portions of first electrodes of the plurality of transistors of the pixel driving circuit, including the first transistor T1, the third transistor T3, the fourth transistor T4, the second reset transistor Tr2, the third reset transistor Tr3, and the driving transistor Td. Optionally, the first semiconductor material layer SML1 further includes at least respective portions of second electrodes of the plurality of transistors of the pixel driving circuit, including the first transistor T1, the third transistor T3, the fourth transistor T4, the second reset transistor Tr2, the third reset transistor Tr3, and the driving transistor Td. Optionally, the first semiconductor material layer SML1 includes the active layers, the first electrodes, and the second electrodes of the plurality of transistors of the pixel driving circuit, including the first transistor T1, the third transistor T3, the fourth transistor T4, the second reset transistor Tr2, the third reset transistor Tr3, and the driving transistor Td. Various suitable semiconductor materials can be used to fabricate the first semiconductor material layer SML1. Examples of semiconductor materials used to fabricate the first semiconductor material layer SML1 include silicon-based semiconductor materials, such as polysilicon, monocrystalline silicon, and amorphous silicon.

[0120] Figure 5B The components of each of the plurality of transistors (T1, T3, T4, Tr2, Tr3, and Td) in the pixel driving circuit are labeled with labels. For example, the first transistor T1 includes an active layer ACT1, a first electrode S1, and a second electrode D1. The third transistor T3 includes an active layer ACT3, a first electrode S3, and a second electrode D3. The fourth transistor T4 includes an active layer ACT4, a first electrode S4, and a second electrode D4. The second reset transistor Tr2 includes an active layer ACTr2, a first electrode Sr2, and a second electrode Dr2. The third reset transistor Tr3 includes an active layer ACTr3, a first electrode Sr3, and a second electrode Dr3. The driving transistor Td includes an active layer ACTd, a first electrode Sd, and a second electrode Dd.

[0121] Optionally, the active layers (ACT1, ACT3, ACT4, ACTr2, ACTr3, and ACTd), the first electrodes (S1, S3, S4, Sr2, Sr3, and Sd), and the second electrodes (D1, D3, D4, Dr2, Dr3, and Dd) of the respective transistors (T1, T3, T4, Tr2, Tr3, and Td) are located in the same layer.

[0122] In some embodiments, the active layers (ACT1, ACT3, ACT4, ACTr2, and ACTd) of the plurality of transistors (T1, T3, T4, Tr2, and Td), at least portions of the first electrodes (S1, S3, S4, Sr2, and Sd), and at least portions of the second electrodes (D1, D3, D4, Dr2, and Dd) in the pixel driving circuit are part of the monolithic structure. Optionally, in the same pixel driving circuit, a portion of the third reset transistor Tr3 (ACTr3, Sr3, Dr3) in the first semiconductor material layer is spaced apart from the monolithic structure (T1, T3, T4, Tr2, and Td).

[0123] Reference is made to Figure 2A , Figure 5A , Figure 5C , Figure 6A and Figure 6B In some embodiments, the first gate metal layer Gate1 includes a plurality of first gate lines (e.g., a respective first gate line first branch GL1-1), a plurality of light emission control signal lines (e.g., a respective light emission control signal line em), a first gate pad GEP1, a second gate pad GEP2, and at least portions of the first capacitor electrode Ce1 of the storage capacitor Cst. Figure 5A The array substrate shown in Figure 3A differs from the array substrate shown in Figure 5A at least in that the first gate metal layer Gate1 in the array substrate shown in further includes a first node connection line Cln1.

[0124] In some embodiments, the first node connection line Cln1 in the pixel driving circuit connects a plurality of components of the pixel driving circuit to the node N1. Referring to Figure 6A , the first node connection line Cln1 is connected to the first capacitor electrode Ce1 and to the second transistor T2 (e.g., to the first electrode S2 of the second transistor T2) through a node connection pad NCP in the first signal line layer SD1. Optionally, the first node connection line Cln1 corresponds to the node N1 described in Figure 2A .

[0125] In some embodiments, the first node connection line Cln1 crosses a respective second gate line GL2 of the plurality of second gate lines. As shown in Figure 5A , Figure 5D and Figure 6A , the first node connection line Cln1 crosses a respective second gate line in the second gate metal layer Gate2. The orthogonal projection of the first node connection line Cln1 on the substrate substrate at least partially overlaps the orthogonal projection of the respective second gate line on the substrate substrate.

[0126] In some embodiments, the first node connection line Clnl and the first capacitor electrode Cel of the storage capacitor Cst are part of an integral structure. The first node connection line Clnl extends away from the first capacitor electrode Cel of the storage capacitor Cst.

[0127] In some embodiments, each of the first gate lines includes a plurality of branches respectively in a plurality of layers. In one example, each of the first gate lines includes a respective first gate line first branch GL1-1 (as shown) in the first gate metal layer Gate1 and a respective first gate line second branch GL1-2 (as shown) in the first signal line layer SD1. Optionally, the orthogonal projection of each first gate line first branch GL1-1 on the substrate BS at least partially (e.g., at least 80%, at least 85%, at least 90%, at least 95%, at least 98%, or at least 99%) overlaps with the orthogonal projection of the respective first gate line second branch GL1-2 on the substrate BS. Figure 5C Figure 5I In some embodiments, each of the first gate lines includes a plurality of branches respectively in a plurality of layers. In one example, each of the first gate lines includes a respective first gate line first branch GL1-1 (as shown) in the first gate metal layer Gate1 and a respective first gate line second branch GL1-2 (as shown) in the first signal line layer SD1. Optionally, the orthogonal projection of each first gate line first branch GL1-1 on the substrate BS at least partially (e.g., at least 80%, at least 85%, at least 90%, at least 95%, at least 98%, or at least 99%) overlaps with the orthogonal projection of the respective first gate line second branch GL1-2 on the substrate BS.

[0128] Various suitable electrode materials and various suitable fabrication methods can be used to fabricate the first gate metal layer Gate1. For example, the conductive material can be deposited on the substrate by a plasma-enhanced chemical vapor deposition (PECVD) process and patterned. Examples of suitable conductive materials for fabricating the first gate metal layer Gate1 include, but are not limited to, aluminum, copper, molybdenum, chromium, aluminum-copper alloy, copper-molybdenum alloy, molybdenum-aluminum alloy, aluminum-chromium alloy, copper-chromium alloy, molybdenum-chromium alloy, copper-molybdenum-aluminum alloy, etc. Optionally, at least portions of the plurality of first gate lines (e.g., the respective first gate line first branches GL1-1), the plurality of light emission control signal lines (e.g., the respective light emission control signal lines em), the first gate pad GEP1, the second gate pad GEP2, the first capacitor electrode Cel of the storage capacitor Cst, and the first node connection line Clnl are in the same layer.

[0129] In some embodiments, the first gate pad GEP1 includes a gate Gr2 of a second reset transistor Tr2 in the pixel driving circuit. In some embodiments, the second gate pad GEP2 includes a gate Gr3 of a third reset transistor Tr3 in the pixel driving circuit. The first gate pad GEP1 and the second gate pad GEP2 are respectively connected to a respective second reset control signal line rst2 in the plurality of second reset control signal lines.

[0130] Reference is made to Figure 2A , Figure 5A , Figure 5D , Figure 6A and Figure 6B ​In some embodiments, the second gate metal layer Gate2 includes the plurality of first reset control signal lines (e.g., the respective first reset control signal line first branch rst1-1), the plurality of third reset signal lines (e.g., the respective third reset signal line Vint3), the gate connection pad GCP, and at least part of the second capacitor electrode Ce2 of the storage capacitor Cst. Various suitable electrode materials and various suitable fabrication methods can be used to fabricate the second gate metal layer Gate2. For example, the conductive material can be deposited on the substrate by a plasma-enhanced chemical vapor deposition (PECVD) process and patterned. Examples of suitable conductive materials for fabricating the second gate metal layer Gate2 include, but are not limited to, aluminum, copper, molybdenum, chromium, aluminum-copper alloy, copper-molybdenum alloy, molybdenum-aluminum alloy, aluminum-chromium alloy, copper-chromium alloy, molybdenum-chromium alloy, copper-molybdenum-aluminum alloy, etc. Optionally, the plurality of first reset control signal lines (e.g., the respective first reset control signal line first branch rst1-1), the plurality of third reset signal lines (e.g., the respective third reset signal line Vint3), the gate connection pad GCP, and at least part of the second capacitor electrode Ce2 of the storage capacitor Cst are located in the same layer.

[0131] Figure 5A The array substrate shown in FIG. 1A is different from the array substrate shown in FIG. 1B at least in that, Figure 3A The array substrate shown in FIG. 1A is different from the array substrate shown in FIG. 1B at least in that, Figure 5A The second gate metal layer Gate2 in the array substrate shown in FIG. 1A does not include the plurality of second gate lines (e.g., the respective second gate line GL2). However, Figure 5A The second gate metal layer Gate2 in the array substrate described in FIG. 1C includes the gate connection pad GCP. Referring to Figure 6B The gate connection pad GCP connects the third gate pad GEP3 in the third gate metal layer Gate3 to the respective second gate line GL2 in the plurality of second gate lines in the first signal line layer SD1. The gate scan signal provided by each second gate line GL2 is transmitted to the gate G2 of the second transistor T2 via the gate connection pad GCP.

[0132] Referring to Figure 6B In some embodiments, the respective second gate line GL2 is connected to the gate connection pad GCP via a ninth via v9. The third gate pad GEP3 is connected to the gate connection pad GCP by a tenth via v10. In one example, the ninth via v9 extends through the passivation layer PVX, the second interlayer dielectric layer ILD2, and the first interlayer dielectric layer ILD1. In another example, the tenth via v10 extends through the second interlayer dielectric layer ILD2 and the first interlayer dielectric layer ILD1.

[0133] In some embodiments, the respective first reset control signal line includes a plurality of branches respectively located at a plurality of layers. In one example, the respective first reset control signal line includes a respective first reset control signal line first branch rst1-1 (as shown in Figure 5D ) in a second gate metal layer Gate2 and a respective first reset control signal line second branch rst1-2 (as shown in Figure 5I ) in a first signal line layer SD1. Optionally, a footprint of the respective first reset control signal line first branch rst1-1 on the substrate BS at least partially (e.g., at least 80%, at least 85%, at least 90%, at least 95%, at least 98%, or at least 99%) overlaps with a footprint of the respective first reset control signal line second branch rst1-2 on the substrate BS.

[0134] Referring to Figure 2A , Figure 5A , Figure 5E , Figure 6A and Figure 6B , in some embodiments, the second semiconductor material layer SML2 includes at least an active layer ACT2 of the second transistor T2 and an active layer ACTr1 of the first reset transistor Tr1. Optionally, the second semiconductor material layer SML2 further includes at least a portion of a first electrode S2 of the second transistor T2 and at least a portion of a first electrode Sr1 of the first reset transistor Tr1. Optionally, the second semiconductor material layer SML2 further includes at least a portion of a second electrode D2 of the second transistor T2 and at least a portion of a second electrode Dr1 of the first reset transistor Tr1. Optionally, the second semiconductor material layer SML2 includes the active layer ACT2, the first electrode S2, and the second electrode D2 of the second transistor T2; and the active layer ACTr1, the first electrode Sr1, and the second electrode Dr1 of the first reset transistor Tr1. In the present array substrate, at least the active layer ACT2 of the second transistor T2 and the active layer ACTr1 of the first reset transistor Tr1 are located at different layers from at least active layers of other transistors. Various suitable semiconductor materials can be used to fabricate the second semiconductor material layer SML2. Examples of semiconductor materials used to fabricate the second semiconductor material layer SML2 include metal oxide-based semiconductor materials (e.g., indium gallium zinc oxide) and metal oxynitride-based semiconductor materials (e.g., zinc oxynitride).

[0135] Figure 5EThe labels are used to label the components of the second transistor T2 and the first reset transistor Trl. For example, the second transistor T2 includes an active layer ACT2, a first electrode S2, and a second electrode D2; the first reset transistor Trl includes an active layer ACTrl, a first electrode Sr1, and a second electrode Dr1. Optionally, the active layer ACT2, the first electrode S2, and the second electrode D2 of the second transistor T2; and the active layer ACTrl, the first electrode Sr1, and the second electrode Dr1 of the first reset transistor Trl are located in the same layer. Optionally, the active layer ACT2 of the second transistor T2 and the active layer ACTrl of the first reset transistor Trl are part of an integral structure. Optionally, the active layer ACT2, the first electrode S2, and the second electrode D2 of the second transistor T2; and the active layer ACTrl, the first electrode Sr1, and the second electrode Dr1 of the first reset transistor Trl are part of an integral structure.

[0136] Referring to Figure 2A , Figure 5A , Figure 5F , Figure 6A and Figure 6B In some embodiments, the third gate metal layer Gate3 includes a third gate pad GEP3 and a fourth gate pad GEP4. Various suitable electrode materials and various suitable fabrication methods can be used to fabricate the third gate metal layer Gate3. For example, the conductive material can be deposited on the substrate by a plasma-enhanced chemical vapor deposition (PECVD) process and patterned. Examples of suitable conductive materials for fabricating the third gate metal layer Gate3 include, but are not limited to, aluminum, copper, molybdenum, chromium, aluminum-copper alloy, copper-molybdenum alloy, molybdenum-aluminum alloy, aluminum-chromium alloy, copper-chromium alloy, molybdenum-chromium alloy, copper-molybdenum-aluminum alloy, etc. Optionally, the third gate pad GEP3 and the fourth gate pad GEP4 are located in the same layer.

[0137] In some embodiments, the third gate pad GEP3 includes a gate G2 of a second transistor T2 in the pixel driving circuit. In some embodiments, the fourth gate pad GEP4 includes a gate Gr1 of a first reset transistor Trl in the pixel driving circuit. The third gate pad GEP3 is connected to a respective second gate line GL2 in the plurality of second gate lines through a gate connection pad (referred to as “GCP” in Figure 5I ). The fourth gate pad GEP4 is connected to a respective first reset control signal line rst1 in the plurality of first reset control signal lines. In one example, the fourth gate pad GEP4 is connected to a respective first reset control signal line second branch (referred to as “rst1-2” in Figure 5I ).

[0138] Figure 5G A via extending through the first interlayer dielectric layer ILD1 is shown.

[0139] Figure 5H The via extending through the passivation layer PVX is shown.

[0140] Referring to Figure 2A , Figure 5A , Figure 5I , Figure 6A and Figure 6B In some embodiments, the first signal line layer SD1 includes a plurality of second gate lines (e.g., respective second gate lines GL2), a plurality of first reset signal lines (e.g., respective first reset signal lines Vint1); a plurality of second reset signal lines (e.g., respective second reset signal lines Vint2); at least part of a plurality of first reset control signal lines (e.g., respective first reset control signal line second branch rst1-2), at least part of a plurality of first gate lines (e.g., respective first gate line second branch GL1-2), a plurality of second reset control signal lines (e.g., respective second reset control signal line rst2); a node connection pad NCP; a relay electrode RE; a second node connection line Cln2; a third node connection line Cln3; a voltage connection pad VCP; a data signal connection pad DCP; and a reset signal connection pad Cli.

[0141] Various suitable conductive materials and various suitable manufacturing methods can be used to manufacture the first signal line layer SD1. For example, the conductive material can be deposited on the substrate by a plasma-enhanced chemical vapor deposition (PECVD) process and patterned. Examples of suitable conductive materials for manufacturing the first signal line layer include, but are not limited to, titanium, aluminum, copper, molybdenum, chromium, aluminum-copper alloy, copper-molybdenum alloy, molybdenum-aluminum alloy, aluminum-chromium alloy, copper-chromium alloy, molybdenum-chromium alloy, copper-molybdenum-aluminum alloy, etc. In some embodiments, the first signal line layer includes a plurality of sub-layers stacked together. In one example, the first signal line layer includes a stacked titanium / aluminum / titanium multi-layer structure. In another example, the first signal line layer includes a stacked molybdenum / aluminum / molybdenum multi-layer structure.

[0142] Optionally, the plurality of second gate lines (e.g., respective second gate lines GL2), the plurality of first reset signal lines (e.g., respective first reset signal lines Vint1); the plurality of second reset signal lines (e.g., respective second reset signal lines Vint2); at least part of the plurality of first reset control signal lines (e.g., respective first reset control signal line second branch rst1-2), at least part of the plurality of first gate lines (e.g., respective first gate line second branch GL1-2), the plurality of second reset control signal lines (e.g., respective second reset control signal line rst2); the node connection pad NCP; the relay electrode RE; the second node connection line Cln2; the third node connection line Cln3; the voltage connection pad VCP; the data signal connection pad DCP; and the reset signal connection pad Cli are located in the same layer.

[0143] In some embodiments, a node connection pad NCP in the pixel driving circuit connects multiple components of the pixel driving circuit to the node N1. Referring to Figure 6A , the node connection pad NCP is connected to the first node connection line Cln1 through an eighth via v8, and to the second transistor T2 (e.g., to the first electrode S2 of the second transistor T2) through a seventh via v7. The first node connection line Cln1 is connected to the first capacitor electrode Cel. Optionally, the first node connection line Cln1 corresponds to the node N1 described in Figure 2A . In one example, the seventh via v7 extends through the passivation layer PVX and the second interlayer dielectric layer ILD2. In another example, the eighth via v8 extends through the passivation layer PVX, the second interlayer dielectric layer ILD2, the first interlayer dielectric layer ILD1, and the insulating layer IN. In another example, the node connection pad NCP is located in the first signal line layer SD1, the first node connection line Cln1 is located in the first gate metal layer Gate1 with the first capacitor electrode Cel, and the first electrode S2 of the second transistor T2 is located in the second semiconductor material layer SML2.

[0144] Referring to Figure 2A , Figure 5A , Figure 5C , Figure 5D and Figure 6A , in some embodiments, in the hole region H, there is no portion of the second capacitor electrode Ce2. Optionally, in addition to the hole region H where there is no portion of the second capacitor electrode Ce2, the orthogonal projection of the second capacitor electrode Ce2 on the substrate

[0145] Referring to Figure 5A , Figure 5I , Figure 5K and Figure 6A , a data signal connection pad DCP in the pixel driving circuit connects a respective data line DL to the first electrode S1 of the first transistor T1, through which a data signal provided by the respective data line DL is transmitted to the first electrode S1 of the first transistor T1.

[0146] In some embodiments, each of the first gate lines includes a plurality of branches respectively located in a plurality of layers. In one example, each of the first gate lines includes a respective first gate line first branch GL1-1 (as shown in Figure 5C ) in a first gate metal layer Gate1 and a respective first gate line second branch GL1-2 (as shown in Figure 5I ) in a first signal line layer SD1. Optionally, a footprint of the respective first gate line first branch GL1-1 on the substrate BS at least partially (e.g., at least 80%, at least 85%, at least 90%, at least 95%, at least 98%, or at least 99%) overlaps with a footprint of the respective first gate line second branch GL1-2 on the substrate BS.

[0147] In some embodiments, each of the first reset control signal lines includes a plurality of branches respectively located in a plurality of layers. In one example, each of the first reset control signal lines includes a respective first reset control signal line first branch rst1-1 (as shown in Figure 5D ) in a second gate metal layer Gate2 and a respective first reset control signal line second branch rst1-2 (as shown in Figure 5I ) in the first signal line layer SD1. Optionally, a footprint of the respective first reset control signal line first branch rst1-1 on the substrate BS at least partially (e.g., at least 80%, at least 85%, at least 90%, at least 95%, at least 98%, or at least 99%) overlaps with a footprint of the respective first reset control signal line second branch rst1-2 on the substrate BS.

[0148] Referring to Figure 5A , Figure 5D , Figure 5F , Figure 5I , Figure 6A and Figure 6B , a gate connection pad GCP in the second gate metal layer Gate2 connects a third gate pad GEP3 in the third gate metal layer Gate3 to a respective second gate line GL2 of a plurality of second gate lines in the first signal line layer SD1. A gate scan signal provided by each of the second gate lines GL2 is transmitted to the gate G2 of the second transistor T2 through the gate connection pad GCP. Referring to Figure 6B , each of the second gate lines GL2 is connected to the gate connection pad GCP through a ninth via v9. The third gate pad GEP3 is connected to the gate connection pad GCP through a tenth via v10. In one example, the ninth via v9 extends through the passivation layer PVX, the second interlayer dielectric layer ILD2, and the first interlayer dielectric layer ILD1. In another example, the tenth via v10 extends through the second interlayer dielectric layer ILD2 and the first interlayer dielectric layer ILD1.

[0149] Referring to Figure 5A , Figure 5D 、 Figure 5I 、 Figure 5K 、 Figure 6A and Figure 6B The voltage connection pad VCP connects the corresponding first voltage supply line Vdd and the second capacitor electrode Ce2 of the storage capacitor. Referring to Figure 6A The corresponding first voltage supply line Vdd is connected to the voltage connection pad VCP through a third via v3. The voltage connection pad VCP is connected to the second capacitor electrode Ce2 of the storage capacitor through a fourth via v4. In one example, the third via v3 extends through the first planarization layer PLN1. In another example, the fourth via v4 extends through the passivation layer PVX, the second interlayer dielectric layer ILD2 and the first interlayer dielectric layer ILD1.

[0150] Referring to Figure 5A 、 Figure 5B 、 Figure 5I 、 Figure 5K 、 Figure 6A and Figure 6B The relay electrode RE connects the anode connection pad ACP and the second electrode D4 of the fourth transistor T4 in the pixel driving circuit. The anode connection pad ACP is also connected to the anode of the light emitting element.

[0151] Referring to Figure 5A 、 Figure 5B 、 Figure 5D 、 Figure 5I 、 Figure 6A and Figure 6B The reset signal connection line Cli connects the corresponding third reset signal line Vint3 and the first electrode Sr3 of the third reset transistor Tr3 in the pixel driving circuit, thereby providing the reset signal to the first electrode Sr3 of the third reset transistor Tr3 in the pixel driving circuit.

[0152] Referring to Figure 5A 、 Figure 5B 、 Figure 5I 、 Figure 6A and Figure 6B The second node connection line Cln2 in the pixel driving circuit is connected to the second electrode D3 of the third transistor T3 in the pixel driving circuit, and connected to the second electrode Dr3 of the third reset transistor Tr3 in the pixel driving circuit.

[0153] Referring to Figure 5A 、 Figure 5B 、 Figure 5I 、 Figure 6A and Figure 6B The third node connection line Cln3 in the pixel driving circuit is connected to the second electrode D2 of the second transistor T2 in the pixel driving circuit, and connected to the second electrode Dd of the driving transistor Td and the first electrode S4 of the fourth transistor T4 in the pixel driving circuit.

[0154] FIG. 5J A via extending through the first planarization layer PLN1 is shown.

[0155] Reference is made to FIG. 2A , FIG. 5A , FIG. 5K , FIG. 6A and FIG. 6B In some embodiments, the second signal line layer SD2 includes a plurality of first voltage supply lines (e.g., respective first voltage supply lines Vdd), a plurality of second voltage supply lines (e.g., respective second voltage supply lines Vss), a plurality of data lines (e.g., respective data lines DL), and anode contact pads ACP. Various suitable conductive materials and various suitable fabrication methods can be used to fabricate the second signal line layer SD2. For example, the conductive material can be deposited on the substrate by a plasma-enhanced chemical vapor deposition (PECVD) process and patterned. Examples of suitable conductive materials for fabricating the second signal line layer SD2 include, but are not limited to, titanium, aluminum, copper, molybdenum, chromium, aluminum-copper alloy, copper-molybdenum alloy, molybdenum-aluminum alloy, aluminum-chromium alloy, copper-chromium alloy, molybdenum-chromium alloy, copper-molybdenum-aluminum alloy, etc. In some embodiments, the second signal line layer includes a plurality of sub-layers stacked together. In one example, the second signal line layer includes a stacked titanium / aluminum / titanium multi-layer structure. In another example, the second signal line layer includes a stacked molybdenum / aluminum / molybdenum multi-layer structure. Optionally, the plurality of first voltage supply lines (e.g., respective first voltage supply lines Vdd), the plurality of second voltage supply lines (e.g., respective second voltage supply lines Vss), the plurality of data lines (e.g., respective data lines DL), and the anode contact pads ACP are located in the same layer.

[0156] FIG. 7 is a schematic diagram showing a structure of a pixel driving circuit in an array substrate in some embodiments according to the present disclosure. FIG. 8 is a cross-sectional view along line E-E’ in FIG. 7 . FIG. 7 and FIG. 8 show an array substrate in an alternative embodiment. Reference is made to FIG. 7 In the alternative embodiment, the array substrate includes a first node connection line Cln1 in the first signal line layer SD1. The first node connection line Cln1 connects a plurality of components of the pixel driving circuit to the node N1. Reference is made to FIG. 8 The first node connection line Cln1 is connected to the first capacitor electrode Cel by an eleventh via v11 and to the second transistor T2 (e.g., to the first electrode S2 of the second transistor T2) by a twelfth via v12.

[0157] In FIG. 7 and FIG. 8In the alternative embodiment shown, each of the plurality of second gate lines includes a plurality of branches at a plurality of layers, respectively. In one example, each of the second gate lines includes a respective second gate line first branch GL2-1 in a second gate metal layer Gate2 and a respective second gate line second branch GL2-2 in a third gate metal layer Gate3. Optionally, a footprint of the respective second gate line first branch GL2-1 on the substrate base BS at least partially (e.g., at least 80%, at least 85%, at least 90%, at least 95%, at least 98%, or at least 99%) overlaps a footprint of the respective second gate line second branch GL2-2 on the substrate base BS.

[0158] In the alternative embodiment shown, FIG. 7 and FIG. 8 In the alternative embodiment shown, the first node connection line Cln1 crosses the respective second gate line first branch GL2-1 in the second gate metal layer Gate2 and the respective second gate line second branch GL2-2 in the third gate metal layer Gate3. The inventors of the present disclosure found that by crossing the first node connection line Cln1 with two layers of second gate line branches, the presence of two layers of second gate line branches under the first node connection line Cln1 causes the surface of the passivation layer PVX to be uneven, where the first node connection line Cln1 crosses the respective second gate line first branch GL2-1 in the second gate metal layer Gate2 and the respective second gate line second branch GL2-2 in the third gate metal layer Gate3.

[0159] FIG. 9 is a cross-sectional view of the area where the first node connection line crosses the respective second gate line first branch and the respective second gate line second branch. As shown, FIG. 9 The presence of the respective second gate line first branch GL2-1 in the second gate metal layer Gate2 and the respective second gate line second branch GL2-2 in the third gate metal layer Gate3 forms a relatively steep slope that the first node connection line Cln1 climbs over. The inventors of the present disclosure found that the relatively steep slope results in an increase in loading in the first node connection line Cln1 and an overall increase in loading in the pixel driving circuit having the first node connection line Cln1. In comparison, FIG. 9 to the array substrate shown in FIG. 4A and FIG. 6A the array substrate shown in

[0160] In the array substrate, there are two parasitic capacitances C1 and C2. The first capacitance C1 is formed between the second semiconductor material layer (e.g., including FIG. 3E or FIG. 5EThe overall structure of the active layer ACT2 of the second transistor and the active layer ACTrl of the first reset transistor) and the corresponding first gate line (e.g., including the corresponding first gate line first branch GL1-1 in the first gate metal layer and the corresponding first gate line second branch GL1-2 in the first signal line layer). The second capacitance C2 is formed between the first node connection line Cln1 and the corresponding second gate line. The inventors of the present disclosure found that a higher comparison of C1 to C2 helps to achieve an increase in the dark state margin. The dark state margin refers to the voltage difference between the voltage required to completely turn off a sub-pixel and the voltage required to produce a small amount of light in the sub-pixel. When the dark state margin is too small, it can result in “false contouring” or “image sticking”. An increase in the dark state margin avoids “false contouring” or “image sticking”.

[0161] Reference is made to FIG. 8 and FIG. 9 When the first node connection line Cln1 crosses two second gate line branches (including the corresponding second gate line first branch GL2-1 in the second gate metal layer Gate2 and the corresponding second gate line second branch GL2-2 in the third gate metal layer Gate3), the second capacitance C2 increases, resulting in a decrease in the dark state margin.

[0162] The inventors of the present disclosure found that by crossing the first node connection line Cln1 with only one layer of the second gate line (see, e.g., FIG. 4A or FIG. 6A ), the second capacitance C2 can be reduced, resulting in an increase in the dark state margin.

[0163] Reference is made to FIG. 3D or FIG. 5I In some embodiments, each second gate line GL2 includes a first portion P1 and a second portion P2. Reference is made to FIGS. 3A-3K and FIGS. 5A-5K In some embodiments, the first portion P1 has a footprint on the substrate that at least partially overlaps with a footprint of the active layer ACT2 of the second transistor T2 on the substrate and does not overlap with a footprint of the first node connection line Cln1 on the substrate. In some embodiments, the second portion P2 has a footprint on the substrate that at least partially overlaps with a footprint of the first node connection line Cln1 on the substrate and does not overlap with a footprint of the active layer ACT2 of the second transistor T2 on the substrate.

[0164] In some embodiments, the first portion P1 has a first average line width w1 at a location where the first portion P1 intersects the active layer ACT2 of the second transistor T2, and the second portion P2 has a second average line width w2 at a location where the second portion P2 intersects the first connection line Cln1. In some embodiments, each of the second gate lines GL2 extends along a first direction. The first average line width w1 and the second average line width w2 are line widths along a second direction that is perpendicular to the first direction.

[0165] In some embodiments, the first average line width w1 is greater than the second average line width w2. The inventors of the present disclosure have found that by having a relatively smaller second average line width, the overlapping area between the corresponding second gate line GL2 and the first connection line Cln1 can be further reduced, and the second capacitance C2 can be further reduced, resulting in an increased dark state margin.

[0166] Referring to FIG. 3A , FIG. 3K , FIG. 5A and FIG. 5K In some embodiments, the array substrate includes a plurality of first voltage supply lines, a plurality of second voltage supply lines, and a plurality of data lines arranged alternately. Each of the plurality of first voltage supply lines, the plurality of second voltage supply lines, and the plurality of data lines extends along a direction substantially parallel to the second direction DR2. As used herein, the term “substantially parallel” means an angle in a range of 0 degrees to about 45 degrees, such as 0 degrees to about 5 degrees, 0 degrees to about 10 degrees, 0 degrees to about 15 degrees, 0 degrees to about 20 degrees, 0 degrees to about 25 degrees, 0 degrees to about 30 degrees.

[0167] In some embodiments, the second signal line layer further includes a plurality of fourth reset signal lines extending along a direction substantially parallel to the second direction DR2. FIG. 10 is a schematic diagram showing a structure of a second signal line layer in an array substrate in some embodiments according to the present disclosure. Referring to FIG. 10 In some embodiments, the array substrate includes a plurality of first voltage supply lines, a plurality of second voltage supply lines, a plurality of fourth reset signal lines (e.g., respective fourth reset signal lines Vint4), and a plurality of data lines. In some embodiments, the plurality of pixel driving circuits are arranged into a plurality of columns, including a (2k-1)th column C(2k-1) and a (2k)th column C(2k) in K columns, K and k being positive integers, 1≤k≤K / 2. Referring to FIG. 10 In some embodiments, the plurality of fourth reset signal lines are present in the (2k-1)th column C(2k-1) but not present in the (2k)th column C(2k). The plurality of second voltage supply lines are present in the (2k)th column C(2k) but not present in the (2k-1)th column C(2k-1).

[0168] As used herein, the terms "first (2k-l) column" and "first (2k) column" are used in the context of K columns. The array substrate can or can not include additional columns before the first column of the K columns and / or additional columns after the last column of the K columns. In the context of the array substrate, the term "first (2k-l) column" does not necessarily denote an odd column, and the term "first (2k) column" does not necessarily denote an even column. In one example, the first (2k-l) column is an odd column in the context of the K columns, but can be an even column in the context of the array substrate. In another example, the first (2k-l) column is an odd column in the context of the K columns, and is also an odd column in the context of the array substrate. In one example, the first (2k) column is an even column in the context of the K columns, but can be an odd column in the context of the array substrate. In another example, the first (2k) column is an even column in the context of the K columns, and is also an even column in the context of the array substrate.

[0169] The plurality of fourth reset signal lines can form an interconnected reset signal network. In one example, the plurality of fourth reset signal lines and the plurality of first reset signal lines form the interconnected reset signal network. In another example, the plurality of fourth reset signal lines and the plurality of second reset signal lines form the interconnected reset signal network. In another example, the plurality of fourth reset signal lines and the plurality of third reset signal lines form the interconnected reset signal network.

[0170] FIG. 11 An interconnected reset signal network in some embodiments according to the present disclosure is shown. Reference is made to FIG. 11 In some embodiments, the interconnected reset signal network includes a plurality of first reset signal lines, a plurality of second reset signal lines, and a plurality of fourth reset signal lines interconnected together. The plurality of first reset signal lines extends in a direction substantially parallel to a first direction DR1; the plurality of second reset signal lines extends in a direction substantially parallel to the first direction DR1; and the plurality of fourth reset signal lines extends in a direction substantially parallel to a second direction DR2. In one example, the plurality of first reset signal lines and the plurality of second reset signal lines are in a first signal line layer. In another example, the plurality of fourth reset signal lines is in a second signal line layer. Optionally, each first reset signal line Vint1 is connected to one or more of the plurality of fourth reset signal lines. Optionally, each second reset signal line Vint2 is connected to one or more of the plurality of fourth reset signal lines. Optionally, each fourth reset signal line Vint4 is connected to one or more of the plurality of first reset signal lines and to one or more of the plurality of second reset signal lines.

[0171] FIG. 12 An interconnected reset signal network in some embodiments according to the present disclosure is shown. Reference is made toFIG. 12 In some embodiments, the interconnect reset signal network includes a plurality of third reset signal lines and a plurality of fourth reset signal lines interconnected together. The plurality of third reset signal lines extend in a direction substantially parallel to the first direction DR1; and the plurality of fourth reset signal lines extend in a direction substantially parallel to the second direction DR2. In one example, the plurality of third reset signal lines are in the second gate metal layer. In another example, the plurality of fourth reset signal lines are in the second signal line layer. Optionally, each third reset signal line Vint3 is connected to one or more fourth reset signal lines of the plurality of fourth reset signal lines. Optionally, each fourth reset signal line Vint4 is connected to one or more third reset signal lines of the plurality of third reset signal lines.

[0172] Referring to FIG. 3A , FIG. 3D , FIG. 3I , FIG. 5A , FIG. 5D and FIG. 5I the plurality of first reset signal lines and the plurality of second reset signal lines are in the first signal line layer; and the plurality of third reset signal lines are in the second gate metal layer.

[0173] In alternative embodiments, the plurality of first reset signal lines are in the first signal line layer; the plurality of second reset signal lines are in the second gate metal layer; and the plurality of third reset signal lines are in the third gate metal layer.

[0174] In alternative embodiments, the plurality of first reset signal lines are in the first signal line layer; the plurality of second reset signal lines are in the second gate metal layer; and the plurality of third reset signal lines are in the first signal line layer.

[0175] In alternative embodiments, the plurality of first reset signal lines are in the second gate metal layer; and the plurality of second reset signal lines are in the first signal line layer; and the plurality of third reset signal lines are in the second gate metal layer.

[0176] In alternative embodiments, the plurality of first reset signal lines are in the third gate metal layer; and the plurality of second reset signal lines are in the first signal line layer; and the plurality of third reset signal lines are in the second gate metal layer.

[0177] FIG. 13 is a schematic diagram showing the structure of a voltage connection pad in an array substrate in some embodiments according to the present disclosure. Referring to FIG. 13In some embodiments, the voltage connection pad includes a main portion MP and an extension portion EP extending away from the main portion MP. In some embodiments, the main portion MP extends along a direction substantially parallel to the first direction DR1, and the extension portion EP extends along a direction substantially parallel to the second direction DR2 away from the main portion MP. The second direction DR2 is different from the first direction DR1. Optionally, the main portion MP and the extension portion EP are part of a unitary structure.

[0178] Referring to FIG. 13 , FIGS. 3A-3K , FIGS. 4A-4B , FIGS. 5A-5K and FIGS. 6A-6B In some embodiments, the array substrate includes a plurality of first voltage supply lines Vdd extending along a direction substantially parallel to the second direction DR2. The main portion MP connects each of the first voltage supply lines Vdd to the second capacitor electrode Ce2 of the storage capacitor. The extension portion EP connects the main portion MP to the first electrode S3 of the third transistor T3. The extension portion EP intersects with a respective one of the plurality of light emission control signal lines em. A footprint of the extension portion EP on the substrate BS partially overlaps with a footprint of the respective light emission control signal line em on the substrate BS.

[0179] In some embodiments, each of the first voltage supply lines Vdd is connected to the main portion MP through a third via v3. The main portion MP is connected to the second capacitor electrode Ce2 of the storage capacitor through a fourth via v4. In one example, the third via v3 extends through the first planarization layer PLN1. In another example, the fourth via v4 extends through the passivation layer PVX, the second interlayer dielectric layer ILD2, and the first interlayer dielectric layer ILD1.

[0180] In some embodiments, the main portion MP and the extension portion EP are in the first signal line layer SD1, each of the light emission control signal lines em is in the first gate metal layer Gate1, and each of the first voltage supply lines Vdd is in the second signal line layer SD2.

[0181] In some embodiments, the main body portion MP includes a first main body portion MP1 and a second main body portion MP2. The first main body portion MP1 connects each of the first voltage supply lines Vdd and the second capacitor electrodes Ce2 of the storage capacitors. A projection of the first main body portion MP1 on the substrate

[0182] In some embodiments, the first main body portion MP1 has a first average pad width pw1, and the second main body portion MP2 has a second average pad width pw2. In some embodiments, the first average pad width pw1 and the second average pad width pw2 are pad widths in a direction substantially parallel to the second direction DR2. In some embodiments, the first average pad width pw1 is larger than the second average pad width pw2.

[0183] In some embodiments, the voltage connection pad has a T-shape.

[0184] Referring to FIGS. 3A-3K , FIGS. 4A-4B , FIGS. 5A-5K and FIGS. 6A-6B In some embodiments, a projection of each of the first voltage supply lines Vdd on the substrate substrate BS covers a projection of the first node connection line Cln1 on the substrate substrate BS. With this structure, interference with the first node connection line can be reduced.

[0185] Referring to FIGS. 3A-3K , FIGS. 4A-4B , FIGS. 5A-5K and FIGS. 6A-6B In some embodiments, a projection of each of the first voltage supply lines Vdd on the substrate substrate BS covers a projection of the active layer of the second transistor T2 and the first reset transistor Tr1 on the substrate substrate BS. With this structure, stability of the second transistor T2 and the first reset transistor Tr1 can be enhanced.

[0186] In some embodiments, the first parasitic capacitance CI is formed between the second semiconductor material layer SML2 and the corresponding first gate line. The second parasitic capacitance C2 is formed between the first node connection line Clnl and the corresponding second gate line. In some embodiments, a ratio of the first parasitic capacitance to the second parasitic capacitance is greater than 2.0, such as greater than 2.1, greater than 2.2, greater than 2.3, greater than 2.4, greater than 2.5, greater than 2.6, greater than 2.7, greater than 2.8, greater than 2.9, greater than 3.0, greater than 3.1, greater than 3.2, greater than 3.3, greater than 3.4, greater than 3.5, greater than 3.6, greater than 3.7, greater than 3.8, greater than 3.9, or greater than 4.0. In one example, the ratio of the first parasitic capacitance to the second parasitic capacitance is greater than 2.3. In another example, the ratio of the first parasitic capacitance to the second parasitic capacitance is between 2.3 and 3.5. The inventors of the present disclosure found that a higher comparison of CI to C2 helps to achieve an increase in dark state margin. By having a ratio between 2.3 and 3.5, the array substrate can achieve an increase in dark state margin while making full use of layout space.

[0187] In some embodiments, each of the first gate lines comprises a corresponding first gate line first branch GL1-1 in the first gate metal layer Gate1 and a corresponding first gate line second branch GL1-2 in the first signal line layer SD1, which is located on a side of the first gate metal layer Gate1 away from the substrate base BS. The corresponding first gate line second branch GL1-2 is connected to the corresponding first gate line first branch GL1-1 through one or more vias. The first parasitic capacitance CI is formed between the second semiconductor material layer SML2 and the corresponding first gate line first branch GL1-1 and between the second semiconductor material layer SML2 and the corresponding first gate line second branch GL1-2. Optionally, the first parasitic capacitance is greater than at least twice the second parasitic capacitance. By providing the corresponding first gate line first branch GL1-1 and the corresponding first gate line second branch GL1-2, the resistance of the corresponding first gate line can be reduced.

[0188] FIG. 14 is a cross-sectional view along the F-F’ line in FIG. 3A . Referring to FIG. 14 , the first capacitance CI is represented in the cross-sectional view. The second capacitance C2 is represented in FIG. 4B , FIG. 6B and FIG. 8 .

[0189] In another aspect, the present disclosure provides a display device comprising an array substrate described herein or manufactured by a method described herein, and one or more integrated circuits connected to the array substrate. Examples of suitable display devices include, but are not limited to, electronic paper, mobile phones, tablet computers, televisions, monitors, notebook computers, digital photo frames, GPS, etc. Optionally, the display device is an organic light-emitting diode display device. Optionally, the display device is a micro light-emitting diode display device. Optionally, the display device is a mini light-emitting diode display device.

[0190] In another aspect, the present disclosure provides a method of manufacturing an array substrate. In some embodiments, the method comprises forming a plurality of pixel drive circuits, forming a plurality of first voltage supply lines, and forming a plurality of light-emitting control signal lines. Optionally, forming each pixel drive circuit of the plurality of pixel drive circuits comprises forming a drive transistor, forming a first light-emitting control transistor, forming a storage capacitor, and forming a voltage connection pad. Optionally, forming the voltage connection pad comprises forming a body portion and forming an extension portion extending away from the body portion. Optionally, the body portion connects a respective first voltage supply line of the plurality of first voltage supply lines with a second capacitor electrode of the storage capacitor. Optionally, the extension portion connects the body portion with a first electrode of the first light-emitting control transistor. Optionally, the extension portion intersects a respective light-emitting control signal line of the plurality of light-emitting control signal lines.

[0191] The foregoing description of embodiments of the application has been presented for the purposes of illustration and description. It is not intended to be exhaustive or to limit the application to the precise form disclosed. The description was presented as illustrative of the broadest aspects of the application that are and can be claimed as it is and only limited by the appended claims. Obviously, many modifications and variations will be apparent to those skilled in the art. The embodiments were chosen and described in order to explain the principles of the application and its best mode of practical application to thereby enable others skilled in the art to understand the application for various embodiments and with various modifications that are suited to the particular use or implementation. The scope of the application is to be defined by the claims and their equivalents, where all terms are meant to be construed in their broadest reasonable sense, unless otherwise indicated. Thus, the terms "the invention," "the present invention," or similar referents used in the context of the detailed description are not intended to be limiting of the claimed subject matter, and will be included in the scope of the claims along with the equivalents thereof. The present invention is only limited by the claims appended hereto and encompasses all variations falling within the scope of the claims, which are to be interpreted in accordance with the principles of patent law. Furthermore, these claims can refer to "a," "an" or "the" article, which is intended to be interpreted to mean "at least one" or "one or more." Also, any application recitations of "first," "second," or "third" or similar language are not intended to be construed as limiting the number or order of elements. Any advantages and benefits provided by the described embodiments can not apply in all instances. It should be understood that various changes can be made by those skilled in the art which would be apparent to one skilled in the art. Such changes are not to be considered limiting of the scope of the application as defined by the appended claims and their equivalents. Furthermore, elements and components of the disclosure can be arranged and designed in a wide variety of different configurations, all of which are intended to fall within the scope of the present disclosure. Also, the elements and components of the disclosure can be interchanged with other elements and components that serve the same function or are otherwise suitable for use in the same or similar manner.

Claims

1. An array substrate comprising a plurality of first gate lines, a plurality of second gate lines, and a plurality of pixel driving circuits; wherein each of the plurality of pixel driving circuits comprises a driving transistor, a data writing transistor, a compensation transistor, a storage capacitor, a first node connecting line connecting a gate of the driving transistor and a first electrode of the compensation transistor; each of the plurality of first gate lines is configured to provide a gate scanning signal to the data writing transistor; each of the plurality of second gate lines is configured to provide a gate scanning signal to the compensation transistor; wherein the array substrate comprises a first semiconductor material layer and a second semiconductor material layer located on a side of the first semiconductor material layer away from a substrate; the first semiconductor material layer comprises at least an active layer of the driving transistor and the data writing transistor; the second semiconductor material layer comprises at least an active layer of the compensation transistor; a first parasitic capacitance is formed between the second semiconductor material layer and the corresponding first gate line; a second parasitic capacitance is formed between the first node connecting line and the corresponding second gate line; wherein a ratio of the first parasitic capacitance to the second parasitic capacitance is greater than 2.

3.

2. The array substrate according to claim 1, wherein, The ratio of the first parasitic capacitance to the second parasitic capacitance is between 2.3 and 3.

5.

3. The array substrate of claim 1, wherein the first node connecting line crosses the corresponding second gate line; in a region where a footprint of the first node connecting line on the substrate overlaps with a footprint of the corresponding second gate line on the substrate, the array substrate does not comprise any other conductive component whose footprint on the substrate overlaps with the footprint of the first node connecting line on the substrate; and the layer where the first node connecting line is located is spaced apart from the corresponding second gate line by at least two different insulating layers and semiconductor material layers.

4. The array substrate according to claim 3, wherein, each of the plurality of pixel driving circuits further comprises a third gate pad and a gate connecting pad connecting the third gate pad and the corresponding second gate line; a footprint of the third gate pad and the corresponding second gate line on the substrate overlaps with a footprint of the active layer of the compensation transistor on the substrate; and the third gate pad, the gate connecting pad, and the active layer of the compensation transistor are respectively located in four different layers. the corresponding second gate line is located in a second gate metal layer comprising a second capacitor electrode of the storage capacitor; 5. The array substrate according to claim 4, wherein, the active layer of the compensation transistor is located in the second semiconductor material layer, which is located on a side of the second gate metal layer away from the substrate; the third gate pad is located in a third gate metal layer, which is located on a side of the second semiconductor material layer away from the second gate metal layer; and the gate connecting pad is located in a first signal line layer, which is located on a side of the third gate metal layer away from the second semiconductor material layer. ​ ​ 6. The array substrate according to claim 4, wherein, The gate connection pad is in a second gate metal layer including a second capacitor electrode of the storage capacitor; The active layer of the compensation transistor is in a second semiconductor material layer, which is on a side of the second gate metal layer away from the substrate; The third gate pad is in a third gate metal layer, which is on a side of the second semiconductor material layer away from the second gate metal layer; And The corresponding second gate line is in a first signal line layer, which is on a side of the third gate metal layer away from the second semiconductor material layer.

7. The array substrate according to claim 3, wherein, The gate connection pad is in a second gate metal layer including a second capacitor electrode of the storage capacitor; The active layer of the compensation transistor is in a second semiconductor material layer, which is on a side of the second gate metal layer away from the substrate; And The first node connection line is in a first signal line layer, which is on a side of the second semiconductor material layer away from the second gate metal layer.

8. The array substrate of claim 3, wherein, The first node connection line is in a first gate metal layer including a first capacitor electrode of the storage capacitor; The active layer of the compensation transistor is in a second semiconductor material layer, which is on a side of the first gate metal layer away from the substrate; And The corresponding second gate line is in a first signal line layer, which is on a side of the second semiconductor material layer away from the first gate metal layer.

9. The array substrate of claim 8, wherein, The first node connection line and the first capacitor electrode are part of an integral structure.

10. The array substrate of claim 8, wherein, The respective pixel driving circuit further includes a node connection pad in the first signal line layer including the corresponding second gate line; and The node connection pad connects the first node connection line in the first gate metal layer and the first electrode of the compensation transistor in the second semiconductor material layer.

11. The array substrate of claim 10, wherein, The node connection pad is connected to the first node connection line through an eighth via and to the first electrode of the compensation transistor through a seventh via; The seventh via extends through a passivation layer and a second interlayer dielectric layer; And The eighth via extends through the passivation layer, the second interlayer dielectric layer, a first interlayer dielectric layer and an insulating layer.

12. The array substrate according to any one of claims 3 to 11, wherein, The corresponding second gate line includes a first portion and a second portion; A footprint of the first portion on the substrate at least partially overlaps a footprint of the active layer of the compensation transistor on the substrate and does not overlap a footprint of the first node connection line on the substrate; A footprint of the second portion on the substrate at least partially overlaps the footprint of the first node connection line on the substrate and does not overlap the footprint of the active layer of the compensation transistor on the substrate; The corresponding second gate line extends along a first direction; The first portion has a first average line width along a second direction at a position where the first portion intersects the active layer of the compensation transistor, the second direction being perpendicular to the first direction; The second portion has a second average line width in the second direction at a location where the second portion crosses the first node connection line; and The first average line width is greater than the second average line width.

13. The array substrate of claim 12, further comprising a plurality of first voltage supply lines and a plurality of light emission control signal lines. wherein Each of the plurality of pixel driving circuits comprises a first light emission control transistor and a voltage connection pad; The voltage connection pad comprises a main body portion and an extension portion extending away from the main body portion; The main body portion connects a respective first voltage supply line of the plurality of first voltage supply lines with a second capacitor electrode of the storage capacitor; The extension portion connects the main body portion with a first electrode of the first light emission control transistor; and The extension portion crosses a respective light emission control signal line of the plurality of light emission control signal lines.

14. The array substrate of claim 13, wherein, The main body portion comprises a first main body portion and a second main body portion; The first main body portion connects the respective first voltage supply line with the second capacitor electrode; A footprint of the first main body portion on the substrate and a footprint of the second capacitor electrode on the substrate at least partially overlap, and a footprint of the respective first voltage supply line on the substrate at least partially overlaps; A footprint of the second main body portion on the substrate and a footprint of the second capacitor electrode on the substrate do not overlap, and a footprint of the respective first voltage supply line on the substrate does not overlap, while a footprint of the second electrode of the driving transistor on the substrate at least partially overlaps; The first main body portion has a first average pad width along a direction substantially parallel to the second direction; The second main body portion has a second average pad width along the direction substantially parallel to the second direction; and The first average pad width is greater than the second average pad width. Each of the plurality of light emission control signal lines is in a first gate metal layer; 15. The array substrate of claim 14, wherein, The main body portion and the extension portion are in a first signal line layer on a side of the first gate metal layer away from the substrate; The respective first voltage supply line is in a second signal line layer on a side of the first signal line layer away from the first gate metal layer; The respective first voltage supply line is connected to the first main body portion by a third via extending through a first planarization layer; The first main body portion is connected to the second capacitor electrode by a fourth via extending through a passivation layer, a second interlayer dielectric layer, and a first interlayer dielectric layer. A footprint of the respective first voltage supply line on the substrate covers the footprint of the first node connection line on the substrate. Each of the plurality of pixel driving circuits further comprises a first reset transistor; 16. The array substrate according to any one of claims 13 to 15, wherein, Active layers of the compensation transistor and the first reset transistor are in a second semiconductor material layer; and 17. The array substrate according to any one of claims 13 to 15, wherein, The first main body portion is connected to the second capacitor electrode by a fourth via extending through a passivation layer, a second interlayer dielectric layer, and a first interlayer dielectric layer. ​ ​ A positive projection of the respective first voltage supply line on the substrate wafer covers a positive projection of active layers of the compensation transistor and the first reset transistor on the substrate wafer.

18. The array substrate of any one of claims 13 to 15, further comprising a plurality of second voltage supply lines, a plurality of fourth reset signal lines, and a plurality of data lines in a same layer as the plurality of first voltage supply lines; The plurality of pixel driving circuits are arranged into a plurality of columns, including a (2k-1)th column C(2k-1) and a (2k)th column C(2k) of K columns, K and k being positive integers, 1≤k≤K / 2; The plurality of fourth reset signal lines exist in the (2k-1)th column C(2k-1) but not in the (2k)th column C(2k); and The plurality of second voltage supply lines exist in the (2k)th column C(2k) but not in the (2k-1)th column C(2k-1).

19. The array substrate of claim 18, further comprising a plurality of reset signal lines extending along a direction substantially parallel to the first direction; The plurality of first voltage supply lines, the plurality of second voltage supply lines, the plurality of fourth reset signal lines, and the plurality of data lines extend along a direction substantially parallel to the second direction; The array substrate comprises: an interconnection reset signal network comprising the plurality of fourth reset signal lines and the plurality of reset signal lines; each reset signal line of the plurality of reset signal lines is connected to one or more fourth reset signal lines of the plurality of fourth reset signal lines; and each fourth reset signal line of the plurality of fourth reset signal lines is connected to one or more reset signal lines of the plurality of reset signal lines.

20. An array substrate comprising a plurality of first gate lines, a plurality of second gate lines, and a plurality of pixel driving circuits; wherein each of the plurality of pixel driving circuits comprises a driving transistor, a data write transistor, a compensation transistor, a storage capacitor, a first node connection line connecting a gate of the driving transistor and a first electrode of the compensation transistor; each of the plurality of first gate lines is configured to provide a gate scanning signal to the data write transistor; each of the plurality of second gate lines is configured to provide a gate scanning signal to the compensation transistor; wherein the array substrate comprises a first semiconductor material layer and a second semiconductor material layer located on a side of the first semiconductor material layer away from a substrate wafer; the first semiconductor material layer comprises at least active layers of the driving transistor and the data write transistor; the second semiconductor material layer comprises at least an active layer of the compensation transistor; a first parasitic capacitance is formed between the second semiconductor material layer and a respective first gate line; a second parasitic capacitance is formed between the first node connection line and a respective second gate line; the respective first gate line comprises a respective first gate line first branch in a first gate metal layer and a respective first gate line second branch in a first signal line layer, the first signal line layer being on a side of the first gate metal layer distal to the substrate base plate; the respective first gate line second branch is connected to the respective first gate line first branch by one or more vias; the first parasitic capacitance is formed between the second semiconductor material layer and the respective first gate line first branch and between the second semiconductor material layer and the respective first gate line second branch; and the first parasitic capacitance is greater than at least twice the second parasitic capacitance.

21. A display device comprising the array substrate according to any one of claims 1 to 19 and one or more integrated circuits connected to the array substrate.

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