Integrated Circuit Processing Flow Management System and Method Based on Big Data

Abstract

The present invention relates to the field of integrated circuits, and specifically to an integrated circuit processing flow management system and method based on big data, comprising a chip processing event acquisition module, a detection abnormality event determination module, a key processing link analysis module, a correlation analysis module, a sampling warning signal output module, and an adjustment verification module; the chip processing event acquisition module is used to acquire chip processing events using DFT design; the detection abnormality event determination module is used to determine chip processing events with detection abnormalities; the key processing link analysis module is used to analyze key processing links that affect detection abnormalities; the correlation analysis module is used to determine whether there is a correlation between processing data and detection data after the first application in chip processing events of the same type of chips that are marked as detection abnormalities; and the sampling warning signal output module is used to output sampling warning signals for each type of chip when testing using DFT based on the existence or non-existence of the correlation relationship.

Description

Technical Field

[0001] The present invention relates to the field of integrated circuit technology, and in particular to an integrated circuit processing flow management system and method based on big data. Background Art

[0002] Currently, DFT technology is often implemented in some chip manufacturing processes that require sophisticated and complex manufacturing processes. After chip manufacturing is completed, a portion of chips will be selected for DFT testing to evaluate and verify the quality and reliability of chip processing. These selected chips will be tested on ATE, and test vectors generated by DFT logic will be used to detect possible manufacturing defects in the chips. If the test results show that the chips are defective, they will be repaired or eliminated according to the specific situation.

[0003] However, the cost of using DFT technology to perform chip quality inspection is high, so it is worth further research to adjust the sampling ratio of different types of chips when they need to be inspected based on parameter changes in the processing flow to reduce the technical difficulty and high cost of using DFT inspection while ensuring the rationality of chip sampling. Summary of the Invention

[0004] The purpose of the present invention is to provide an integrated circuit processing flow management system and method based on big data to solve the problems raised in the above background technology.

[0005] In order to solve the above technical problems, the present invention provides the following technical solution: an integrated circuit processing flow management method based on big data, characterized by comprising the following analysis steps:

[0006] Step S100: Obtain chip processing events for which a DFT design is applied. A chip processing event refers to the process from implementing a DFT design to completing chip processing and performing performance testing, and then outputting a qualified test result to first application. Sample data from the performance test record and test data after the first application are extracted. Based on the sample data and test data, chip processing events with test anomalies are determined.

[0007] Step S200: extracting the chip processing flow recorded in the abnormal chip processing event detection and the processing data of each processing link in the processing flow; analyzing the key processing links that affect the abnormality detection based on the processing data;

[0008] Step S300: Chips that use the same processing flow are grouped into one category. A determination is made as to whether there is a correlation between the processing data and the test data after the first application, recorded in the chip processing events marked as abnormal. Based on the existence of the correlation, a sampling warning signal is output for each type of chip when testing using DFT.

[0009] Step S400: Remove chip processing events with abnormal detection, mark other chip processing events in the historical records as normal processing events, adjust the sampling data of the normal processing event records, verify the abnormal detection stability of the chip processing events of the corresponding chip type after adjustment, and feedback to the processing flow management system.

[0010] Furthermore, determining a chip processing event with a detection anomaly based on the sampling data and the detection data includes the following specific steps:

[0011] The sampling data records the sampled chips, sampling ratio B, and sampling result T. The sampling ratio B refers to the ratio of the number of sampled chips selected for performance testing based on DFT design to the total number of sampled chips in the same batch. The sampling result T refers to the proportion of sampled chips that failed the test.

[0012] The detection data refers to the application detection abnormality ratio P from the completion of chip processing to application. The application detection abnormality ratio is the ratio of the number of application devices detected as abnormal to the total number of application devices corresponding to all chips;

[0013] Using the formula: Q = B * TP;

[0014] Calculate the sampling anomaly index Q of the chip processing event. When Q<0 and |Q| is greater than or equal to the difference threshold preset by the system, mark the corresponding chip processing event as a detection anomaly and output it.

[0015] Furthermore, step S200 includes the following specific steps:

[0016] Step S210: Extract chip processing events marked as abnormal for the same type of chips and store them in a first event set corresponding to the chip type; the first event set also records chip processing events of the same type of chips that are normal; the processing data records the parameter types and corresponding values required to be stored in each processing link;

[0017] Step S220: extract the chip processing events that are recorded and detected normally in the first event set as standard processing events, obtain the fluctuation range L of all parameter values recorded in each processing link of the standard processing event record, and store the fluctuation range in correspondence with the corresponding parameter type; the fluctuation range refers to plotting the recorded parameters on a bar graph with the horizontal axis as the number of parameter records and the vertical axis as the parameter value, and taking the vertical axis of the bar graph corresponding to the maximum horizontal axis in the bar graph as the standard value A, constructing the fluctuation range L, L = [Aa, A+a], A+a ≤ the parameter value corresponding to the highest bar graph, Aa ≥ the parameter value corresponding to the lowest bar graph; when the horizontal axis corresponding to the highest bar graph is greater than or equal to n, output A+a = the parameter value corresponding to the highest bar graph, and when the horizontal axis corresponding to the lowest bar graph is greater than or equal to n, output Aa = the parameter value corresponding to the lowest bar graph; n is the number of critical parameter records preset by the system; a is the parameter fluctuation value preset by the system;

[0018] Step S230: Obtain chip processing events marked as detected abnormalities in each first event set, mark the parameter values recorded in each processing link in each chip processing event that do not belong to the fluctuation range L corresponding to the same processing link as abnormal parameters, and calculate the parameter abnormality ratio U of each processing link, U = (E1 / E2)*[(1 / E1)∑(D1 / D2)], D1 represents the number of abnormal parameters, D2 represents the total number of parameter records of the same type; E1 represents the number of parameter types marked as abnormal, and E2 represents the total number of parameter types recorded in the corresponding processing link; the larger the parameter abnormality ratio U is, the more serious the abnormal state of the corresponding processing link is; mark the processing link corresponding to U greater than U0 in each type of chip as the key processing link; U0 represents the parameter abnormality ratio threshold.

[0019] Furthermore, step S300 includes the following specific steps:

[0020] Step S310: Obtain all key processing links in chip processing events corresponding to the same type of chip, extract the parameter change ratio U and the sampling abnormality index Q of the corresponding chip processing events for several groups of the same key processing links in the historical records; calculate the Pearson correlation coefficient r corresponding to each type of key processing link;

[0021] Step S320: When r=0, the output processing data has no correlation with the detection data after the first application; when the corresponding chip is tested using DFT, the original sampling ratio signal is output;

[0022] When r≠0, the output processing data is correlated with the detection data after the first application; the parameter change ratio of each key processing link of each type of chip is obtained as input data and the corresponding sampling abnormality index is used as output data to construct a functional relationship model: q(Q)=k1*U1+k2*U2+......+km *U m +ε; Substitute multiple sets of input data and output data to obtain the 1st, 2nd, ...mth reference coefficients k1, k2, ..., k of the corresponding chip type based on the functional relationship model m And the error coefficients ε, U1, U2, ..., U m It represents the parameter change ratio of the 1st, 2nd, ..., mth key processing links;

[0023] Step S330: Extract the minimum value Qmin of the sampling anomaly index of the chip processing event output in the functional relationship model corresponding to each type of chip as the critical warning value; substitute the parameter change ratio calculated by the parameter data of each processing link corresponding to the same type of chip; when the output value Q0 is less than Qmin, output the original sampling ratio signal when the corresponding type of chip is tested using DFT; when the output value Q0 is greater than or equal to Qmin, output the adjusted sampling ratio signal when the corresponding type of chip is tested using DFT;

[0024] Step S340: Adjusting the sampling ratio means obtaining the sampling anomaly index of the historical chip processing event with the smallest difference from the output value Q0 as the target index, extracting the sampling ratio B obtained during the target index calculation process as the warning sampling ratio, and using DFT to test the real-time analysis chip to determine the sampling ratio, and outputting a warning signal greater than the warning sampling ratio.

[0025] Furthermore, step S400 includes:

[0026] Step S410: Adjusting the sampling data of the normal processing event record refers to reducing the sampling ratio of the chip type corresponding to the normal processing event when using DFT testing, marking the chip type with the adjusted sampling ratio as the chip to be investigated, and marking the corresponding chip processing event as the chip processing event to be investigated;

[0027] Step S420: Obtain the real-time sampling anomaly index of the chip processing event to be examined. When the real-time sampling anomaly index is less than 0 and the absolute value of the real-time sampling anomaly index is greater than or equal to the system preset difference threshold, output an adjusted chip processing event anomaly detection unstable signal, modify the sampling data of the corresponding type of chip to the original sampling ratio; and feedback; when the real-time sampling anomaly index is greater than 0 or the real-time sampling anomaly index is less than 0 and the absolute value of the real-time sampling anomaly index is less than the system preset difference threshold, retain the adjusted sampling ratio and update it; and output an adjusted chip processing event anomaly detection stable signal;

[0028] Step S430: Based on the abnormality detection stable signal, continue to reduce the sampling ratio of the corresponding type of chip until the adjusted chip processing event abnormality detection unstable signal is output, return to the previous adjustment event, and determine that the sampling ratio recorded in the previous adjustment event is the final sampling ratio of the corresponding type of chip.

[0029] The integrated circuit processing flow management system based on big data includes a chip processing event acquisition module, an abnormal event detection and determination module, a key processing link analysis module, a correlation relationship analysis module, a sampling warning signal output module, and an adjustment and verification module;

[0030] The chip processing event acquisition module is used to obtain chip processing events using DFT design;

[0031] The detection abnormality event determination module is used to determine the chip processing event with detection abnormality based on the sampling data and the detection data;

[0032] The key processing link analysis module is used to analyze the key processing links that affect the detection of abnormalities based on processing data;

[0033] The correlation analysis module is used to determine whether there is a correlation between the processing data and the detection data after the first application in the chip processing events marked as detection anomalies in the same chip records;

[0034] The sampling warning signal output module is used to output sampling warning signals for each type of chip when testing using DFT based on the existence or non-existence of the correlation relationship;

[0035] The adjustment and verification module is used to remove abnormal chip processing events, mark other chip processing events in the historical records as normal processing events, adjust the sampling data of normal processing event records, and verify the abnormal detection stability of the chip processing events of the corresponding chip type after adjustment.

[0036] Furthermore, the key processing link analysis module includes a first event set generation unit, a fluctuation interval construction unit, and a parameter change ratio calculation unit;

[0037] The first event set generating unit is used to extract chip processing events of the same type of chip that are marked as detected abnormalities and store them in a first event set corresponding to the chip type;

[0038] The fluctuation interval construction unit is used to extract the chip processing events with normal detection records in the first event set as standard processing events, and obtain the fluctuation intervals of all parameter values recorded in each processing link of the standard processing event records;

[0039] The parameter variation ratio calculation unit is used to obtain chip processing events marked as detected abnormalities in each first event set, mark the parameter values recorded in each processing link in each chip processing event that do not belong to the fluctuation range corresponding to the same processing link as variation parameters, calculate the parameter variation ratio of each processing link, and mark the processing links corresponding to the parameter variation ratio of each type of chip that is greater than the parameter variation ratio threshold as key processing links.

[0040] Furthermore, the correlation relationship analysis module includes a correlation coefficient analysis unit, a function relationship model construction unit, a data substitution unit and a sampling ratio adjustment unit;

[0041] The correlation coefficient analysis unit is used to calculate the Pearson correlation coefficient corresponding to each key processing link;

[0042] The function relationship model building unit is used to obtain the parameter change ratio of each key processing link recorded for each type of chip as input data and the corresponding sampling abnormality index as output data to build a function relationship model;

[0043] The data substitution unit is used to extract the minimum value of the sampling anomaly index of the output chip processing event in the functional relationship model corresponding to each type of chip as the critical warning value; substitute the parameter change ratio calculated by the parameter data corresponding to each processing link of the same type of chip; and transmit the signal to the sampling warning signal output module based on the output result;

[0044] The sampling ratio adjustment unit is used to adjust the sampling ratio when the output value is greater than or equal to the critical warning value.

[0045] Furthermore, the adjustment and verification module includes a data marking unit to be inspected, a data verification unit, and a sampling ratio confirmation unit;

[0046] The data marking unit to be examined is used to mark the chip type for adjusting the sampling ratio as the chip to be examined, and the corresponding chip processing event as the chip processing event to be examined;

[0047] The data verification unit is used to verify the sampling anomaly index for reducing the sampling ratio;

[0048] The sampling ratio confirmation unit is used to continuously reduce the final sampling ratio of the chip that outputs the abnormality detection stable signal.

[0049] Compared with the prior art, the present invention has the following beneficial effects: the present invention extracts and analyzes chip processing events recorded by various types of chips implementing DFT technology, determines whether the parameter data of each processing link of the processing flow recorded in the chip processing event is abnormal, and combines the device abnormality results obtained after the chip processing is completed and the DFT performance test is passed and applied to the equipment to verify the degree of influence of the sampling data on the comprehensiveness of the processing test results of the same batch of chips during the DFT performance test; based on this, the corresponding sampling ratio after the implementation of DFT technology for different types of chips is analyzed, and the parameter changes of each processing link in the processing flow are used to determine the sampling ratio after the processing is completed, thereby reducing the cost of using DFT while improving the accuracy of detection; in addition, the present application also realizes the analysis of the reduction of the sampling ratio in normal processing events, verifies whether the detection accuracy is guaranteed after the ratio is reduced, and then determines whether it is reduced; thereby further intelligently and rationally utilizing big data to realize the effective utilization of DFT detection resources and the combination of performance detection. BRIEF DESCRIPTION OF THE DRAWINGS

[0050] The accompanying drawings are used to provide a further understanding of the present invention and constitute a part of the specification. Together with the embodiments of the present invention, they are used to explain the present invention and do not constitute a limitation of the present invention. In the accompanying drawings:

[0051] Figure 1 It is a structural diagram of the integrated circuit processing flow management system based on big data of the present invention. DETAILED DESCRIPTION

[0052] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of the present invention.

[0053] See also Figure 1 , the present invention provides a technical solution: an integrated circuit processing flow management system based on big data, including a chip processing event acquisition module, an abnormal event detection determination module, a key processing link analysis module, a correlation relationship analysis module, a sampling warning signal output module and an adjustment and verification module;

[0054] The chip processing event acquisition module is used to obtain chip processing events using DFT design;

[0055] The detection abnormality event determination module is used to determine the chip processing event with detection abnormality based on the sampling data and the detection data;

[0056] The key processing link analysis module is used to analyze the key processing links that affect the detection of abnormalities based on processing data;

[0057] The correlation analysis module is used to determine whether there is a correlation between the processing data and the detection data after the first application in the chip processing events marked as detection anomalies in the same chip records;

[0058] The sampling warning signal output module is used to output sampling warning signals for each type of chip when testing using DFT based on the existence or non-existence of the correlation relationship;

[0059] The adjustment and verification module is used to remove abnormal chip processing events, mark other chip processing events in the historical records as normal processing events, adjust the sampling data of normal processing event records, and verify the abnormal detection stability of the chip processing events of the corresponding chip type after adjustment.

[0060] The key processing link analysis module includes a first event set generation unit, a fluctuation interval construction unit, and a parameter change ratio calculation unit;

[0061] The first event set generating unit is used to extract chip processing events of the same type of chip that are marked as detected abnormalities and store them in a first event set corresponding to the chip type;

[0062] The fluctuation interval construction unit is used to extract the chip processing events with normal detection records in the first event set as standard processing events, and obtain the fluctuation intervals of all parameter values recorded in each processing link of the standard processing event records;

[0063] The parameter variation ratio calculation unit is used to obtain chip processing events marked as detected abnormalities in each first event set, mark the parameter values recorded in each processing link in each chip processing event that do not belong to the fluctuation range corresponding to the same processing link as variation parameters, calculate the parameter variation ratio of each processing link, and mark the processing links corresponding to the parameter variation ratio of each type of chip that is greater than the parameter variation ratio threshold as key processing links.

[0064] The correlation relationship analysis module includes a correlation coefficient analysis unit, a function relationship model construction unit, a data substitution unit and a sampling ratio adjustment unit;

[0065] The correlation coefficient analysis unit is used to calculate the Pearson correlation coefficient corresponding to each key processing link;

[0066] The function relationship model building unit is used to obtain the parameter change ratio of each key processing link recorded for each type of chip as input data and the corresponding sampling abnormality index as output data to build a function relationship model;

[0067] The data substitution unit is used to extract the minimum value of the sampling anomaly index of the output chip processing event in the functional relationship model corresponding to each type of chip as the critical warning value; substitute the parameter change ratio calculated by the parameter data corresponding to each processing link of the same type of chip; and transmit the signal to the sampling warning signal output module based on the output result;

[0068] The sampling ratio adjustment unit is used to adjust the sampling ratio when the output value is greater than or equal to the critical warning value.

[0069] The adjustment and verification module includes a data marking unit to be inspected, a data verification unit and a sampling ratio confirmation unit;

[0070] The data marking unit to be examined is used to mark the chip type for adjusting the sampling ratio as the chip to be examined, and the corresponding chip processing event as the chip processing event to be examined;

[0071] The data verification unit is used to verify the sampling anomaly index for reducing the sampling ratio;

[0072] The sampling ratio confirmation unit is used to continuously reduce the final sampling ratio of the chip that outputs the abnormality detection stable signal.

[0073] The integrated circuit processing flow management method based on big data is characterized by comprising the following analysis steps:

[0074] Step S100: Obtain chip processing events for which a DFT design is applied. A chip processing event refers to the process from implementing a DFT design to completing chip processing and performing performance testing, and then outputting a qualified test result to first application. Sample data from the performance test record and test data after the first application are extracted. Based on the sample data and test data, chip processing events with test anomalies are determined.

[0075] Step S200: extracting the chip processing flow recorded in the abnormal chip processing event detection and the processing data of each processing link in the processing flow; analyzing the key processing links that affect the abnormality detection based on the processing data;

[0076] Step S300: Chips that use the same processing flow are grouped into one category. A determination is made as to whether there is a correlation between the processing data and the test data after the first application, recorded in the chip processing events marked as abnormal. Based on the existence of the correlation, a sampling warning signal is output for each type of chip when testing using DFT.

[0077] Step S400: Remove chip processing events with abnormal detection, mark other chip processing events in the historical records as normal processing events, adjust the sampling data of the normal processing event records, verify the abnormal detection stability of the chip processing events of the corresponding chip type after adjustment, and feedback to the processing flow management system.

[0078] Determining chip processing events with detection anomalies based on sampling data and detection data includes the following specific steps:

[0079] The sampling data records the sampled chips, sampling ratio B, and sampling result T. Sampling ratio B refers to the ratio of the number of sampled chips selected for performance testing based on DFT design to the total number of sampled chips in the same batch. Sampling result T refers to the proportion of sampled chips that failed the test. The qualified test result is considered based on the overall proportion of sampled sampled chips. If the qualified standard is set to less than or equal to 1 / 10, then when the sampling result is 3 / 100, the sampled chip test result is qualified.

[0080] The detection data refers to the application detection abnormality ratio P from the completion of chip processing to application. The application detection abnormality ratio is the ratio of the number of application devices detected as abnormal to the total number of application devices corresponding to all chips;

[0081] Using the formula: Q = B * TP;

[0082] Calculate the sampling anomaly index Q of the chip processing event. When Q<0 and |Q| is greater than or equal to the difference threshold preset by the system, mark the corresponding chip processing event as a detection anomaly and output it.

[0083] The chips analyzed in this application are all chips that implement and apply DFT technology.

[0084] Step S200 includes the following specific steps:

[0085] Step S210: Extract chip processing events marked as abnormal for the same type of chips and store them in a first event set corresponding to the chip type; the first event set also records chip processing events of the same type of chips that are normal; the processing data records the parameter types and corresponding values required to be stored in each processing link;

[0086] Step S220: extract the chip processing events that are recorded and detected normally in the first event set as standard processing events, obtain the fluctuation range L of all parameter values recorded in each processing link of the standard processing event record, and store the fluctuation range in correspondence with the corresponding parameter type; the fluctuation range refers to plotting the recorded parameters on a bar graph with the horizontal axis as the number of parameter records and the vertical axis as the parameter value, and taking the vertical axis of the bar graph corresponding to the maximum horizontal axis in the bar graph as the standard value A, constructing the fluctuation range L, L = [Aa, A+a], A+a ≤ the parameter value corresponding to the highest bar graph, Aa ≥ the parameter value corresponding to the lowest bar graph; when the horizontal axis corresponding to the highest bar graph is greater than or equal to n, output A+a = the parameter value corresponding to the highest bar graph, and when the horizontal axis corresponding to the lowest bar graph is greater than or equal to n, output Aa = the parameter value corresponding to the lowest bar graph; n is the number of critical parameter records preset by the system; a is the parameter fluctuation value preset by the system; it can be adjusted based on the parameter type of different processing links; if the total number of records is 100 times, n can be set to 10 times;

[0087] Step S230: Obtain chip processing events marked as detected abnormalities in each first event set, mark the parameter values recorded in each processing link in each chip processing event that do not belong to the fluctuation range L corresponding to the same processing link as abnormal parameters, and calculate the parameter abnormality ratio U of each processing link, U = (E1 / E2)*[(1 / E1)∑(D1 / D2)], D1 represents the number of abnormal parameters, D2 represents the total number of parameter records of the same type; E1 represents the number of parameter types marked as abnormal, and E2 represents the total number of parameter types recorded in the corresponding processing link; the larger the parameter abnormality ratio U is, the more serious the abnormal state of the corresponding processing link is; mark the processing link corresponding to U greater than U0 in each type of chip as the key processing link; U0 represents the parameter abnormality ratio threshold.

[0088] Step S300 includes the following specific steps:

[0089] Step S310: Obtain all key processing links in chip processing events corresponding to the same type of chip, extract the parameter change ratio U and the sampling abnormality index Q of the corresponding chip processing events for several groups of the same key processing links in the historical records; calculate the Pearson correlation coefficient r corresponding to each type of key processing link;

[0090] Step S320: When r=0, there is no correlation between the output processing data and the detection data after the first application; when the corresponding chip is tested using DFT, the original sampling ratio signal is output; in this application, the original sampling ratio is the same in all sampling links, that is, the sampling ratio of each chip in the chip processing event recorded by analyzing the historical sampling data;

[0091] When r≠0, the output processing data is correlated with the detection data after the first application; the parameter change ratio of each key processing link of each type of chip is obtained as input data and the corresponding sampling abnormality index is used as output data to construct a functional relationship model: q(Q)=k1*U1+k2*U2+......+k m *U m +ε; Substitute multiple sets of input data and output data to obtain the 1st, 2nd, ...mth reference coefficients k1, k2, ..., k of the corresponding chip type based on the functional relationship model m And the error coefficients ε, U1, U2, ..., U m It represents the parameter change ratio of the 1st, 2nd, ..., mth key processing links;

[0092] Step S330: Extract the minimum value Qmin of the sampling anomaly index of the chip processing event output in the functional relationship model corresponding to each type of chip as the critical warning value; substitute the parameter change ratio calculated by the parameter data of each processing link corresponding to the same type of chip; when the output value Q0 is less than Qmin, output the original sampling ratio signal when the corresponding type of chip is tested using DFT; when the output value Q0 is greater than or equal to Qmin, output the adjusted sampling ratio signal when the corresponding type of chip is tested using DFT;

[0093] Step S340: Adjusting the sampling ratio means obtaining the sampling anomaly index of the historical chip processing event with the smallest difference from the output value Q0 as the target index, extracting the sampling ratio B obtained during the target index calculation process as the warning sampling ratio, and using DFT to test the real-time analysis chip to determine the sampling ratio, and outputting a warning signal greater than the warning sampling ratio.

[0094] Step S400 includes:

[0095] Step S410: Adjusting the sampling data of the normal processing event record refers to reducing the sampling ratio of the chip type corresponding to the normal processing event when using DFT testing. The reduction ratio can be manually adjusted based on the actual sampling ratio. For example, if the initial sampling ratio is 1 / 10, it can be adjusted to 1 / 12. The chip type with the adjusted sampling ratio is marked as a chip to be examined, and the corresponding chip processing event is marked as a chip processing event to be examined.

[0096] Step S420: Obtain the real-time sampling anomaly index of the chip processing event to be examined. When the real-time sampling anomaly index is less than 0 and the absolute value of the real-time sampling anomaly index is greater than or equal to the system preset difference threshold, output an adjusted chip processing event anomaly detection unstable signal, modify the sampling data of the corresponding type of chip to the original sampling ratio; and feedback; when the real-time sampling anomaly index is greater than 0 or the real-time sampling anomaly index is less than 0 and the absolute value of the real-time sampling anomaly index is less than the system preset difference threshold, retain the adjusted sampling ratio and update it; and output an adjusted chip processing event anomaly detection stable signal;

[0097] Step S430: Based on the abnormality detection stable signal, continue to reduce the sampling ratio of the corresponding type of chip until the adjusted chip processing event abnormality detection unstable signal is output, return to the previous adjustment event, and determine that the sampling ratio recorded in the previous adjustment event is the final sampling ratio of the corresponding type of chip.

[0098] It should be noted that, in this document, relational terms such as first and second, etc., are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the terms "comprises," "comprising," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that includes a list of elements includes not only those elements but also other elements not explicitly listed, or elements inherent to such process, method, article, or apparatus.

[0099] Finally, it should be noted that the above descriptions are merely preferred embodiments of the present invention and are not intended to limit the present invention. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art will be able to modify the technical solutions described in the aforementioned embodiments or substitute equivalents for some of the technical features. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention shall be included within the scope of protection of the present invention.

Claims

1. An integrated circuit processing flow management method based on big data, characterized in that: The analysis steps include: Step S100: Obtaining a chip processing event for applying a DFT design, wherein the chip processing event refers to the process from implementing the DFT design to performing performance testing after chip processing is completed, and then to outputting a qualified test result and applying the chip for the first time; Extracting sampling data from performance test records and test data after the first application; determining chip processing events with test anomalies based on the sampling data and test data; Step S200: extracting the chip processing flow recorded in the abnormal chip processing event detection and the processing data of each processing link in the processing flow; analyzing the key processing links that affect the abnormality detection based on the processing data; The step S200 includes the following specific steps: Step S210: Extract chip processing events marked as abnormal for chips of the same type and store them in a first event set corresponding to the chip type; the first event set also records chip processing events of the same type that are normal; the processing data records the parameter types and corresponding values required to be stored in each processing link; Step S220: extracting the chip processing events that are recorded and detected normally in the first event set as standard processing events, obtaining the fluctuation range L of all parameter values recorded in each processing link of the standard processing event record, and storing the fluctuation range in correspondence with the corresponding parameter type; the fluctuation range refers to plotting the recorded parameters on a bar graph composed of the horizontal axis as the number of parameter records and the vertical axis as the parameter value, and taking the vertical axis of the bar graph corresponding to the maximum horizontal axis in the bar graph as the standard value A, constructing the fluctuation range L, L = [Aa, A+a], A+a ≤ the parameter value corresponding to the highest bar graph, Aa ≥ the parameter value corresponding to the lowest bar graph; when the horizontal axis corresponding to the highest bar graph is greater than or equal to n, output A+a = the parameter value corresponding to the highest bar graph, and when the horizontal axis corresponding to the lowest bar graph is greater than or equal to n, output Aa = the parameter value corresponding to the lowest bar graph; n is the number of critical parameter records preset by the system; a is the parameter fluctuation value preset by the system; Step S230: Obtain chip processing events marked as abnormal detection in each first event set, mark the parameter values of each processing link record in each chip processing event that do not belong to the fluctuation range L corresponding to the same processing link as abnormal parameters, and calculate the parameter abnormality ratio U of each processing link, U = (E1 / E2)*[(1 / E1)∑(D1 / D2)], D1 represents the number of abnormal parameters, D2 represents the total number of parameter records of the same type; E1 represents the number of parameter types marked as abnormal, and E2 represents the total number of parameter types recorded in the corresponding processing link; mark the processing link corresponding to U greater than U0 in each type of chip as the key processing link; U0 represents the parameter abnormality ratio threshold; Step S300: Chips that use the same processing flow are grouped into one category. A determination is made as to whether there is a correlation between the processing data and the test data after the first application, recorded in the chip processing events marked as abnormal. Based on the existence of the correlation, a sampling warning signal is output for each type of chip when testing using DFT. The step S300 includes the following specific steps: Step S310: Obtain all key processing links in chip processing events corresponding to the same type of chip, extract the parameter change ratio U and the sampling anomaly index Q of the corresponding chip processing events for several groups of the same key processing links in historical records; wherein Q = B*TP, B represents the sampling ratio, which refers to the ratio of the number of sampled object chips that were performance tested based on the DFT design to the total number of object chips in the same batch; T represents the sampling result, which refers to the proportion of sampled object chips that failed the test results after sampling; P represents the test data, which refers to the application test anomaly ratio after the chip processing is completed and applied, and the application test anomaly ratio is the ratio of the number of application devices detected as abnormal to the total number of application devices corresponding to all chips; calculate the Pearson correlation coefficient r corresponding to each type of key processing link; Step S320: When r=0, the output processing data has no correlation with the detection data after the first application; when the corresponding chip is tested using DFT, the original sampling ratio signal is output; When r≠0, the output processing data is correlated with the detection data after the first application; the parameter change ratio of each key processing link of each type of chip is obtained as input data and the corresponding sampling abnormality index is used as output data to construct a functional relationship model: q(Q)=k1*U1+k2*U2+......+k m *U m +ε; Substitute multiple sets of input data and output data to obtain the 1st, 2nd, ...mth reference coefficients k1, k2, ..., k of the corresponding chip type based on the functional relationship model m And the error coefficients ε, U1, U2, ..., U m It represents the parameter change ratio of the 1st, 2nd, ..., mth key processing links; Step S330: Extract the minimum value Qmin of the sampling anomaly index of the chip processing event output in the functional relationship model corresponding to each type of chip as the critical warning value; substitute the parameter change ratio calculated by the parameter data of each processing link corresponding to the same type of chip; when the output value Q0 is less than Qmin, output the original sampling ratio signal when the corresponding type of chip is tested using DFT; when the output value Q0 is greater than or equal to Qmin, output the adjusted sampling ratio signal when the corresponding type of chip is tested using DFT; Step S340: Adjusting the sampling ratio refers to obtaining the sampling anomaly index of the historical chip processing events with the smallest difference from the output value Q0 as the target index, extracting the sampling ratio B obtained in the target index calculation process as the warning sampling ratio, and testing the real-time analysis chip using DFT to determine the sampling ratio, outputting a warning signal greater than the warning sampling ratio; Step S400: Remove chip processing events with abnormal detection, mark other chip processing events in the historical records as normal processing events, adjust the sampling data of the normal processing event records, verify the abnormal detection stability of the chip processing events of the corresponding chip type after adjustment, and feedback to the processing flow management system.

2. The integrated circuit processing flow management method based on big data according to claim 1, characterized in that: The method of determining a chip processing event with a detection abnormality based on the sampling data and the detection data includes the following specific steps: The sampling data records the sampling object chip, sampling ratio B and sampling result T, and obtains the sampling abnormality index Q corresponding to the chip processing event calculated based on the sampling ratio B, sampling result T and detection data P according to the formula in step S310; When Q<0 and |Q| is greater than or equal to the difference threshold preset by the system, the corresponding chip processing event is marked as a detection anomaly and output.

3. The integrated circuit processing flow management method based on big data according to claim 1, characterized in that: The step S400 includes: Step S410: Adjusting the sampling data of the normal processing event record refers to reducing the sampling ratio of the chip type corresponding to the normal processing event when using DFT testing, marking the chip type with the adjusted sampling ratio as the chip to be investigated, and marking the corresponding chip processing event as the chip processing event to be investigated; Step S420: Obtain the real-time sampling anomaly index of the chip processing event to be examined. When the real-time sampling anomaly index is less than 0 and the absolute value of the real-time sampling anomaly index is greater than or equal to the system preset difference threshold, output an adjusted chip processing event anomaly detection unstable signal, modify the sampling data of the corresponding type of chip to the original sampling ratio; and feedback; when the real-time sampling anomaly index is greater than 0 or the real-time sampling anomaly index is less than 0 and the absolute value of the real-time sampling anomaly index is less than the system preset difference threshold, retain the adjusted sampling ratio and update it; and output an adjusted chip processing event anomaly detection stable signal; Step S430: Based on the abnormality detection stable signal, continue to reduce the sampling ratio of the corresponding type of chip until the adjusted chip processing event abnormality detection unstable signal is output, return to the previous adjustment event, and determine that the sampling ratio recorded in the previous adjustment event is the final sampling ratio of the corresponding type of chip.

4. An integrated circuit processing flow management system based on big data, such as the integrated circuit processing flow management method based on big data according to any one of claims 1 to 3, characterized in that: It includes chip processing event acquisition module, abnormal event detection determination module, key processing link analysis module, correlation relationship analysis module, sampling warning signal output module and adjustment verification module; The chip processing event acquisition module is used to acquire chip processing events using DFT design; The detection abnormality event determination module is used to determine the chip processing event with detection abnormality based on the sampling data and the detection data; The key processing link analysis module is used to analyze the key processing links that affect the detection of abnormalities based on processing data; The correlation analysis module is used to determine whether there is a correlation between the processing data and the detection data after the first application in the chip processing event marked as detection abnormality in the chip records of the same type; The sampling warning signal output module is used to output a sampling warning signal when testing using DFT for each type of chip based on the existence or non-existence of the correlation relationship; The adjustment and verification module is used to remove chip processing events with abnormal detection, mark other chip processing events recorded in the history as normal processing events, adjust the sampling data of the normal processing event records, and verify the abnormal detection stability of the chip processing events of the corresponding chip type after adjustment.

5. The integrated circuit processing flow management system based on big data according to claim 4, characterized in that: The key processing link analysis module includes a first event set generation unit, a fluctuation interval construction unit and a parameter change ratio calculation unit; The first event set generating unit is used to extract chip processing events of the same type of chip that are marked as detected abnormalities and store them in a first event set corresponding to the chip type; The fluctuation interval construction unit is used to extract the chip processing events with normal detection records in the first event set as standard processing events, and obtain the fluctuation intervals of all parameter values recorded in each processing link of the standard processing event records; The parameter variation ratio calculation unit is used to obtain chip processing events marked as detected abnormalities in each first event set, mark the parameter values recorded in each processing link in each chip processing event that do not belong to the fluctuation range corresponding to the same processing link as variation parameters, calculate the parameter variation ratio of each processing link, and mark the processing links corresponding to the parameter variation ratios of each type of chip that are greater than the parameter variation ratio threshold as key processing links.

6. The integrated circuit processing flow management system based on big data according to claim 5, characterized in that: The correlation relationship analysis module includes a correlation coefficient analysis unit, a function relationship model construction unit, a data substitution unit and a sampling ratio adjustment unit; The correlation coefficient analysis unit is used to calculate the Pearson correlation coefficient corresponding to each type of key processing link; The functional relationship model construction unit is used to obtain the parameter change ratio of each key processing link recorded for each type of chip as input data and the corresponding sampling abnormality index as output data to construct a functional relationship model; The data substitution unit is used to extract the minimum value of the sampling anomaly index of the chip processing event output in the functional relationship model corresponding to each type of chip as a critical warning value; substitute the parameter change ratio calculated by the parameter data corresponding to each processing link of the same type of chip; and transmit a signal to the sampling warning signal output module based on the output result; The sampling ratio adjustment unit is used to adjust the sampling ratio when the output value is greater than or equal to the critical warning value.

7. The integrated circuit processing flow management system based on big data according to claim 6, characterized in that: The adjustment and verification module includes a data marking unit to be inspected, a data verification unit and a sampling ratio confirmation unit; The to-be-investigated data marking unit is used to mark the chip type for adjusting the sampling ratio as the to-be-investigated chip, and the corresponding chip processing event as the to-be-investigated chip processing event; The data verification unit is used to verify the sampling anomaly index of the reduced sampling ratio; The sampling ratio confirmation unit is used to continuously reduce the chip that outputs the abnormality detection stable signal to determine the final sampling ratio.

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