Chip testing method and circuit

Abstract

The present invention provides a chip testing method and circuit, wherein the chip testing method includes: obtaining an eye diagram of a chip to be tested, and obtaining a reference test point and at least one edge test point located around the reference test point based on the eye diagram; detecting the reference test point and the edge test point based on a test data signal, and outputting the detection results of the reference test point and the edge test point respectively; determining whether the upper and lower limits of the chip to be tested meet the requirements based on the detection results of the reference test point and the edge test point. The above invention can effectively improve the efficiency and accuracy of chip edge testing.

Description

Technical Field

[0001] The present invention relates to the field of chip testing technology, and more specifically, to a chip testing method and a corresponding testing circuit structure. Background Art

[0002] DRAM (Dynamic Random Access Memory) is currently the most commonly used system memory storage. Its testing mainly includes edge testing of its upper and lower limits of input and output. By testing DRAM, it can be ensured that its performance meets user needs.

[0003] However, currently, DRAM performance testing is usually done by using an oscilloscope to capture superimposed signals to obtain an eye diagram to evaluate signal integrity, or by using a professional test system to test the chip. This method is costly and has low accuracy, and thus cannot achieve the optimization of the input and output characteristics of dynamic random access memory. Summary of the invention

[0004] In view of the above problems, an object of the present invention is to provide a chip testing method and circuit to solve the problems of high cost or low accuracy in existing chip testing methods.

[0005] The chip testing method provided by the present invention comprises:

[0006] Acquire an eye diagram of the chip to be tested, and acquire a reference test point and at least one edge test point located around the reference test point based on the eye diagram;

[0007] Detecting the reference test point and the edge test point based on the test data signal, and outputting the detection results of the reference test point and the edge test point respectively;

[0008] Determine whether the upper and lower limit values ​​of the chip to be tested meet the requirements according to the test results of the benchmark test point and the edge test point.

[0009] In addition, an optional technical solution is that at least one edge test point is provided.

[0010] In addition, an optional technical solution is that the edge test point includes a first edge test point, a second edge test point, a third edge test point and a fourth edge test point; wherein,

[0011] The horizontal coordinates of the first edge test point and the second edge test point are the reference upper limit signal Ref_up, and the horizontal coordinates of the third edge test point and the fourth edge test point are the reference lower limit signal Ref_dn;

[0012] The ordinates of the first edge test point and the third edge test point are the data selection left signal DQS_Left, and the ordinates of the second edge test point and the fourth edge test point are the data selection right signal DQS_Right;

[0013] The horizontal coordinate of the reference test point is the reference signal Ref_cen, and the vertical coordinate of the reference test point is the data selection reference signal DQS_CEN.

[0014] In addition, an optional technical solution is that the first edge test point, the second edge test point, the third edge test point and the fourth edge test point meet the following conditions:

[0015] Ref_up=Ref_cen+a

[0016] Ref_dn= Ref_cen-b

[0017] DQS_Left=DQS_CEN-c

[0018] DQS_Right = DQS_CEN+d

[0019] Wherein, a and b represent the vertical coordinate difference between the edge test point and the reference test point, and c and d represent the horizontal coordinate difference between the edge test point and the reference test point.

[0020] In addition, an optional technical solution is that the longitudinal coordinate difference between the edge test point and the reference test point and the horizontal coordinate difference between the edge test point and the reference test point are controlled by registers.

[0021] On the other hand, the present invention also provides a chip testing circuit, which uses the above chip testing method to test the chip to be tested, and the chip testing circuit includes: an amplifier module, a sampler module connected to the output end of the amplifier module, and a logic processing module connected to the output end of the sampler module; wherein,

[0022] The amplifier module is used to amplify the reference signals of the benchmark test points and edge test points determined according to the eye diagram of the chip to be tested;

[0023] The sampler module is used to sample and process the output signal of the amplifier module and the data selection signals of the reference test point and the edge test point;

[0024] The logic processing module is used to perform XOR processing on the output signal of the sampler module and output the detection result of the chip to be detected.

[0025] In addition, an optional technical solution is that the reference signal of the benchmark test point is a reference reference signal Ref_cen;

[0026] The reference signal of the edge test point includes a reference upper limit signal Ref_up and a reference lower limit signal Ref_dn;

[0027] The data selection signal of the reference test point is a data selection reference signal DQS_CEN;

[0028] The data selection signal of the edge test point includes a data selection left signal DQS_Left and a data selection right signal DQS_Right.

[0029] In addition, an optional technical solution is that the amplifier module includes a first amplifier, a second amplifier and a third amplifier;

[0030] The sampler module includes a first sampler connected to the first amplifier, a second sampler and a third sampler connected to the second amplifier, and a fourth sampler and a fifth sampler connected to the third amplifier;

[0031] The logic processing module includes an XOR processing module connected to the first sampler, the second sampler, the third sampler, the fourth sampler and the fifth sampler;

[0032] The XOR processing module directly outputs the detection result of the chip to be detected.

[0033] In addition, an optional technical solution is that the logic processing module includes a first logic processing module connected to the first sampler and the second sampler, a second logic processing module connected to the first sampler and the third sampler, a third logic processing module connected to the first sampler and the third sampler, and a fourth logic processing module connected to the first sampler and the fourth sampler;

[0034] The detection result of the chip to be detected is determined according to the comparison of the output results of the first logic processing module, the second logic processing module, the third logic processing module and the fourth logic processing module.

[0035] In addition, an optional technical solution is that when the output results of the first logic processing module, the second logic processing module, the third logic processing module and the fourth logic processing module are all qualified, it indicates that the detection result of the chip to be detected meets the requirements.

[0036] By utilizing the above chip testing method and circuit, the benchmark test point and multiple edge test points located around the benchmark test point can be determined according to the eye diagram of the chip to be tested, and then the benchmark test point and the edge test point can be tested. According to the test results of each point, it can be determined whether the upper and lower limit values ​​of the chip to be tested meet the requirements. Multiple test points can be tested at one time, which not only has a fast test speed and high accuracy, but also can lock the location of the error point when the test result is unqualified, saving test time and cost.

[0037] In order to achieve the above and related purposes, one or more aspects of the present invention include the features that will be described in detail later. The following description and the accompanying drawings describe some exemplary aspects of the present invention in detail. However, these aspects indicate only some of the various ways in which the principles of the present invention can be used. In addition, the present invention is intended to include all these aspects and their equivalents. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] By referring to the following description in conjunction with the accompanying drawings, and with a more comprehensive understanding of the present invention, other objects and results of the present invention will become more apparent and easy to understand. In the accompanying drawings:

[0039] Figure 1 is a flow chart of a chip testing method according to an embodiment of the present invention;

[0040] Figure 2 A schematic diagram of a chip testing method according to an embodiment of the present invention;

[0041] Figure 3 The principle of the chip test circuit according to the embodiment of the present invention is shown in FIG. Figure 1 ;

[0042] Figure 4 The principle of the chip test circuit according to the embodiment of the present invention is shown in FIG. Figure 2 ;

[0043] Figure 5 The principle of the chip test circuit according to the embodiment of the present invention is shown in FIG. Figure 3 .

[0044] The same reference numerals throughout the drawings indicate similar or corresponding features or functions. DETAILED DESCRIPTION

[0045] In the following description, for the purpose of illustration, in order to provide a comprehensive understanding of one or more embodiments, many specific details are set forth. However, it is apparent that these embodiments may also be implemented without these specific details. In other examples, for ease of describing one or more embodiments, known structures and devices are shown in the form of block diagrams.

[0046] It should be noted that the terms "first", "second", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchangeable where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, system, product, or server that includes a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products, or devices.

[0047] In the description of the present invention, it is to be understood that the terms “center”, “longitudinal”, “lateral”, “length”, “width”, “thickness”, “up”, “down”, “front”, “back”, “left”, “right”, “vertical”, “horizontal”, “top”, “bottom”, “inside”, “outside”, “clockwise”, “counterclockwise”, “axial”, “radial”, “circumferential”, etc., indicating orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the referred device or element must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as limiting the present invention.

[0048] To describe the chip testing method of the present invention in detail, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0049] Figure 1 FIG. 2 shows a schematic flow chart of a chip testing method according to an embodiment of the present invention. Figure 2 The schematic principle of the chip testing method according to the embodiment of the present invention is shown.

[0050] like Figure 1 and Figure 2 As shown together, the chip testing method of the embodiment of the present invention includes:

[0051] S100: Acquire an eye diagram of a chip to be tested, and acquire a reference test point and at least one edge test point located around the reference test point based on the eye diagram.

[0052] Among them, the eye diagram of the chip to be tested can be obtained in various ways. After the eye diagram is determined, the benchmark test point on it can be obtained according to the system. The benchmark test point can also be understood as the best test point in the eye diagram. Then, based on the benchmark test point, at least one edge test point around it is obtained. The selection of the edge test point can be controlled by a register.

[0053] S200: Detecting the reference test points and the edge test points based on the test data signal, and outputting the detection results of the reference test points and the edge test points respectively.

[0054] S300: Determine whether the upper and lower limit values ​​of the chip to be tested meet the requirements according to the test results of the reference test point and the edge test point.

[0055] Among them, the benchmark test points and edge test points are tested based on the test data signal, and the test results corresponding to the benchmark test points and edge test points can be output respectively. According to the test results of each point, it can be inferred whether the test results of the chip to be tested meet the requirements. For example, when the test results of the benchmark test point and all edge test points meet the requirements, that is, the output results of the comparison between Flag_ and Out_center shown in the figure are consistent and the test is successful, indicating that the test result of the chip to be tested is qualified. Otherwise, when any test point has an abnormal test result, that is, the output results of the comparison between Flag_ and Out_center are inconsistent, it indicates that there is a problem with the chip to be tested.

[0056] In a specific embodiment of the present invention, at least one edge test point is provided. When multiple edge test points are provided, each edge test point can be provided at any position around the reference test point, or can be provided to be symmetrically or evenly distributed about the reference test point. For example, Figure 2 In the principle schematic diagram shown, the edge test points include a first edge test point located at the upper left corner of the eye diagram, a second edge test point located at the upper right corner, a third edge test point located at the lower left corner and a fourth edge test point located at the lower right corner, and the reference test point is located at the center of the four edge test points; wherein the abscissas of the first edge test point and the second edge test point are the reference upper limit signal Ref_up, and the abscissas of the third edge test point and the fourth edge test point are the reference lower limit signal Ref_dn; the ordinates of the first edge test point and the third edge test point are the data selection left signal DQS_Left, and the ordinates of the second edge test point and the fourth edge test point are the data selection right signal DQS_Right; the abscissa of the reference test point is the reference reference signal Ref_cen, and the ordinate of the reference test point is the data selection reference signal DQS_CEN.

[0057] Specifically, the first edge test point, the second edge test point, the third edge test point and the fourth edge test point meet the following conditions:

[0058] Ref_up=Ref_cen+a

[0059] Ref_dn= Ref_cen-b

[0060] DQS_Left=DQS_CEN-c

[0061] DQS_Right = DQS_CEN+d

[0062] Among them, a and b represent the vertical coordinate difference between the edge test point and the reference test point, c and d represent the horizontal coordinate difference between the edge test point and the reference test point, a, b, c and d can all be controlled by registers, and the present invention does not limit the values ​​of the two.

[0063] Corresponding to the above-mentioned chip testing method, the present invention also provides a chip testing circuit for testing the chip to be tested using the above-mentioned chip testing method, wherein the chip testing circuit may include: an amplifier module, a sampler module connected to the output end of the amplifier module, and a logic processing module connected to the output end of the sampler module, the amplifier module is used to amplify the reference signals of the benchmark test points and edge test points determined according to the eye diagram of the chip to be tested; the sampler module is used to sample and process the output signal of the amplifier module and the data selection signals of the benchmark test points and edge test points; the logic processing module is used to perform XOR processing on the output signal of the sampler module, and output the detection result of the chip to be tested.

[0064] It can be seen that the data processing flow of the above-mentioned test circuit is as follows: the reference signals of the benchmark test points and edge test points determined according to the eye diagram of the chip to be tested are respectively input into the amplifier module; the output signal of the amplifier module and the data selection signals of the benchmark test points and edge test points are input into the sampler module; the output signal of the sampler module is input into the logic processing module, and finally the test result of the chip to be tested is output through the logic processing module.

[0065] Among them, the reference signal of the benchmark test point is the reference reference signal Ref_cen; the reference signal of the edge test point includes the reference upper limit signal Ref_up and the reference lower limit signal Ref_dn; the data selection signal of the benchmark test point is the data selection reference signal DQS_CEN; the data selection signal of the edge test point includes the data selection left signal DQS_Left and the data selection right signal DQS_Right.

[0066] Specifically, Figure 3 FIG. 4 shows a schematic structure of a chip testing circuit according to an embodiment of the present invention.

[0067] like Figure 3 As shown, in this embodiment, the amplifier module of the chip test circuit includes a first amplifier, a second amplifier, a third amplifier, a fourth amplifier and a fifth amplifier arranged in sequence from top to bottom, the sampler includes a first sampler, a second sampler, a third sampler, a fourth sampler and a fifth sampler, and the logic processing module includes a first processing module, a second processing module, a third processing module and a fourth processing module.

[0068] Among them, the input signal of the reverse input terminal of the first amplifier is the reference reference signal Ref_cen, the input signal of the non-inverting input terminal is DQ0 (DQ signal is the data signal output by the data bus), and the output signal of the output terminal of the first amplifier is input into the first sampler together with the data selection reference signal DQS_CEN. Similarly, the input signal of the reverse input terminal of the second amplifier and the third amplifier is the reference upper limit signal Ref_up, and the input signal of the non-inverting input terminal is DQ0. The input signal of the reverse input terminal of the fourth amplifier and the fifth amplifier is the reference lower limit signal Ref_dn, and the input signal of the non-inverting input terminal is DQ0.

[0069] Further, the input signal of the second sampler includes the output signal of the second amplifier and the data selection left signal DQS_Left, the input signal of the third sampler includes the output signal of the third amplifier and the data selection right signal DQS_Right, the input signal of the fourth sampler includes the output signal of the fourth amplifier and the data selection left signal DQS_Left, and the input signal of the fifth sampler includes the output signal of the fifth amplifier and the data selection right signal DQS_Right. Then, the output result of the first sampler and the output results of each sampler are simultaneously input into the corresponding logic processing module, and Out_center is output through the first sampler. Flag_upper_left, Flag_upper_right, Flag_down_left and Flag_ down _ right are output respectively through the first processing module, the second processing module, the third processing module and the fourth processing module. When all the output results are consistent, it indicates that the chip to be tested has passed the test.

[0070] In order to simplify the circuit structure, Figure 4 In the schematic structure of the chip test circuit shown, the amplifier module includes only three amplifiers, thereby saving the number of amplifier modules used and reducing the test cost.

[0071] In this embodiment, the amplifier module includes a first amplifier, a second amplifier and a third amplifier arranged from top to bottom; the sampler module includes a first sampler connected to the first amplifier, a second sampler and a third sampler connected to the second amplifier, and a fourth sampler and a fifth sampler connected to the third amplifier; the logic processing module includes a first logic processing module connected to the first sampler and the second sampler, a second logic processing module connected to the first sampler and the third sampler, a third logic processing module connected to the first sampler and the third sampler, and a fourth logic processing module connected to the first sampler and the fourth sampler; finally, according to the comparison of the output results of the first logic processing module, the second logic processing module, the third logic processing module and the fourth logic processing module, when the output results of the first logic processing module, the second logic processing module, the third logic processing module and the fourth logic processing module are all consistent, it indicates that the detection result of the chip to be detected meets the requirements.

[0072] Further, in Figure 5 In the schematic structure of the chip test circuit shown in the figure, the logic processing module is integrated, that is, the output results of the first sampler to the fifth sampler are simultaneously input into the logic processing module, and the logic processing module can be an XOR processing module, and then the test result of the chip to be tested is directly output through an XOR processing module, saving the result comparison and judgment process. Figure 5 The test circuit structure shown is more concise, but when the chip test result is failed, Figure 5 The circuit results shown do not allow for direct determination of the location of the failure point, but Figure 3 or Figure 4 The circuit structure shown can output multiple test results, thereby determining the specific error point location.

[0073] It should be noted that the above Figure 4 and Figure 5 The data processing process of the specific example shown can be referred to Figure 3 The description in the embodiments will not be repeated here, and Figure 3 , Figure 4 and Figure 5 The circuit structures shown may also be combined with each other, such as a test circuit structure including three amplifiers and a logic processing module, which is not limited by the present invention.

[0074] The chip testing method and circuit according to the present invention can determine the reference test point and multiple edge test points located around the reference test point based on the eye diagram information of the chip to be tested, detect the reference test point and the edge test point through the chip testing circuit, and determine whether the chip to be tested is qualified based on the test results of each point. By testing multiple test points at one time, the test speed and accuracy are improved. At the same time, when the test result is unqualified, the specific location of the error point can be locked, saving testing time and cost.

[0075] The chip testing method and circuit according to the present invention are described as an example with reference to the accompanying drawings. However, those skilled in the art should understand that various improvements can be made to the chip testing method and circuit proposed by the present invention without departing from the content of the present invention. Therefore, the protection scope of the present invention should be determined by the content of the attached claims.

Claims

1. A chip testing method, characterized in that: include: Acquire an eye diagram of the chip to be tested, and acquire a reference test point and at least one edge test point located around the reference test point based on the eye diagram; Detecting the reference test point and the edge test point based on the test data signal, and outputting the detection results of the reference test point and the edge test point respectively; Determine whether the upper and lower limit values ​​of the chip to be tested meet the requirements according to the test results of the benchmark test point and the edge test point; The edge test points include a first edge test point, a second edge test point, a third edge test point and a fourth edge test point; wherein, The horizontal coordinates of the first edge test point and the second edge test point are the reference upper limit signal Ref_up, and the horizontal coordinates of the third edge test point and the fourth edge test point are the reference lower limit signal Ref_dn; The ordinates of the first edge test point and the third edge test point are the data selection left signal DQS_Left, and the ordinates of the second edge test point and the fourth edge test point are the data selection right signal DQS_Right; The horizontal coordinate of the reference test point is the reference signal Ref_cen, and the vertical coordinate of the reference test point is the data selection reference signal DQS_CEN.

2. The chip testing method according to claim 1, characterized in that: The first edge test point, the second edge test point, the third edge test point and the fourth edge test point meet the following conditions: Wherein, a and b represent the vertical coordinate difference between the edge test point and the reference test point, and c and d represent the horizontal coordinate difference between the edge test point and the reference test point.

3. The chip testing method according to claim 2, characterized in that: The difference between the ordinate of the edge test point and the reference test point and the difference between the ordinate of the edge test point and the reference test point are controlled by registers.

4. A chip testing circuit, characterized in that: The chip to be tested is tested using the chip testing method according to any one of claims 1 to 3, wherein the chip testing circuit comprises: an amplifier module, a sampler module connected to the output end of the amplifier module, and a logic processing module connected to the output end of the sampler module; wherein: The amplifier module is used to amplify the reference signals of the benchmark test points and edge test points determined according to the eye diagram of the chip to be tested; The sampler module is used to sample and process the output signal of the amplifier module and the data selection signals of the reference test point and the edge test point; The logic processing module is used to perform XOR processing on the output signal of the sampler module and output the detection result of the chip to be detected.

5. The chip testing circuit according to claim 4, characterized in that: The reference signal of the benchmark test point is a reference reference signal Ref_cen; The reference signal of the edge test point includes a reference upper limit signal Ref_up and a reference lower limit signal Ref_dn; The data selection signal of the reference test point is a data selection reference signal DQS_CEN; The data selection signal of the edge test point includes a data selection left signal DQS_Left and a data selection right signal DQS_Right.

6. The chip testing circuit according to claim 4, characterized in that: The amplifier module includes a first amplifier, a second amplifier and a third amplifier; The sampler module includes a first sampler connected to the first amplifier, a second sampler and a third sampler connected to the second amplifier, and a fourth sampler and a fifth sampler connected to the third amplifier; The logic processing module includes an XOR processing module connected to the first sampler, the second sampler, the third sampler, the fourth sampler and the fifth sampler; The XOR processing module directly outputs the detection result of the chip to be detected.

7. The chip testing circuit according to claim 6, characterized in that: The logic processing module includes a first logic processing module connected to the first sampler and the second sampler, a second logic processing module connected to the first sampler and the third sampler, a third logic processing module connected to the first sampler and the third sampler, and a fourth logic processing module connected to the first sampler and the fourth sampler; The detection result of the chip to be detected is determined according to the comparison of the output results of the first logic processing module, the second logic processing module, the third logic processing module and the fourth logic processing module.

8. The chip testing circuit according to claim 7, characterized in that: When the output results of the first logic processing module, the second logic processing module, the third logic processing module and the fourth logic processing module are all consistent, it indicates that the detection result of the chip to be detected meets the requirements.

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