Test circuit, test method and chip stacking structure

Abstract

The present disclosure provides a test circuit, a test method and a chip stacking structure. The test circuit is applied to a logic chip, and includes: a first register module, which is electrically connected to a first path and a first silicon through-hole of the logic chip, and when a first test enable signal is at a first level, it is configured as a linear feedback shift register, and receives a first test signal at a first speed through the first path; when the first test enable signal is at a second level, it is configured as a common shift register, and according to a serial test protocol, the numerical value in the first register module is serially output to obtain a first test result signal. The present disclosure is at least conducive to speed testing of logic chips before stacking, saving test costs.

Description

Technical Field

[0001] The embodiments of the present disclosure relate to the field of semiconductor technology, and in particular to a test circuit, a test method, and a chip stacking structure. Background Art

[0002] With the development of integrated circuit technology, the production process of semiconductor devices has made significant progress. However, in recent years, the development of two-dimensional semiconductor technology has encountered various challenges: physical limits, existing development technology limits, and storage electron density limits. In this context, in order to solve the difficulties encountered by two-dimensional semiconductor devices and pursue lower production costs per unit storage unit, multiple chips can be stacked to form three-dimensional semiconductor devices using bonding processes (e.g., hybrid bonding, bumping, wire bonding). The testing of three-dimensional semiconductor devices, such as high bandwidth memory (HBM), has the characteristics of long and complex processes, resulting in high testing costs. Summary of the invention

[0003] The embodiments of the present disclosure provide a test circuit, a test method and a chip stacking structure, which are at least beneficial for speed testing of logic chips before stacking, thereby saving test costs.

[0004] In a first aspect, an embodiment of the present disclosure provides a test circuit, which is applied to a logic chip, including:

[0005] The first register module is electrically connected to the first path and the first through silicon via of the logic chip. When the first test enable signal is at a first level, it is configured as a linear feedback shift register to receive the first test signal at a first speed through the first path. When the first test enable signal is at a second level, it is configured as an ordinary shift register to output the numerical value in the first register module in series according to a serial test protocol to obtain a first test result signal.

[0006] In some embodiments, the test circuit further includes:

[0007] The second register module is electrically connected to the second path and the second silicon through via of the logic chip. In the mode of testing the write path in the second path, when the second test enable signal is at the first level, it is configured as a linear feedback shift register, and receives the second test signal at the first speed through the write path of the second path. When the second test enable signal is at the second level, it is configured as an ordinary shift register, and according to the serial test protocol, the numerical value in the second register module is serially output to obtain a second test result signal; in the mode of testing the read path in the second path, when the second test enable signal is at the second level, it is configured as an ordinary shift register, and according to the serial test protocol, an initial value is written to the second register module. When the second test enable signal is at the first level, it is configured as a linear feedback shift register, generates pseudo-random data, and outputs the pseudo-random data at the first speed through the read path in the second path.

[0008] In some embodiments, the first path is a command address path for transmitting a command address signal of the logic chip, and the second path is a data path for transmitting a data signal of the logic chip.

[0009] In some embodiments, the first path includes a first receiver, a command decoder, and a first sampling circuit, wherein the first receiver is electrically connected to the command address port of the logic chip; the write path in the second path includes a second receiver, a first serial-to-parallel conversion circuit, and a first transmitter, wherein the second receiver is electrically connected to the data port of the logic chip, and the first transmitter is electrically connected to the second silicon via; the read path in the second path includes a third receiver, a second serial-to-parallel conversion circuit, and a second transmitter, wherein the third receiver is electrically connected to the second silicon via, and the second transmitter is electrically connected to the data port.

[0010] In some embodiments, the first test signal is sent by the host and transmitted to the first register module via the command address port of the logic chip and the first path; the second test signal is sent by the host and transmitted to the second register module via the data port of the logic chip and the write path in the second path; the pseudo-random data is transmitted to the host via the first transmitter, the read path in the second path and the data port.

[0011] In some embodiments, the first test signal is sent by the test interface circuit of the logic chip, and is transmitted to the first register module via a third transmitter electrically connected to the command address port and the first path; the second test signal is sent by the test interface circuit of the logic chip, and is transmitted to the second register module via the second serial-to-parallel conversion circuit, the second transmitter and a write path in the second path; the pseudo-random data is transmitted to the multi-input shift register of the logic chip via the first transmitter, the third receiver and the second serial-to-parallel conversion circuit.

[0012] In some embodiments, the first register module includes:

[0013] A first input selection unit is configured such that a first input terminal receives the first test signal, a second input terminal receives test data written according to a serial test protocol, a control terminal receives the first test enable signal, when the first test enable signal is at a first level, an output terminal outputs the signal received at the first input terminal, and when the first test enable signal is at a second level, an output terminal outputs the signal received at the second input terminal;

[0014] A first clock selection unit is configured to receive a first clock signal at a first input terminal and a second clock signal at a second input terminal, and output the signal received at the first input terminal when the first test enable signal is at a first level, and output the signal received at the second input terminal when the first test enable signal is at a second level; wherein the first clock signal is used to sample a command address signal of the logic chip, and the second clock signal is a clock signal under a serial test protocol;

[0015] The first register unit includes a first AND gate, a second AND gate, a first XOR gate, a second XOR gate and M single-edge triggers; the first input end of the first AND gate receives the first test enable signal, and the second input end is electrically connected to the output end of the Mth single-edge trigger; the first input end of the first XOR gate is electrically connected to the output end of the first AND gate, and the second input end is electrically connected to the output end of the first input selection unit; the first input end of the second AND gate receives the first test enable signal, and the second input end is electrically connected to the output end of the Mth single-edge trigger; the first input end of the second XOR gate is electrically connected to the output end of the second AND gate, and the second input end is electrically connected to the output end of the Nth The output end of the single-edge trigger is electrically connected; the input end of the first single-edge trigger is electrically connected to the output end of the first XOR gate, the input end of the i-th single-edge trigger is electrically connected to the output end of the (i-1)-th single-edge trigger, the input end of the (N+1)-th single-edge trigger is electrically connected to the output end of the second XOR gate, the input end of the j-th single-edge trigger is electrically connected to the output end of the (j-1)-th single-edge trigger, the output end of the M-th single-edge trigger outputs the first test result signal, and the clock ends of the M single-edge triggers are all electrically connected to the output end of the first clock selection unit; wherein M, N, i and j are all positive integers, M>N, 2≤i≤N, (N+1) <j≤M。

[0016] In some embodiments, M=5, N=2.

[0017] In some embodiments, the second register module includes:

[0018] a second input selection unit, configured such that a first input terminal receives the second test signal, a second input terminal receives test data written according to a serial test protocol, a control terminal receives the second test enable signal, when the second test enable signal is at a first level, an output terminal outputs the signal received at the first input terminal, and when the second test enable signal is at a second level, an output terminal outputs the signal received at the second input terminal;

[0019] The second clock selection unit is configured such that the first input terminal receives a third clock signal, the second input terminal receives a fourth clock signal, and the third input terminal receives a fifth clock signal; when the second test enable signal is at a second level, the first output terminal outputs the signal received by the first input terminal; when the second test enable signal is at a first level and in a mode of testing a write path in the second path, the first output terminal outputs the signal received by the second input terminal; when the second test enable signal is at a first level and in a mode of testing a read path in the second path, the first output terminal outputs the signal received by the third input terminal; the signal output by the first output terminal is recorded as the sixth clock signal, and the signal output by the second output terminal is recorded as the seventh clock signal, and the seventh clock signal is opposite in phase to the sixth clock signal; wherein the third clock signal is a clock signal under a serial test protocol, the fourth clock signal is a clock signal used in a write path in the second path, and the fifth clock signal is a clock signal used in a read path in the second path;

[0020] The second register unit includes a third AND gate, a fourth AND gate, a third XOR gate, a fourth XOR gate and A dual-edge triggers; the first input end of the third AND gate receives the second test enable signal, and the second input end is electrically connected to the output end of the Ath dual-edge trigger; the first input end of the third XOR gate is electrically connected to the output end of the third AND gate, and the second input end is electrically connected to the output end of the second input selection unit; the first input end of the fourth AND gate receives the second test enable signal, and the second input end is electrically connected to the output end of the Ath dual-edge trigger; the first input end of the fourth XOR gate is electrically connected to the output end of the fourth AND gate, and the second input end is electrically connected to the output end of the Bth dual-edge trigger The input end of the first dual-edge trigger is electrically connected to the output end of the third XOR gate, the input end of the xth dual-edge trigger is electrically connected to the output end of the (x-1)th dual-edge trigger, the input end of the (B+1)th dual-edge trigger is electrically connected to the output end of the fourth XOR gate, the input end of the yth dual-edge trigger is electrically connected to the output end of the (y-1)th dual-edge trigger, the output end of the Ath dual-edge trigger outputs the second test result signal or the pseudo-random data, the first clock ends of the A dual-edge triggers all receive the sixth clock signal, and the second clock ends all receive the seventh clock signal; wherein A, B, x and y are all positive integers, A>B, 2≤x≤B, (B+1) <y≤A。

[0021] In some embodiments, A=5, B=2.

[0022] In some embodiments, the dual-edge trigger samples in response to the rising edge of the clock signal received at the first clock end when the second test enable signal is at the second level, and samples in response to the rising and falling edges of the clock signal received at the first clock end when the second test enable signal is at the first level.

[0023] In some embodiments, the dual-edge trigger comprises:

[0024] A first gated inverter is configured such that an input terminal is electrically connected to an input terminal of the dual-edge trigger, and a control terminal is electrically connected to a second clock terminal of the dual-edge trigger;

[0025] A first inverter is configured such that an input terminal is electrically connected to a reset terminal of the dual-edge trigger;

[0026] A first NOR gate, configured such that a first input terminal is electrically connected to an output terminal of the first gate-controlled inverter, and a second input terminal is electrically connected to an output terminal of the first inverter;

[0027] A second gated inverter is configured such that an input terminal is electrically connected to an output terminal of the first NOR gate, and a control terminal is electrically connected to a first clock terminal of the dual-edge trigger;

[0028] A third gated inverter is configured such that an input end is electrically connected to an output end of the first NOR gate, a control end is electrically connected to a first clock end of the dual-edge trigger, and an output end is electrically connected to a first input end of the first NOR gate;

[0029] A second inverter is configured such that an input end is electrically connected to an output end of the second gate-controlled inverter, and an output end is electrically connected to an output end of the dual-edge trigger;

[0030] a fourth gated inverter, configured such that an input end is electrically connected to the input end of the dual-edge trigger, and a control end is electrically connected to the first clock end of the dual-edge trigger;

[0031] a fifth AND gate, configured such that a first input terminal is electrically connected to the second test enable signal, a second input terminal is electrically connected to the output terminal of the fourth gate-controlled inverter, and an output terminal is electrically connected to the second input terminal of the second NOR gate;

[0032] The second NOR gate is configured such that a first input terminal is electrically connected to an output terminal of the first NAND gate;

[0033] a fifth gated inverter, configured such that an input end is electrically connected to the output end of the second NOR gate, a control end is electrically connected to the second clock end of the dual-edge trigger, and an output end is electrically connected to the input end of the second inverter;

[0034] a sixth gated inverter, configured such that an input end is electrically connected to the output end of the second NOR gate, a control end is electrically connected to the second clock end of the dual-edge trigger, and an output end is electrically connected to the second input end of the fifth AND gate;

[0035] A first OR gate, configured such that a first input terminal is electrically connected to the second test enable signal, and a second input terminal is electrically connected to the output terminal of the dual-edge trigger;

[0036] The first NAND gate is configured such that a first input terminal is electrically connected to a reset terminal of the dual-edge trigger, and a second input terminal is electrically connected to an output terminal of the first OR gate.

[0037] In some embodiments, the serial test protocol is the IEEE 1500 test protocol.

[0038] In a second aspect, an embodiment of the present disclosure provides a testing method applied to a logic chip, including:

[0039] Writing a first test signal to a first register module of the logic chip through a first path of the logic chip at a first speed;

[0040] Controlling the first register module to operate in a linear feedback shift register mode;

[0041] Controlling the first register module to operate in a common shift register mode, and outputting the values ​​in the first register module in series according to a serial test protocol to obtain a first test result signal;

[0042] Comparing the first test result signal with an expected value to determine whether the first path of the logic chip can work normally at a first speed;

[0043] The first register module is electrically connected to a first through silicon via of the logic chip.

[0044] In some embodiments, the testing method further comprises:

[0045] Writing a second test signal to a second register module of the logic chip at a first speed through a write path in a second path of the logic chip;

[0046] Controlling the second register module to operate in a linear feedback shift register mode;

[0047] Controlling the second register module to operate in a common shift register mode, and outputting the values ​​in the second register module in series according to a serial test protocol to obtain a second test result signal;

[0048] Comparing the second test result signal with an expected value to determine whether a write path in the second path of the logic chip can work normally at a first speed;

[0049] The second register module is electrically connected to a second through silicon via of the logic chip.

[0050] In some embodiments, the testing method further comprises:

[0051] Controlling the second register module to operate in a common shift register mode, and writing an initial value to the second register module according to a serial test protocol;

[0052] Controlling the second register module to operate in a linear feedback shift register mode to generate pseudo-random data;

[0053] outputting the pseudo-random data at a first speed through a read path in the second path;

[0054] The pseudo-random data is compared with an expected value to determine whether a read path in a second path of the logic chip can work normally at a first speed.

[0055] In a third aspect, an embodiment of the present disclosure provides a chip stacking structure, comprising a logic chip and at least one stacking unit, wherein the logic chip and the at least one stacking unit are stacked in sequence along a first direction; each of the stacking units comprises a plurality of memory chips stacked in sequence along the first direction, wherein the first direction is perpendicular to a top surface of each of the memory chips;

[0056] The logic chip includes the test circuit as described in the first aspect.

[0057] The technical solution provided by the embodiments of the present disclosure has at least the following advantages:

[0058] By designing the test circuit, the speed of the logic chip can be tested, so that part of the test of the HBM device can be moved forward. That is, the logic chip is tested before stacking, and the logic chips with qualified speed are screened out and then stacked with the memory chip. This can greatly reduce the testing cost and stacking cost. BRIEF DESCRIPTION OF THE DRAWINGS

[0059] One or more embodiments are exemplarily illustrated by pictures in the corresponding drawings, which do not constitute a limitation on the embodiments. Elements with the same reference numerals in the drawings are represented as similar elements, and the figures in the drawings do not constitute a scale limitation unless otherwise stated. In order to more clearly illustrate the embodiments of the present disclosure or the technical solutions in the traditional technology, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0060] Figure 1 A schematic diagram of the structure of a test circuit and a logic chip provided in an embodiment of the present disclosure;

[0061] Figure 2 A schematic diagram of the structure of another test circuit and logic chip provided in an embodiment of the present disclosure;

[0062] Figure 3 A schematic diagram of the structure of a specific test circuit and logic chip provided in an embodiment of the present disclosure;

[0063] Figure 4 A schematic diagram of the structure of another specific test circuit and logic chip provided in an embodiment of the present disclosure;

[0064] Figure 5 A circuit diagram of a first register module provided in an embodiment of the present disclosure;

[0065] Figure 6a is an equivalent circuit diagram of a first register unit in one case;

[0066] Figure 6b is an equivalent circuit diagram of the first register unit in another case;

[0067] Figure 7 A circuit diagram of a second register module provided in an embodiment of the present disclosure;

[0068] Figure 8 is an equivalent circuit diagram of the second register unit in one case;

[0069] Fig. 9 A circuit diagram of a dual-edge trigger provided by an embodiment of the present disclosure;

[0070] Fig.10 A flow chart of a testing method provided in an embodiment of the present disclosure;

[0071] Fig.11 A flowchart of another testing method provided by an embodiment of the present disclosure;

[0072] Fig.12 A flowchart of another testing method provided by an embodiment of the present disclosure;

[0073] Fig.13 A schematic diagram of a chip stacking structure provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0074] The following will be combined with the drawings in the embodiments of the present disclosure to clearly and completely describe the technical solutions in the embodiments of the present disclosure. It is understood that the specific embodiments described herein are only used to explain the relevant application, not to limit the application. It should also be noted that, for the convenience of description, only the parts related to the relevant application are shown in the drawings. Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those generally understood by technicians in the technical field of the present disclosure. The terms used herein are only for the purpose of describing the embodiments of the present disclosure and are not intended to limit the present disclosure. In the following description, "some embodiments" are involved, which describe a subset of all possible embodiments, but it is understood that "some embodiments" can be the same subset or different subsets of all possible embodiments, and can be combined with each other without conflict. It should be noted that the terms "first\second\third" involved in the embodiments of the present disclosure are only used to distinguish similar objects, and do not represent a specific order for the objects. It is understandable that "first\second\third" can be interchanged with a specific order or sequence where permitted, so that the embodiments of the present disclosure described here can be implemented in an order other than that illustrated or described here.

[0075] Dynamic Random Access Memory (DRAM)

[0076] Synchronous Dynamic Random Access Memory (SDRAM)

[0077] Double Data Rate SDRAM (DDR)

[0078] Low Power DDR (LPDDR)

[0079] High Bandwidth Memory (HBM)

[0080] Through Silicon Via (TSV)

[0081] Command (CMD)

[0082] Linear Feedback Shift Register (LFSR)

[0083] Multi-input Shift Register (MISR)

[0084] HBM devices include stacked logic chips and memory chips. The testing process of HBM devices is long and complicated. The speed-related tests of HBM devices are mainly concentrated after the logic chips and memory chips have been stacked. Even if it is found that some devices do not meet the speed standards, the stacked logic chips and memory chips can only be discarded together, which leads to high testing costs.

[0085] Based on this, the embodiment of the present disclosure provides a test circuit, which is applied to a logic chip, including: a first register module, which is electrically connected to the first path and the first silicon through-hole of the logic chip, and when the first test enable signal is at the first level, it is configured as a linear feedback shift register, and receives the first test signal at the first speed through the first path; when the first test enable signal is at the second level, it is configured as a common shift register, and according to the serial test protocol, the numerical value in the first register module is serially output to obtain a first test result signal. In this way, through the design of the test circuit, the speed test of the logic chip is performed, so that part of the test of the HBM device is moved forward, that is, the logic chip is tested before stacking, and the logic chip with qualified speed is screened out, and then stacked with the memory chip, which can greatly reduce the test cost and stacking cost.

[0086] The embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings.

[0087] In one embodiment of the present disclosure, see Figure 1 , which shows a schematic diagram of the structure of a logic chip 40 provided in an embodiment of the present disclosure, wherein the logic chip 40 includes a test circuit 10. Figure 1 As shown, the test circuit 10 includes:

[0088] The first register module 11 is electrically connected to the first path 20 and the first through silicon via 30 of the logic chip 40. When the first test enable signal is at a first level, it is configured as a linear feedback shift register (LFSR) to receive the first test signal at a first speed through the first path 20; when the first test enable signal is at a second level, it is configured as a common shift register to serially output the numerical value in the first register module 11 according to the serial test protocol to obtain a first test result signal.

[0089] When the speed test is performed on the first path 20 of the logic chip 40, the logic chip 40 can be set to run at the first speed, and the first test signal can be written to the first register module 11 at the first speed through the first path 20. At this time, the first register module 11 is configured as an LFSR by setting the first test enable signal to the first level. The working principle of the LFSR is to generate different output data in different clock cycles according to the input signal and the structure of the LFSR. The working principle of the LFSR is to perform a polynomial division, and the structure of the LFSR represents an intrinsic polynomial, that is, a divisor. The signal input to the LFSR represents the exponent of the dividend in the polynomial division, and the output data represents the exponent of the remainder of the polynomial division. The number of bits of the output data is the same as the number of triggers DFF in the LFSR structure. For example, if the LFSR includes 5 DFFs, then the data output by the LFSR is 5 bits. If the first test signal includes 16 bits of data, then the LFSR receives all the 16 bits of data in the first test signal within 16 clock cycles. After the 16th clock cycle, the data output by each DFF in the LFSR is related to the exponent of the remainder after the polynomial division. At this time, the first test enable signal is set to the second level, the first register module 11 is configured as a common shift register, and the numerical value in the first register module 11 is serially output according to the serial test protocol, that is, the result of each DFF in the original LFSR is serially output to obtain the first test result signal. If the first test result signal is consistent with the expected value, it means that there is no error in the first test signal at the first speed, and the first path 20 of the logic chip 40 can operate normally at the first speed, that is, it passes the test at the first speed. It can be understood that different first speeds can be set, and the value of the first speed can be continuously increased, so that the limit speed at which the logic chip 40 can operate normally can be tested. Logic chips with qualified speeds are screened out and then stacked with storage chips, which can greatly reduce the testing cost and stacking cost.

[0090] The logic chip includes a plurality of silicon through vias, each of which has a corresponding first register module for speed testing. In the test mode according to the serial test protocol, each silicon through via can be connected in series, that is, the first test result signal output by the first register module corresponding to each silicon through via is serially output in sequence. The overall data of the serial output is compared with the expected value to determine whether the logic chip can operate normally at the first speed. When writing the first test signal, the first mode register module 11 is set to LFSR, mainly to compress the data and improve the test efficiency. In order to improve the accuracy and reliability of the test, a large amount of data needs to be written to the first path 20. If the data is not compressed, the output test data will be very large. In addition, there are many silicon through vias in the logic chip, so the test efficiency will be very low. When using LFSR, no matter how large the number of data bits of the first test signal is, the number of bits output is fixed, as mentioned above, it is determined by the structure of the LFSR. For example, if the LFSR includes 5 DFFs, the data output by the LFSR is 5 bits. No matter how much data the first test signal has, the output data of the first register module 11 corresponding to the first through silicon via is 5 bits, which is multiplied by the number of through silicon vias in the logic chip 40, and is the total number of test data bits output under the test mode of the serial test protocol. In this way, using the LFSR can greatly compress the amount of data to be tested and improve the test efficiency.

[0091] In some embodiments, the serial test protocol is the IEEE 1500 test protocol.

[0092] In some embodiments, Figure 2 As shown, the test circuit 10 further includes:

[0093] The second register module 12 is electrically connected to the second path 60 and the second silicon through via 50 of the logic chip 40. In the mode of testing the write path 61 in the second path, when the second test enable signal is at the first level, it is configured as a linear feedback shift register, and receives the second test signal at a first speed through the write path 61 of the second path. When the second test enable signal is at the second level, it is configured as an ordinary shift register. According to the serial test protocol, the numerical value in the second register module 12 is serially output to obtain a second test result signal; in the mode of testing the read path 62 in the second path, when the second test enable signal is at the second level, it is configured as an ordinary shift register. According to the serial test protocol, an initial value is written to the second register module 12. When the second test enable signal is at the first level, it is configured as a linear feedback shift register, generates pseudo-random data, and outputs the pseudo-random data at the first speed through the read path 62 in the second path.

[0094] In some embodiments, the first path 20 is a command address path for transmitting a command address signal of the logic chip 40 , and the second path 60 is a data path for transmitting a data signal of the logic chip 40 .

[0095] In the mode of testing the write path 61 in the second path 60, the test method is similar to that of testing the first path 20. When the write path 61 in the second path 60 of the logic chip 40 is speed tested, the logic chip 40 can be set to run at the first speed, and the second test signal is written to the second register module 12 at the first speed through the write path 61 in the second path 60. At this time, the second register module 12 is configured as an LFSR by setting the second test enable signal to the first level. When the second test signal has been completely received, the second test enable signal is set to the second level, and the second register module 12 is configured as a common shift register. According to the serial test protocol, the numerical value in the second register module 12 is serially output, that is, the result of each DFF in the original LFSR is serially output to obtain a second test result signal. If the second test result signal is consistent with the expected value, it means that there is no error in the process of the second test signal being transmitted from the write path 61 in the second path 60 to the second register module 12 at the first speed, which means that the write path 61 in the second path 60 of the logic chip 40 can operate normally at the first speed, that is, it has passed the test at the first speed.

[0096] In the mode of testing the read path 62 in the second path, when the second test enable signal is at the second level, the second register module 12 is configured as a common shift register, and an initial value is written to the second register module 12 according to the serial test protocol. The initial value is a seed value that is not all 0, that is, the initial value cannot be all 0. After the initial value is written, the second test enable signal is set to the first level, and the second register module 12 is configured as an LFSR, so that the LFSR can be in 2 n -1 states to generate pseudo-random data, where n is the number of DFFs in the LFSR. The pseudo-random data is output at the first speed through the read path 62 in the second path 60, and compared with the expected value. If the output pseudo-random data is consistent with the expected value, it means that there is no error in the process of outputting data from the read path 62 in the second path 60, which means that the read path 62 in the second path 60 of the logic chip 40 can operate normally at the first speed, that is, it has passed the test at the first speed.

[0097] Through the design of the test circuit 10, the first path 20 and the second path 60 of the logic chip 40, that is, the command address path and the data path, are tested at various speeds. Only when both the first path 20 and the second path 60 pass the speed test, it means that the logic chip 40 can operate normally at the speed. In this way, logic chips with qualified speeds can be screened out and then stacked with memory chips, which can greatly reduce the testing cost and stacking cost.

[0098] In some embodiments, Figure 3 and Figure 4 As shown, the first path 20 includes a first receiver 21, a command decoder 22, and a first sampling circuit 23, wherein the first receiver 21 is electrically connected to the command address port CA of the logic chip 40; the write path 61 in the second path 60 includes a second receiver 611, a first serial-to-parallel conversion circuit 612 and a first transmitter 613, wherein the second receiver 611 is electrically connected to the data port DQ of the logic chip 40, and the first transmitter 613 is electrically connected to the second silicon via 50; the read path 62 in the second path 60 includes a third receiver 623, a second serial-to-parallel conversion circuit 622 and a second transmitter 621, wherein the third receiver 623 is electrically connected to the second silicon via 50, and the second transmitter 621 is electrically connected to the data port DQ.

[0099] The first receiver 21 in the first path 20 is electrically connected to the command address port CA of the logic chip 40 for receiving the command address signal. The command decoder 22 decodes the command address signal to obtain the corresponding command or specific address. The first sampling circuit 23 samples the decoded command or address and synchronizes with the clock. At the same time, the sampled command and address are sent to the first silicon via 30. The second receiver 611 in the second path 60 is electrically connected to the data port DQ of the logic chip 40 for receiving the data signal. The first serial-to-parallel conversion circuit 612 performs serial-to-parallel conversion on the data in the write path 61. The first transmitter 613 is electrically connected to the second silicon via 50 for driving the output data. The third receiver 623 in the read path 62 is electrically connected to the second silicon via 50 for receiving data from the second silicon via 50. The second serial-to-parallel conversion circuit 622 performs parallel-to-serial conversion on the data in the read path 62. The second transmitter 621 is electrically connected to the data port DQ for driving the data.

[0100] In some embodiments, Figure 3As shown, the first test signal is sent by the host 70 and transmitted to the first register module 11 via the command address port CA of the logic chip 40 and the first path 20; the second test signal is sent by the host 70 and transmitted to the second register module 12 via the data port DQ of the logic chip 40 and the write path 61 in the second path 60; the pseudo-random data is transmitted to the host 70 via the first transmitter 613, the read path 62 in the second path 60 and the data port DQ. Because the first transmitter 613 is electrically connected to the second register module 12, the pseudo-random data can be received. The output end of the first transmitter 613 is electrically connected to the second silicon through via 50, and the input end of the third receiver 623 is also electrically connected to the second silicon through via 50, so the pseudo-random data can be sent to the read path 62 in the second path 60 through the first transmitter 613.

[0101] In some embodiments, Figure 4 As shown, the first test signal is sent by the test interface circuit 80 of the logic chip 40, and is transmitted to the first register module 11 via the third transmitter 41 electrically connected to the command address port CA and the first path 20; the second test signal is sent by the test interface circuit 80 of the logic chip 40, and is transmitted to the second register module 12 via the second serial-to-parallel conversion circuit 622, the second transmitter 621 and the write path 61 in the second path 60; the pseudo-random data is transmitted to the multi-input shift register 63 of the logic chip 40 via the first transmitter 613, the third receiver 623 and the second serial-to-parallel conversion circuit 622.

[0102] In order to avoid connecting more circuits to the command address port CA and the data port DQ, increasing the capacitive load and affecting the quality of the received signal, the test interface circuit 80 on the logic chip 40 does not directly send a test signal to the command address port CA and the data port DQ. Since the output end of the third transmitter 41 is electrically connected to the command address port CA and the input end of the first receiver 21 is electrically connected to the command address port CA, the output end of the third transmitter 41 is electrically connected to the input end of the first receiver 21, and the first test signal can be sent to the first path 20 through the third transmitter 41 and transmitted to the first register module 11. Since the second test signal sent by the test interface circuit 80 is parallel data, it is first converted from parallel to serial through the second serial-to-parallel conversion circuit 622. Since the output end of the second transmitter 621 and the input end of the second receiver 611 are both electrically connected to the data port DQ, the second test signal can be sent to the write path 61 in the second path through the second transmitter 621, and then transmitted to the second register module 12. The pseudo-random data is transmitted to the multi-input shift register 63 of the logic chip 40 via the first transmitter 613 , the third receiver 623 and the second serial-to-parallel conversion circuit 622 , and is compared with the expected value in the multi-input shift register MISR.

[0103] In some embodiments, Figure 5 As shown, the first register module 11 includes:

[0104] The first input selection unit 111 is configured such that the first input terminal receives a first test signal, the second input terminal receives test data written according to a serial test protocol, the control terminal receives a first test enable signal, when the first test enable signal is at a first level, the output terminal outputs the signal received at the first input terminal, and when the first test enable signal is at a second level, the output terminal outputs the signal received at the second input terminal;

[0105] The first clock selection unit 112 is configured to receive a first clock signal at a first input terminal and a second clock signal at a second input terminal, and output the signal received at the first input terminal when the first test enable signal is at a first level, and output the signal received at the second input terminal when the first test enable signal is at a second level; wherein the first clock signal is used to sample a command address signal of a logic chip, and the second clock signal is a clock signal under a serial test protocol;

[0106] The first register unit 113 includes a first AND gate AND1, a second AND gate AND2, a first XOR gate XOR1, a second XOR gate XOR2 and M single-edge triggers (1131, 1132, 1133, 1134 and 1135 are shown as examples in the figure); the first input end of the first AND gate AND1 receives the first test enable signal, and the second input end is electrically connected to the output end of the Mth single-edge trigger; the first input end of the first XOR gate XOR1 is electrically connected to the output end of the first AND gate AND1, and the second input end is electrically connected to the output end of the first input selection unit; the first input end of the second AND gate AND2 receives the first test enable signal, and the second input end is electrically connected to the output end of the Mth single-edge trigger. The second input end is electrically connected to the output end of the Mth single-edge trigger; the first input end of the second XOR gate XOR2 is electrically connected to the output end of the second AND gate AND2, and the second input end is electrically connected to the output end of the Nth single-edge trigger; the input end of the 1st single-edge trigger is electrically connected to the output end of the first XOR gate XOR1, the input end of the i-th single-edge trigger is electrically connected to the output end of the (i-1)th single-edge trigger, the input end of the (N+1)th single-edge trigger is electrically connected to the output end of the second XOR gate XOR2, the input end of the j-th single-edge trigger is electrically connected to the output end of the (j-1)th single-edge trigger, and the output end of the Mth single-edge trigger outputs the first test result signal, and the clock ends of the M single-edge triggers are all electrically connected to the output end of the first clock selection unit; wherein M, N, i and j are all positive integers, M>N, 2≤i≤N, (N+1) <j≤M。

[0107] It can be understood that when the first test enable signal is at the first level, the first register module 11 is configured as an LFSR and needs to receive the first test signal, so the first input selection unit 111 outputs the first test signal to the first register unit 113, and the first clock selection unit 112 outputs the first clock signal to the first register unit 113, and the first clock signal is used to sample the command address signal of the logic chip. Since the first path is a command address path, it is used to transmit the command address signal of the logic chip. Therefore, when the first path transmits the first test signal during the test, the first clock signal also samples the first test signal, and the first register unit 113 also uses the first clock signal, which is conducive to the smooth reception of the first test signal. When the first test enable signal is at the second level, the first register module 11 is configured as an ordinary shift register, and it is necessary to serially output the numerical value in the first register unit 113 according to the serial test protocol to obtain the first test result signal, so the first clock selection unit 112 outputs the second clock signal, and the second clock signal is the clock signal under the serial test protocol. The first input selection unit 111 outputs the test data written according to the serial test protocol. However, in this case, according to the serial test protocol, the numerical value in the first register unit 113 needs to be output serially, so the written test data is empty, that is, no test data is written, or a fixed value that does not affect the serial output of the numerical value in the first register unit 113 is written.

[0108] In some embodiments, M=5, N=2. Figure 5 , the first register unit 113 is shown as an example with M=5 and N=2. The M single-edge triggers can be composed of D triggers, wherein the reset end of the D trigger can be connected to the reset signal of the logic chip, or the reset signal indicating the end of the test, etc., which is not specifically shown in the figure.

[0109] Taking the first level as a high level and the second level as a low level as an example, when the first test enable signal is at the first level, the first register unit 113 is configured as a LFSR, and its equivalent circuit is as follows: Figure 6a As shown. The first test signal enters the LFSR from the second input terminal Datain of the first XOR gate XOR1. Taking M=5 and N=2 as an example, the intrinsic polynomial P(x) of this LFSR is x 5 +x 2+1. As mentioned above, the working principle of LFSR is to perform a polynomial division. The structure of LFSR represents an intrinsic polynomial, that is, the divisor. The signal input to LFSR represents the exponent of the dividend in the polynomial division, and the output data represents the exponent of the remainder of the polynomial division. The number of bits of the output data is the same as the number of flip-flops DFF in the LFSR structure. Table 1 below shows a specific example. Datain represents one bit of data in the first test signal received in each step, that is, in each clock cycle, Q <1> …Q <5> In the example of Table 1, the first test signal includes 16-bit data 0110101100111010, which enters the LFSR in 16 clock cycles. After the 16th clock cycle, the data Q output by each DFF in the LFSR is <1> To Q <5> They are 11100 respectively.

[0110]

[0111] When the first test enable signal is at the second level, the first register unit 113 is configured as a common shift register, and its equivalent circuit is as follows: Figure 6b According to the serial test protocol, the value in the first register unit 113 is serially output, that is, the data Q output by each DFF in the original LFSR <1> To Q <5> Serially output to obtain a first test result signal.

[0112] It should be noted that in Figure 6a and Figure 6b In the figure, the connection of the clock terminal of each trigger is not specifically drawn in order to illustrate the equivalent circuit of the first register unit 113 in different situations. In fact, the clock terminal of each trigger is still connected to the output terminal of the first clock selection unit 112.

[0113] In some embodiments, Figure 7 As shown, the second register module 12 includes:

[0114] The second input selection unit 121 is configured such that the first input terminal receives the second test signal, the second input terminal receives the test data written according to the serial test protocol, the control terminal receives the second test enable signal, when the second test enable signal is at the first level, the output terminal outputs the signal received at the first input terminal, and when the second test enable signal is at the second level, the output terminal outputs the signal received at the second input terminal;

[0115] The second clock selection unit 122 is configured such that the first input terminal receives the third clock signal, the second input terminal receives the fourth clock signal, and the third input terminal receives the fifth clock signal. When the second test enable signal is at the second level, the first output terminal outputs the signal received at the first input terminal. When the second test enable signal is at the first level and in the mode of testing the write path 61 in the second path 60, the first output terminal outputs the signal received at the second input terminal. When the second test enable signal is at the first level and in the mode of testing the read path 62 in the second path 60, the first output terminal outputs the signal received at the third input terminal. The signal outputted from the first output terminal is recorded as the sixth clock signal, and the signal outputted from the second output terminal is recorded as the seventh clock signal, and the seventh clock signal is opposite in phase to the sixth clock signal. The third clock signal is a clock signal under the serial test protocol, the fourth clock signal is a clock signal used in the write path 61 in the second path 60, and the fifth clock signal is a clock signal used in the read path 62 in the second path 60.

[0116] The second register unit 123 includes a third AND gate AND3, a fourth AND gate AND4, a third XOR gate XOR3, a fourth XOR gate XOR4 and A double-edge triggers (1231, 1232, 1233, 1234 and 1235 are shown as examples in the figure); the first input end of the third AND gate AND3 receives the second test enable signal, and the second input end is electrically connected to the output end of the Ath double-edge trigger; the first input end of the third XOR gate XOR3 is electrically connected to the output end of the third AND gate AND3, and the second input end is electrically connected to the output end of the second input selection unit; the first input end of the fourth AND gate AND4 receives the second test enable signal, and the second input end is electrically connected to the output end of the second input selection unit. The first input terminal of the fourth XOR gate XOR4 is electrically connected to the output terminal of the fourth AND gate AND4, and the second input terminal is electrically connected to the output terminal of the Bth dual edge trigger; the input terminal of the 1st dual edge trigger is electrically connected to the output terminal of the third XOR gate XOR3, the input terminal of the xth dual edge trigger is electrically connected to the output terminal of the (x-1)th dual edge trigger, the input terminal of the (B+1)th dual edge trigger is electrically connected to the output terminal of the fourth XOR gate XOR4, the input terminal of the yth dual edge trigger is electrically connected to the output terminal of the (y-1)th dual edge trigger, and the output terminal of the Ath dual edge trigger outputs a second test result signal or pseudo-random data, the first clock terminals of the A dual edge triggers all receive the sixth clock signal, and the second clock terminals all receive the seventh clock signal; wherein A, B, x and y are all positive integers, A>B, 2≤x≤B, (B+1) <y≤A。

[0117] In some embodiments, A=5, B=2. Figure 7 , the second register unit 123 is illustrated by taking A=5, B=2 as an example.

[0118] In the mode of testing the write path 61 in the second path 60, when the second test enable signal is at the first level, the second register module 12 is configured as an LFSR and needs to receive the second test signal, so the second input selection unit 121 outputs the second test signal to the second register unit 123, and the second clock selection unit 122 outputs the fourth clock signal to the second register unit 123, and the fourth clock signal is the clock signal used in the write path 61 in the second path 60. In this way, the second register unit 123 uses the same clock as the write path 61, which is conducive to the smooth reception of the second test signal. At this time, the second register unit 123 is configured as an LFSR, and its equivalent circuit diagram is also as shown Figure 6a As shown, the working principle is similar to that of the aforementioned first register unit 113, and will not be repeated here. In the mode of testing the write path 61 in the second path 60, when the second test enable signal is at the second level, the second clock selection unit 122 outputs a third clock signal, and the third clock signal is a clock signal under the serial test protocol. The second input selection unit 121 outputs the test data written according to the serial test protocol, but in this case, according to the serial test protocol, it is necessary to output the numerical value in the second register unit 123 serially, so the written test data is empty, that is, no test data is written, or a fixed value that does not affect the serial output of the numerical value in the second register unit 123 is written. The second register unit 123 is configured as an ordinary shift register, and its equivalent circuit diagram is also shown in Figure 6b As shown, according to the serial test protocol, the values ​​in the second register unit 123 are serially output to obtain a second test result signal. It can be understood that in the mode of testing the write path 61 in the second path 60, the working principle of the second register module 12 is similar to the working principle of the first register module 11 when testing the first path 20.

[0119] In the mode of testing the read path 62 in the second path 60, when the second test enable signal is at the second level, the second input selection unit 121 outputs the test data written according to the serial test protocol, the second clock selection unit 122 outputs the third clock signal, the third clock signal is the clock signal under the serial test protocol, and the second register unit 123 is configured as a common shift register, and its equivalent circuit diagram is also as shown in FIG. Figure 6bAs shown, according to the serial test protocol, the initial value is written to the second register unit 123 through the second input selection unit 121. After the initial value is written, the second test enable signal is set to the first level, and the second input selection unit 121 outputs the second test signal to the second register unit 123. Since the read path is tested at this time, the second test signal is empty, or is a fixed value that does not affect the operation of the LFSR at this time, such as 0. The second clock selection unit 122 outputs the fifth clock signal to the second register unit 123. The fifth clock signal is the clock signal used in the read path 62 in the second path 60. In this way, the second register unit 123 uses the same clock as the read path 62, which is conducive to the second register unit to output data smoothly. At this time, the second register unit 123 is configured as an LFSR to generate pseudo-random data, and its equivalent circuit diagram is shown as follows. Figure 8 As shown. In this example, the LFSR includes 5 flip-flops, so the LFSR can jump between 31 states to generate pseudo-random data. Table 2 below shows a specific example. In step 0, the initial value 10000 is written, and the output Q of each flip-flop in step 1 to 30 is <1> To Q <5> As shown in the table. In Step 31, Q <1> To Q <5> The value of returns to 10000 and starts adjusting between 31 states again. The pseudo-random data output by the LFSR is the output Q of the last trigger. <5> .

[0120]

[0121] It should be noted that in Figure 8 In the figure, the connection of the clock terminal is not drawn mainly to illustrate the equivalent circuit of the second register unit 123. In fact, the first clock terminal of each dual-edge trigger receives the sixth clock signal, and the second clock terminal receives the seventh clock signal. The sixth clock signal and the seventh clock signal have opposite phases. The dual-edge trigger may also have a reset terminal. Figure 7 and Figure 8 Not shown in the figure, the reset terminal can be connected to the reset signal of the logic chip, or the reset signal indicating the end of the test, etc.

[0122] In some embodiments, the dual-edge trigger performs sampling in response to the rising edge of the clock signal received at the first clock terminal when the second test enable signal is at the second level, and performs sampling in response to the rising edge and falling edge of the clock signal received at the first clock terminal when the second test enable signal is at the first level. Because in the mode of testing the write path 61 or the read path 62 of the second path 60, the reception of the second test signal or the output of pseudo-random data is in high-speed mode, the dual-edge trigger is required to perform sampling at both the rising edge and the falling edge of the clock. In the test mode according to the serial test protocol, whether the second test result signal is serially output or the initial value is written, a very high speed is not required, so the dual-edge trigger can be made to sample only at the rising edge of the clock, which can save power consumption.

[0123] In some embodiments, Fig. 9 As shown, the dual-edge trigger includes:

[0124] The first gate inverter G1 is configured such that an input terminal is electrically connected to an input terminal D of a dual-edge trigger, and a control terminal is electrically connected to a second clock terminal Clkb of the dual-edge trigger;

[0125] The first inverter N1 is configured such that an input terminal thereof is electrically connected to a reset terminal Rst of a dual-edge trigger;

[0126] A first NOR gate Nor1 is configured such that a first input terminal is electrically connected to an output terminal of the first gate-controlled inverter G1, and a second input terminal is electrically connected to an output terminal of the first inverter N1;

[0127] The second gated inverter G2 is configured such that an input end is electrically connected to an output end of the first NOR gate Nor1, and a control end is electrically connected to a first clock end Clk of the dual-edge trigger;

[0128] The third gated inverter G3 is configured such that an input end is electrically connected to the output end of the first NOR gate Nor1, a control end is electrically connected to the first clock end Clk of the dual-edge trigger, and an output end is electrically connected to the first input end of the first NOR gate Nor1;

[0129] The second inverter N2 is configured such that an input end is electrically connected to an output end of the second gated inverter G2, and an output end is electrically connected to an output end Q of the dual-edge trigger;

[0130] The fourth gate inverter G4 is configured such that an input terminal is electrically connected to an input terminal D of the dual-edge trigger, and a control terminal is electrically connected to a first clock terminal Clk of the dual-edge trigger;

[0131] The fifth AND gate And5 is configured such that a first input terminal is electrically connected to the second test enable signal Test, a second input terminal is electrically connected to the output terminal of the fourth gate-controlled inverter G4, and an output terminal is electrically connected to the second input terminal of the second NOR gate Nor2.

[0132] The second NOR gate Nor2 is configured such that a first input terminal is electrically connected to an output terminal of the first NAND gate Nand1;

[0133] The fifth gated inverter G5 is configured such that an input end is electrically connected to the output end of the second NOR gate Nor2, a control end is electrically connected to the second clock end Clkb of the dual-edge trigger, and an output end is electrically connected to the input end of the second inverter N2;

[0134] The sixth gate-controlled inverter G6 is configured such that an input end is electrically connected to the output end of the second NOR gate Nor2, a control end is electrically connected to the second clock end Clkb of the dual-edge trigger, and an output end is electrically connected to the second input end of the fifth AND gate And5;

[0135] A first OR gate OR1 is configured such that a first input terminal is electrically connected to a second test enable signal Test, and a second input terminal is electrically connected to an output terminal Q of a dual-edge trigger;

[0136] The first NAND gate Nand1 is configured such that a first input terminal is electrically connected to a reset terminal Rst of a dual-edge trigger, and a second input terminal is electrically connected to an output terminal of the first OR gate OR1.

[0137] When the second test enable signal Test is at a high level, OR1 outputs a high level, the output of Nand1 depends on the signal of the reset terminal Rst, and the first input terminal of And5 receives a high level. When the reset terminal receives a high level and does not reset, the trigger composed of G1, Nor1, G3 and G2 samples at the rising edge of the first clock terminal Clk, and the trigger composed of G4, And5, Nor2, G6 and G5 samples at the falling edge of the first clock terminal Clk, thereby forming a double-edge sampling function. When the second test enable signal Test is at a low level, And5 outputs a low level, and the output of G4 cannot be transmitted backward, so sampling cannot be performed at the falling edge of the first clock terminal Clk. Only the trigger composed of G1, Nor1, G3 and G2 samples at the rising edge of the first clock terminal Clk. Nor2, G5, N2, OR1 and Nand1 form a latch structure, which is conducive to the maintenance of the output.

[0138] In summary, the test circuit provided by the embodiment of the present disclosure can perform speed tests on both the command address path and the read / write path in the data path in the logic chip by designing the corresponding register module before the silicon through-hole via. This allows part of the test of the HBM device to be moved forward, that is, the logic chip is tested before stacking, and the logic chip with qualified speed is screened out and then stacked with the memory chip, which can greatly reduce the test cost and stacking cost.

[0139] In another embodiment of the present disclosure, see Fig.10 , which shows a flow chart of a testing method. Fig.10 As shown, the method is applied to a logic chip, comprising:

[0140] S101, writing a first test signal to a first register module of a logic chip through a first path of the logic chip at a first speed;

[0141] S102, controlling the first register module to operate in a linear feedback shift register mode;

[0142] S103, controlling the first register module to operate in a common shift register mode, and outputting the values ​​in the first register module in series according to a serial test protocol to obtain a first test result signal;

[0143] S104: Compare the first test result signal with the expected value to determine whether the first path of the logic chip can work normally at the first speed.

[0144] The first register module is electrically connected to a first through silicon via of the logic chip.

[0145] If the first test result signal is consistent with the expected value, it means that there is no error in the process of transmitting the first test signal from the first path to the first register module at the first speed, which means that the first path of the logic chip can operate normally at the first speed, that is, it has passed the test at the first speed. It is understandable that different first speeds can be set and the value of the first speed can be continuously increased to test the maximum speed at which the logic chip can operate normally. Screening out logic chips with qualified speeds and stacking them with memory chips can greatly reduce the testing cost and stacking cost.

[0146] The logic chip includes a plurality of through silicon vias, each of which has a corresponding first register module for speed testing. In a test mode according to a serial test protocol, each through silicon via can be connected in series, that is, the first test result signal output by the first register module corresponding to each through silicon via is sequentially output in series. The overall data of the serial output is compared with the expected value to determine whether the logic chip can operate normally at the first speed.

[0147] In some embodiments, see Fig.11 , the test method also includes:

[0148] S201, writing a second test signal to a second register module of the logic chip at a first speed through a write path in a second path of the logic chip;

[0149] S202, controlling the second register module to operate in a linear feedback shift register mode;

[0150] S203, controlling the second register module to operate in a common shift register mode, and outputting the values ​​in the second register module in series according to the serial test protocol to obtain a second test result signal;

[0151] S204: Compare the second test result signal with the expected value to determine whether the write path in the second path of the logic chip can work normally at the first speed.

[0152] The second register module is electrically connected to a second through silicon via of the logic chip.

[0153] If the second test result signal is consistent with the expected value, it means that there is no error in the process of the second test signal being transmitted from the write path in the second path to the second register module at the first speed, which means that the write path in the second path of the logic chip can operate normally at the first speed, that is, it has passed the test at the first speed.

[0154] In some embodiments, see Fig.12 , the test method also includes:

[0155] S301, controlling the second register module to operate in a common shift register mode, and writing an initial value to the second register module according to a serial test protocol;

[0156] S302, controlling the second register module to operate in a linear feedback shift register mode to generate pseudo-random data;

[0157] S303, outputting pseudo-random data at a first speed through a read path in the second path;

[0158] S304: Compare the pseudo-random data with the expected value to determine whether the read path in the second path of the logic chip can work normally at the first speed.

[0159] If the output pseudo-random data is consistent with the expected value, it means that there is no error in the process of outputting data from the read path in the second path, which means that the read path in the second path of the logic chip can operate normally at the first speed, that is, it has passed the test at the first speed.

[0160] In some embodiments, the first path is a command address path for transmitting a command address signal of the logic chip, and the second path is a data path for transmitting a data signal of the logic chip.

[0161] The test method can perform the above test on the first path and the second path of the logic chip, that is, the command address path and the data path, at various speeds. Only when both the first path and the second path pass the speed test, it means that the logic chip can operate normally at this speed. In this way, logic chips with qualified speeds can be screened out and then stacked with memory chips, which can greatly reduce the testing cost and stacking cost.

[0162] In another embodiment of the present disclosure, see Fig.13 , which shows a schematic diagram of a chip stacking structure.

[0163] like Fig.13 As shown, the chip stacking structure includes a logic chip 40 and at least one stacking unit 90, and the logic chip 40 and the at least one stacking unit 90 are stacked in sequence along a first direction; each stacking unit includes a plurality of memory chips 91 stacked in sequence along the first direction, and the first direction is perpendicular to the top surface of each memory chip 91; the logic chip 40 includes the test circuit in the aforementioned embodiment.

[0164] The logic chip 40 included in the chip stacking structure can be subjected to the aforementioned speed test using the test circuit included therein before stacking, and only logic chips with qualified speeds are stacked with the memory chip. This can ensure the quality and yield of the chip stacking structure and reduce the testing and stacking costs.

[0165] The above are only preferred embodiments of the present disclosure and are not intended to limit the scope of protection of the present disclosure. It should be noted that in the present disclosure, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such a process, method, article or device. In the absence of further restrictions, an element defined by the sentence "includes one..." does not exclude the presence of other identical elements in the process, method, article or device including the element. The above serial numbers of the embodiments of the present disclosure are only for description and do not represent the advantages and disadvantages of the embodiments. The methods disclosed in several method embodiments provided by the present disclosure can be arbitrarily combined without conflict to obtain new method embodiments. The features disclosed in several product embodiments provided by the present disclosure can be arbitrarily combined without conflict to obtain new product embodiments. The features disclosed in several method or device embodiments provided by the present disclosure can be arbitrarily combined without conflict to obtain new method embodiments or device embodiments. The above are only specific embodiments of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any technician familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present disclosure, which should be included in the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be based on the protection scope of the claims.

Claims

1. A test circuit, characterized in that: Applied to logic chips, including: a first register module electrically connected to the first path and the first through silicon via of the logic chip, configured as a linear feedback shift register to receive the first test signal at a first speed through the first path when the first test enable signal is at a first level; configured as a common shift register to serially output the values ​​in the first register module according to a serial test protocol to obtain a first test result signal when the first test enable signal is at a second level; Wherein, the first register module includes a first register unit, a first input selection unit and a first clock selection unit; The first register unit includes M triggers, where M is a positive integer; when the first test enable signal is at a first level, it is configured as a linear feedback shift register; when the first test enable signal is at a second level, it is configured as a common shift register; The first input selection unit is configured to provide the first test signal to the first register unit in response to the first test enable signal; The first clock selection unit is configured to provide a first clock signal or a second clock signal to the first register unit in response to the first test enable signal, wherein the first clock signal is used to sample the command address signal of the logic chip, and the second clock signal is a clock signal under the serial test protocol.

2. The test circuit according to claim 1, characterized in that: Also includes: a second register module, electrically connected to the second path and the second through silicon via of the logic chip, configured as a linear feedback shift register in a mode of testing a write path in the second path when a second test enable signal is at a first level, receiving a second test signal at the first speed through the write path of the second path, and configured as a common shift register when the second test enable signal is at a second level, and outputting the values ​​in the second register module in series according to the serial test protocol to obtain a second test result signal; In the mode of testing the read path in the second path, when the second test enable signal is at the second level, it is configured as a normal shift register, and an initial value is written to the second register module according to the serial test protocol. When the second test enable signal is at the first level, it is configured as a linear feedback shift register to generate pseudo-random data, and the pseudo-random data is output at the first speed through the read path in the second path.

3. The test circuit according to claim 2, characterized in that: The first path is a command address path, which is used to transmit the command address signal of the logic chip, and the second path is a data path, which is used to transmit the data signal of the logic chip.

4. The test circuit according to claim 3, characterized in that: The first path includes a first receiver, a command decoder, and a first sampling circuit, wherein the first receiver is electrically connected to the command address port of the logic chip; the write path in the second path includes a second receiver, a first serial-to-parallel conversion circuit, and a first transmitter, wherein the second receiver is electrically connected to the data port of the logic chip, and the first transmitter is electrically connected to the second silicon via; the read path in the second path includes a third receiver, a second serial-to-parallel conversion circuit, and a second transmitter, wherein the third receiver is electrically connected to the second silicon via, and the second transmitter is electrically connected to the data port.

5. The test circuit according to claim 4, characterized in that: The first test signal is sent by the host and transmitted to the first register module via the command address port of the logic chip and the first path; the second test signal is sent by the host and transmitted to the second register module via the data port of the logic chip and the write path in the second path; the pseudo-random data is transmitted to the host via the first transmitter, the read path in the second path and the data port.

6. The test circuit according to claim 4, characterized in that: The first test signal is sent by the test interface circuit of the logic chip, and is transmitted to the first register module via the third transmitter electrically connected to the command address port and the first path; the second test signal is sent by the test interface circuit of the logic chip, and is transmitted to the second register module via the second serial-to-parallel conversion circuit, the second transmitter and the write path in the second path; the pseudo-random data is transmitted to the multi-input shift register of the logic chip via the first transmitter, the third receiver and the second serial-to-parallel conversion circuit.

7. The test circuit according to claim 1, characterized in that: The first input selection unit is configured such that a first input terminal receives the first test signal, a second input terminal receives the test data written according to the serial test protocol, a control terminal receives the first test enable signal, when the first test enable signal is at a first level, an output terminal outputs the signal received at the first input terminal, and when the first test enable signal is at a second level, an output terminal outputs the signal received at the second input terminal; The first clock selection unit is configured to receive the first clock signal at a first input terminal and the second clock signal at a second input terminal, output the signal received at the first input terminal when the first test enable signal is at a first level, and output the signal received at the second input terminal when the first test enable signal is at a second level; the M triggers are M single-edge triggers; The first register unit includes a first AND gate, a second AND gate, a first XOR gate, a second XOR gate and the M single-edge triggers; the first input end of the first AND gate receives the first test enable signal, and the second input end is electrically connected to the output end of the Mth single-edge trigger; the first input end of the first XOR gate is electrically connected to the output end of the first AND gate, and the second input end is electrically connected to the output end of the first input selection unit; the first input end of the second AND gate receives the first test enable signal, and the second input end is electrically connected to the output end of the Mth single-edge trigger; the first input end of the second XOR gate is electrically connected to the output end of the second AND gate, and the second input end is electrically connected to the output end of the first input selection unit. The output end of the Nth single-edge trigger is electrically connected to the output end of the Nth single-edge trigger; the input end of the 1st single-edge trigger is electrically connected to the output end of the first XOR gate, the input end of the i-th single-edge trigger is electrically connected to the output end of the (i-1)th single-edge trigger, the input end of the (N+1)th single-edge trigger is electrically connected to the output end of the second XOR gate, the input end of the j-th single-edge trigger is electrically connected to the output end of the (j-1)th single-edge trigger, the output end of the M-th single-edge trigger outputs the first test result signal, and the clock ends of the M single-edge triggers are all electrically connected to the output end of the first clock selection unit; wherein N, i and j are all positive integers, M>N, 2≤i≤N, (N+1) <j≤M。 8. The test circuit according to claim 7, characterized in that: M=5,N=2.

9. The test circuit according to claim 2, characterized in that: The second register module comprises: a second input selection unit, configured such that a first input terminal receives the second test signal, a second input terminal receives the test data written according to the serial test protocol, a control terminal receives the second test enable signal, when the second test enable signal is at a first level, an output terminal outputs the signal received at the first input terminal, and when the second test enable signal is at a second level, an output terminal outputs the signal received at the second input terminal; The second clock selection unit is configured such that the first input terminal receives a third clock signal, the second input terminal receives a fourth clock signal, and the third input terminal receives a fifth clock signal; when the second test enable signal is at a second level, the first output terminal outputs the signal received by the first input terminal; when the second test enable signal is at a first level and in a mode of testing a write path in the second path, the first output terminal outputs the signal received by the second input terminal; when the second test enable signal is at a first level and in a mode of testing a read path in the second path, the first output terminal outputs the signal received by the third input terminal; the signal output by the first output terminal is recorded as the sixth clock signal, and the signal output by the second output terminal is recorded as the seventh clock signal, and the seventh clock signal is opposite in phase to the sixth clock signal; wherein the third clock signal is a clock signal under the serial test protocol, the fourth clock signal is a clock signal used in the write path in the second path, and the fifth clock signal is a clock signal used in the read path in the second path; The second register unit includes a third AND gate, a fourth AND gate, a third XOR gate, a fourth XOR gate and A dual-edge triggers; the first input end of the third AND gate receives the second test enable signal, and the second input end is electrically connected to the output end of the Ath dual-edge trigger; the first input end of the third XOR gate is electrically connected to the output end of the third AND gate, and the second input end is electrically connected to the output end of the second input selection unit; the first input end of the fourth AND gate receives the second test enable signal, and the second input end is electrically connected to the output end of the Ath dual-edge trigger; the first input end of the fourth XOR gate is electrically connected to the output end of the fourth AND gate, and the second input end is electrically connected to the output end of the Bth dual-edge trigger The input end of the first dual-edge trigger is electrically connected to the output end of the third XOR gate, the input end of the xth dual-edge trigger is electrically connected to the output end of the (x-1)th dual-edge trigger, the input end of the (B+1)th dual-edge trigger is electrically connected to the output end of the fourth XOR gate, the input end of the yth dual-edge trigger is electrically connected to the output end of the (y-1)th dual-edge trigger, the output end of the Ath dual-edge trigger outputs the second test result signal or the pseudo-random data, the first clock ends of the A dual-edge triggers all receive the sixth clock signal, and the second clock ends all receive the seventh clock signal; wherein A, B, x and y are all positive integers, A>B, 2≤x≤B, (B+1) <y≤A。 10. The test circuit according to claim 9, characterized in that: A=5, B=2.

11. The test circuit according to claim 9, characterized in that: The dual-edge trigger performs sampling in response to the rising edge of the clock signal received at the first clock end when the second test enable signal is at the second level, and performs sampling in response to the rising and falling edges of the clock signal received at the first clock end when the second test enable signal is at the first level.

12. The test circuit according to claim 11, characterized in that: The dual-edge trigger comprises: A first gated inverter is configured such that an input terminal is electrically connected to an input terminal of the dual-edge trigger, and a control terminal is electrically connected to a second clock terminal of the dual-edge trigger; A first inverter is configured such that an input terminal is electrically connected to a reset terminal of the dual-edge trigger; A first NOR gate, configured such that a first input terminal is electrically connected to an output terminal of the first gate-controlled inverter, and a second input terminal is electrically connected to an output terminal of the first inverter; A second gated inverter is configured such that an input terminal is electrically connected to an output terminal of the first NOR gate, and a control terminal is electrically connected to a first clock terminal of the dual-edge trigger; A third gated inverter is configured such that an input end is electrically connected to an output end of the first NOR gate, a control end is electrically connected to a first clock end of the dual-edge trigger, and an output end is electrically connected to a first input end of the first NOR gate; A second inverter is configured such that an input end is electrically connected to an output end of the second gate-controlled inverter, and an output end is electrically connected to an output end of the dual-edge trigger; a fourth gated inverter, configured such that an input end is electrically connected to the input end of the dual-edge trigger, and a control end is electrically connected to the first clock end of the dual-edge trigger; a fifth AND gate, configured such that a first input terminal is electrically connected to the second test enable signal, a second input terminal is electrically connected to the output terminal of the fourth gate-controlled inverter, and an output terminal is electrically connected to the second input terminal of the second NOR gate; The second NOR gate is configured such that a first input terminal is electrically connected to an output terminal of the first NAND gate; a fifth gated inverter, configured such that an input end is electrically connected to the output end of the second NOR gate, a control end is electrically connected to the second clock end of the dual-edge trigger, and an output end is electrically connected to the input end of the second inverter; a sixth gated inverter, configured such that an input end is electrically connected to the output end of the second NOR gate, a control end is electrically connected to the second clock end of the dual-edge trigger, and an output end is electrically connected to the second input end of the fifth AND gate; A first OR gate, configured such that a first input terminal is electrically connected to the second test enable signal, and a second input terminal is electrically connected to the output terminal of the dual-edge trigger; The first NAND gate is configured such that a first input terminal is electrically connected to a reset terminal of the dual-edge trigger, and a second input terminal is electrically connected to an output terminal of the first OR gate.

13. The test circuit according to claim 1, characterized in that: The serial test protocol is the IEEE 1500 test protocol.

14. A testing method, characterized in that: Applied to a logic chip, implemented by the test circuit according to any one of claims 1 to 13, comprising: Writing a first test signal to a first register module of the logic chip through a first path of the logic chip at a first speed; When the first test enable signal is at a first level, controlling the first register module to operate in a linear feedback shift register mode; When the first test enable signal is at a second level, the first register module is controlled to operate in a common shift register mode, and the numerical value in the first register module is serially output according to a serial test protocol to obtain a first test result signal; Comparing the first test result signal with an expected value to determine whether the first path of the logic chip can work normally at a first speed; The first register module is electrically connected to a first through silicon via of the logic chip.

15. The testing method according to claim 14, characterized in that: Also includes: Writing a second test signal to a second register module of the logic chip at a first speed through a write path in a second path of the logic chip; Controlling the second register module to operate in a linear feedback shift register mode; Controlling the second register module to operate in a common shift register mode, and outputting the values ​​in the second register module in series according to the serial test protocol to obtain a second test result signal; Comparing the second test result signal with an expected value to determine whether a write path in the second path of the logic chip can work normally at a first speed; The second register module is electrically connected to a second through silicon via of the logic chip.

16. The testing method according to claim 15, characterized in that: Also includes: Controlling the second register module to operate in a common shift register mode, and writing an initial value to the second register module according to the serial test protocol; Controlling the second register module to operate in a linear feedback shift register mode to generate pseudo-random data; outputting the pseudo-random data at a first speed through a read path in the second path; The pseudo-random data is compared with an expected value to determine whether a read path in a second path of the logic chip can work normally at a first speed.

17. A chip stacking structure, characterized in that: The device comprises a logic chip and at least one stacking unit, wherein the logic chip and the at least one stacking unit are sequentially stacked along a first direction; each of the stacking units comprises a plurality of memory chips sequentially stacked along the first direction, wherein the first direction is perpendicular to a top surface of each of the memory chips; The logic chip comprises the test circuit as described in any one of claims 1-13.

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