Semiconductor structure and method for forming the same

Abstract

The present invention provides a semiconductor structure and a method for forming the same, wherein the method for forming the semiconductor structure comprises: providing a substrate, wherein the substrate has a first doping region; forming one or more voltage-resistant structures in the first doping region, wherein the dielectric constant of the voltage-resistant structures is lower than that of the first doping region, and the voltage-resistant structures have one or more protrusions and / or depressions; forming a body region in the first doping region, wherein the doping type of the body region is consistent with that of the first doping region and the doping concentration is greater than that of the first doping region, wherein the bottom surface of the body region is located above the top surface of the voltage-resistant structure. The above technical solution can improve the breakdown voltage of the semiconductor structure.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing technology, and in particular to a semiconductor structure and a forming method thereof. Background Art

[0002] Compared with current-controlled power devices, voltage-controlled power devices control the operating current of the device by controlling the gate voltage. At the same time, as a majority-carrier device, it is not affected by the minority-carrier storage effect and has a switching speed much faster than that of current-controlled devices, so it can be used in high-frequency environments.

[0003] However, the electrical performance of existing voltage-controlled power devices is poor.

[0004] Therefore, how to provide a technical solution to improve the electrical performance of voltage-controlled power devices has become a technical problem that needs to be solved urgently. Summary of the invention

[0005] In view of this, an embodiment of the present invention provides a semiconductor structure and a method for forming the same, which can improve the breakdown voltage of the semiconductor structure.

[0006] In order to solve the above technical problems, an embodiment of the present invention provides a method for forming a semiconductor structure.

[0007] The method of forming a semiconductor structure includes:

[0008] Providing a substrate, wherein the substrate has a first doped region;

[0009] One or more voltage-resistant structures are formed in the first doping region, wherein the dielectric constant of the voltage-resistant structures is lower than that of the first doping region, and the voltage-resistant structures have one or more protrusions and / or depressions;

[0010] A body region is formed in the first doping region, wherein the doping type of the body region is consistent with that of the first doping region and the doping concentration is higher than that of the first doping region, wherein the bottom surface of the body region is located above the top surface of the voltage-withstand structure.

[0011] Optionally, forming a voltage-resistant structure in the first doping region includes:

[0012] Performing a first round of ion implantation in the first doping region to obtain an initial voltage-resistant structure;

[0013] A second round of ion implantation is performed in the first doping region to form one or more protrusions and / or depressions on the surface of the initial voltage-withstanding structure to obtain a voltage-withstanding structure.

[0014] Optionally, there are multiple pressure-resistant structures, and there is a spacing area between every two adjacent pressure-resistant structures.

[0015] Optionally, before forming the voltage-withstand structure in the first doping region, the method for forming the semiconductor structure further includes:

[0016] A deep well doping region is formed in the first doping region, and the deep well doping region has a doping type different from that of the first doping region.

[0017] Optionally, the voltage-withstand structure is located in the deep well doping region.

[0018] Optionally, before forming the body region in the first doped region, the method for forming the semiconductor structure further includes:

[0019] forming a drift region in the first doped region;

[0020] forming a field dielectric layer on the drift region;

[0021] forming a gate dielectric layer on the first doped region adjacent to the field dielectric layer, wherein the gate dielectric layer is adjacent to the field dielectric layer;

[0022] forming a gate structure on the gate dielectric layer and the field dielectric layer;

[0023] The body region is adjacent to the drift region and is located on one side of the field dielectric layer, and the side is adjacent to the gate dielectric layer.

[0024] Optionally, the method further comprises:

[0025] forming a source region in the body region exposed by the gate dielectric layer;

[0026] A drain region is formed in the drift region exposed by the field dielectric layer.

[0027] Optionally, along the direction from the drain region to the source region, the first doped region includes at least the following three adjacent regions:

[0028] a first region located below the drain region, a third region located below the source region, and a second region located between the first region and the third region;

[0029] There are multiple pressure-resistant structures, and the multiple pressure-resistant structures are distributed in the first area, the second area, and the third area;

[0030] There is a first distance between every two adjacent pressure-resistant structures, wherein the first distance between every two adjacent pressure-resistant structures located in the first region and / or the third region is greater than the first distance between every two adjacent pressure-resistant structures located in the second region.

[0031] Optionally, the method for forming a semiconductor structure further includes:

[0032] Ions are implanted into the body region to obtain an extraction region in the body region, wherein the extraction region and the body region have the same doping type, the extraction region has a higher doping concentration than the body region, and the extraction region is adjacent to the source region.

[0033] Optionally, the semiconductor structure is a symmetrical LDMOS device, which includes two symmetrical semiconductor units, the body region belongs to the semiconductor unit, and the two semiconductor units share the same body region.

[0034] Optionally, the semiconductor structure is an LDMOS device, the LDMOS device includes a semiconductor unit, and the body region belongs to the semiconductor unit;

[0035] The method of forming a semiconductor structure also includes:

[0036] Ion implantation is performed on the first doped region to obtain a connection region, which is ring-shaped; the depth of the connection region is less than the depth of the deep well doped region, and the connection region is connected to the deep well doped region, the doping type of the connection region is consistent with that of the deep well doped region, and the doping concentration is less than or equal to that of the deep well doped region.

[0037] Optionally, the method for forming a semiconductor structure further includes:

[0038] Ion implantation is performed on the connection region to obtain a first isolation ring in the connection region, wherein the doping type of the first isolation ring is consistent with that of the connection region, and the doping concentration of the first isolation ring is higher than that of the connection region.

[0039] Optionally, the semiconductor structure is an LDMOS device, the LDMOS device includes a semiconductor unit, and the body region belongs to the semiconductor unit;

[0040] Before forming the body region, the method for forming the semiconductor structure further includes:

[0041] The substrate is etched to obtain an isolation ring groove, wherein the isolation ring groove is arranged around the semiconductor unit;

[0042] The isolation ring groove is filled to obtain a second isolation ring.

[0043] To solve the above technical problems, an embodiment of the present invention provides a semiconductor structure. The semiconductor structure includes:

[0044] A substrate having a first doped region therein;

[0045] One or more voltage-resistant structures located in the first doping region, the dielectric constant of the voltage-resistant structures being lower than that of the first doping region, and the voltage-resistant structures having one or more protrusions and / or depressions;

[0046] The body region is located in the first doping region, the doping type of the body region is consistent with that of the first doping region and the doping concentration is higher than that of the first doping region, wherein the bottom surface of the body region is located above the top surface of the voltage-withstand structure.

[0047] Optionally, there are multiple pressure-resistant structures, and there is a spacing area between every two adjacent pressure-resistant structures.

[0048] Optionally, the semiconductor structure further comprises:

[0049] The deep well doping region is located in the first doping region, and the doping type of the deep well doping region is different from that of the first doping region.

[0050] Optionally, the voltage-withstand structure is located in the deep well doping region.

[0051] Optionally, the semiconductor structure further comprises:

[0052] a drift region located within the first doped region;

[0053] a field dielectric layer located on the drift region;

[0054] A gate dielectric layer located on the first doped region adjacent to the field dielectric layer, the gate dielectric layer being adjacent to the field dielectric layer;

[0055] A gate structure located on a gate dielectric layer and a field dielectric layer; wherein the body region is adjacent to the drift region and is located on one side of the field dielectric layer, and the side is adjacent to the gate dielectric layer;

[0056] A source region located in a body region exposed by the gate dielectric layer;

[0057] The drain region is located in the drift region exposed by the field dielectric layer.

[0058] Optionally, along the direction from the drain region to the source region, the first doped region includes at least the following three adjacent regions:

[0059] a first region located below the drain region, a third region located below the source region, and a second region located between the first region and the third region;

[0060] There are multiple pressure-resistant structures, and the multiple pressure-resistant structures are distributed in the first area, the second area, and the third area;

[0061] There is a first distance between every two adjacent pressure-resistant structures, wherein the first distance between every two adjacent pressure-resistant structures located in the first region and / or the third region is greater than the first distance between every two adjacent pressure-resistant structures located in the second region.

[0062] Optionally, the semiconductor structure further comprises:

[0063] The extraction region is located in the body region, wherein the extraction region and the body region have the same doping type, the extraction region has a higher doping concentration than the body region, and the extraction region is adjacent to the source region.

[0064] Optionally, the semiconductor structure is a symmetrical LDMOS device, which includes two symmetrical semiconductor units, the body region belongs to the semiconductor unit, and the two semiconductor units share the same body region.

[0065] Optionally, the semiconductor structure is an LDMOS device, the LDMOS device includes a semiconductor unit, and the body region belongs to the semiconductor unit;

[0066] The semiconductor structure also includes:

[0067] A connection region located in the first doping region, the connection region is ring-shaped; the depth of the connection region is less than the depth of the deep well doping region, and the connection region is connected to the deep well doping region, the doping type of the connection region is consistent with the deep well doping region, and the doping concentration is less than or equal to the deep well doping region.

[0068] Optionally, a first isolation ring is located in the connection region, wherein the doping type of the first isolation ring is consistent with that of the connection region, and the doping concentration of the first isolation ring is higher than that of the connection region.

[0069] Optionally, the semiconductor structure is an LDMOS device, the LDMOS device includes a semiconductor unit, and the body region belongs to the semiconductor unit;

[0070] The semiconductor structure also includes:

[0071] The second isolation ring is located in the first doping region, and the second isolation ring groove is arranged around the semiconductor unit.

[0072] Compared with the prior art, the technical solution of the embodiment of the present invention has the following advantages:

[0073] Since the bottom surface of the body region is located above the top surface of the voltage-resistant structure, the depth of the bottom surface of the body region is less than the depth of the top surface of the voltage-resistant structure, that is, the voltage-resistant structure is located below the body region, and the voltage-resistant structure is deeply buried in the substrate; and the dielectric constant of the voltage-resistant structure is lower than that of the first doped region. Compared with the case where no voltage-resistant structure is provided, the voltage-resistant structure can increase the pressure-bearing ratio of the first doped region below the body region corresponding to the position of the voltage-resistant structure, thereby increasing the breakdown voltage of the semiconductor structure; at the same time, since the voltage-resistant structure has one or more protrusions and / or depressions, the protrusions and / or depressions can bind the ionized charges, enhance the electric field strength within the voltage-resistant structure, and further increase the pressure-bearing ratio of the voltage-resistant structure, thereby further increasing the breakdown voltage of the semiconductor structure.

[0074] Furthermore, by successively forming the initial pressure-resistant structure and the raised portion and / or recessed portion of the pressure-resistant structure, the accuracy of the position of the raised portion and / or recessed portion on the initial pressure-resistant structure can be improved.

[0075] Furthermore, the first doped regions at both ends of the spacing region can be connected through the spacing region, so that the spacing region between every two adjacent voltage-resistant structures can be used as a heat dissipation channel to improve the heat dissipation performance of the semiconductor structure.

[0076] Furthermore, the two PN junctions formed between the deep well doping region and the first doping regions on both sides thereof are in opposite directions, thereby reducing the probability of carrier interconnection between the first doping regions on both sides of the deep well doping region, thereby achieving electrical isolation between the first doping regions on both sides of the deep well doping region.

[0077] Furthermore, by arranging the voltage-resistant structure in the deep well doping region, the amount of charges bound by the voltage-resistant structure can be further increased, thereby further increasing the pressure-bearing value of the voltage-resistant structure.

[0078] Furthermore, the charges bound on the voltage-resistant structure can increase the electric field within the adjacent voltage-resistant structure. By reducing the first distance between every two adjacent voltage-resistant structures in the first region and / or the third region, the electric field and the voltage-resistant value within the voltage-resistant structure in the first region and / or the third region can be increased, thereby increasing the breakdown voltage of the semiconductor structure at the drain region along the direction perpendicular to the substrate surface and reducing the probability of premature breakdown of the semiconductor structure at the drain region.

[0079] Furthermore, the doping type of the connection region is consistent with that of the deep well doping region, that is, different from the doping type of the first doping region, so that a PN junction can be formed between the connection region and the first doping region to avoid the influence of carriers in the connection region entering the first doping region on the semiconductor unit. BRIEF DESCRIPTION OF THE DRAWINGS

[0080] In order to more clearly illustrate the technical solutions of the embodiments of this specification, the drawings required for use in the embodiments of this specification or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this specification. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0081] Figure 1 is a flow chart of a method for forming a semiconductor structure in an embodiment of the present invention;

[0082] Figures 2 to 5 It is a schematic cross-sectional structure diagram corresponding to each step in a method for forming a semiconductor structure in an embodiment of the present invention.

[0083] Description of reference numerals:

[0084] Substrate 100, first doped region 110, deep well doped region 120, connection region 130, drift region 140, body region 150, source region 160, drain region 170, first isolation ring 180, extraction region 190, voltage-resistant structure 200, initial voltage-resistant structure 210, protrusion 220, first spacing d, second isolation ring 300, field dielectric layer 410, gate dielectric layer 420, gate structure 430. DETAILED DESCRIPTION

[0085] As before, the performance of existing voltage-controlled power devices is poor.

[0086] Taking the MOS diffused-Double Lateral (LDMOS) device as an example, if the peak electric field in the LDMOS device exceeds the critical electric field, the device will break down. The voltage at this time is called the breakdown voltage of the LDMOS device.

[0087] The breakdown voltage of existing LDMOS devices is relatively low.

[0088] In order to solve the above technical problems, in an embodiment of the present invention, one or more voltage-resistant structures can be formed in the first doping region of the substrate, the voltage-resistant structure having one or more protrusions and / or recessed portions, and a dielectric constant lower than that of the first doping region, and then a body region is formed in the first doping region of the substrate, and the bottom surface of the body region is located above the top surface of the voltage-resistant structure.

[0089] By adopting the above scheme, since the bottom surface of the body region is located above the top surface of the voltage-resistant structure, the depth of the bottom surface of the body region is less than the depth of the top surface of the voltage-resistant structure, that is, the voltage-resistant structure is located below the body region, and the voltage-resistant structure is deeply buried in the substrate; and the dielectric constant of the voltage-resistant structure is lower than that of the first doped region. Compared with the case where no voltage-resistant structure is provided, the voltage-resistant structure can increase the pressure-bearing ratio of the first doped region below the body region corresponding to the position of the voltage-resistant structure, thereby increasing the breakdown voltage of the semiconductor structure; at the same time, since the voltage-resistant structure has one or more protrusions and / or depressions, the protrusions and / or depressions can bind the ionized charges, enhance the electric field strength within the voltage-resistant structure, and further increase the pressure-bearing ratio of the voltage-resistant structure, thereby further increasing the breakdown voltage of the semiconductor structure.

[0090] In order to make the above-mentioned objects, features and beneficial effects of the present invention more obvious and easy to understand, specific embodiments of the present invention are described in detail below with reference to the accompanying drawings.

[0091] Reference Figure 1 , Figure 1 A flow chart of a method for forming a semiconductor structure in an embodiment of the present invention is shown. The method for forming a semiconductor device may include steps S11 to S13:

[0092] Step S11: providing a substrate, wherein the substrate has a first doped region;

[0093] Step S12: forming one or more voltage-resistant structures in the first doping region, wherein the dielectric constant of the voltage-resistant structures is lower than that of the first doping region, and the voltage-resistant structures have one or more protrusions and / or depressions;

[0094] Step S13: forming a body region in the first doping region, wherein the doping type of the body region is consistent with that of the first doping region and the doping concentration is higher than that of the first doping region, wherein the bottom surface of the body region is located above the top surface of the voltage-withstand structure.

[0095] The following combination Figures 2 to 5 The above-mentioned formation method is explained.

[0096] Figures 2 to 5 It is a schematic cross-sectional structure diagram corresponding to each step in a method for forming a semiconductor structure in an embodiment of the present invention.

[0097] Reference Figure 2 , providing a substrate 100, wherein the substrate 100 has a first doping region 110.

[0098] The substrate 100 is used to provide a process platform for the subsequent formation of a semiconductor structure.

[0099] The substrate 100 may be a silicon substrate, or the material of the substrate 100 may also include germanium, silicon germanium, silicon carbide, gallium arsenide or indium gallium. The substrate 100 may also be a silicon substrate on an insulator or a germanium substrate on an insulator, or a substrate on which an epitaxial layer (Epitaxylayer, Epilayer) is grown.

[0100] The first doped region 110 is used to reduce the resistance of the substrate 100, thereby reducing power consumption and heat of the semiconductor structure.

[0101] The doping type of the first doping region 110 may be P-type doping or N-type doping.

[0102] It should be noted that, in the following description, P-type doping may be used as an example for explanation, but it does not constitute a limitation on the specific doping type used in the first doping region 110 .

[0103] Continue to refer to Figure 2 , a deep well doping region 120 is formed in the first doping region 110 .

[0104] The deep well doping region 120 and the first doping region 110 have different doping types.

[0105] Specifically, the two PN junctions formed between the deep well doping region 120 and the first doping regions 110 on both sides thereof are inversely spaced, thereby reducing the probability of carrier interconnection between the first doping regions 110 on both sides of the deep well doping region 120, thereby achieving electrical isolation between the first doping regions 110 on both sides of the deep well doping region 120.

[0106] Continue to refer to Figure 2 , an initial voltage-withstanding structure 210 is formed in the first doping region 110 .

[0107] The dielectric constant of the initial voltage-withstanding structure 210 is lower than that of the first doped region 110 .

[0108] Specifically, the dielectric constant of the initial voltage-withstanding structure 210 is lower than that of the first doped region 110 . Under the same path length, the initial voltage-withstanding structure 210 bears a higher voltage, thereby improving the breakdown voltage of the semiconductor structure.

[0109] In some embodiments, the initial voltage-resistant structure 210 may be formed by ion implantation and annealing in a subsequent process. For example, oxygen ions may be implanted. For example, nitrogen ions may be implanted.

[0110] Reference Figure 3 , a pressure-resistant structure 200 is formed based on the initial pressure-resistant structure 210 .

[0111] The pressure-resistant structure 200 has a protrusion 220 and / or a depression (not shown) formed on the surface of the initial pressure-resistant structure 210 .

[0112] It should be noted that in the embodiment shown in the figure, the formation of the protrusion 220 is used as an example for description. In a specific implementation, a recessed portion may also be formed, or a plurality of protrusions 220 may be formed to obtain a recessed portion between adjacent protrusions 220 .

[0113] Specifically, the raised portion 220 and / or the recessed portion can bind the charges generated by ionization in the first doped region 110, and the charges can further increase the voltage borne by the voltage-resistant structure 200, thereby increasing the breakdown voltage of the semiconductor structure; at the same time, by successively forming the initial voltage-resistant structure 210 and the raised portion 220 and / or the recessed portion of the voltage-resistant structure 200, the accuracy of the position of the raised portion 220 and / or the recessed portion on the initial voltage-resistant structure 210 can be increased.

[0114] In some embodiments, the protrusion 220 can be obtained by ion implantation and subsequent annealing. For example, oxygen ions or nitrogen ions can be implanted into the first doping region 110 outside the initial voltage-resistant structure 210 to obtain the protrusion 220, which is adjacent to the surface of the initial voltage-resistant structure 210.

[0115] In some embodiments, the recessed portion may be formed by ion implantation and subsequent annealing. For example, ions capable of inverting the initial voltage-resistant structure 210 may be implanted into the initial voltage-resistant structure 210 and then annealed in a subsequent process to obtain the recessed portion, such as hydrogen ions, and the recessed portion is adjacent to the first doped region 110.

[0116] In some embodiments, there may be multiple protrusions 220 and / or recesses on the pressure-resistant structure 200 .

[0117] Specifically, providing a plurality of protrusions 220 and / or recesses can increase the surface area of ​​the voltage-resistant structure 200 , thereby increasing the amount of bound charges, thereby further increasing the voltage that the voltage-resistant structure 200 can withstand.

[0118] In some embodiments, there may be a plurality of voltage-resistant structures 200 , and a spacing region may be provided between every two adjacent voltage-resistant structures 200 . The spacing between the spacing regions is a first spacing d, and the spacing regions belong to the first doping region 110 .

[0119] Specifically, the first doped regions 110 at both ends of the spacing region can be connected through the spacing region, so the spacing region can serve as a heat dissipation channel to improve the heat dissipation performance of the semiconductor structure.

[0120] In some embodiments, the protrusion 220 and / or the depression may be located on a side of the pressure-resistant structure 200 adjacent to the surface of the substrate 100 .

[0121] Specifically, compared with the first doped region 110 on the side of the voltage-resistant structure 200 away from the surface of the substrate 100, the first doped region 110 on the side adjacent to the surface of the substrate 100 has more ionized charges. By arranging the protrusion 220 and / or the recessed portion on the side of the voltage-resistant structure 200 adjacent to the top surface of the substrate 100, the amount of bound charges can be increased, thereby further increasing the pressure-bearing value of the voltage-resistant structure 200.

[0122] It should be noted that the above embodiments do not constitute a limitation on the location of the protrusion 220 and / or the depression on the pressure-resistant structure 200. For example, the protrusion 220 and / or the depression may be located on the side of the pressure-resistant structure 200 away from the surface of the substrate 100. For example, the protrusion 220 and / or the depression may be located on the side of the pressure-resistant structure 200 adjacent to and / or away from an adjacent pressure-resistant structure 200.

[0123] In some embodiments, the voltage-resistant structure 200 may be located in the deep well doping region 120 .

[0124] Specifically, disposing the voltage-resistant structure 200 in the deep well doping region 120 can further increase the amount of charges bound by the voltage-resistant structure 200 , thereby further increasing the pressure-resistant value of the voltage-resistant structure 200 .

[0125] It should be noted that, in the following description, the voltage-resistant structure 200 located in the deep well doping region 120 may be used as an example for illustration, but this does not constitute a limitation on the positional relationship between the voltage-resistant structure 200 and the deep well doping region 120. For example, the depth of the deep well doping region 120 may be greater than the depth of the voltage-resistant structure 200. For example, the depth of the deep well doping region 120 may be less than the depth of the voltage-resistant structure 200.

[0126] It should be noted that the annealing treatments on the initial pressure-resistant structure 210 and the protruding portion 220 may be performed simultaneously or separately.

[0127] Reference Figure 4 , a second isolation ring 300 is formed on the substrate 100 .

[0128] Specifically, the second isolation ring 300 is a ring structure, which can achieve electrical isolation between the inside and outside of the ring.

[0129] In some embodiments, the material of the second isolation ring 300 may be silicon dioxide.

[0130] Specifically, the step of forming the second isolation ring 300 may include: etching the substrate 100 to obtain an isolation ring groove; and filling the isolation ring groove to obtain the second isolation ring 300 .

[0131] Continue to refer to Figure 4 , a connection region 130 is formed in the first doping region 110 .

[0132] The depth of the connection region 130 is less than the depth of the deep well doping region 120 , and the connection region 130 is connected to the deep well doping region 120 .

[0133] Specifically, the connection region 130 is used as a channel for removing the carriers accumulated in the deep well doping region 120 , thereby preventing the carriers accumulated in the deep well doping region 120 from affecting the potential below the deep well doping region 120 .

[0134] In some embodiments, the doping type of the connection region 130 is consistent with that of the deep well doping region 120 , and the doping concentration of the connection region 130 is less than or equal to that of the deep well doping region 120 .

[0135] Specifically, the doping type of the connection region 130 is consistent with that of the deep well doping region 120, that is, different from the doping type of the first doping region 110, so that a PN junction can be formed between the connection region 130 and the first doping region 110, avoiding the influence of carriers in the connection region 130 entering the first doping region 110 on the semiconductor unit.

[0136] In some embodiments, the connection region 130 is located outside the second isolation ring 300 .

[0137] In some embodiments, the connection region 130 is ring-shaped and is disposed around the second isolation ring 300 .

[0138] Continue to refer to Figure 4 , a drift region 140 is formed in the first doping region 110 .

[0139] The doping type of the drift region 140 is different from that of the first doping region 110 .

[0140] In some embodiments, the drift region 140 and the connection region 130 may be formed in various orders. For example, the connection region 130 may be formed during the process of forming the drift region 140. For example, the drift region 140 may be formed after the connection region 130. For example, the drift region 140 may be formed before the connection region 130.

[0141] In some embodiments, the drift region 140 is located inside the second isolation ring 300 , and the drift region 140 and the connection region 130 are spaced apart.

[0142] Specifically, the connection region 130 and the drift region 140 are spaced apart, and the spaced region therebetween belongs to the first doped region 110 . The first doped region 110 is inversely connected to the PN junction formed with the connection region 30 and the drift region 140 , thereby reducing the probability of carriers in the connection region 130 entering the drift region 140 .

[0143] In some embodiments, the drift region 140 and the connection region 130 are formed after the second isolation ring 300 .

[0144] Specifically, the second isolation ring 300 can play a mask blocking role during the formation of the drift region 140 and the connection region 130 , so that the formed connection region 130 is spaced apart from the drift region 140 .

[0145] Reference Figure 5 , a field dielectric layer 410 is formed on the drift region 140 ; ​​a gate dielectric layer 420 is formed on the first doped region 110 adjacent to the field dielectric layer 410 , and the gate dielectric layer 420 is adjacent to the field dielectric layer 410 ; and a gate structure 430 is formed on the gate dielectric layer 420 and the field dielectric layer 410 .

[0146] In some embodiments, a side of the field dielectric layer 410 away from the gate dielectric layer 420 is located above the drift region 140 .

[0147] In this way, when the gate structure 430 is pressurized, a new electric field peak can be introduced on the surface of the drift region 140 , optimizing the electric field distribution on the surface of the substrate 100 and reducing the probability of breakdown of the semiconductor structure at the interface between the drift region 140 and the body region 150 .

[0148] Continue to refer to Figure 5 , a body region 150 is formed in the first doping region 110 .

[0149] The body region 150 and the first doping region 110 have different doping types. The body region 150 is adjacent to the drift region 140 . The body region 150 is located on one side of the field dielectric layer 410 , and the side is adjacent to the gate dielectric layer 420 .

[0150] Specifically, the step of forming the body region 150 may include: forming an initial body region 150 (not shown) in the first doped region 110 exposed on the side of the gate dielectric layer 420 away from the field dielectric layer 410 ; and annealing the initial body region 150 to obtain the body region 150 .

[0151] Through annealing treatment, the doped ions in the initial body region 150 can diffuse toward the side of the drift region 140, and the doping concentration of the body region 150 in the diffusion region can be gradually reduced in the direction toward the drift region 140, thereby optimizing the electric field distribution on the surface of the substrate 100 and improving the breakdown voltage along the surface of the substrate 100.

[0152] In some embodiments, a bottom surface of the body region 150 is located above a top surface of the voltage-withstanding structure 200 .

[0153] Specifically, the voltage-resistant structure 200 can optimize the electric field distribution in the first doped region 110 below the body region 150 , and improve the breakdown voltage of the semiconductor structure at the body region 150 in a direction vertical to the surface of the substrate 100 .

[0154] In some embodiments, the depth of the deep well doped region 120 is greater than the depth of the body region 150 .

[0155] Continue to refer to Figure 5 , a source region 160 is formed in the body region 150 exposed by the gate dielectric layer 420 .

[0156] The source region 160 and the body region 150 have different doping types.

[0157] Continue to refer to Figure 5 , a drain region is formed in the drift region 140 exposed by the field dielectric layer 410 .

[0158] The doping type of the drain region is consistent with that of the source region 160 , and the doping concentration of the drain region is higher than that of the drift region 140 .

[0159] Continue to refer to Figure 5 , a first isolation ring 180 is formed in the connection area 130 .

[0160] The first isolation ring 180 has the same doping type as the connection region 130 , and has a higher doping concentration than the connection region 130 .

[0161] Specifically, the first isolation ring 180 is used to extract carriers from the deep well doping region 120 into the connection region 130 .

[0162] In some embodiments, the first isolation ring 180 is a ring-shaped structure, which is disposed around the second isolation ring 300 .

[0163] In some embodiments, the source region 160 and the drain region can be formed in a variety of orders. For example, the drain region is formed during the process of forming the source region 160. For example, the source region 160 can be formed after the drain region. For example, the source region 160 can be formed before the drain region.

[0164] In some embodiments, the source region 160 and the first isolation ring 180 may be formed in various orders. For example, the first isolation ring 180 is formed during the process of forming the source region 160. For example, the source region 160 may be formed after the first isolation ring 180. For example, the source region 160 may be formed before the first isolation ring 180.

[0165] In some embodiments, along the direction from the drain region toward the source region 160, the first doped region 110 includes at least the following three adjacent regions: a first region located below the drain region, a third region located below the source region 160, and a second region located between the first region and the third region, and the voltage-resistant structure 200 is distributed in the first region, the second region, and the third region.

[0166] In some embodiments, a first distance d between every two adjacent pressure-resistant structures 200 located in the first region is greater than a first distance d between every two adjacent pressure-resistant structures 200 located in the second region.

[0167] Specifically, the bound charges on the voltage-resistant structure 200 can increase the electric field within the adjacent voltage-resistant structure 200. By reducing the first distance d between every two adjacent voltage-resistant structures 200 located in the first region, the electric field and the pressure-bearing value within the voltage-resistant structure 200 located in the first region can be increased, thereby increasing the breakdown voltage of the semiconductor structure at the drain region along the direction vertical to the surface of the substrate 100 and reducing the probability of premature breakdown of the semiconductor structure at the drain region.

[0168] In some embodiments, a first distance d between every two adjacent pressure-resistant structures 200 in the third region is greater than a first distance d between every two adjacent pressure-resistant structures 200 in the second region.

[0169] Specifically, by reducing the first distance d between every two adjacent voltage-resistant structures 200 located in the third region, the electric field and the pressure-bearing value within the voltage-resistant structure 200 located in the third region can be increased, thereby increasing the breakdown voltage of the semiconductor structure at the source region 160 along the direction vertical to the surface of the substrate 100 and reducing the probability of premature breakdown of the semiconductor structure at the source region 160.

[0170] Continue to refer to Figure 5 , an extraction region 190 is formed in the source region 160.

[0171] The extraction region 190 and the body region 150 have the same doping type, and the doping concentration of the extraction region 190 is higher than that of the body region 150 .

[0172] Specifically, the extraction region 190 can extract carriers accumulated in the body region 150, reduce the potential fluctuation between the gate structure 430 and the source structure, thereby improving the stability of the voltage difference between the gate structure 430 and the source structure, wherein the source structure is subsequently formed on the source region 160 and the extraction region 190.

[0173] In some embodiments, the extraction region 190 is adjacent to the source region 160 and adjacent to the body region 150 .

[0174] Specifically, the adjacency of the extraction region 190 and the source region 160 enables the subsequently formed source structure to cover both the extraction region 190 and the source structure, thereby reducing the complexity of subsequent processes; the adjacency of the extraction region 190 and the body region 150 can improve the efficiency of extracting carriers accumulated in the body region 150 .

[0175] In some embodiments, ion implantation may be performed on the source region 160 to obtain an extraction region 190 within the source region 160 .

[0176] In some embodiments, the semiconductor structure may be an LDMOS device, which includes a semiconductor unit, wherein the semiconductor unit may include a drift region 140 , a body region 150 , a source region 160 , a drain region, an extraction region 190 , a gate dielectric layer 420 , a field dielectric layer 410 , and a gate structure 430 .

[0177] Furthermore, the semiconductor structure may be a symmetrical LDMOS device. The symmetrical LDMOS device includes two symmetrical semiconductor units. The two symmetrical semiconductor units share the same body region 150 and extraction region 190 .

[0178] It should be pointed out that, in addition to the shared body region 150, each semiconductor unit in the symmetrical LDMOS device may have its own drift region 140, source region 160, drain region, extraction region 190, gate dielectric layer 420, field dielectric layer 410 and gate structure 430, and the above-mentioned parts may be completely consistent or not completely consistent.

[0179] Specifically, sharing the same body region 150 and extraction region 190 can improve the current driving capability of the LDMOS device, while also simplifying the layout and improving the integration of the device.

[0180] Furthermore, the semiconductor unit is located inside the second isolation ring 300 , and the connection region 130 and the first isolation ring 180 are located outside the second isolation ring 300 .

[0181] Specifically, the second isolation ring 300 is disposed around the semiconductor unit, and can achieve electrical isolation between the semiconductor units of adjacent semiconductor structures.

[0182] In an embodiment of the present invention, a semiconductor structure may also be provided. Figures 2 to 5 The semiconductor structure may include: a substrate 100, wherein the substrate 100 has a first doping region 110; one or more voltage-resistant structures 200 located in the first doping region 110, wherein the dielectric constant of the voltage-resistant structure 200 is lower than that of the first doping region 110, and the voltage-resistant structure 200 has one or more protrusions 220 and / or recesses; a body region 150 located in the first doping region 110, wherein the doping type of the body region 150 is consistent with the doping type of the first doping region 110 and the doping concentration is higher than that of the first doping region 110, wherein the bottom surface of the body region 150 is located above the top surface of the voltage-resistant structure 200.

[0183] In some embodiments, there are multiple pressure-resistant structures 200 , and a spacing area may be provided between every two adjacent pressure-resistant structures 200 .

[0184] In some embodiments, the semiconductor structure may further include: a deep well doping region 120 located in the first doping region 110 , and the deep well doping region 120 and the first doping region 110 have different doping types.

[0185] Furthermore, the voltage-withstand structure 200 may be located in the deep well doping region 120 .

[0186] In some embodiments, the semiconductor structure may further include: a drift region 140 located in the first doped region 110; a field dielectric layer 410 located on the drift region 140; a gate dielectric layer 420 located on the first doped region 110 adjacent to the field dielectric layer 410, the gate dielectric layer 420 being adjacent to the field dielectric layer 410; a gate structure 430 located on the gate dielectric layer 420 and the field dielectric layer 410; wherein the body region 150 is adjacent to the drift region 140 and is located on one side of the field dielectric layer 410, and the side is adjacent to the gate dielectric layer 420; a source region 160 located in the body region 150 exposed by the gate dielectric layer 420; and a drain region located in the drift region 140 exposed by the field dielectric layer 410.

[0187] Furthermore, along the direction from the drain region toward the source region 160, the first doped region 110 may include at least the following three adjacent regions: a first region located below the drain region, a third region located below the source region 160, and a second region located between the first region and the third region; the number of the voltage-resistant structures 200 is multiple, and the multiple voltage-resistant structures 200 are distributed in the first region, the second region and the third region; there is a first spacing d between every two adjacent voltage-resistant structures 200, wherein the first spacing d between every two adjacent voltage-resistant structures 200 located in the first region and / or the third region is greater than the first spacing d between every two adjacent voltage-resistant structures 200 located in the second region.

[0188] Furthermore, the semiconductor structure may further include: an extraction region 190 located in the body region 150 , wherein the extraction region 190 has the same doping type as the body region 150 , and the doping concentration of the extraction region 190 is higher than that of the body region 150 , and the extraction region 190 is adjacent to the source region 160 .

[0189] In some embodiments, the semiconductor structure may be a symmetrical LDMOS device. The symmetrical LDMOS device includes two symmetrical semiconductor units. The body region 150 belongs to the semiconductor unit, and the two semiconductor units share the same body region 150 .

[0190] In some embodiments, the semiconductor structure may be an LDMOS device, the LDMOS device includes a semiconductor unit, and the body region 150 belongs to the semiconductor unit; the semiconductor structure may also include: a connection region 130 located in the first doping region 110, the connection region 130 is ring-shaped; the depth of the connection region 130 is less than the depth of the deep well doping region 120, and is connected to the deep well doping region 120, the doping type of the connection region 130 is consistent with the deep well doping region 120, and the doping concentration is less than or equal to the deep well doping region 120.

[0191] In some embodiments, the semiconductor structure may further include a first isolation ring 180 located in the connection region 130 , wherein the doping type of the first isolation ring 180 is consistent with that of the connection region 130 , and the doping concentration of the first isolation ring 180 is higher than that of the connection region 130 .

[0192] In some embodiments, the semiconductor structure may be an LDMOS device, which includes a semiconductor unit, and the body region 150 belongs to the semiconductor unit; the semiconductor structure may also include: a second isolation ring 300 located in the first doped region 110, and the second isolation ring 300 groove is arranged around the semiconductor unit.

[0193] It should be noted that for the principle, specific implementation and beneficial effects of the semiconductor structure, please refer to the previous article and Figures 1 to 5 The description related to the method for forming the semiconductor structure shown is not repeated here.

[0194] It should be noted that the semiconductor structure in the embodiment of the present invention can be formed by the formation method described in the above embodiment, or by other formation methods. For the specific description of the semiconductor structure in the embodiment of the present invention, reference can be made to the corresponding description in the above embodiment, and this embodiment will not be repeated here.

[0195] It is understandable that the term "and / or" in this article is only a description of the association relationship of the associated objects, indicating that there can be three relationships. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. In addition, the character " / " in this article indicates that the associated objects before and after are in an "or" relationship.

[0196] It is understood that the "multiple" mentioned herein refers to two or more than two. The first, second, third, etc. descriptions in the embodiments of the present application are only used for illustration and distinction of the described objects, and have no order, nor do they represent any special limitation on the number of devices in the embodiments of the present application, and cannot constitute any limitation on the embodiments of the present application.

[0197] It is understandable that multiple embodiment schemes are described herein, and the various optional methods introduced in each embodiment scheme can be combined and cross-referenced with each other without conflict, thereby extending a variety of possible embodiment schemes, which can all be considered as embodiment schemes disclosed and open to the public by the present invention.

[0198] Although the embodiments of the present invention are disclosed above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the scope defined by the claims.

Claims

1. A method for forming a semiconductor structure, characterized in that: include: Providing a substrate, wherein the substrate has a first doped region; forming a deep well doping region in the first doping region, wherein the deep well doping region has a different doping type from the first doping region; forming one or more voltage-resistant structures in the deep well doping region of the first doping region, wherein the dielectric constant of the voltage-resistant structures is lower than that of the first doping region, and the voltage-resistant structures have one or more protrusions and / or depressions; A body region is formed in the first doping region, wherein the doping type of the body region is consistent with that of the first doping region and the doping concentration is higher than that of the first doping region, wherein the bottom surface of the body region is located above the top surface of the voltage-resistant structure.

2. The forming method according to claim 1, characterized in that: Forming the voltage-resistant structure in the first doping region includes: Performing a first round of ion implantation in the first doping region to obtain an initial voltage-resistant structure; A second round of ion implantation is performed in the first doping region to form one or more protrusions and / or depressions on the surface of the initial voltage-resistant structure to obtain the voltage-resistant structure.

3. The forming method according to claim 1, characterized in that: There are multiple pressure-resistant structures, and there is a spacing area between every two adjacent pressure-resistant structures.

4. The forming method according to claim 1, characterized in that: Before forming the body region in the first doping region, the method further includes: forming a drift region in the first doped region; forming a field dielectric layer on the drift region; forming a gate dielectric layer on the first doped region adjacent to the field dielectric layer, wherein the gate dielectric layer is adjacent to the field dielectric layer; forming a gate structure on the gate dielectric layer and the field dielectric layer; The body region is adjacent to the drift region and is located on one side of the field dielectric layer, and the side is adjacent to the gate dielectric layer.

5. The forming method according to claim 4, characterized in that: The method further comprises: forming a source region in the body region exposed by the gate dielectric layer; A drain region is formed in the drift region exposed by the field dielectric layer.

6. The forming method according to claim 5, characterized in that: Along the direction from the drain region to the source region, the first doped region includes at least the following three adjacent regions: a first region located below the drain region, a third region located below the source region, and a second region located between the first region and the third region; There are multiple pressure-resistant structures, and the multiple pressure-resistant structures are distributed in the first area, the second area, and the third area; There is a first distance between every two adjacent pressure-resistant structures, wherein the first distance between every two adjacent pressure-resistant structures located in the first area and / or the third area is greater than the first distance between every two adjacent pressure-resistant structures located in the second area.

7. The forming method according to claim 5, characterized in that: The method further comprises: Ion implantation is performed on the body region to obtain an extraction region in the body region, wherein the extraction region has the same doping type as the body region, the doping concentration of the extraction region is higher than that of the body region, and the extraction region is adjacent to the source region.

8. The forming method according to claim 5, characterized in that: The semiconductor structure is a symmetrical LDMOS device, which includes two symmetrical semiconductor units. The body region belongs to the semiconductor unit, and the two semiconductor units share the same body region.

9. The forming method according to claim 1, characterized in that: The semiconductor structure is an LDMOS device, the LDMOS device includes a semiconductor unit, and the body region belongs to the semiconductor unit; The method further comprises: Ion implantation is performed on the first doped region to obtain a connection region, wherein the connection region is ring-shaped; the depth of the connection region is less than the depth of the deep well doped region, and the connection region is connected to the deep well doped region; the doping type of the connection region is consistent with that of the deep well doped region, and the doping concentration is less than or equal to that of the deep well doped region.

10. The forming method according to claim 9, characterized in that: The method further comprises: Ion implantation is performed on the connection region to obtain a first isolation ring in the connection region, wherein the doping type of the first isolation ring is consistent with that of the connection region and the doping concentration is higher than that of the connection region.

11. The forming method according to claim 1, characterized in that: The semiconductor structure is an LDMOS device, the LDMOS device includes a semiconductor unit, and the body region belongs to the semiconductor unit; Before forming the body region, the method further comprises: Etching the substrate to obtain an isolation ring groove, wherein the isolation ring groove is arranged around the semiconductor unit; The isolation ring groove is filled to obtain a second isolation ring.

12. A semiconductor structure, characterized in that: include: A substrate, wherein the substrate has a first doping region, wherein the first doping region has a deep well doping region, and the deep well doping region and the first doping region have a doping type different from each other; One or more voltage-resistant structures located in the deep well doping region of the first doping region, wherein the dielectric constant of the voltage-resistant structures is lower than that of the first doping region, and the voltage-resistant structures have one or more protrusions and / or depressions; A body region located in the first doping region, wherein the doping type of the body region is consistent with that of the first doping region and the doping concentration is higher than that of the first doping region, wherein the depth of the body region is less than the depth of the voltage-withstand structure.

13. The semiconductor structure according to claim 12, characterized in that: There are multiple pressure-resistant structures, and there is a spacing area between every two adjacent pressure-resistant structures.

14. The semiconductor structure according to claim 12, characterized in that: Also includes: a drift region located in the first doped region; a field dielectric layer located on the drift region; A gate dielectric layer located on the first doped region adjacent to the field dielectric layer, the gate dielectric layer being adjacent to the field dielectric layer; A gate structure located on the gate dielectric layer and the field dielectric layer; wherein the body region is adjacent to the drift region and is located on one side of the field dielectric layer, and the side is adjacent to the gate dielectric layer; a source region located in the body region exposed by the gate dielectric layer; A drain region is located in the drift region exposed by the field dielectric layer.

15. The semiconductor structure according to claim 14, characterized in that: Along the direction from the drain region to the source region, the first doped region includes at least the following three adjacent regions: a first region located below the drain region, a third region located below the source region, and a second region located between the first region and the third region; There are multiple pressure-resistant structures, and the multiple pressure-resistant structures are distributed in the first area, the second area, and the third area; There is a first distance between every two adjacent pressure-resistant structures, wherein the first distance between every two adjacent pressure-resistant structures located in the first area and / or the third area is greater than the first distance between every two adjacent pressure-resistant structures located in the second area.

16. The semiconductor structure according to claim 14, characterized in that Also includes: An extraction region is located in the body region, wherein the extraction region has the same doping type as the body region and a higher doping concentration than the body region, and the extraction region is adjacent to the source region.

17. The semiconductor structure according to claim 14, characterized in that The semiconductor structure is a symmetrical LDMOS device, which includes two symmetrical semiconductor units. The body region belongs to the semiconductor unit, and the two semiconductor units share the same body region.

18. The semiconductor structure according to claim 12, characterized in that: The semiconductor structure is an LDMOS device, the LDMOS device includes a semiconductor unit, and the body region belongs to the semiconductor unit; The semiconductor structure further comprises: A connection area located in the first doping area, the connection area is ring-shaped; the depth of the connection area is less than the depth of the deep well doping area, and the connection area is connected to the deep well doping area, the doping type of the connection area is consistent with the deep well doping area, and the doping concentration is less than or equal to the deep well doping area.

19. The semiconductor structure according to claim 18, characterized in that Also includes: A first isolation ring is located in the connection region, wherein the first isolation ring has the same doping type as the connection region and the doping concentration of the first isolation ring is higher than that of the connection region.

20. The semiconductor structure according to claim 12, wherein: The semiconductor structure is an LDMOS device, the LDMOS device includes a semiconductor unit, and the body region belongs to the semiconductor unit; The semiconductor structure further comprises: A second isolation ring is located in the first doping region, and the second isolation ring groove is arranged around the semiconductor unit.

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