A semiconductor structure

Abstract

The present disclosure provides a semiconductor structure comprising a first chip and a second chip, wherein the first chip includes a first signal rewiring pattern; the second chip is soldered to the first chip and includes a first power rewiring pattern; wherein the first power rewiring pattern is disposed opposite the first signal rewiring pattern, and the projection of the first power rewiring pattern on the first chip at least partially overlaps the first signal rewiring pattern. In the semiconductor structure provided by the present disclosure, the projection of the first power rewiring pattern on the second chip on the first chip overlaps at least a portion of the first signal rewiring pattern, thereby enabling the first power rewiring pattern to provide a reference plane for the first signal rewiring pattern, effectively improving the signal integrity of the semiconductor structure.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and in particular to a semiconductor structure. Background Art

[0002] Stacked packaging is a relatively common semiconductor packaging technology. However, the semiconductor structure formed by this packaging technology will produce more losses during signal transmission, thereby affecting the performance of the semiconductor structure. Summary of the Invention

[0003] The following is an overview of the subject matter described in detail in this disclosure. This overview is not intended to limit the scope of the claims.

[0004] The present disclosure provides a semiconductor structure, comprising:

[0005] A first chip including a first signal rewiring;

[0006] a second chip, soldered on the first chip, the second chip including a first power rewiring;

[0007] The first power rewiring is arranged opposite to the first signal rewiring, and the first power rewiring at least partially covers the first signal rewiring in the projection area of ​​the first chip.

[0008] According to some embodiments of the present disclosure, the first chip also includes a second power rewiring corresponding to the first power rewiring, and the second power rewiring and the first signal rewiring are arranged alternately along a first direction. The first power rewiring covers at least a portion of the structure of the first signal rewiring adjacent to the second power rewiring corresponding to the first power rewiring in the projection area of ​​the first chip.

[0009] According to some embodiments of the present disclosure, the first power rewiring includes a power rewiring body extending along the second direction and an extension portion extending from at least one side of the power rewiring body toward the first direction, and the extension portion covers a partial structure of the first signal rewiring adjacent to the second power rewiring corresponding to the first power rewiring in the projection area of ​​the first chip.

[0010] According to some embodiments of the present disclosure, the second chip also includes a second signal rewiring corresponding one-to-one to the first signal rewiring, and in the second direction, there is a preset distance between the outer end of the power rewiring body and the outer end of the second signal rewiring, and the extension portion is located between the outer end of the power rewiring body and the outer end of the second signal rewiring.

[0011] According to some embodiments of the present disclosure, a plurality of first power rewiring lines are provided, the plurality of first power rewiring lines including a first power line for connecting a high level and a second power line for connecting a low level, the first power line and the second power line being located on both sides of the second signal rewiring line;

[0012] The extension portion is provided on the second power line, and a distance between the extension portion and the first power line is smaller than a distance between the first power line and the second signal redistribution wiring; and / or,

[0013] The width of the second power line is greater than the width of the second signal redistribution line.

[0014] According to some embodiments of the present disclosure, the first power rewiring is connected to the corresponding second power rewiring via a plurality of conductive connection portions.

[0015] According to some embodiments of the present disclosure, the plurality of conductive connection portions connecting one of the first power rewiring lines and one of the second power rewiring lines are arranged along a second direction, and the second direction is an extension direction of the first power rewiring line.

[0016] According to some embodiments of the present disclosure, each of the conductive connection portions is connected to a power rewiring body of the first power rewiring.

[0017] According to some embodiments of the present disclosure, an arrangement density of conductive connection portions corresponding to the first power rewiring lines connected to a high level is greater than an arrangement density of conductive connection portions corresponding to the first power rewiring lines connected to a low level.

[0018] According to some embodiments of the present disclosure, the semiconductor structure further includes a packaging substrate, the first chip and the second chip are stacked on the packaging substrate, and the first chip or the second chip is connected to the packaging substrate via a wire.

[0019] In the semiconductor structure provided by the embodiment of the present disclosure, the projection of the first power rewiring on the second chip on the first chip covers at least a portion of the structure of the first signal rewiring on the first chip. Therefore, the first power rewiring can provide a reference plane for the first signal rewiring. When the first signal rewiring transmits a signal, the reference plane can provide a low-impedance return path for the first signal rewiring, so that the signal current can flow back through the reference plane, thereby reducing the signal transmission delay and power consumption, and thus improving the signal transmission quality. On the other hand, the reference plane can have a good shielding effect, avoiding electromagnetic coupling between the first signal rewiring and external interference sources. Under the action of the reference plane, the first signal rewiring can be regarded as a microstrip line with better signal transmission characteristics, and the signal integrity of the semiconductor structure can be effectively improved.

[0020] Still other aspects will become apparent upon reading and understanding the accompanying drawings and detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] The accompanying drawings, which are incorporated into and constitute a part of the specification, illustrate embodiments of the present disclosure and, together with the description, are used to explain the principles of the embodiments of the present disclosure. In these drawings, similar reference numerals are used to represent similar elements. The drawings described below are some embodiments of the present disclosure, not all embodiments. For those skilled in the art, other drawings can be derived from these drawings without inventive effort.

[0022] Figure 1 is a schematic diagram of a semiconductor package in the related art;

[0023] Figure 2 is a schematic structural diagram of a semiconductor structure according to an exemplary embodiment;

[0024] Figure 3 is a schematic structural diagram of a semiconductor structure after removing the second chip body according to an exemplary embodiment;

[0025] Figure 4 is a top view of a semiconductor structure after removing the second chip body according to an exemplary embodiment;

[0026] Figure 5 is a schematic structural diagram of a semiconductor structure after removing the second chip body according to another exemplary embodiment;

[0027] Figure 6 is a top view of a semiconductor structure after the second chip body is removed according to another exemplary embodiment;

[0028] Figure 7 is a cross-sectional view of a semiconductor structure along a first direction according to an exemplary embodiment;

[0029] Figure 8 is a partial cross-sectional view of a semiconductor structure along a first power line in a second direction according to an exemplary embodiment;

[0030] Figure 9 is a partial cross-sectional view of a semiconductor structure along an extension portion in a second direction according to an exemplary embodiment;

[0031] Figure 10 is a schematic diagram of a circuit layout of a first conductive layer according to an exemplary embodiment;

[0032] Figure 11 FIG. 4 is a schematic diagram showing a circuit layout of a second conductive layer according to an exemplary embodiment.

[0033] Reference numerals:

[0034] This application:

[0035] 1. First chip; 101. First chip body; 2. Second chip; 201. Second chip body; 3. First redistribution layer; 301. First dielectric material layer; 302. First conductive layer; 3021. First signal redistribution; 3022. Second power redistribution; 3022a. Third power line; 3022b. Fourth power line; 303. Second dielectric material layer; 304. First soldering portion; 305. First solder pad; 4. Second redistribution layer; 401. Third dielectric material layer; 402. Second conductive layer; 4021. First power redistribution; 4021 a. First power line; 4021b. Second power line; 4022. Second signal redistribution; 403. Fourth dielectric material layer; 404. Second welding portion; 405. Second soldering pad; 5. Power redistribution body; 6. Extension portion; 7. Conductive connection portion; 9. Package substrate; 10. External terminal; 11. Isolation layer; 12. First through hole; 13. Second through hole; 14. Third through hole; 15. Fourth through hole; 16. First surface; 17. Second surface; 18. First contact surface; 19. Second contact surface; 20. Third contact surface; 21. Wire; 22. Solder pad.

[0036] Related technologies:

[0037] 1', first chip; 2', second chip; 3', first redistribution layer; 4', second redistribution layer; 7', conductive connection portion; 9', packaging substrate; 21', wire. DETAILED DESCRIPTION

[0038] In order to make the purpose, technical solutions and advantages of the embodiments of the present disclosure clearer, the technical solutions in the disclosed embodiments will be clearly and completely described below in conjunction with the drawings in the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, rather than all of the embodiments. Based on the embodiments in the present disclosure, all other embodiments obtained by those skilled in the art without making creative work are within the scope of protection of the present disclosure. It should be noted that, in the absence of conflict, the embodiments in the present disclosure and the features in the embodiments can be arbitrarily combined with each other.

[0039] The advancement of integrated circuit (IC) process technology has increased the signal density of the chip. In order to effectively maintain the quality of signal transmission, the existing technology usually adopts the chip-on-chip (COC) packaging form. Figure 1The semiconductor package in the related art includes a package substrate 9' and a first chip 1' and a second chip 2' stacked on the package substrate 9'. The first chip 1' includes a first redistribution layer 3' having a first signal redistribution (not shown in the figure), and the second chip 2' includes a second redistribution layer 4' having a second signal redistribution (not shown in the figure). The first signal redistribution and the second signal redistribution are electrically connected via a conductive connection portion 7', and the first signal redistribution is electrically connected to the package substrate 9' via a wire 21'. To save costs, the first redistribution layer 3' and the second redistribution layer 4' are usually single-layer metal layers, and the single-layer metal layer is configured for power supply and signal transmission. Due to the single-layer metal layer design, the first signal redistribution has no reference plane in the vertical direction for reflow and shielding, which can easily cause excessive signal loss in the first signal redistribution during transmission, affecting signal integrity.

[0040] Based on this, the present disclosure provides a semiconductor structure, in which the projection of the first power rewiring on the second chip on the first chip covers at least part of the structure of the first signal rewiring on the first chip. Therefore, the first power rewiring can provide a reference plane for the first signal rewiring. When the first signal rewiring transmits a signal, the reference plane can provide a low-impedance return path for the first signal rewiring, so that the signal current can flow back through the reference plane, reducing the transmission delay and power consumption of the signal, thereby improving the signal transmission quality. On the other hand, the reference plane can have a good shielding effect to avoid electromagnetic coupling between the first signal rewiring and external interference sources. Under the action of this reference plane, the first signal rewiring can be regarded as a microstrip line with better signal transmission characteristics, and the signal integrity of the semiconductor structure can be effectively improved.

[0041] An exemplary embodiment of the present disclosure provides a semiconductor structure such as Figure 2 and Figure 3 As shown, the semiconductor structure includes a first chip 1 and a second chip 2, the first chip 1 includes a first signal rewiring 3021, the first chip 1 is soldered to the second chip 2, and the second chip 2 includes a first power rewiring 4021, the first power rewiring 4021 can be a power line or a ground line, the first power rewiring 4021 is arranged opposite to the first signal rewiring 3021, and the first power rewiring 4021 covers at least part of the first signal rewiring 3021 in the projection area of ​​the first chip 1, and the covering method can be Figure 3 and Figure 4 The partial coverage shown may also mean that the first power rewiring 4021 completely covers the first signal rewiring 3021 in the projection area of ​​the first chip 1. Figure 4 In FIG, the covered portion of the first signal redistribution wiring 3021 is shown by a dotted line.

[0042] It can be understood that the relative arrangement of the first power rewiring 4021 and the first signal rewiring 3021 mentioned herein means that the arrangement directions of the two are relative to each other. Figure 3 and Figure 4 As shown, the first power rewiring 4021 and the first signal rewiring 3021 are arranged opposite each other in the Z direction. The first power rewiring 4021 and the first signal rewiring 3021 are respectively arranged on two opposing surfaces of the first chip 1 and the second chip 2. For example, if the second chip 2 is arranged above the first chip 1, the lower surface of the second chip 2 is opposite the upper surface of the first chip 1, the first power rewiring 4021 is arranged on the lower surface of the second chip 2, and the first signal rewiring 3021 is arranged on the upper surface of the first chip 1.

[0043] In this embodiment, since the projection of the first power rewiring 4021 on the second chip 2 on the first chip 1 covers at least part of the structure of the first signal rewiring 3021 on the first chip 1, the first power rewiring 4021 can provide a reference plane for the first signal rewiring 3021. When the first signal rewiring 3021 transmits a signal, the reference plane can provide a low-impedance return path for the first signal rewiring 3021, so that the signal current can flow back through the reference plane, reducing the signal transmission delay and power consumption, thereby improving the signal transmission quality. On the other hand, the reference plane can have a good shielding effect, avoiding electromagnetic coupling between the first signal rewiring 3021 and external interference sources. Under the action of the reference plane, the first signal rewiring 3021 can be regarded as a microstrip line with better signal transmission characteristics, and the signal integrity (SI) of the semiconductor structure can be effectively improved.

[0044] Of course, it is understandable that reference Figure 2 The first chip 1 can be located above or below the second chip 2, which is not limited in this embodiment.

[0045] In some embodiments, such as Figure 2 and Figure 3 As shown, the first chip 1 further includes a second power rewiring 3022 corresponding to the first power rewiring 4021. The second power rewiring 3022 and the first signal rewiring 3021 are arranged along a first direction (e.g., Figure 3 X direction shown) interlaced arrangement settings, refer to Figure 3 In the projection area of ​​the first chip 1 , the first power rewiring 4021 covers at least a portion of the first signal rewiring 3021 adjacent to the second power rewiring 3022 corresponding to the first power rewiring 4021 .

[0046] The first signal rewiring 3021 and the second power rewiring 3022 may be arranged in sequence at intervals. The first power rewiring 4021 may cover the first signal rewiring 3021 located on one side of the corresponding second power rewiring 3022 in the projection area of ​​the first chip 1 , or may cover the first signal rewiring 3021 located on both sides of the corresponding second power rewiring 3022 .

[0047] In other embodiments, at least two first signal rewirings 3021 may also be set between two adjacent second power rewirings 3022. In this case, the first power rewiring 4021 may cover multiple first signal rewirings 3021 located on one side of the corresponding second power rewiring 3022, or may cover multiple first signal rewirings 3021 located on both sides of the corresponding second power rewiring 3022.

[0048] In this embodiment, the second power rewiring 3022 is arranged corresponding to the first power rewiring 4021. The first power rewiring 4021 can provide a reference plane for the first signal rewiring 3021 adjacent to the corresponding second power rewiring 3022. This ensures the signal integrity of each first signal rewiring 3021 of the first chip 1, thereby ensuring the performance stability and reliability of the semiconductor structure. In addition, because the reference plane can provide a low-impedance return path, it can disperse and absorb power noise, returning the power noise to the first power rewiring 4021, and reducing current fluctuations and voltage variations in the second power rewiring 4021. Therefore, the reference plane provided by the first power rewiring in the present disclosure can effectively improve the power integrity (PI) of the semiconductor structure.

[0049] In some embodiments, reference Figure 3 , and combined with Figure 10 The first power rewiring 4021 includes a second direction (e.g. Figure 3 The power rewiring body 5 extends in the Y direction as shown in the figure, and the extension portion 6 extends from at least one side of the power rewiring body 5 in the first direction X, and the extension portion 6 covers at least a portion of the structure of the first signal rewiring 3021 adjacent to the second power rewiring 3022 corresponding to the first power rewiring 4021 in the projection area of ​​the first chip 1.

[0050] like Figure 3As shown, the power rewiring body 5 extending along the second direction Y can be positioned opposite the second power rewiring 3022, and can be connected to the second power rewiring 3022 via a conductive connection portion 7, described below, to achieve electrical connection between the first power rewiring 4021 and the second power rewiring 3022. In this embodiment, the extension portion 6 can extend from one side of the power rewiring body 5 along the first direction X to cover at least a portion of one or more first signal rewiring 3021 adjacent to the second power rewiring 3022. This extension portion 6, together with the power rewiring body 5, forms a reference plane and provides electromagnetic shielding for each first signal rewiring 3021, ensuring good signal transmission characteristics and signal integrity for the first signal rewiring 3021.

[0051] In some embodiments, at least two second power rewiring wires 3022 may be disposed between two adjacent first signal rewiring wires 3021. In this case, a first power rewiring wire 4021 may be disposed in a one-to-one correspondence with each second power rewiring wire 3022, or a single first power rewiring wire 4021 may correspond to each second power rewiring wire 3021 between adjacent first signal rewiring wires 3021. When multiple first power rewiring wires 4021 are provided, one of the first power rewiring wires 4021 may cover a first signal rewiring wire 3021 located to one side of a second power rewiring wire 3022. This first power rewiring wire 4021 may be located adjacent to a second signal rewiring wire 4022.

[0052] Of course, it is understood that the extension portion 6 can also be divided into a first extension portion and a second extension portion, wherein the first extension portion extends from one side of the power rewiring body 5 in the first direction X, and the second extension portion extends from the other side of the power rewiring body 5 in the opposite direction. The first extension portion can cover the first signal rewiring 3021 on the side of the second power rewiring 3022 opposite the power rewiring body 5, while the second extension portion can cover the first signal rewiring 3021 on the other side of the second power rewiring 3022 opposite the power rewiring body 5. With this arrangement, the projection of a first power rewiring 4021 on the first chip 1 can cover the first signal rewiring 3021 on both sides of the second power rewiring 3022 opposite it. Thus, the first and second extension portions provide a reference plane for the first signal rewiring 3021 on both sides of the second power rewiring 3022. In this embodiment, a single first power rewiring 4021 can provide a reference plane for multiple first signal rewiring 3021, thereby simplifying the manufacturing process of the second chip 2, ensuring signal integrity while reducing production costs.

[0053] In some embodiments, reference Figure 3 and Figure 4 The second chip 2 also includes a second signal rewiring 4022 corresponding one-to-one to the first signal rewiring 3021. In the second direction Y, there is a preset distance L between the outer end of the power rewiring body 5 and the outer end of the second signal rewiring 4022, and the extension portion 6 is located between the outer end of the power rewiring body 5 and the outer end of the second signal rewiring 4022.

[0054] One or more second signal rewiring traces 4022 may be disposed between two adjacent first power rewiring traces 4021. The length of the second signal rewiring trace 4022 in the second direction Y can be relatively short. Specifically, the length of the second signal rewiring trace 4022 only needs to be sufficient to ensure interfacing with the first signal rewiring trace 3021. In this embodiment, arranging the extension portion 6 within a predetermined distance L ensures that the projection of the extension portion 6 on the first chip 1 provides good coverage of the first signal rewiring trace 3021 in the second direction Y, thereby ensuring that the first power rewiring trace 4021 provides a complete reference plane. Furthermore, arranging the extension portion 6 within the predetermined distance L allows the end face of the extension portion 6 to be flush with the end of the power rewiring trace body 5, facilitating layout design and improving development efficiency.

[0055] In other embodiments, in the first direction X, the extension portion 6 extends from at least one side of the power rewiring body 5 in the first direction X, and in the second direction Y, the two outer end portions of the extension portion 6 are respectively flush with the two outer end portions of the power rewiring body 5, so that the extension portion 6 can achieve full coverage of the first signal rewiring 3021. Such a configuration can improve the shielding effect of the reference plane, avoid electromagnetic coupling between the first signal rewiring 3021 and external interference sources, and further improve the signal integrity of the first signal rewiring 3021.

[0056] In some embodiments, the first power rewiring 4021 is provided with multiple lines, referring to Figure 5 , and combined with Figure 6 and Figure 10 The plurality of first power rewiring lines 4021 include a first power line 4021a for connecting a high level and a second power line 4021b for connecting a low level, wherein the first power line 4021a is the aforementioned power line, and the second power line 4021b is the aforementioned ground line. The first power line 4021a and the second power line 4021b are located on both sides of the second signal rewiring line 4022, and the extension portion 6 is provided on the second power line 4021b. Figure 6 The distance between the extension portion 6 and the first power line 4021a is smaller than the distance between the first power line 4021a and the second signal redistribution 4022. Figure 6The distance between the first power line 4021a and the second signal rewiring 4022 is shown as D1, and the covered portion of the first signal rewiring 3021 is shown as D2. Figure 6 Shown in dashed lines.

[0057] In this embodiment, the spacing D1 between the extension 6 and the first power line 4021a is smaller than the spacing D2 between the first power line 4021a and the second signal rewiring 4022. By shortening the spacing D1 between the extension 6 and the first power line 4021a, the first power line 4021a has a good return path, thereby improving the current distribution network. Furthermore, as previously described, the first signal rewiring 3021 and the second signal rewiring 4022 are provided in a one-to-one correspondence. Therefore, in this embodiment, when the spacing D1 between the extension 6 and the first power line 4021a is smaller than the spacing D2 between the first power line 4021a and the second signal rewiring 4022, the outer edge of the second signal rewiring 4022 in the first direction X does not extend beyond the side edges of the extension 6. This ensures that the projection of the second power line 4021b onto the first chip 1 in the first direction X effectively covers the first signal rewiring 3021.

[0058] In some embodiments, continue to refer to Figure 6 The width of the second power line 4021b is greater than the width of the second signal redistribution 4022. Figure 6 As shown by W1, the width of the second signal redistribution 4022 is Figure 6 It is shown as W2 in the figure.

[0059] In this embodiment, reference Figure 5 and Figure 7 The width W1 of the second power line 4021b is approximately equivalent to the spacing between adjacent second signal rewiring lines 4022. That is, the width W1 of the second power line 4021b determines the spacing between adjacent second signal rewiring lines 4022. Therefore, the larger the width W1 of the second power line 4021b, the larger the spacing between adjacent second signal rewiring lines 4022. If the width W1 of the second power line 4021b is greater than the width W2 of the second signal rewiring lines 4022, there will be a larger spacing between adjacent second signal rewiring lines 4022, effectively reducing signal crosstalk between adjacent second signal rewiring lines 4022. Similarly, the first signal rewiring lines 3021 that correspond one-to-one with the second signal rewiring lines 4022 also have a larger spacing, thereby effectively reducing signal crosstalk between adjacent first signal rewiring lines 3021.

[0060] It is understood that the first power line 4021a can also be used to provide a reference plane for the first signal rewiring 3021. For example, the frequency of the signal can be used to determine whether the first power line 4021a or the second power line 4021b is used to provide the reference plane for the first signal rewiring 3021. In the embodiment where the first power line 4021a is used to provide the reference plane for the first signal rewiring 3021, the extension 6 is provided on the first power line 4021a, and the extension 6 covers at least a portion of the first signal rewiring 3021. The width of the first power line 4021a can be set to be greater than the width of the second signal rewiring 4022 to increase the spacing between adjacent second signal rewiring 4022.

[0061] In some embodiments, reference Figure 2-Figure 8 The first power rewiring 4021 is connected to the corresponding second power rewiring 3022 via a plurality of conductive connection portions 7 .

[0062] The provision of the conductive connection portions 7 shortens the current transmission path between the first power rewiring 4021 and the second power rewiring 3022. In this embodiment, multiple conductive connection portions 7 provide multiple parallel circuit transmission paths. This arrangement reduces the parasitic resistance between the first power rewiring 4021 and the second power rewiring 3022, thereby reducing the thermal impact of current density on the first power rewiring 4021 and the second power rewiring 3022. Furthermore, the provision of multiple conductive connection portions 7 reduces the inductance and impedance between the first power rewiring 4021 and the second power rewiring 3022, thereby effectively improving the current carrying capacity and signal integrity of the first power rewiring 4021 and the second power rewiring 3022. Furthermore, the multiple conductive connection portions 7 provide excellent support for the first power rewiring 4021 and the second power rewiring 3022.

[0063] Exemplarily, the conductive connection portion 7 includes a conductive bump or a solder ball, etc., and the multiple conductive connection portions 7 can be regular in shape, such as a column or a cube. The shapes of the multiple conductive connection portions 7 can be the same or different, and this embodiment does not impose any restrictions on this.

[0064] In some embodiments, reference Figures 2 to 5 The plurality of conductive connection portions 7 connecting a first power redistribution wiring 4021 and a second power redistribution wiring 3022 are arranged along the second direction Y, and the second direction Y is the extending direction of the first power redistribution wiring 4021 .

[0065] In this embodiment, the multiple conductive connection portions 7 can be evenly spaced along the second direction Y. This arrangement allows the multiple conductive connection portions 7 to form an effective electromagnetic shielding structure and reduce the influence of the magnetic field generated by the first power rewiring 4021 and the second power rewiring 3022, thereby reducing potential interference from electromagnetic induction on the first signal rewiring 3021 and the second signal rewiring 4022. Furthermore, during signal transmission, parameters such as signal transmission speed, waveform, and stability are all crucial. Evenly spaced conductive connection portions 7 can reduce crosstalk and coupling between adjacent first signal rewiring 3021 or adjacent second signal rewiring 4022, thereby improving signal integrity.

[0066] In other embodiments, the plurality of conductive connection portions 7 may be irregularly distributed between the first power rewiring 4021 and the second power rewiring 3022. In this embodiment, within certain signal frequency ranges, the dispersed or irregularly arranged conductive connection portions 7 can disrupt the resonance conditions of the circuit or wire 21, thereby suppressing the occurrence of resonance and resonant phenomena, thereby avoiding signal distortion or waveform distortion.

[0067] It should be noted that the height and number of the conductive connection portions 7 can be specifically set according to the spacing between the first power redistribution wiring 4021 and the second power redistribution wiring 3022 and the length in the second direction Y.

[0068] In some embodiments, reference Figure 3 and Figure 5 , each conductive connection part 7 is connected to the power rewiring body 5 of the first power rewiring 4021.

[0069] Since the power rewiring body 5 and the second power rewiring 3022 are arranged relative to each other, in this embodiment, connecting the power rewiring body 5 to the conductive connecting part 7 can reduce the effective length of the conductive connecting part 7 as much as possible, thereby shortening the transmission path of the conductive connecting part 7, so as to further reduce the parasitic resistance between the first power rewiring 4021 and the second power rewiring 3022, and ensure that the heat effect of the current on the first power rewiring 4021 and the second power rewiring 3022 is relatively small.

[0070] In some embodiments, the arrangement density of the conductive connection portions 7 corresponding to the first power rewiring 4021 connected to the high level is greater than the arrangement density of the conductive connection portions 7 corresponding to the first power rewiring 4021 connected to the low level. Figure 5 In the illustrated embodiment, the arrangement density of the conductive connection portions 7 corresponding to the first power lines 4021 a is greater than the arrangement density of the conductive connection portions 7 corresponding to the second power lines 4021 b .

[0071] refer to Figure 5, and combined with Figure 11 The second power rewiring 3022 may include a third power line 3022a for connecting a high level and a fourth power line 3022b for connecting a low level, wherein, in combination with Figure 7 The first power line 4021a is arranged corresponding to the third power line 3022a, and the second power line 4021b is arranged corresponding to the fourth power line 3022b.

[0072] As previously described, the multiple conductive connecting portions 7 provided between the first power line 4021a and the third power line 3022a can improve the current carrying capacity of the first power line 4021a and the third power line 3022a. Similarly, the multiple conductive connecting portions 7 provided between the second power line 4021b and the fourth power line 3022b can improve the current carrying capacity of the second power line 4021b and the fourth power line 3022b. In this embodiment, because the first power rewiring 4021, which connects to a high level, needs to carry a higher current, a larger number of conductive connecting portions 7 are provided on the first power rewiring 4021, i.e., the first power line 4021a, which connects to a high level. This provides more conductive paths between the first power line 4021a and the third power line 3022a, thereby reducing the voltage difference between the first power line 4021a and the third power line 3022a and improving the stability of the power supply. Furthermore, providing more conductive connecting portions 7 provides more thermal paths, thereby improving heat dissipation and conduction efficiency, thereby improving the thermal management capability and stability of the semiconductor structure.

[0073] In some embodiments, the first signal rewiring 3021 and the second signal rewiring 4022 that are disposed opposite to each other are connected via a single conductive connection portion 7 . The conductive connection portion 7 is electrically connected to the first signal rewiring 3021 and the second signal rewiring 4022 .

[0074] In an exemplary embodiment of the present disclosure, referring to Figure 2-Figure 9 The semiconductor structure further includes a packaging substrate 9 , on which the first chip 1 and the second chip 2 are stacked. The first chip 1 or the second chip 2 is connected to the packaging substrate 9 via a wire 21 .

[0075] Among them, one end of the wire 21 can be connected to at least one side of the first signal rewiring 3021 or the second power rewiring 3022, and the other end is connected to the packaging substrate 9. In this embodiment, the first chip 1 and the second chip 2 can be stacked in sequence on the surface of the packaging substrate 9, wherein the surface of the first chip 1 can have multiple solder pads 22, and the solder pads 22 can be arranged at the two side edges of the first chip 1, and the solder pads 22 of the first chip 1 are electrically connected to the packaging substrate 9 through the wire 21.

[0076] In some embodiments, reference Figure 2-7 The bottom of the package substrate 9 is provided with a plurality of external terminals 10, which may be, for example, solder balls. In this embodiment, the plurality of external terminals 10 electrically connect the semiconductor structure to another structure, such as an interposer substrate (not shown) or a circuit board (not shown).

[0077] In some embodiments, reference Figure 7-Figure 9 An isolation layer 11 is provided between the first chip 1 and the second chip 2 . The isolation layer 11 may be formed between the first chip 1 and the second chip 2 during the packaging process, for example.

[0078] In this embodiment, the isolation layer 11 can prevent signal crosstalk between the first chip 1 and the second chip 2 to ensure signal stability and integrity. At the same time, it can provide physical support for the second chip 2 and provide insulation protection between the first chip 1 and the second chip 2 to avoid short circuit problems caused by electrical contact between the first chip 1 and the second chip 2.

[0079] In an exemplary embodiment of the present disclosure, referring to Figure 7 The first chip 1 may include a first redistribution layer 3 and a first chip body 101. The first redistribution layer 3 includes a first dielectric material layer 301, a first conductive layer 302, a second dielectric material layer 303, a first soldering portion 304, and a first soldering pad 305. The first dielectric material layer 301 is disposed above and covers the first soldering pad 305. The second dielectric material layer 303 is disposed above the first conductive layer 302. Figure 9 The first dielectric material layer 301 has a first through hole 12. At least a portion of the surface of the first pad 305 is exposed in the first through hole 12 and contacts the first conductive layer 302, thereby achieving electrical connection between the first pad 305 and the first conductive layer 302. The second dielectric material layer 303 has a second through hole 13. A portion of the surface of the first conductive layer 302 is exposed in the second through hole 13 and contacts the first soldering portion 304 in the second through hole 13, thereby achieving electrical connection between the first conductive layer 302 and the first soldering portion 304. Figure 8 and Figure 9 The first bonding pad 305 may be electrically connected to a circuit structure (not shown) in the first chip body 101 .

[0080] In some embodiments, continue to refer to Figure 7The second chip 2 may include a second redistribution layer 4 and a second chip body 201. The second redistribution layer 4 includes a third dielectric material layer 401, a second conductive layer 402, a fourth dielectric material layer 403, a second soldering portion 404, and a plurality of second solder pads 405. The third dielectric material layer 401 is disposed above and covers the second solder pads 405. The fourth dielectric material layer 403 is disposed above the second conductive layer 402. Figure 9 The third dielectric material layer 401 has a third through hole 14. At least a portion of the surface of the second pad 405 is exposed in the third through hole 14 and contacts the second conductive layer 402, thereby achieving electrical connection between the second pad 405 and the second conductive layer 402. The fourth dielectric material layer 403 has a fourth through hole 15. A portion of the surface of the second conductive layer 402 is exposed in the fourth through hole 15 and contacts the second soldering portion 404 in the fourth through hole 15, thereby achieving electrical connection between the second conductive layer 402 and the second soldering portion 404. Figure 8 and Figure 9 The second bonding pad 405 can be electrically connected to the circuit structure (not shown) in the second chip body 201.

[0081] In this embodiment, the first conductive layer 302 includes a first signal rewiring 3021 and a second power rewiring 3022, and the second conductive layer 402 includes a first power rewiring 4021 and a second signal rewiring 4022, wherein the second through-grooves 13 for exposing the surface of the second power rewiring 3022 and the fourth through-holes 15 for exposing the surface of the first power rewiring 4021 correspond to each other and are provided in plurality, and the second through-holes 13 for exposing the first signal rewiring 3021 and the fourth through-holes 15 for exposing the second signal rewiring 4022 correspond to each other and are provided in plurality, wherein the conductive connection The two ends of the connection portion 7 are respectively connected to the first welding portion 304 in the second through hole 13 and the second welding portion 404 in the fourth through hole 15, so as to electrically connect the first signal rewiring 3021 and the second signal rewiring 4022, or to realize the electrical connection between the first power rewiring 4021 and the second power rewiring 3022, wherein the first dielectric material layer 301, the second dielectric material layer 303, the third dielectric material layer 401 and the fourth dielectric material layer 403 can form electrical isolation to prevent mutual interference between signals, and can provide support for the first conductive layer 302 and the second conductive layer 402.

[0082] For example, the materials of the first dielectric material layer 301, the second dielectric material layer 303, the third dielectric material layer 401, and the fourth dielectric material layer 403 can be the same or different. For example, the materials of the first dielectric material layer 301, the second dielectric material layer 303, the third dielectric material layer 401, and the fourth dielectric material layer 403 can be polysilicon. The materials of the first conductive layer 302 and the second conductive layer 402 can be copper or other metals. The materials of the first welding portion 304 and the second welding portion 404 can be copper, nickel, silver, and other metal materials with good conductivity, for example, which are not specifically limited in this embodiment.

[0083] In some embodiments, reference Figure 8 and Figure 9 The package substrate 9 may include a first surface 16 and a second surface 17. During the fabrication process of the semiconductor structure disclosed herein, a first chip 1 may be formed on the first surface 16 of the package substrate 9. The first chip 1 may have a first contact surface 18 and a second contact surface 19 opposite to the first contact surface 18. The first redistribution layer 3 may be formed on the second contact surface 19. The second chip 2 may have a third contact surface 20. During the fabrication process of the semiconductor structure, a second redistribution layer 4 may be formed on the third contact surface 20. The first redistribution layer 3 located on the second contact surface 19 and the second redistribution layer 4 located on the second chip 2 are arranged opposite to each other and are mirror-symmetrical. Figure 10 and Figure 11 A first chip 1 and a second chip 2 are shown which are configured to be in a face-to-face mirror-symmetrical relationship after assembly.

[0084] After the second chip 2 is assembled, Figure 10 and Figure 11 The first welding portion 304 in contact with the third power line 3022a can be arranged face to face with the second welding portion 404 in contact with the first power line 4021a, the first welding portion 304 in contact with the fourth power line 3022b can be arranged face to face with the second welding portion 404 in contact with the second power line 4021b, and the first welding portion 304 in contact with the first signal rewiring 3021 can be arranged face to face with the second welding portion 404 in contact with the second signal rewiring 4022.

[0085] Continue to refer Figure 10 and Figure 11 After the first chip 1 and the second chip 2 are arranged face to face, the projection of the extension portion 6 on the second chip 2 on the first chip 1 can cover the first signal rewiring 3021 of part of the first chip 1, so as to reduce the length of the signal transmission path and shorten the current transmission path, thereby reducing the signal loss during the transmission process to improve the integrity of the signal. In addition, the heat generated by the current transmission can be reduced to ensure that the semiconductor structure has stable performance.

[0086] The various embodiments or implementation methods in this specification are described in a progressive manner. Each embodiment focuses on the differences from other embodiments, and the same or similar parts between the various embodiments can be referenced to each other.

[0087] In the description of this specification, reference to the terms "embodiment", "exemplary embodiment", "some embodiments", "illustrative embodiment", "example", etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present disclosure.

[0088] In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described can be combined in any suitable manner in any one or more embodiments or examples.

[0089] In the description of the present disclosure, it should be noted that the terms "center", "up", "down", "left", "right", "vertical", "horizontal", "inside", "outside", etc., indicating orientations or positional relationships, are based on the orientations or positional relationships shown in the accompanying drawings. They are only for the convenience of describing the present disclosure and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation. Therefore, they cannot be understood as limitations on the present disclosure.

[0090] It is to be understood that the terms "first", "second", etc. used in the present disclosure can be used to describe various structures in the present disclosure, but these structures are not limited by these terms. These terms are only used to distinguish a first structure from another structure.

[0091] In one or more of the accompanying drawings, identical elements are represented by similar reference numerals. For clarity, many parts in the accompanying drawings are not drawn to scale. In addition, certain well-known parts may not be shown. For simplicity, a structure obtained after several steps may be described in a single figure. Many specific details of the present disclosure, such as device structure, materials, dimensions, processing techniques, and technologies, are described below to facilitate a clearer understanding of the present disclosure. However, as will be appreciated by those skilled in the art, the present disclosure may be practiced without following these specific details.

[0092] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present disclosure, rather than to limit them. Although the present disclosure has been described in detail with reference to the above embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the above embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present disclosure.

Claims

1. A semiconductor structure, characterized in that The semiconductor structure comprises: A first chip including a first signal rewiring; a second chip, soldered on the first chip, the second chip including a first power rewiring; The first power rewiring is arranged opposite to the first signal rewiring, and the first power rewiring at least partially covers the first signal rewiring in the projection area of ​​the first chip; The first chip further includes a second power rewiring corresponding to the first power rewiring, the second power rewiring and the first signal rewiring being arranged interspersed with each other along a first direction, and the first power rewiring covering at least a portion of the first signal rewiring adjacent to the second power rewiring corresponding to the first power rewiring in a projection area of ​​the first chip; Among them, the first power rewiring includes a power rewiring body extending along the second direction and an extension portion extending from at least one side of the power rewiring body to the first direction, and the extension portion covers a partial structure of the first signal rewiring adjacent to the second power rewiring corresponding to the first power rewiring in the projection area of ​​the first chip.

2. The semiconductor structure according to claim 1, wherein: The second chip also includes a second signal rewiring corresponding one-to-one to the first signal rewiring. In the second direction, there is a preset distance between the outer end of the power rewiring body and the outer end of the second signal rewiring, and the extension portion is located between the outer end of the power rewiring body and the outer end of the second signal rewiring.

3. The semiconductor structure according to claim 2, wherein: The first power rewiring is provided with a plurality of lines, the plurality of first power rewiring lines including a first power line for connecting a high level and a second power line for connecting a low level, the first power line and the second power line being located on both sides of the second signal rewiring; The extension portion is provided on the second power line, and a distance between the extension portion and the first power line is smaller than a distance between the first power line and the second signal redistribution wiring; and / or, The width of the second power line is greater than the width of the second signal redistribution line.

4. The semiconductor structure according to any one of claims 1 to 3, characterized in that: The first power rewiring is connected to the corresponding second power rewiring via a plurality of conductive connection portions.

5. The semiconductor structure according to claim 4, wherein: The plurality of conductive connection portions connecting one of the first power rewiring lines and one of the second power rewiring lines are arranged along a second direction, and the second direction is an extending direction of the first power rewiring line. The semiconductor structure according to claim 4 , wherein: Each of the conductive connection portions is connected to a power rewiring body of the first power rewiring.

7. The semiconductor structure according to claim 4, wherein: The arrangement density of the conductive connection parts corresponding to the first power rewiring connected to a high level is greater than the arrangement density of the conductive connection parts corresponding to the first power rewiring connected to a low level.

8. The semiconductor structure according to any one of claims 1 to 3, characterized in that: The semiconductor structure further includes a packaging substrate, the first chip and the second chip are stacked on the packaging substrate, and the first chip or the second chip is connected to the packaging substrate via a wire.

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