A method, apparatus, device, storage medium and program product for encryption and decryption

Abstract

The application discloses an encryption and decryption method, device, equipment, storage medium and program product, and relates to the technical field of communication, so as to reduce encryption and decryption overhead. The method comprises the following steps: acquiring a composite bit block container; and sending the composite bit block container to a receiving end. The embodiment of the application can reduce encryption and decryption overhead.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of communication, and in particular to an encryption and decryption method, device, equipment, storage medium and program product. BACKGROUND

[0002] Ethernet is widely used in data centers, carrier networks, industrial Internet, Internet of Things, vehicle Ethernet and other scenarios. Since Ethernet is a shared communication link, any device connected to Ethernet can receive transmitted data, which makes network attacks more likely to occur in Ethernet. Therefore, measures such as data encryption, secure communication protocols and physical security enhancements are needed to prevent eavesdropping attacks.

[0003] Existing network encryption mechanisms include Transport Layer Security (TLS), Internet Protocol Security (IPSec) and MAC security (MACSec), which are used to provide security services at different network layers. However, the above encryption mechanisms have large overheads. SUMMARY

[0004] Embodiments of the present application provide an encryption and decryption method, device, equipment, storage medium and program product to reduce encryption and decryption overhead.

[0005] In a first aspect, the embodiments of the present application provide an encryption method applied to a physical layer (PHY) chip of a sending end, comprising:

[0006] obtaining a composite bit block container;

[0007] sending the composite bit block container to a receiving end;

[0008] The composite bit block container includes N bit container subblocks, each bit container subblock includes Q Low Density Parity Check Code (LDCP) code blocks, and each LDCP code block includes an Auxiliary Bit of 1 bit. The Auxiliary Bits of Q bits of M bit container subblocks of the composite bit block container are used to carry composite bit block container related information.

[0009] N represents the number of bit container subblocks included in the composite bit block container, M is an integer and N≥M≥1, and Q is an integer greater than or equal to 1.

[0010] Optionally, the composite bit block container related information includes:

[0011] a first indication, used for indicating a bitstream type, the bitstream type including a single bitstream or a composite bitstream container;

[0012] a second indication, used for identifying a start sub-block of the composite bitstream container;

[0013] a third indication, used for identifying a length of the composite bitstream container.

[0014] Optionally, if N>18, a second bit sub-block to an (N-17)th bit sub-block of the composite bit block container are reserved sub-blocks; an (N-16)th bit sub-block to an (N-1)th bit sub-block of the composite bit block container are used for carrying key-related information; and an Nth bit sub-block of the composite bit block container is an end sub-block of the composite bitstream container; or

[0015] if N=18, an (N-16)th bit sub-block to an (N-1)th bit sub-block of the composite bit block container are used for carrying key-related information; and an Nth bit sub-block of the composite bit block container is an end sub-block of the composite bitstream container.

[0016] Optionally, the method further includes:

[0017] acquiring a data frame from a media access control (MAC) layer through a physical coding sublayer (PCS) of the PHY chip and a reconciliation sublayer (RS);

[0018] encoding and scrambling the data frame through the PCS layer;

[0019] adding a lane overhead to the data frame after the encoding and scrambling operation through the PCS layer, to obtain a to-be-processed data frame;

[0020] performing LDPC encoding on the to-be-processed data frame through the PCS layer, to obtain the LDCP code block.

[0021] In a second aspect, an embodiment of the present application provides a decryption method, applied to a PHY chip of a receiving end, and including:

[0022] receiving a composite bit block container sent by a sending end;

[0023] decrypting the composite bit block container to obtain decrypted information;

[0024] The composite bit block container includes N bit container subblocks, each of which includes Q LDCP code blocks, and each of the LDCP code blocks includes 1-bit Auxiliary Bit; the Q Auxiliary Bits of the M bit container subblocks of the composite bit block container are used to carry composite bit block container related information.

[0025] N represents the number of bit container subblocks included in the composite bit block container, M is an integer and N≥M≥1, and Q is an integer greater than or equal to 1.

[0026] Optionally, the composite bit block container related information includes:

[0027] A first indication used to indicate a bit stream type, the bit stream type including a single bit stream or a composite bit stream container;

[0028] A second indication used to identify a starting subblock of the composite bit stream container;

[0029] A third indication used to identify a length of the composite bit stream container.

[0030] Optionally, if N>18, the second bit subblock to the N-17th bit subblock of the composite bit block container are reserved subblocks; the N-16th bit subblock to the N-1th bit subblock of the composite bit block container are used to carry key related information; and the Nth bit subblock of the composite bit block container is an ending subblock of the composite bit stream container; or

[0031] If N=18, the N-16th bit subblock to the N-1th bit subblock of the composite bit block container are used to carry key related information; and the Nth bit subblock of the composite bit block container is an ending subblock of the composite bit stream container.

[0032] Optionally, the decryption of the composite bit block container to obtain the decrypted information includes:

[0033] If the first indication of the composite bit block container related information is used to indicate that the bit stream type is a composite bit stream container, the starting subblock of the composite bit stream container and the length of the composite bit stream container are determined according to the second indication and the third indication respectively;

[0034] The ending subblock of the composite bit stream container is determined according to the starting subblock of the composite bit stream container and the length of the composite bit stream container, and key related information is obtained;

[0035] The composite bit stream container is decrypted by using the key related information to obtain the decrypted information.

[0036] Optionally, the method further comprises:

[0037] performing LDPC decoding on the decrypted information through a PCS layer of the PHY chip, and removing channel additional codes in information obtained after the LDPC decoding to obtain information to be processed;

[0038] performing descrambling and decoding operations on the information to be processed through the PCS layer of the PHY chip, and sending the information to be processed to a MAC layer through an RS layer.

[0039] In a third aspect, an encryption device is provided, which is applied to a PHY chip of a sending end and comprises:

[0040] a first obtaining module, configured to obtain a composite bit block container;

[0041] a first sending module, configured to send the composite bit block container to a receiving end;

[0042] The composite bit block container comprises N bit container subblocks, each of which comprises Q LDCP code blocks, and each of the LDCP code blocks comprises one bit of Auxiliary Bit; and the Q bits of Auxiliary Bit of M bit container subblocks of the composite bit block container are used to carry composite bit block container related information.

[0043] N represents the number of bit container subblocks included in the composite bit block container, M is an integer and N≥M≥1, and Q is an integer greater than or equal to 1.

[0044] Optionally, the composite bit block container related information comprises:

[0045] a first indication, used to indicate a bit stream type, the bit stream type comprising a single bit stream or a composite bit stream container;

[0046] a second indication, used to identify a starting subblock of the composite bit stream container;

[0047] a third indication, used to identify the length of the composite bit stream container.

[0048] Optionally, if N>18, the second bit subblock to the N-17th bit subblock of the composite bit block container are reserved subblocks; the N-16th bit subblock to the N-1th bit subblock of the composite bit block container are used to carry key related information; and the Nth bit subblock of the composite bit block container is an ending subblock of the composite bit stream container; or

[0049] If N=18, the N-16th bit sub-block to the N-1th bit sub-block of the composite bit block container are used to carry the key-related information; and the Nth bit sub-block of the composite bit block container is an end sub-block of the composite bit stream container.

[0050] Optionally, the apparatus further comprises a first processing module configured to:

[0051] acquire a data frame from a MAC layer via RS through a PCS layer of the PHY chip;

[0052] perform encoding and scrambling operations on the data frame through the PCS layer;

[0053] add a channel append code to the data frame after the encoding and scrambling operations through the PCS layer to obtain a to-be-processed data frame;

[0054] perform LDPC encoding on the to-be-processed data frame through the PCS layer to obtain the LDCP code block.

[0055] In a fourth aspect, an embodiment of the present application provides a decryption apparatus applied to a PHY chip of a receiving end, and comprising:

[0056] a first receiving module configured to receive a composite bit block container sent by a sending end;

[0057] a first decryption module configured to decrypt the composite bit block container to obtain decrypted information;

[0058] The composite bit block container comprises N bit container sub-blocks, each bit container sub-block comprises Q LDCP code blocks, and each LDCP code block comprises one bit of Auxiliary Bit; Q bits of Auxiliary Bit of M bit container sub-blocks of the composite bit block container are used to carry composite bit block container-related information.

[0059] N represents the number of bit container sub-blocks included in the composite bit block container, M is an integer and N≥M≥1, and Q is an integer greater than or equal to 1.

[0060] Optionally, the composite bit block container-related information comprises:

[0061] a first indication configured to indicate a bit stream type, the bit stream type comprising a single bit stream or a composite bit stream container;

[0062] a second indication configured to identify a start sub-block of the composite bit stream container;

[0063] a third indication configured to identify the length of the composite bit stream container.

[0064] Optionally, if N>18, the second bit sub-block to the N-17th bit sub-block of the composite bit block container are reserved sub-blocks; the N-16th bit sub-block to the N-1th bit sub-block of the composite bit block container are used to carry key-related information; and the Nth bit sub-block of the composite bit block container is an end sub-block of the composite bit stream container; or

[0065] If N=18, the N-16th bit sub-block to the N-1th bit sub-block of the composite bit block container are used to carry key-related information; and the Nth bit sub-block of the composite bit block container is an end sub-block of the composite bit stream container.

[0066] Optionally, the first decryption module is further configured to:

[0067] If the first indication of the composite bit block container-related information indicates that the bit stream type is a composite bit stream container, the starting sub-block of the composite bit stream container and the length of the composite bit stream container are determined according to the second indication and the third indication respectively.

[0068] The end sub-block of the composite bit stream container is determined according to the starting sub-block of the composite bit stream container and the length of the composite bit stream container, and key-related information is obtained.

[0069] The composite bit stream container is decrypted by using the key-related information, and the decrypted information is obtained.

[0070] Optionally, the apparatus further includes a first processing module configured to:

[0071] The decrypted information is LDPC-decoded by the PCS layer of the PHY chip, and a channel additional code in the information obtained after the LDPC decoding is removed, so as to obtain information to be processed.

[0072] The information to be processed is subjected to descrambling and decoding operations by the PCS layer of the PHY chip, and is sent to the MAC layer through the RS layer.

[0073] In a fifth aspect, an encryption apparatus is provided in an embodiment of the present application, which is applied to a PHY chip of a sending end and includes a processor and a transceiver.

[0074] The processor is configured to obtain a composite bit block container.

[0075] The transceiver is configured to send the composite bit block container to a receiving end.

[0076] The composite bit block container includes N bit container subblocks, each of which includes Q LDCP code blocks, and each of the LDCP code blocks includes 1 bit of Auxiliary Bit; and the Q bits of Auxiliary Bit of the M bit container subblocks of the composite bit block container are used to carry composite bit block container related information.

[0077] N represents the number of bit container subblocks included in the composite bit block container, M is an integer and N≥M≥1, and Q is an integer greater than or equal to 1.

[0078] Optionally, the composite bit block container related information includes:

[0079] a first indication used to indicate a bit stream type, the bit stream type including a single bit stream or a composite bit stream container;

[0080] a second indication used to identify a starting subblock of the composite bit stream container;

[0081] a third indication used to identify the length of the composite bit stream container.

[0082] Optionally, if N>18, the second bit subblock to the N-17th bit subblock of the composite bit block container are reserved subblocks; the N-16th bit subblock to the N-1th bit subblock of the composite bit block container are used to carry key related information; and the Nth bit subblock of the composite bit block container is an ending subblock of the composite bit stream container; or

[0083] if N=18, the N-16th bit subblock to the N-1th bit subblock of the composite bit block container are used to carry key related information; and the Nth bit subblock of the composite bit block container is an ending subblock of the composite bit stream container.

[0084] Optionally, the processor is further configured to:

[0085] acquire a data frame from a media access control (MAC) layer through a PCS layer and an RS layer of the PHY chip;

[0086] perform encoding and scrambling operations on the data frame through the PCS layer;

[0087] add a channel append code to the data frame after the encoding and scrambling operations to obtain a to-be-processed data frame;

[0088] perform LDPC encoding on the to-be-processed data frame through the PCS layer to obtain the LDCP code block.

[0089] In a sixth aspect, an embodiment of the present application provides a decryption device applied to a PHY chip of a receiving end, including a processor and a transceiver.

[0090] the transceiver, configured to receive a composite bit block container sent by a sending end;

[0091] the processor, configured to decrypt the composite bit block container to obtain decrypted information;

[0092] wherein the composite bit block container comprises N bit block sub-blocks, each bit block sub-block comprises Q LDCP code blocks, and each LDCP code block comprises 1-bit Auxiliary Bit; Q Auxiliary Bits of M bit block sub-blocks of the composite bit block container are used to carry composite bit block container related information.

[0093] wherein N represents the number of bit block sub-blocks included in the composite bit block container, M is an integer and N≥M≥1, and Q is an integer greater than or equal to 1.

[0094] Optionally, the composite bit block container related information comprises:

[0095] a first indication, used to indicate a bit stream type, wherein the bit stream type comprises a single bit stream or a composite bit stream container;

[0096] a second indication, used to identify a starting sub-block of the composite bit stream container;

[0097] a third indication, used to identify the length of the composite bit stream container.

[0098] Optionally, if N>18, the second bit sub-block to the N-17th bit sub-block of the composite bit block container are reserved sub-blocks; the N-16th bit sub-block to the N-1th bit sub-block of the composite bit block container are used to carry key related information; and the Nth bit sub-block of the composite bit block container is an ending sub-block of the composite bit stream container; or

[0099] if N=18, the N-16th bit sub-block to the N-1th bit sub-block of the composite bit block container are used to carry key related information; and the Nth bit sub-block of the composite bit block container is an ending sub-block of the composite bit stream container.

[0100] Optionally, the processor is further configured to:

[0101] if the first indication of the composite bit block container related information is used to indicate that the bit stream type is the composite bit stream container, the starting sub-block of the composite bit stream container and the length of the composite bit stream container are determined according to the second indication and the third indication respectively;

[0102] determining an ending sub-block of the composite bit stream container according to the starting sub-block of the composite bit stream container and a length of the composite bit stream container, and obtaining key-related information;

[0103] decrypting the composite bit stream container by using the key-related information to obtain the decrypted information.

[0104] Optionally, the processor is further configured to:

[0105] performing LDPC decoding on the decrypted information through a PCS layer of the PHY chip, and removing channel additional codes in information obtained after the LDPC decoding to obtain information to be processed;

[0106] performing descrambling and decoding operations on the information to be processed through the PCS layer of the PHY chip, and sending the information to be processed to a MAC layer through an RS layer.

[0107] In a seventh aspect, an embodiment of the present application further provides a communication device, including a memory, a processor, and a program stored in the memory and executable on the processor, and the processor implements steps of the encryption method or the decryption method when executing the program.

[0108] In an eighth aspect, an embodiment of the present application further provides a readable storage medium, and the readable storage medium stores a program, and the program implements steps of the encryption method or the decryption method when being executed by a processor.

[0109] In a ninth aspect, an embodiment of the present application further provides a computer program product, including computer instructions, and the computer instructions implement steps of the encryption method or the decryption method when being executed by a processor.

[0110] In the embodiment of the present application, the Auxiliary Bit of the LDCP code block is used to carry the composite bit block container-related information, no additional bandwidth overhead is introduced, and therefore the encryption and decryption overhead can be reduced. BRIEF DESCRIPTION OF DRAWINGS

[0111] Figure 1 is one of process flow diagrams of the encryption method or the decryption method provided by the embodiment of the present application;

[0112] Figure 2 is another one of process flow diagrams of the encryption method or the decryption method provided by the embodiment of the present application;

[0113] Figure 3 is one of process flow diagrams of the information processing method provided by the embodiment of the present application;

[0114] Figure 4 is a schematic diagram of the LDPC code block in the embodiment of the present application;

[0115] Figure 5Fig. 1 is a schematic diagram of a composite bitstream container structure according to an embodiment of the present application;

[0116] Figure 6 Fig. 2 is a schematic diagram of an encryption and decryption architecture and process according to an embodiment of the present application;

[0117] Figure 7 Fig. 3 is a flowchart of an information processing method according to an embodiment of the present application;

[0118] Figure 8 Fig. 4 is a structural diagram of an information processing apparatus according to an embodiment of the present application;

[0119] Figure 9 Fig. 5 is a structural diagram of an information processing apparatus according to an embodiment of the present application;

[0120] Figure 10 Fig. 6 is a structural diagram of an information processing apparatus according to an embodiment of the present application;

[0121] Figure 11 Fig. 7 is a structural diagram of an information processing apparatus according to an embodiment of the present application. DETAILED DESCRIPTION

[0122] In the embodiments of the present application, the term "and / or" is used to describe an association relationship between associated objects, which means that there can be three kinds of relationships, for example, A and / or B can mean that there are three cases of A alone, A and B together, and B alone. The character " / " generally represents an "or" relationship between the associated objects before and after it.

[0123] In the embodiments of the present application, the term "a plurality of" means two or more, and other quantifiers are similar.

[0124] The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative labor fall within the scope of the present application.

[0125] The existing network encryption mechanism has the following disadvantages:

[0126] 1. IPSec can provide security services at the network layer, and implement encryption and authentication mechanisms by establishing an IPSec tunnel between two secure gateways to protect the security of network layer data between the two parties. However, when a user needs to protect the data link layer network or the physical layer network, IPSec will not meet the needs. At the same time, IPSec needs to perform complex encapsulation operations on the original data packet, such as encapsulating the authentication packet header, the encrypted security payload packet header, and the packet tail. In the encapsulation process, a large packet encapsulation overhead will be introduced, occupying a certain bandwidth resource. When the data packet is processed by IPSec encryption and decryption, there is also a millisecond-level processing delay, which needs to be carefully evaluated for its impact on business latency.

[0127] 2. MACSec is a data link layer security encryption communication technology based on existing protocols, which can ensure the security of data frames between Ethernet devices and reduce the risk of information leakage and malicious network attacks. However, MACSec still has security vulnerabilities. On the one hand, MACSec cannot provide encryption protection for the Ethernet frame header, nor can it hide the traffic characteristics such as sending frequency and Ethernet frame length, which makes the unencrypted Ethernet frame header vulnerable to traffic model analysis attacks by attackers, thereby inferring the user's privacy and behavior. The standard group has proposed various protection schemes to solve this problem, but these schemes are still under discussion and will also introduce additional overhead, latency jitter, and increase the complexity of implementation. On the other hand, MACSec cannot encrypt priority traffic control frames or pause frames. The feasible solution under discussion involves modifying the existing MAC layer architecture, which will increase the complexity of the solution implementation.

[0128] In summary, due to the cost and use of the existing scheme, it needs to be further improved to make it easier to deploy in operator networks.

[0129] PHYSec is a security encryption technology that works at the physical layer of Ethernet and performs encryption and decryption on the physical layer bit stream. The Ethernet frame header at the data link layer and the IP header at the network layer are all payloads of the physical layer bit stream, so PHYSec can protect all upper layer protocols and data and hide traffic characteristics, with extremely high security. Taking 10G-BASET as an example, the deployment of PHYSec is in the PHY of the chip. Based on this, the embodiments of the present application propose a physical layer data encryption technology using a PHY chip based on LDPC code words. The embodiments of the present application construct a new physical layer coding format by combining the Auxiliary Bit field of the LDPC code block to carry the related information of the composite bit block container, and implement physical layer data encryption of the composite bit stream container in the PHY chip.

[0130] As Figure 1The diagram illustrates the processing procedure of an embodiment of this application. The plaintext bitstream from the sending end is encrypted at the physical layer to obtain the ciphertext bitstream. The receiving end, after obtaining the ciphertext bitstream, decrypts it at the physical layer to obtain the plaintext bitstream.

[0131] PHYSec is implemented at the physical layer, offloading the encryption and decryption algorithms to the underlying PHY chip to achieve line-speed encryption and decryption. For example... Figure 2 The diagram illustrates the PHYSec data encryption process. After encrypting the plaintext bitstream, a ciphertext bitstream is obtained. The receiving end, upon receiving the ciphertext bitstream, decrypts it to obtain the plaintext bitstream.

[0132] The following is a detailed description of different embodiments.

[0133] See Figure 3 , Figure 3 This is a flowchart of the encryption method provided in the embodiments of this application, applied to the PHY chip at the transmitting end, such as... Figure 3 As shown, it includes the following steps:

[0134] Step 301: Obtain the composite bit block container.

[0135] This step primarily involves forming a composite bit block container based on LDCP code blocks. The composite bit block container may include a start bit container sub-block, a reserved sub-block, an end bit container sub-block, etc.

[0136] In this embodiment of the application, the composite bit block container includes N bit container sub-blocks, each bit container sub-block includes Q LDCP code blocks, and each LDCP code block includes 1 bit of Auxiliary Bit; the Q bits of Auxiliary Bit in the M bit container sub-blocks of the composite bit block container are used to carry information related to the composite bit block container; where N represents the number of bit container sub-blocks included in the composite bit block container, M is an integer and N≥M≥1, and Q is an integer greater than or equal to 1.

[0137] like Figure 4As shown, the composition of the LDPC code block is shown. Taking 10G-BASET as an example, in the 10GBase-T encoding process, every 64 bit information, plus the control / data flag bit, constitutes a 65 bit block, 50 blocks constitute a group, and each group adds 8 bit cyclic redundancy check code (CRC). Therefore, a total of 65*50+8=3258 bits are generated, and a 1-bit channel auxiliary code (Auxiliary Bit) is added, which is a total of 3259 bits. That is, an LDCP code block includes 3259 bits. Among them, the 3259 bits are divided into two parts, 3*512 bits (including channel auxiliary code) are transmitted by unprotected mode, and the other 1723 bits plus 325 parity check codes are transmitted by LDPC (1723, 2048) protection mode. Among them, the Auxiliary Bit field is a usable field. In the embodiments of the present application, the Auxiliary Bit field is used to carry composite bit block container related information, such as bit stream type, length of composite bit block container, starting sub-block of composite bit stream container and the like.

[0138] Among them, the composite bit block container related information includes:

[0139] The first indication is used to indicate the bit stream type, and the bit stream type includes a single bit stream or a composite bit stream container. For example, 2 bits 00 are used to indicate the bit stream type, 00 represents a single bit stream, 11 represents a composite bit stream container, and the others are reserved;

[0140] The second indication is used to identify the starting sub-block of the composite bit stream container, for example, 4 bits can be used to indicate;

[0141] The third indication is used to identify the length of the composite bit stream container, that is, the number of bit container sub-blocks included in the composite bit stream container, for example, 10 bits can be used to represent.

[0142] In the embodiments of the present application, in the N bit container sub-blocks, any one or multiple sub-blocks can be used to carry the composite bit block container related information. Among them, N≥18, M=16 / Q, Q can take values such as 8, 16, 32, etc.

[0143] If Q=16, M=1, the 16 bits of Auxiliary Bit of one bit container sub-block of the composite bit block container are used to carry the composite bit block container related information, for example, the 16 bits of Auxiliary Bit of the first bit container sub-block of the composite bit block container can be used to carry the composite bit block container related information.

[0144] If Q=8 and M=2, the 16-bit AuxiliaryBit of the two bit container sub-blocks of the composite bit block container is used to carry information related to the composite bit block container. For example, the 16-bit AuxiliaryBit of the first and second bit container sub-blocks of the composite bit block container is used to carry information related to the composite bit block container.

[0145] Similarly, if Q = 32, then the 16-bit Auxiliary Bit of the 0.5 bit container sub-block of the composite bit block container is used to carry information related to the composite bit block container.

[0146] In this embodiment of the application, the composite bit block container may further include reserved sub-blocks, end sub-blocks, sub-blocks for carrying key-related information, etc.

[0147] Specifically, if N > 18, the second to N-17th bit sub-blocks of the composite bit block container are reserved sub-blocks; the N-16th to N-1th bit sub-blocks of the composite bit block container are used to carry key-related information; the Nth bit sub-block of the composite bit block container is the end sub-block of the composite bit stream container; or

[0148] If N = 18, the (N-16)th to (N-1)th bit sub-blocks of the composite bit block container are used to carry key-related information; the Nth bit sub-block of the composite bit block container is the end sub-block of the composite bit stream container. That is, in this case, reserved sub-blocks may not be included.

[0149] like Figure 5 As shown, taking N > 18 and Q = 16 as an example, this is a schematic diagram of the composite bitstream container structure of an embodiment of this application, including a container start sub-block, a reserved sub-block, a sub-block for carrying key-related information, and a container end sub-block. N bit sub-blocks (16 LDCP code blocks (3259 bits) constitute one sub-block) are combined to form a composite bit block container, which serves as the smallest encryption / decryption unit of PHYSec. The first bit sub-block carries the aforementioned composite bit block container-related information. In this case, the second to N-17th bit sub-blocks of the composite bit block container are reserved sub-blocks; the N-16th to N-1th bit sub-blocks of the composite bit block container are used to carry key-related information (e.g., 256 bits); and the Nth bit block of the composite bit block container is the end sub-block of the composite bitstream container.

[0150] For example, if Q=8 and N>36, the first and second bit sub-blocks of the composite bit block container are start sub-blocks; the third to N-34th bit sub-blocks are reserved sub-blocks; the N-33rd to N-2nd bit sub-blocks are used to carry key-related information; and the N-1th to Nth bit sub-blocks are end sub-blocks of the composite bit stream container.

[0151] According to the above description, it can be seen that the start sub-block of the composite bit block container occupies 16 bits, the sub-block used to carry key-related information occupies 256 bits, and the end sub-block occupies 16 bits, a total of 288 bits. On this basis, the reserved sub-blocks can also be included. Therefore, the values of Q and N can be set on this basis.

[0152] In the embodiments of the present application, the data encryption of PHYSec mainly provides confidentiality protection and integrity protection of data to prevent data leakage and tampering. PHYSec performs encryption and decryption on data based on a symmetric encryption algorithm, and optional algorithms include Advanced Encryption Standard (AES), SM4, etc. Therefore, the encryption method of the embodiments of the present application can be flexibly selected according to the use scenario. Then, the key-related information is mainly information related to the encryption algorithm, for example, can include random numbers, key-related information, etc.

[0153] As shown in Table 1, the descriptions of the sub-blocks of the composite bit block container are as follows:

[0154] Table 1

[0155]

[0156] In the above embodiments, the composite bit stream scheme formed based on the Auxiliary bit of the LDCP code block can be compatible with most PHY chips, has good universality, and can be applicable to data center networks, wide area network scenarios, and also can be applicable to widely used vehicle scenarios.

[0157] Step 302, sending the composite bit block container to the receiving end.

[0158] In the embodiments of the present application, the Auxiliary Bit of the LDCP code block is used to carry the composite bit block container-related information, without introducing additional bandwidth overhead, so as to reduce the encryption and decryption overhead. At the same time, the scheme of the embodiments of the present application has the advantage of high bandwidth utilization rate for bandwidth-sensitive use scenarios such as data center interconnection and enterprise park.

[0159] In the embodiment of the present application, for the sending end, the data frame can be acquired from the MAC layer through the RS of the PCS of the PHY chip; the data frame is encoded and scrambled through the PCS layer; the channel additional code is added to the data frame after the encoding and scrambling operation through the PCS layer, to obtain the to-be-processed data frame; the to-be-processed data frame is LDPC encoded through the PCS layer, to obtain the LDCP code block.

[0160] Referring to Figure 6 , Figure 6 is a flowchart of the decryption method provided in the embodiment of the present application, applied to the PHY chip of the receiving end, as shown in Figure 6 , comprising the following steps:

[0161] Step 601, receiving the composite bit block container sent by the sending end.

[0162] The composite bit block container comprises N bit container subblocks, each bit container subblock comprises Q LDCP code blocks, and each LDCP code block comprises 1 bit of Auxiliary Bit; the Q bits of Auxiliary Bit of the M bit container subblocks of the composite bit block container are used to carry the composite bit block container related information.

[0163] N represents the number of the bit container subblocks included in the composite bit block container, M is an integer and N≥M≥1, and Q is an integer greater than or equal to 1.

[0164] The structure of the composite bit block container can be as described above.

[0165] Step 602, decrypting the composite bit block container to obtain the decrypted information.

[0166] In this step, if the first indication of the composite bit block container related information is used to indicate that the bit stream type is a composite bit stream container, the starting subblock of the composite bit stream container and the length of the composite bit stream container are determined according to the second indication and the third indication respectively. Then, the ending subblock of the composite bit stream container is determined according to the starting subblock of the composite bit stream container and the length of the composite bit stream container, and the key related information is acquired. Finally, the composite bit stream container is decrypted by using the key related information, to obtain the decrypted information.

[0167] In the process of acquiring the key related information, the content of each subblock of the composite bit stream container can be read and parsed from the starting subblock of the composite bit stream container, until the key related information is acquired.

[0168] In the embodiments of the present application, the Auxiliary Bit of the LDCP code block is used to carry the composite bit block container related information, without introducing additional bandwidth overhead, thereby reducing the encryption and decryption overhead. Meanwhile, the scheme of the embodiments of the present application has the advantage of high bandwidth utilization rate for bandwidth-sensitive use scenarios such as data center interconnection and enterprise park.

[0169] Optionally, on the basis of the above-mentioned embodiments, the decrypted information can be LDPC decoded by the PCS layer of the PHY chip, and the channel additional code in the information obtained after the LDPC decoding is removed to obtain the information to be processed. The information to be processed is subjected to descrambling and decoding operations by the PCS layer of the PHY chip, and is sent to the MAC layer through the RS layer.

[0170] In the embodiments of the present application, the PHYSec works in the Ethernet physical layer. Taking 10G-BASET as an example, the PHYSec is deployed in the PHY of the chip, and the encryption and decryption architecture and process thereof are as shown in Figure 7 The data frame is sent from the MAC layer of the sending end to the PHY chip of the sending end, is converted into plaintext bit stream after the encoding and scrambling operations in the PCS layer, and is converted into ciphertext bit stream by the encryption module. After entering the optical module for transmission, the PHY chip of the receiving end receives the ciphertext bit stream, restores it into plaintext bit stream by the decryption module, and then sends it to the subsequent processing.

[0171] Specifically, for the sending end, the data frame can be acquired from the MAC layer through the PCS of the PHY chip and the RS; the data frame is subjected to encoding and scrambling operations by the PCS layer; the channel additional code is added to the data frame subjected to the encoding and scrambling operations by the PCS layer to obtain the data frame to be processed; the data frame to be processed is subjected to LDPC encoding by the PCS layer to obtain the LDCP code block. The LDCP code block is converted into ciphertext bit stream by the encryption module. After entering the optical module for transmission, the PHY chip of the receiving end receives the ciphertext bit stream, restores it into plaintext bit stream by the decryption module. Then, the plaintext bit stream is subjected to LDPC decoding by the PCS layer of the PHY chip, and the channel additional code in the information obtained after the LDPC decoding is removed to obtain the information. The information is subjected to descrambling and decoding operations by the PCS layer of the PHY chip, and is sent to the MAC layer through the RS layer.

[0172] As shown in Table 2, the comparison of several different encryption schemes is shown. It can be seen from the comparison that the encryption scheme of the physical layer of the embodiments of the present application has small encryption overhead, small encryption delay and simple implementation.

[0173] Table 2

[0174]

[0175]

[0176] Referring to Figure 8 , Figure 8 is a structural diagram of an encryption device provided by an embodiment of the present application, which is applied to a PHY chip of a sending end, as shown in Figure 8 , the encryption device comprises:

[0177] a first acquisition module 801, configured to acquire a composite bit block container;

[0178] a first sending module 802, configured to send the composite bit block container to a receiving end;

[0179] , the composite bit block container comprises N bit container subblocks, each bit container subblock comprises Q LDCP code blocks, and each LDCP code block comprises 1-bit Auxiliary Bit; the Q Auxiliary Bits of the M bit container subblocks of the composite bit block container are used to carry composite bit block container related information;

[0180] , wherein N represents the number of bit container subblocks included in the composite bit block container, M is an integer and N≥M≥1, and Q is an integer greater than or equal to 1.

[0181] Optionally, the composite bit block container related information comprises:

[0182] a first indication, used to indicate a bit stream type, the bit stream type comprising a single bit stream or a composite bit stream container;

[0183] a second indication, used to identify a starting subblock of the composite bit stream container;

[0184] a third indication, used to identify the length of the composite bit stream container.

[0185] Optionally, the second bit subblock to the N-17th bit subblock of the composite bit block container are reserved subblocks;

[0186] the N-16th bit subblock to the N-1th bit subblock of the composite bit block container are used to carry key related information;

[0187] the Nth bit subblock of the composite bit block container is an ending subblock of the composite bit stream container.

[0188] Optionally, the device further comprises a first processing module, configured to:

[0189] acquire a data frame from a MAC layer through a PCS layer of the PHY chip via RS;

[0190] perform encoding and scrambling operations on the data frame through the PCS layer.

[0191] The PCS layer adds a channel additional code to the data frame after the encoding and scrambling operation to obtain a to-be-processed data frame;

[0192] The PCS layer performs LDPC encoding on the to-be-processed data frame to obtain the LDCP code block.

[0193] The device provided in the embodiment of the present application can execute the method provided in the above embodiment, and has similar implementation principles and technical effects, which will not be described here again.

[0194] Referring to Figure 9 , Figure 9 is a structural diagram of a decryption device provided in the embodiment of the present application, applied to a PHY chip of a receiving end. As shown in Figure 9 , the decryption device comprises:

[0195] The first receiving module 901 is configured to receive a composite bit block container sent by a sending end.

[0196] The first decryption module 902 is configured to decrypt the composite bit block container to obtain decrypted information.

[0197] The composite bit block container comprises N bit container subblocks, each bit container subblock comprises Q LDCP code blocks, and each LDCP code block comprises an Auxiliary Bit of 1 bit; the Auxiliary Bits of Q bits of M bit container subblocks of the composite bit block container are used to carry composite bit block container related information.

[0198] N represents the number of bit container subblocks included in the composite bit block container, M is an integer and N≥M≥1, and Q is an integer greater than or equal to 1.

[0199] Optionally, the composite bit block container related information comprises:

[0200] A first indication is used to indicate a bit stream type, and the bit stream type comprises a single bit stream or a composite bit stream container.

[0201] A second indication is used to identify a starting subblock of the composite bit stream container.

[0202] A third indication is used to identify the length of the composite bit stream container.

[0203] Optionally, the second bit subblock to the N-17th bit subblock of the composite bit block container are reserved subblocks.

[0204] The N-16th bit subblock to the N-1th bit subblock of the composite bit block container are used to carry key related information.

[0205] The Nth bit sub-block of the composite bit block container is an end sub-block of the composite bit stream container.

[0206] Optionally, the first decryption module is further configured to:

[0207] If the first indication of the composite bit block container related information indicates that the bit stream type is a composite bit stream container, the starting sub-block of the composite bit stream container and the length of the composite bit stream container are determined according to the second indication and the third indication respectively;

[0208] According to the starting sub-block of the composite bit stream container and the length of the composite bit stream container, the end sub-block of the composite bit stream container is determined, and key related information is obtained;

[0209] The composite bit stream container is decrypted by using the key related information, and the decrypted information is obtained.

[0210] Optionally, the apparatus can further include a first processing module configured to:

[0211] The decrypted information is LDPC decoded by the PCS layer of the PHY chip, and the channel additional code in the information obtained after the LDPC decoding is removed, so as to obtain information to be processed;

[0212] The information to be processed is subjected to descrambling and decoding operations by the PCS layer of the PHY chip, and is sent to the MAC layer through the RS layer.

[0213] The apparatus provided by the embodiments of the present application can execute the above-mentioned method embodiments, and the implementation principles and technical effects are similar, and the present embodiment will not be described here.

[0214] Referring to Figure 10 , Figure 10 is a structural diagram of an encryption apparatus provided by the embodiments of the present application, and is applied to a PHY chip of a sending end, as shown in Figure 10 The encryption apparatus includes a processor 1001 and a transceiver 1002.

[0215] The processor 1001 is configured to obtain a composite bit block container.

[0216] The transceiver 1002 is configured to send the composite bit block container to a receiving end.

[0217] The composite bit block container includes N bit container sub-blocks, each of which includes Q LDCP code blocks, and each of the LDCP code blocks includes 1-bit Auxiliary Bit; the Q Auxiliary Bits of the M bit container sub-blocks of the composite bit block container are used to carry composite bit block container related information.

[0218] N represents the number of bit container sub-blocks included in the composite bit block container, M is an integer and N≥M≥1, and Q is an integer greater than or equal to 1.

[0219] Optionally, the composite bit block container related information includes:

[0220] A first indication is used to indicate a bit stream type, and the bit stream type includes a single bit stream or a composite bit stream container.

[0221] A second indication is used to identify a starting sub-block of the composite bit stream container.

[0222] A third indication is used to identify the length of the composite bit stream container.

[0223] Optionally, the second bit sub-block to the N-17th bit sub-block of the composite bit block container are reserved sub-blocks.

[0224] The N-16th bit sub-block to the N-1th bit sub-block of the composite bit block container are used to carry key related information.

[0225] The Nth bit sub-block of the composite bit block container is an end sub-block of the composite bit stream container.

[0226] Optionally, the processor 1001 is further configured to:

[0227] acquire a data frame from a media access control (MAC) layer through a PCS layer and an RS layer of the PHY chip;

[0228] perform encoding and scrambling operations on the data frame through the PCS layer;

[0229] add a channel append code to the data frame after the encoding and scrambling operations through the PCS layer to obtain a to-be-processed data frame;

[0230] perform LDPC encoding on the to-be-processed data frame through the PCS layer to obtain the LDCP code block.

[0231] The apparatus provided in the embodiments of the present application can execute the method embodiments, and the implementation principles and technical effects are similar, which will not be described here again.

[0232] Referring to Figure 11 , Figure 11is a structural diagram of a decryption device provided by an embodiment of the present application, and is applied to a PHY chip of a receiving end. Figure 11 As shown in the figure, the decryption device comprises a processor 1101 and a transceiver 1102.

[0233] The transceiver 1102 is configured to receive a composite bit block container sent by a sending end.

[0234] The processor 1101 is configured to decrypt the composite bit block container to obtain decrypted information.

[0235] The composite bit block container comprises N bit block subblocks, each bit block subblock comprises Q LDCP code blocks, and each LDCP code block comprises an Auxiliary Bit of 1 bit; the Auxiliary Bits of Q bits of M bit block subblocks of the composite bit block container are configured to carry composite bit block container related information.

[0236] N represents the number of bit block subblocks included in the composite bit block container, M is an integer and N≥M≥1, and Q is an integer greater than or equal to 1.

[0237] Optionally, the composite bit block container related information comprises:

[0238] a first indication configured to indicate a bit stream type, the bit stream type comprising a single bit stream or a composite bit stream container;

[0239] a second indication configured to identify a starting subblock of the composite bit stream container;

[0240] a third indication configured to identify the length of the composite bit stream container.

[0241] Optionally, the second bit subblock to the N-17th bit subblock of the composite bit block container are reserved subblocks.

[0242] The N-16th bit subblock to the N-1th bit subblock of the composite bit block container are configured to carry key related information.

[0243] The Nth bit subblock of the composite bit block container is an ending subblock of the composite bit stream container.

[0244] Optionally, the processor 1101 is further configured to:

[0245] If the first indication of the composite bit block container related information is configured to indicate that the bit stream type is a composite bit stream container, the starting subblock of the composite bit stream container and the length of the composite bit stream container are determined according to the second indication and the third indication respectively.

[0246] determine an ending sub-block of the composite bitstream container according to the starting sub-block of the composite bitstream container and a length of the composite bitstream container, and obtain key-related information;

[0247] decrypt the composite bitstream container by using the key-related information to obtain the decrypted information.

[0248] Optionally, the processor 1101 is further configured to:

[0249] perform LDPC decoding on the decrypted information through a PCS layer of the PHY chip, and remove a channel additional code in information obtained after the LDPC decoding to obtain to-be-processed information;

[0250] perform descrambling and decoding operations on the to-be-processed information through the PCS layer of the PHY chip, and send the to-be-processed information to a MAC layer through an RS layer.

[0251] The apparatus provided in the embodiments of the present application can execute the method embodiments, and the implementation principles and technical effects are similar, and thus the apparatus will not be described here again.

[0252] It should be noted that the division of units in the embodiments of the present application is illustrative, and is only a logical function division. In actual implementation, another division manner can be used. In addition, each functional unit in each embodiment of the present application can be integrated in one processing unit, or each unit can be physically present alone, or two or more units can be integrated in one unit. The integrated unit can be realized in the form of hardware or in the form of a software functional unit.

[0253] When the integrated unit is realized in the form of a software functional unit and sold or used as an independent product, the integrated unit can be stored in a processor-readable storage medium. Based on this understanding, the technical solutions of the present application can be embodied in the form of a software product in essence or the part that contributes to the prior art or the whole or part of the technical solutions. The computer software product is stored in a storage medium and includes a plurality of instructions for causing a computer device (which can be a personal computer, a server, or a network device, etc.) or a processor to execute all or part of the steps of the methods described in each embodiment of the present application. The foregoing storage medium includes a U disk, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk, and various storage medium that can store program codes.

[0254] The embodiment of the present application provides a communication device, comprising a memory, a processor and a program stored in the memory and executable on the processor; the processor is used for reading the program in the memory to realize the steps in the information processing method.

[0255] The embodiment of the present application also provides a readable storage medium, and the readable storage medium stores a program, the program is executed by a processor to realize various processes of the information processing method embodiment, and the same technical effects can be achieved. To avoid repetition, details are not described herein. The readable storage medium can be any available medium or data storage device that can be accessed by the processor, including but not limited to a magnetic storage (such as a floppy disk, a hard disk, a magnetic tape, a magneto-optical disk (MO) and the like), an optical storage (such as a CD, a DVD, a BD, a HVD and the like), and a semiconductor storage (such as a ROM, an EPROM, an EEPROM, a non-volatile memory (NAND FLASH), a solid state disk (SSD)) and the like.

[0256] The embodiment of the present application also provides a computer program product, comprising computer instructions, which are executed by a processor to realize various processes of the information processing method embodiment, and the same technical effects can be achieved. To avoid repetition, details are not described herein.

[0257] It should be noted that in this paper, the term "comprising", "including" or any other variant thereof is intended to cover non-exclusive inclusion, so that the process, method, article or device including a series of elements not only includes those elements, but also includes other elements not explicitly listed or inherent to such process, method, article or device. Without more limitations, the element defined by the statement "including a" does not exclude the presence of another identical element in the process, method, article or device including the element.

[0258] Through the description of the above embodiments, those skilled in the art can clearly understand that the above-mentioned embodiment method can be realized by means of software and necessary general hardware platform, of course, it can also be realized by hardware, but in many cases, the former is a better embodiment. According to such understanding, the technical solutions of the present application can be embodied in the form of computer software product, which is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disk), including a plurality of instructions for making a terminal (which can be a mobile phone, computer, server, air conditioner or network equipment) execute the method described in each embodiment of the present application.

[0259] The embodiments of the present application are described above with reference to the accompanying drawings, but the present application is not limited to the specific embodiments described above, and the specific embodiments described above are merely illustrative, but not restrictive, and a person of ordinary skill in the art can make many forms under the inspiration of the present application without departing from the purpose of the present application and the scope protected by the claims.

Claims

1. An encryption method characterized by, A physical layer (PHY) chip applied to a sending end comprises: obtaining a composite bit block container; sending the composite bit block container to a receiving end; wherein the composite bit block container comprises N bit container subblocks, each bit container subblock comprises Q low-density parity-check (LDCP) code blocks, and each LDCP code block comprises 1-bit auxiliary bit; Q bits of auxiliary bit of M bit container subblocks of the composite bit block container are used to carry composite bit block container related information; wherein N represents the number of bit container subblocks included in the composite bit block container, M is an integer and N≥M≥1, and Q is an integer greater than or equal to 1; the composite bit block container is used to carry encryption related information, and the composite bit block container related information is used to obtain key related information.

2. The method of claim 1, wherein, The composite bit block container related information comprises: a first indication used to indicate a bit stream type, the bit stream type comprising a single bit stream or a composite bit stream container; a second indication used to identify a starting subblock of the composite bit stream container; a third indication used to identify the length of the composite bit stream container.

3. The method of claim 2, wherein: if N>18, the second bit subblock to the N-17th bit subblock of the composite bit block container are reserved subblocks; the N-16th bit subblock to the N-1th bit subblock of the composite bit block container are used to carry key related information; and the Nth bit subblock of the composite bit block container is an ending subblock of the composite bit stream container; or if N=18, the N-16th bit subblock to the N-1th bit subblock of the composite bit block container are used to carry key related information; and the Nth bit subblock of the composite bit block container is an ending subblock of the composite bit stream container.

4. The method of claim 1, wherein, The method further comprises: obtaining a data frame from a medium access control (MAC) layer through a reconciliation sublayer (RS) of a physical coding sublayer (PCS) of the PHY chip; encoding and scrambling the data frame through the PCS layer; adding an auxiliary bit to the data frame after the encoding and scrambling operation to obtain a to-be-processed data frame through the PCS layer; performing LDPC encoding on the to-be-processed data frame to obtain the LDCP code block through the PCS layer.

5. A decryption method characterized by, A PHY chip applied to a receiving end comprises: receiving a composite bit block container sent by a sending end; decrypting the composite bit block container to obtain decrypted information; wherein the composite bit block container comprises N bit container subblocks, each bit container subblock comprises Q LDCP code blocks, and each LDCP code block comprises 1-bit auxiliary bit; Q bits of auxiliary bit of M bit container subblocks of the composite bit block container are used to carry composite bit block container related information; wherein N represents the number of bit container subblocks included in the composite bit block container, M is an integer and N≥M≥1, and Q is an integer greater than or equal to 1; The composite bit block container is used to carry encryption related information, and the composite bit block container related information is used to obtain key related information.

6. The method of claim 5, wherein, The composite bit block container related information includes: a first indication used to indicate a bit stream type, the bit stream type including a single bit stream or a composite bit stream container; a second indication used to identify a starting sub-block of the composite bit stream container; a third indication used to identify a length of the composite bit stream container.

7. The method of claim 6, wherein: if N>18, a second bit sub-block to an (N-17)th bit sub-block of the composite bit block container are reserved sub-blocks; an (N-16)th bit sub-block to an (N-1)th bit sub-block of the composite bit block container are used to carry key related information; and an Nth bit sub-block of the composite bit block container is an ending sub-block of the composite bit stream container; or if N=18, an (N-16)th bit sub-block to an (N-1)th bit sub-block of the composite bit block container are used to carry key related information; and an Nth bit sub-block of the composite bit block container is an ending sub-block of the composite bit stream container.

8. The method of claim 6, wherein, The decryption of the composite bit block container to obtain decrypted information includes: if the first indication of the composite bit block container related information is used to indicate that the bit stream type is the composite bit stream container, a starting sub-block of the composite bit stream container and a length of the composite bit stream container are determined according to the second indication and the third indication, respectively; an ending sub-block of the composite bit stream container is determined according to the starting sub-block of the composite bit stream container and the length of the composite bit stream container, and key related information is obtained; the composite bit stream container is decrypted by using the key related information to obtain the decrypted information.

9. The method of claim 5, wherein, The method further includes: the decrypted information is LDPC decoded by a PCS layer of the PHY chip, and a channel additional code in information obtained after the LDPC decoding is removed to obtain to-be-processed information; the to-be-processed information is subjected to descrambling and decoding operations by the PCS layer of the PHY chip, and is sent to a MAC layer through an RS layer.

10. An encryption device, characterized by A PHY chip applied to a sending end includes: a first obtaining module used to obtain a composite bit block container; a first sending module used to send the composite bit block container to a receiving end; wherein the composite bit block container includes N bit container sub-blocks, each bit container sub-block includes Q LDCP code blocks, and each LDCP code block includes an Auxiliary Bit of 1 bit; Q Auxiliary Bits of M bit container sub-blocks of the composite bit block container are used to carry composite bit block container related information; wherein N represents a number of bit container sub-blocks included in the composite bit block container, M is an integer and N≥M≥1, and Q is an integer greater than or equal to 1; the composite bit block container is used to carry encryption related information, and the composite bit block container related information is used to obtain key related information.

11. A decryption device, characterized by A PHY chip applied to a receiving end includes: a first receiving module used to receive a composite bit block container sent by a sending end; and a second obtaining module used to obtain key related information according to the composite bit block container related information. The first decryption module is configured to decrypt the composite bit block container to obtain decrypted information. The composite bit block container includes N bit container sub-blocks, each of which includes Q LDCP code blocks, and each of the LDCP code blocks includes one bit of Auxiliary Bit; and the Q bits of Auxiliary Bit of the M bit container sub-blocks of the composite bit block container are configured to carry composite bit block container related information. N represents the number of bit container sub-blocks included in the composite bit block container, M is an integer and N≥M≥1, and Q is an integer greater than or equal to 1. The composite bit block container is configured to carry encryption related information, and the composite bit block container related information is configured to obtain key related information.

12. An encryption device, characterized by The PHY chip applied to the sending end includes a processor and a transceiver. The processor is configured to obtain a composite bit block container. The transceiver is configured to send the composite bit block container to a receiving end. The composite bit block container includes N bit container sub-blocks, each of which includes Q LDCP code blocks, and each of the LDCP code blocks includes one bit of Auxiliary Bit; and the Q bits of Auxiliary Bit of the M bit container sub-blocks of the composite bit block container are configured to carry composite bit block container related information. N represents the number of bit container sub-blocks included in the composite bit block container, M is an integer and N≥M≥1, and Q is an integer greater than or equal to 1. The composite bit block container is configured to carry encryption related information, and the composite bit block container related information is configured to obtain key related information.

13. A decryption device, characterized by The PHY chip applied to the receiving end includes a processor and a transceiver. The transceiver is configured to receive a composite bit block container sent by a sending end. The processor is configured to decrypt the composite bit block container to obtain decrypted information. The composite bit block container includes N bit container sub-blocks, each of which includes Q LDCP code blocks, and each of the LDCP code blocks includes one bit of Auxiliary Bit; and the Q bits of Auxiliary Bit of the M bit container sub-blocks of the composite bit block container are configured to carry composite bit block container related information. N represents the number of bit container sub-blocks included in the composite bit block container, M is an integer and N≥M≥1, and Q is an integer greater than or equal to 1. The composite bit block container is configured to carry encryption related information, and the composite bit block container related information is configured to obtain key related information.

14. A communication device comprising: The memory, the processor, and a program stored in the memory and executable on the processor; and the processor is configured to read the program in the memory to implement the steps in the encryption method according to any one of claims 1 to 4 or implement the steps in the decryption method according to any one of claims 5 to 9.

15. A computer readable storage medium for storing a program, characterized in that, The program, when executed by the processor, implements the steps in the encryption method as claimed in any one of claims 1 to 4; or implements the steps in the decryption method as claimed in any one of claims 5 to 9.

16. A computer program product, characterised in that, The program, when executed by the processor, implements the steps in the encryption method as claimed in any one of claims 1 to 4; or implements the steps in the decryption method as claimed in any one of claims 5 to 9.

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