A conversion circuit applied to a gateway electric energy meter and a gateway electric energy meter

Abstract

The present invention relates to a conversion circuit and a gateway electric energy meter applied to a gateway electric energy meter, and belongs to the field of electric energy meters. Among them, the ADC high-speed transmission conversion circuit includes: a delay circuit is used to connect to the data ready end of the analog-to-digital converter of the gateway electric energy meter to output a delay signal whose phase follows the data ready signal; one input end of the OR gate circuit is connected to the output end of the delay circuit, the other input end is grounded, and the output end is connected to the input end of the differential circuit and outputs a shaped and stabilized voltage signal; the output end of the differential circuit is connected to the reset pulse signal end of the counter circuit to generate a reset pulse signal; the clock input end of the counter circuit is used to connect to the clock signal end of the analog-to-digital converter, and the output end is used to connect to the chip select signal end of the microcontroller of the gateway electric energy meter. Since the present invention does not need to call the internal resources of the processor to judge and process the validity of data, the processing time is shortened, thereby improving the reliability of data transmission.

Description

Technical Field

[0001] The invention relates to a conversion circuit applied to a gateway electric energy meter and the gateway electric energy meter, belonging to the field of electric energy meters. Background Art

[0002] The gateway energy meter is a high-precision energy meter used in important nodes such as power generation enterprises' grid connection, cross-regional interconnection lines, provincial grid interconnection lines and provincial grid connection. Its internal principle design uses a high-precision analog-to-digital converter (ADC). Its main function is to convert analog signals (such as voltage and current) into digital signals and transmit them to the processor at high speed. The processor performs relevant operations on the digital signals.

[0003] For gateway electric energy meters, the existing solutions generally use 8-channel 24-bit synchronous ADC integrated chips. The sampling data output has DOUT0~DOUT7, a total of 8 pins. The ADC works as the host and the processor works as the slave. The data flows into the processor for related digital signal processing. In general, the ADC inside the gateway electric energy meter usually uses a non-standard SPI communication protocol. The data transmission is a periodic pulse signal (frame synchronization signal). The falling edge of each signal starts the new ADC high-speed output conversion circuit to output data. When designing, this pin needs to be connected to the external interrupt pin of the processor for synchronous data reception and processing. The DCLK signal always exists during the entire frame period. Such a design has strict requirements on the processor. On the one hand, the processor's main frequency speed needs to be high enough; on the other hand, it is necessary to call the processor's external interrupt, communication bus and other resources to coordinate and cooperate to judge and process the validity of the data. The software design is quite complex and the processing time is long. The constant existence of DCLK leads to high CPU occupancy of the processor, so the data reception is unstable and the reliability is low. Summary of the invention

[0004] The purpose of the present invention is to provide a conversion circuit and a gateway electric energy meter for solving the problem of unstable data reception and low reliability caused by complex software design of a slave processor when a non-standard SPI communication protocol is adopted.

[0005] To achieve the above object, the solution of the present invention includes:

[0006] A conversion circuit applied to a gateway electric energy meter of the present invention comprises a delay circuit, an OR gate circuit, a differential circuit and a counter circuit;

[0007] The delay circuit is used to be connected to the data ready terminal of the analog-to-digital converter of the gateway electric energy meter to output a delay signal whose phase follows the data ready signal;

[0008] One input terminal of the OR gate circuit is connected to the output terminal of the delay circuit, the other input terminal is grounded, and the output terminal is connected to the input terminal of the differentiating circuit;

[0009] The output end of the differential circuit is connected to the reset pulse signal end of the counter circuit to generate a reset pulse signal for triggering the reset of the counter circuit according to the voltage stabilization signal output by the OR gate circuit;

[0010] The clock input end of the counter circuit is used to connect to the clock signal end of the analog-to-digital converter of the gateway electric energy meter, and the output end of the counter circuit is used to connect to the chip select signal end of the processor of the gateway electric energy meter.

[0011] Furthermore, the delay circuit is an RC integration circuit.

[0012] Furthermore, the OR gate circuit includes an OR gate chip 74HC1G.

[0013] Furthermore, the differential circuit is an RC differential circuit.

[0014] Furthermore, the counter circuit includes a counter chip 74HC4040D.

[0015] A gateway electric energy meter of the present invention comprises an analog-to-digital converter and a processor, a delay circuit, an OR gate circuit, a differential circuit and a counter circuit;

[0016] The delay circuit is used to be connected to the data ready terminal of the analog-to-digital converter to output a delay signal whose phase follows the data ready signal;

[0017] One input terminal of the OR gate circuit is connected to the output terminal of the delay circuit, the other input terminal is grounded, and the output terminal is connected to the input terminal of the differentiating circuit;

[0018] The output end of the differential circuit is connected to the reset pulse signal end of the counter circuit to generate a reset pulse signal for triggering the reset of the counter circuit according to the voltage stabilization signal output by the OR gate circuit;

[0019] The clock input terminal of the counter circuit is used to connect to the clock signal terminal of the analog-to-digital converter, and the output terminal of the counter circuit is used to connect to the chip selection signal terminal of the processor.

[0020] Furthermore, the delay circuit is an RC integration circuit.

[0021] Furthermore, the OR gate circuit includes an OR gate chip 74HC1G; and the counter circuit includes a counter chip 74HC4040D.

[0022] Furthermore, the differential circuit is an RC differential circuit.

[0023] Furthermore, the analog-to-digital converter collects data at a sampling frequency of 32 kHz; the data transmission rate is 16 MHz.

[0024] The beneficial effects of the present invention are as follows: as a pioneering invention, the ADC high-speed transmission conversion circuit provided by the present invention includes a delay circuit, an OR gate circuit, a differential circuit and a counter circuit; the delay circuit is used to be connected to the data ready end of the analog-to-digital converter of the gateway electric energy meter to output a delay signal whose phase follows the data ready signal; one input end of the OR gate circuit is connected to the output end of the delay circuit, the other input end is grounded, and the output end is connected to the input end of the differential circuit; the output end of the differential circuit is connected to the reset pulse signal end of the counter circuit to generate a reset pulse signal for triggering the reset of the counter circuit according to the voltage-stabilizing signal output by the OR gate circuit; the clock input end of the counter circuit is used to be connected to the clock signal end of the analog-to-digital converter of the gateway electric energy meter, and the output end of the counter circuit is used to be connected to the chip select signal end of the processor of the gateway electric energy meter. Through the delay circuit, a delay signal that follows the phase of the data-ready signal can be output. By delaying the data-ready signal, the generation of the reset pulse signal can be delayed, which can ensure that when the subsequent counter uses the reset pulse signal to generate a chip select signal and uses the low level validity of the chip select signal to receive data, the received data are all complete valid data of the new cycle, and neither valid data at the end of the previous cycle nor invalid data. Through the circuit conversion to standard SPI, it can be conveniently processed based on the internal SPI interface of the ordinary processor. The entire process does not need to call the internal resources of the processor to judge and process the data validity, which shortens the processing time and thus improves the reliability of data transmission. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1 It is a principle block diagram of a gateway electric energy meter provided by an embodiment of the present invention;

[0026] Figure 2 It is an electrical schematic diagram of an ADC high-speed transmission conversion circuit provided by an embodiment of the present invention;

[0027] Figure 3 The present invention is a schematic diagram of a signal timing control of an ADC high-speed transmission conversion circuit provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0028] In order to make the purpose, technical solutions and advantages of the present invention more clear, the present invention is further described in detail below in conjunction with the accompanying drawings and embodiments.

[0029] The existing gateway smart meter includes an analog-to-digital converter and a microcontroller, and the analog-to-digital converter is directly connected to the microcontroller. Among them, when the analog-to-digital converter of the gateway smart meter adopts an 8-channel 24-bit synchronous ADC integrated chip, at least 6 channels are used to transmit voltage and current data, namely U a , U b , Uc ,I a ,I b and I c , 8 channels collect data simultaneously, 6 of which are sampling data actually used, and the remaining 2 channels are data not actually used. The data of 8 channels will be transmitted to the processor.

[0030] The data output mode can be configured into 3 types: the first output mode is that each channel outputs through its own dedicated pin; the second output mode is that channels 0 to 3 share the DOUT0 pin output, and channels 4 to 7 share the DOUT1 pin output; the third output mode is that 8 channels share the DOUT0 pin output.

[0031] The data transmission time in the first output mode is short, but because each channel has its own dedicated pin and there are many data output channels, it will occupy many IO interface connections, resulting in complex and costly connections between the ADC chip and the processor; although the second output mode has fewer IO interface connections, the data transmission time is long; the third output mode has the least IO interface connections, but the data transmission time is the longest.

[0032] Since the gateway energy meter is designed to have a simple internal circuit and low cost, the ADC in the gateway energy meter usually adopts the third output mode after comprehensive consideration. Since ADC manufacturers usually use non-standard SPI communication protocols in production, but the processor interface is usually a standard SPI interface, when using non-standard SPI communication protocols to communicate with the processor, on the one hand, the processor must use external interrupt pins for synchronization processing; on the other hand, it usually needs to call internal resources for a series of coordinated processing to determine whether the transmitted data is valid. The software processing is very complicated, resulting in poor data transmission reliability.

[0033] In order to improve the reliability of data transmission, the concept of the present invention is: adding an ADC high-speed transmission conversion circuit between the analog-to-digital converter and the microcontroller, the ADC high-speed transmission conversion circuit includes a delay circuit, an OR gate circuit, a differential circuit and a counter circuit; the delay circuit is used to be connected to the data ready end of the analog-to-digital converter to output a delay signal whose phase follows the data ready signal; one input end of the OR gate circuit is connected to the output end of the delay circuit, the other input end is grounded, and the output end is connected to the input end of the differential circuit; the output end of the differential circuit is connected to the reset pulse signal end of the counter circuit to generate a reset pulse signal for triggering the reset of the counter circuit according to the voltage stabilization signal output by the OR gate circuit; the clock input end of the counter circuit is used to connect the clock signal end of the analog-to-digital converter, and the output end of the counter circuit is used to connect the chip select signal end of the microcontroller.

[0034] Through the delay circuit, a delay signal that follows the phase of the data-ready signal can be output. By delaying the data-ready signal, the generation of the reset pulse signal can be delayed, which can ensure that when the subsequent counter uses the reset pulse signal to generate the chip select signal, the low level validity of the chip select signal is used to receive data. The received data are all complete valid data of the new cycle, and neither valid data at the end of the previous cycle nor invalid data. The whole process does not need to call the internal resources of the processor to judge and process the validity of the data, so that the processing time is shortened, and the reliability of data transmission can be improved. The ADC high-speed transmission conversion circuit of the present invention can convert the non-standard SPI transmission mode into a standard SPI transmission mode, so that the processor can directly call the standard SPI communication interface inside the processor, so that the data received by the processor is complete valid data within a cycle, and the external interrupt pin of the processor does not need to be coordinated and the software resources are additionally called to judge the validity of the data, which avoids the problem of high CPU occupancy caused by the continuous existence of DCLK, and also improves the reliability of received data.

[0035] An embodiment of a gateway electric energy meter:

[0036] Figure 1 is a principle block diagram of a gateway electric energy meter provided by an embodiment of the present invention, such as Figure 1 As shown, the gateway electric energy meter includes an analog-to-digital converter, a processor and an ADC high-speed transmission conversion circuit.

[0037] In order to reduce the volume and cost of the gateway electric energy meter, as an optional implementation, the analog-to-digital converter is an analog-to-digital conversion chip as an example for illustration. The present invention does not specifically limit the selection of the chip model of the analog-to-digital conversion chip, and the analog-to-digital conversion chip is AD7768 as an example for illustration.

[0038] The processor may be a microcontroller unit (MCU) or a digital signal processor (DSP), etc., and the present invention does not specifically limit this.

[0039] Whether it is a standard SPI communication protocol or a non-standard SPI communication protocol, it is a master-slave communication mode. Therefore, set the AD7768 as the master and the processor as the slave. Then configure the data output mode of the AD7768 to the third output mode, that is, the data of sampling channels 0 to 7 share the DOUT0 signal line and are transmitted to the MOSI pin of the processor.

[0040] Among them, "M" stands for master, "S" stands for slave, "I" stands for input, and "O" stands for output, so "MOSI" means master output and slave input.

[0041] AD7768 data ready signal terminal Connect the first input terminal of the conversion circuit, the clock signal terminal DCLK of AD7768 is connected to the clock control terminal CLK of the processor and the second input terminal of the conversion circuit respectively, and the output terminal of the ADC high-speed transmission conversion circuit is connected to the chip select signal terminal of the processor .

[0042] Data ready signal terminal The output data is the output signal The DCLK signal output from the clock signal terminal DCLK forms a standard chip select signal after passing through the conversion circuit and SPI clock signal, so that the non-standard SPI signal of AD7768 sampling data can be converted into a standard SPI signal for use by the processor.

[0043] Among them, the specific electrical schematic diagram of the ADC high-speed transmission conversion circuit can be referred to Figure 2 , Figure 2 is an electrical schematic diagram of an ADC high-speed transmission conversion circuit provided by an embodiment of the present invention, such as Figure 2 As shown, the ADC high-speed transmission conversion circuit includes: a delay circuit 1, an OR gate circuit 2, a differential circuit 3 and a counter circuit 4.

[0044] Specifically, the input end of delay circuit 1 is used to connect the data ready end of AD7768. The output end of the delay circuit 1 is connected to an input end of the OR gate circuit 2, and the third end of the delay circuit 1 is grounded GND; the ground end of the OR gate circuit 2 and the other input end of the OR gate circuit are grounded GND, the power end of the OR gate circuit 2 is connected to the power supply VDD, and the output end of the OR gate circuit 2 is connected to the input end of the micro circuit 3; the output end of the differential circuit 3 is connected to the reset pulse signal end MR of the counter circuit 4, and the third end of the differential circuit 3 is grounded GND; the clock input end of the counter circuit 4 It is used to connect the clock signal terminal DCLK of AD7768. The eighth output terminal Q8 of the counter circuit 4 is used to connect the chip select signal terminal of the processor. .

[0045] Delay circuit 1 is used to output a phase-following data-ready signal The delay circuit will cause waveform distortion (slow rising and falling edges), so the OR gate circuit 2 is used to shape and level-follow the delay signal, generate a voltage-stabilizing signal, and ensure the stability of the subsequent differential circuit; the differential circuit 3 is used to generate a sharp pulse wave, and generate a reset pulse signal MR for triggering the reset of the counter circuit 4; the counter circuit 4 is cleared to zero according to the reset pulse signal MR, and then the clock signal DCLK is counted, so that the subsequent chip selection signal logical conversion.

[0046] Among them, the chip select signal It is a signal with high and low levels. When it is at a low level, valid data can be received, and when it is at a high level, SPI data is not received.

[0047] In order to reduce the cost, the delay circuit 1 can be an RC integration circuit. Specifically, the RC integration circuit includes a first resistor R1 and a first capacitor C1, one end of the first resistor R1 is the input end of the delay circuit 1, the other end of the first resistor R1 is the output end of the delay circuit 1, the first end of the first capacitor C1 is connected to the other end of the first resistor R1, and the other end of the first capacitor C1 is the third end of the delay circuit 1, which is grounded GND.

[0048] Among them, in order to reduce costs, the OR gate circuit 2 can use an OR gate chip. The present invention does not specifically limit the chip model of the OR gate chip, and the chip model of the OR gate chip is 74HCT1G as an example for exemplary description. When the OR gate circuit is a 74HCT1G chip, the input terminal A of the 74HCT1G chip is connected to the other end of the first resistor R1, the input terminal B of the 74HCT1G chip and the ground terminal GND of the 74HCT1G chip are connected to the same ground, the power supply terminal VCC of the 74HCT1G chip is connected to the voltage VDD, and the output terminal of the 74HCT1G chip is connected to the input terminal of the differential circuit 3.

[0049] In order to reduce the cost, the differential circuit 3 can be an RC differential circuit. Specifically, the RC differential circuit includes a second resistor R2 and a second capacitor C2, one end of the second capacitor C2 is the input end of the differential circuit 3, the other end of the second capacitor C2 is the output end of the differential circuit 3, one end of the second resistor R2 is connected to the other end of the second capacitor C2, and the other end of the second resistor is the third end of the differential circuit 3, which is grounded GND.

[0050] In order to reduce the cost, the counter circuit 4 can use a counter chip. The present invention does not specifically limit the chip model of the counter chip. The following explanation is given by taking the chip model of the counter chip as 74HC4040D as an example. The counter uses 74HC4040D, which is a 12-level binary asynchronous counter with a clock input ( ) overrides the asynchronous master reset input (MR) and twelve parallel outputs (Q0 to Q11). After reset, the falling edge counter of DCLK advances. Since it is necessary to count 256 DCLK output signals, the counter uses a binary system. 8 =256, so select pin 8 Q8 as the output terminal to output the chip select signal In this example, the chip select signal When the DCLK output signal reaches 256, the chip select signal When pulled high, the data counted are all complete valid data within one ADC sampling point transmission cycle.

[0051] Combine the following Figure 3 illustrate Figure 2 The working principle of the conversion circuit is provided.

[0052] Figure 3 Schematic diagram of signal timing control of an ADC high-speed transmission conversion circuit provided by an embodiment of the present invention, such as Figure 3 As shown, for the ADC, the output data ready signal It is a falling edge frame enable signal, that is, the falling edge marks the start of data transmission. However, since the transmission starts very quickly, the processor responds to the interrupt along the falling edge (the interrupt response process takes a certain amount of time), which often causes the first data bit to be missed. Therefore, when designing, consider The rising edge of the trigger processor interrupt, but if you directly use The rising edge of the reset pulse signal MR will trigger the processor interrupt, which will cause the reset pulse signal MR to be triggered before the data ready signal The chip select signal appears at the rising edge of The data ready signal The rising edge of is pulled low and valid data begins to be counted, but the valid data will include the last valid data of the previous cycle and lack the last valid data of this cycle. The last valid data of this cycle will be regarded as invalid data statistics, resulting in frequent data transmission errors.

[0053] Therefore, in order to reduce the occurrence of data transmission errors, the data ready signal After being delayed by delay circuit 1, a phase-following data-ready signal is generated The purpose of the delayed signal is to utilize The rising edge of triggers SPI communication, responds faster, and then Data transmission starts at the falling edge of , so as not to miss the first valid data bit.

[0054] After delay circuit 1 It will be deformed and needs to be shaped by the OR gate circuit 2 first, that is, a voltage-stabilized signal Y is formed. The width of the pulse signal after shaping is still large, and it becomes a reset pulse signal that lags behind the clock signal DCLK. It will still take up a DCLK time, and then pass through the differential circuit 3. A sharp pulse with a very short maintenance time will be generated at both the rising and falling edges of the voltage-stabilized signal Y (the directions of the rising and falling sharp pulses are opposite).

[0055] The output of the differential circuit 3 is used as the reset pulse signal MR of the counter circuit 4 (only responds to the sharp pulse in the positive direction), which starts counting, that is, realizes the chip selection signal In the original data ready signal The falling edge of is pulled down and becomes a low-level chip select signal When the counter circuit 4 counts a certain amount of clock signal DCLK cycles of effective data transmission, the counter circuit 4 outputs a high-level chip select signal CS.

[0056] The sampling frequency of the ADC is designed to be 32 kHz, so the sampling time t ODR = =31.25 microseconds (μs).

[0057] The data transmission rate of SPI is configured to be 16 MHz, that is, the transmission period of each clock signal DCLK is t DCLK = = 62.5 nanoseconds (ns). The sampling result of each channel is 4 bytes (Byte), so the sampling result of 8 channels is 8 ( )*4 (Byte)*8 (number of channels) = 256 bits, which means that the number of DCLKs for effective data transmission is 256. Since the actual data transmission time is 62.5ns*256=16μs, the data transmission time accounts for about half of the sampling time, that is, 16μs<31.25μs, so the data transmission rate is relatively fast.

[0058] In the original The falling edge of the signal (corresponding to the rising edge of the voltage-stabilizing signal Y output by the OR gate) triggers the reset pulse signal MR. After the reset pulse signal MR appears, the chip select signal The counter circuit 4 starts to count the data output from the DOUT0 pin of AD7768. After counting 256 DCLK signals, the chip select signal CS is pulled high until the data ready signal after the next delay. At the falling edge of , the counter circuit 4 starts to count again.

[0059] Throughout Frame period t ODRThe DCLK signal always exists in the DOUT0 pin of AD7768. The data outputted by the DOUT0 pin includes the valid data of 8 channels (256 DCLK signals). The subsequent DCLK signals are all invalid data. The start mark of the valid data is MSB, and the end mark of the valid data is LSB. The rising edge of The data transmission starts at the falling edge of , which can just count all the valid data without counting the invalid data. Therefore, the processor does not need to call additional resources, which saves the processing time of the processor and improves the timeliness of data transmission. At the same time, because the ADC high-speed transmission conversion circuit can convert the non-standard SPI communication protocol into the standard SPI communication protocol, there is no need to purchase a special processor. Generally, the processor contains the SPI communication unit, which can be automatically configured by the software, saving the cost of components.

[0060] A gateway electric energy meter provided by an embodiment of the present invention can convert a non-standard SPI communication protocol of the ADC into a standard SPI communication protocol by adding an ADC high-speed transmission conversion circuit, which is beneficial for the processor to directly process relevant data without the need for complex processing functions such as external interrupts, and has low requirements for the processor, which can save the solution cost of components and improve universality; on the other hand, since valid data and invalid data can be directly distinguished, only valid data is transmitted to the processor, which reduces the CPU occupancy rate and processing process, and can improve data reliability; thirdly, by utilizing the third output mode of the ADC chip, the connection of other data port lines is reduced, and the conventional field-programmable gate array (FPGA) access solution is avoided, which greatly reduces the design complexity.

[0061] An embodiment of a conversion circuit applied to a gateway electric energy meter:

[0062] For an embodiment of a conversion circuit applied to a gateway electric energy meter, reference may be made to the related description of the ADC high-speed transmission conversion circuit in the aforementioned embodiment of a gateway electric energy meter, which will not be repeated here.

[0063] A conversion circuit applied to a gateway electric energy meter provided in an embodiment of the present invention can achieve the same beneficial effects as the aforementioned gateway electric energy meter, which will not be described in detail here.

Claims

1. A conversion circuit applied to a gateway electric energy meter, characterized in that: Including delay circuit, OR gate circuit, differential circuit and counter circuit; The delay circuit is used to connect to the data ready terminal of the analog-to-digital converter of the gateway electric energy meter to output a delay signal whose phase follows the data ready signal; One input end of the OR gate circuit is connected to the output end of the delay circuit, the other input end is grounded, and the output end is connected to the input end of the differential circuit; The output end of the differential circuit is connected to the reset pulse signal end of the counter circuit to generate a reset pulse signal for triggering the reset of the counter circuit according to the shaped and stabilized voltage signal output by the OR gate circuit; The clock input end of the counter circuit is used to connect to the clock signal end of the analog-to-digital converter of the gateway electric energy meter, and the output end of the counter circuit is used to connect to the chip select signal end of the processor of the gateway electric energy meter.

2. The conversion circuit applied to a gateway electric energy meter according to claim 1, characterized in that: The delay circuit is an RC integration circuit.

3. The conversion circuit applied to a gateway electric energy meter according to claim 1, characterized in that: The OR gate circuit includes an OR gate chip 74HC1G.

4. The conversion circuit applied to a gateway electric energy meter according to claim 1, characterized in that: The differential circuit is an RC differential circuit.

5. The conversion circuit applied to a gateway electric energy meter according to claim 1, characterized in that: The counter circuit includes a counter chip 74HC4040D.

6. A gateway electric energy meter, comprising an analog-to-digital converter and a processor, characterized in that: Also includes: Delay circuits, OR gate circuits, differentiator circuits, and counter circuits; The delay circuit is used to connect to the data ready terminal of the analog-to-digital converter to output a delay signal whose phase follows the data ready signal; One input end of the OR gate circuit is connected to the output end of the delay circuit, the other input end is grounded, and the output end is connected to the input end of the differential circuit; The output end of the differential circuit is connected to the reset pulse signal end of the counter circuit to generate a reset pulse signal for triggering the reset of the counter circuit according to the voltage stabilization signal output by the OR gate circuit; The clock input end of the counter circuit is used to connect to the clock signal end of the analog-to-digital converter, and the output end of the counter circuit is used to connect to the chip select signal end of the processor.

7. The gateway electric energy meter according to claim 6, characterized in that: The delay circuit is an RC integration circuit.

8. The gateway electric energy meter according to claim 6, characterized in that: The OR gate circuit includes an OR gate chip 74HC1G; the counter circuit includes a counter chip 74HC4040D.

9. The gateway electric energy meter according to claim 6, characterized in that: The differential circuit is an RC differential circuit.

10. The gateway electric energy meter according to any one of claims 6 to 9, characterized in that: The analog-to-digital converter collects data at a sampling frequency of 32 kHz; the data transmission rate is 16 MHz.

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