Micro-led device preparation method, micro-led device and display device

Abstract

The present disclosure provides a micro-LED device preparation method, a micro-LED device and a display device. The method comprises: providing a micro-LED epitaxial wafer, the micro-LED epitaxial wafer comprising a first semiconductor layer, a multi-quantum well structure and a second semiconductor layer in sequence from bottom to top; etching the micro-LED epitaxial wafer from the second semiconductor layer until the first semiconductor layer is exposed, and performing surface roughening treatment on the exposed first semiconductor layer to form a roughened surface, thereby obtaining a mesa structure comprising an array of bosses; disposing a first passivation layer, a first metal layer and a second metal layer on the mesa structure, so that the first metal layer is disposed on the second semiconductor layer on the boss in the array of bosses through the first passivation layer, and the second metal layer is disposed on the exposed first semiconductor layer through the first passivation layer, thereby obtaining the micro-LED device.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of semiconductor LEDs, and in particular, to a micro-LED device preparation method, a micro-LED device, and a display device. BACKGROUND

[0002] With the continuous pursuit of display technology, display technology gradually develops in the direction of small size and high resolution, and Micro LED is a representative of miniaturized display technology. Micro LED technology is a three-in-one technology of miniaturization, matrix, and thin film of LED chips, and the size of the pixel points is less than 50 μm. However, there are still some problems in the preparation and structure of Micro LED, which is difficult to meet the increasingly stringent light extraction efficiency requirements brought by pixel miniaturization. SUMMARY

[0003] The scheme of the present disclosure provides a micro-LED device preparation method, a micro-LED device, and a display device.

[0004] According to an aspect of an embodiment of the present disclosure, a micro-LED device preparation method is provided. The method comprises: providing a micro-LED epitaxial wafer, the micro-LED epitaxial wafer comprising a first semiconductor layer, a multi-quantum well structure, and a second semiconductor layer in order from bottom to top; etching the micro-LED epitaxial wafer from the second semiconductor layer until the first semiconductor layer is exposed, and performing surface roughening treatment on the exposed first semiconductor layer to form a roughened surface, to obtain a mesa structure comprising an array of bosses; disposing a first passivation layer, a first metal layer, and a second metal layer on the mesa structure, so that the first metal layer is disposed on the second semiconductor layer on the bosses in the array of bosses through the first passivation layer, and the second metal layer is disposed on the exposed first semiconductor layer through the first passivation layer, to obtain the micro-LED device.

[0005] Further, etching the micro-LED epitaxial wafer from the second semiconductor layer until the first semiconductor layer is exposed, and performing surface roughening treatment on the exposed first semiconductor layer to form a roughened surface to obtain a mesa structure comprising an array of bosses comprises: etching the micro-LED epitaxial wafer from the second semiconductor layer until the first semiconductor layer is exposed, and continuing to etch the exposed first semiconductor layer to form a roughened surface of the first semiconductor layer, wherein the roughened surface is between every two adjacent bosses in the array of bosses and at the periphery of the array of bosses and comprises a triangular protruding portion.

[0006] Further, after etching the micro-LED epitaxial wafer starting from the second semiconductor layer until the first semiconductor layer is exposed, and roughening the exposed first semiconductor layer to form a roughened surface to obtain a mesa structure including a boss array, the method further includes: setting a second passivation layer on the mesa structure, wherein the second passivation layer includes a first contact hole that exposes a predetermined exposed portion of the first semiconductor layer; and setting a conductive layer at least on the predetermined exposed portion of the exposed first semiconductor layer.

[0007] Furthermore, a second passivation layer is provided on the mesa structure, wherein the second passivation layer includes a first contact hole, and the first contact hole exposes a predetermined exposed portion of the first semiconductor layer. This includes: providing a second passivation layer of predetermined thickness along the contour of the mesa structure on the mesa structure, and opening a first contact hole on the second passivation layer, so that the first contact hole exposes the first semiconductor layer between the bosses in the boss array and the periphery of the boss array, wherein the predetermined thickness is equal to one-quarter of the wavelength of the light emitted by the micro LED unit corresponding to the boss.

[0008] Furthermore, providing a conductive layer at least on the predetermined exposed portion of the exposed first semiconductor layer includes: providing an integral conductive layer on the exposed first semiconductor layer and on a second passivation layer on each side of the boss array.

[0009] Furthermore, setting a first passivation layer on the platform structure includes: setting a first passivation layer on the platform structure such that an isolation gap is formed between every two adjacent protrusions of the protrusion array and in the first passivation layer around the protrusion array.

[0010] Further, the first passivation layer is disposed on the platform structure, such that an isolation gap is formed between every two adjacent bosses of the boss array and in the first passivation layer around the boss array, including: depositing the first passivation layer on the platform structure, and controlling the deposition rate of the first passivation layer at the top corner of the boss to form an isolation gap between every two adjacent bosses of the boss array and in the first passivation layer around the boss array.

[0011] Further, the first passivation layer, the first metal layer and the second metal layer are arranged on the mesa structure, so that the first metal layer is arranged on the second semiconductor layer on the pinnacles in the array of pinnacles through the first passivation layer, and the second metal layer is arranged on the exposed first semiconductor layer through the first passivation layer, to obtain the micro-LED device, comprising: arranging the first passivation layer, the first metal layer and the second metal layer on the mesa structure provided with the second passivation layer and the conductive layer, so that the first metal layer is arranged on the second semiconductor layer on the pinnacles in the array of pinnacles through the first passivation layer and the second passivation layer, and the second metal layer is arranged on the conductive layer through the first passivation layer, to obtain the micro-LED device.

[0012] Further, the first passivation layer, the first metal layer and the second metal layer are arranged on the mesa structure provided with the second passivation layer and the conductive layer, so that the first metal layer is arranged on the second semiconductor layer on the pinnacles in the array of pinnacles through the first passivation layer and the second passivation layer, and the second metal layer is arranged on the conductive layer through the first passivation layer, to obtain the micro-LED device, comprising: arranging the first passivation layer on the mesa structure provided with the second passivation layer and the conductive layer, and opening the second contact hole array corresponding to the array of pinnacles and a third contact hole from the first passivation layer, so that each second contact hole in the second contact hole array exposes a part of the second semiconductor layer on the corresponding pinnacles, and the third contact hole exposes a part of the conductive layer; arranging the first metal layer on the exposed part of the second semiconductor layer, and arranging the second metal layer on the exposed part of the conductive layer, to obtain the micro-LED device.

[0013] Further, the first passivation layer, the first metal layer and the second metal layer are arranged on the mesa structure provided with the second passivation layer and the conductive layer, so that the first metal layer is arranged on the second semiconductor layer on the pinnacles in the array of pinnacles through the first passivation layer and the second passivation layer, and the second metal layer is arranged on the conductive layer through the first passivation layer, to obtain the micro-LED device, comprising: arranging the first passivation layer on the mesa structure provided with the second passivation layer and the conductive layer, and opening the second contact hole array corresponding to the array of pinnacles and a third contact hole from the first passivation layer, so that each second contact hole in the second contact hole array exposes a part of the second semiconductor layer on the corresponding pinnacles, and the third contact hole exposes a part of the conductive layer; arranging the first metal layer on the exposed part of the second semiconductor layer, and arranging the second metal layer on the exposed part of the conductive layer, to obtain the micro-LED device.

[0014] Further, the surface of the first metal layer and the surface of the second metal layer are flush with the flat surface of the first passivation layer.

[0015] Further, the micro LED device includes a driving substrate, after a first metal layer is disposed on the exposed part of the second semiconductor layer and a second metal layer is disposed on the exposed part of the conductive layer, the method further includes: bonding the first metal layer and the second metal layer with the driving substrate.

[0016] Further, the micro LED epitaxial wafer further includes a substrate and a third semiconductor layer, the substrate is located on a side of the first semiconductor layer opposite to the multi-quantum well structure, the third semiconductor layer is located between the substrate and the first semiconductor layer, the driving substrate includes a first metal block and a second metal block, a surface of the first metal block and a surface of the second metal block are flush with a surface of the driving substrate, bonding the first metal layer and the second metal layer with the driving substrate includes: bonding the first metal layer with the first metal block, and bonding the second metal layer with the second metal block; removing the substrate and the third semiconductor layer

[0017] According to another aspect of the present disclosure, a micro LED device is also provided. The micro LED device includes a mesa structure, the mesa structure includes a plurality of protrusions and an exposed first semiconductor layer, each protrusion in the plurality of protrusions includes, from bottom to top, a first semiconductor layer, a multi-quantum well structure, and a second semiconductor layer in sequence, the exposed first semiconductor layer includes a roughened surface, and the micro LED device further includes: a first passivation layer disposed on the mesa structure; a first metal layer disposed on the second semiconductor layer on the protrusions in the plurality of protrusions through the first passivation layer, and a second metal layer disposed on the exposed first semiconductor layer through the first passivation layer.

[0018] Further, the roughened surface is between every two adjacent protrusions in the plurality of protrusions and at the periphery of the plurality of protrusions and includes triangular protrusions.

[0019] Further, the micro LED device further includes: a second passivation layer disposed on the mesa structure and including a first contact hole exposing a preset exposed part of the first semiconductor layer; and a conductive layer disposed at least on the preset exposed part of the exposed first semiconductor layer.

[0020] Further, the second passivation layer is disposed along the profile of the protrusions in the mesa structure and has a predetermined thickness, and the first contact hole exposes the first semiconductor layer between the protrusions in the plurality of protrusions and at the periphery of the plurality of protrusions, wherein the predetermined thickness is equal to one fourth of the wavelength of the light emitted by the micro LED unit corresponding to the protrusions.

[0021] Further, the conductive layer is disposed integrally on the exposed first semiconductor layer and on the second passivation layer on each side of the posts of the post array, the conductive layer comprising a third metal layer.

[0022] Further, the first passivation layer comprises isolation gaps between each two adjacent posts of the post array and at the periphery of the post array.

[0023] Further, the isolation gaps are formed by controlling a deposition rate of the first passivation layer at the post top corner locations.

[0024] Further, the first metal layer is disposed on the second semiconductor layer on the posts in the post array through the first passivation layer and the second passivation layer, and the second metal layer is disposed on the conductive layer through the first passivation layer.

[0025] Further, the first passivation layer comprises a first sub-contact hole array corresponding to the post array and a third contact hole, the second passivation layer comprises a second sub-contact hole array aligned with the first sub-contact hole array, the first sub-contact hole array and the second sub-contact hole array constitute a second contact hole array, each second contact hole in the second contact hole array exposes a partial second semiconductor layer on a corresponding post, the third contact hole exposes a partial conductive layer, the first metal layer is disposed on the exposed partial second semiconductor layer, and the second metal layer is disposed on the exposed partial conductive layer.

[0026] Further, the first passivation layer has a flat surface, and each of the third contact holes exposes a partial conductive layer on the first semiconductor layer at the periphery of the post array.

[0027] Further, a surface of the first metal layer and a surface of the second metal layer are flush with the flat surface of the first passivation layer.

[0028] Further, the micro-LED device further comprises a driving substrate, the first metal layer and the second metal layer are bonded to the driving substrate.

[0029] Further, the driving substrate comprises a first metal block and a second metal block, a surface of the first metal block and a surface of the second metal block are flush with a surface of the driving substrate, and the first metal layer is bonded to the first metal block, and the second metal layer is bonded to the second metal block.

[0030] Further, the first semiconductor layer is an n-GaN layer, and the second semiconductor layer is a p-GaN layer.

[0031] According to a further aspect of the embodiments of the present disclosure, a display device is also provided. The display device comprises the micro-LED device described above.

[0032] By applying the technical solution of the present disclosure, the first semiconductor layer can be exposed by etching the micro-LED epitaxial wafer, and the exposed first semiconductor layer can be subjected to surface roughening treatment to form a roughened surface, so as to obtain a mesa structure comprising a mesa array. The mesa array in the mesa structure corresponds to the micro-LED light emitting unit array in the micro-LED chip, the exposed first semiconductor layer corresponds to the part other than the first semiconductor layer in the mesa array, the roughened surface is formed on the exposed first semiconductor layer, and the surface of the first semiconductor layer on the side facing the substrate is the light output surface of the micro-LED light emitting unit array. Therefore, when the micro-LED light emitting unit emits light, part of the light will be totally reflected when reaching the light output surface, so as to be reflected in the first semiconductor layer towards the roughened surface beside the micro-LED light emitting unit. When the reflected light reaches the roughened surface, the roughened surface will reflect the light and correct the reflection angle of the light, so that the light can be reflected towards the light output direction of the micro-LED light emitting unit, thereby increasing the light output efficiency and reducing the optical crosstalk to the adjacent micro-LED light emitting unit. BRIEF DESCRIPTION OF DRAWINGS

[0033] The above and other objects, features and advantages of the exemplary embodiments of the present disclosure will be more apparent from the following detailed description taken in conjunction with the accompanying drawings, in which several embodiments of the present disclosure are shown by way of example, and wherein like or corresponding elements refer to like or corresponding parts throughout the several drawings, in which:

[0034] Figure 1 is a flow chart illustrating a micro-LED device preparation method according to one embodiment of the present disclosure;

[0035] Figures 2-12 is a preparation process flow diagram illustrating a micro-LED device preparation method according to one embodiment of the present disclosure. DETAILED DESCRIPTION

[0036] It should be noted that the embodiments in the present application and the features in the embodiments can be combined with each other without conflict. The present disclosure will be described in detail below with reference to the accompanying drawings and in conjunction with the embodiments.

[0037] It should be noted that the following detailed description is exemplary and is intended to provide further explanation of the present application. Unless otherwise specified, all technical and scientific terms used herein have the same meaning as generally understood by those skilled in the art to which the present application belongs.

[0038] For purposes of the description hereinafter, spatially relative terms, such as "above", "below", "up", "down", "top", "bottom", and the like, can be used for ease of describing the illustrated embodiments. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientations depicted in the figures. For example, if a device described is turned over, then a portion that was above another portion would now be below that portion. Thus, the exemplary term "above" can encompass both a position that is above and a position that is below. The device can be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly. The terms "first", "second", "third", "fourth", etc. can be used to describe various elements in the example embodiments. These designations are not intended to limit the scope of the example embodiments, but are used to distinguish one element from another. The terms "first", "second", "third", "fourth", etc. can be used to describe various elements in the example embodiments. These designations are not intended to limit the scope of the example embodiments, but are used to distinguish one element from another.

[0039] Example embodiments consistent with the present disclosure will now be described in more detail with reference to the drawings. These example embodiments may, however, be implemented in many different forms and should not be construed as limited to the implementations set forth herein. Rather, these example embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the example embodiments to those skilled in the art, and the example embodiments will be readily understood by those skilled in the art from the disclosure hereat with the drawings, in which the thicknesses of layers and regions are exaggerated for clarity, and where the same reference numerals are used throughout several drawings to designate the same elements, descriptions thereof will be omitted.

[0040] In the related art, in a micro LED chip, light emitted by each micro LED light emitting unit in a micro LED light emitting unit array is emitted through a first semiconductor layer, e.g., an n-GaN layer, of the micro LED light emitting unit, specifically, through the first semiconductor layer and through a light exit surface of the first semiconductor layer. However, since part of the light is totally reflected when reaching the light exit surface, the light is reflected toward an opposite surface of the first semiconductor layer adjacent to the light exit surface. The opposite surface causes the light incident thereon to be reflected toward the surface of the first semiconductor layer on the same surface as the light exit surface away from the micro LED light emitting unit that emits the light, and this is repeated to form part of the light propagating in a lateral direction in the first semiconductor layer, so that part of the light emitted by the micro LED light emitting unit is not emitted from the light exit surface, thereby resulting in a low light emission efficiency, and the lateral propagation of part of the light in the first semiconductor layer causes the light to enter the first semiconductor layer corresponding to an adjacent micro LED light emitting unit, thereby forming light crosstalk.

[0041] The present disclosure provides a micro LED device manufacturing method. Referring to Figures 1-12 , Figure 1 is a flowchart illustrating a micro LED device manufacturing method according to an embodiment of the present disclosure;Figures 2-12 is a preparation process flow diagram illustrating a micro-LED device preparation method according to one embodiment of the present disclosure.

[0042] As shown in Figure 1 , the micro-LED device preparation method comprises the following steps S101-S103.

[0043] Step S101: providing a micro-LED epitaxial wafer, the micro-LED epitaxial wafer comprising, in order from bottom to top, a first semiconductor layer, a multi-quantum well structure, and a second semiconductor layer.

[0044] Step S102: etching the micro-LED epitaxial wafer from the second semiconductor layer until the first semiconductor layer is exposed, and performing surface roughening treatment on the exposed first semiconductor layer to form a roughened surface, thereby obtaining a mesa structure comprising an array of protrusions.

[0045] Step S103: disposing a first passivation layer, a first metal layer, and a second metal layer on the mesa structure, such that the first metal layer is disposed on the second semiconductor layer on the protrusions in the array of protrusions through the first passivation layer, and the second metal layer is disposed on the exposed first semiconductor layer through the first passivation layer, thereby obtaining the micro-LED device.

[0046] According to the technical solution, the first semiconductor layer can be exposed by etching the micro-LED epitaxial wafer, and the roughened surface can be formed by performing surface roughening treatment on the exposed first semiconductor layer, thereby obtaining the mesa structure comprising the array of protrusions. The array of protrusions in the mesa structure corresponds to the array of micro-LED light emitting units in the micro-LED chip, the exposed first semiconductor layer corresponds to the part other than the first semiconductor layer in the array of protrusions, the roughened surface is formed on the exposed first semiconductor layer, and the surface of the first semiconductor layer on the side facing the substrate is the light output surface of the array of micro-LED light emitting units. Therefore, when the micro-LED light emitting unit emits light, part of the light will be totally reflected when reaching the light output surface, thereby being reflected towards the roughened surface next to the micro-LED light emitting unit in the first semiconductor layer. When the reflected light reaches the roughened surface, the roughened surface will reflect the light and correct the reflection angle of part of the light, so that the part of the light can be reflected towards the light output direction of the micro-LED light emitting unit, thereby increasing the light output efficiency and reducing the optical crosstalk to the adjacent micro-LED light emitting unit.

[0047] In step S101, a micro-LED epitaxial wafer can be provided, the micro-LED epitaxial wafer comprising, in order from bottom to top, a first semiconductor layer, a multi-quantum well structure, and a second semiconductor layer.

[0048] According to an embodiment of the present disclosure, to prepare a micro-LED device, a micro-LED epitaxial wafer can be obtained first, which can be prepared in advance or in the micro-LED device preparation method of the present disclosure.

[0049] Referring to Figures 2-12 wherein Figure 2 A side view of a micro-LED epitaxial wafer 10 according to an embodiment of the present disclosure is shown. As shown, the micro-LED epitaxial wafer 10 includes, in order from bottom to top, a first semiconductor layer 103, a multi-quantum well structure 104, and a second semiconductor layer 105. As shown, the micro-LED epitaxial wafer 10 can further include a substrate 101 on a side of the first semiconductor layer 103 opposite the multi-quantum well structure 104, and a third semiconductor layer 102 between the substrate 101 and the first semiconductor layer 103. Figure 2 Figure 2 According to an embodiment of the present disclosure, the substrate 101 can include a transparent substrate, which can include a sapphire substrate, the first semiconductor layer 103 can be an n-GaN layer, the second semiconductor layer 105 can be a p-GaN layer, and the third semiconductor layer 102 can be a u-GaN layer. Of course, the above substrate and semiconductor layers can also be any other suitable substrate and semiconductor layers, which are not limited herein.

[0050] In step S102, the micro-LED epitaxial wafer can be etched from the second semiconductor layer until the first semiconductor layer is exposed, and the exposed first semiconductor layer can be subjected to a surface roughening treatment to form a roughened surface to obtain a mesa structure including an array of protrusions.

[0051] According to an embodiment of the present disclosure, after obtaining a micro-LED epitaxial wafer, it can be etched and the first semiconductor surface exposed by etching can be subjected to a roughening treatment to obtain a mesa structure including an array of protrusions. It is worth noting that, according to requirements, the array of protrusions can include, for example, tens to millions of protrusions, for example, when the micro-LED device is used in a lighting device, the number of protrusions can be tens, and when the micro-LED device is used in a display device, the number of protrusions can be hundreds of thousands or even millions.

[0052] According to an embodiment of the present disclosure, after obtaining a micro-LED epitaxial wafer, it can be etched and the first semiconductor surface exposed by etching can be subjected to a roughening treatment to obtain a mesa structure including an array of protrusions. It is worth noting that, according to requirements, the array of protrusions can include, for example, tens to millions of protrusions, for example, when the micro-LED device is used in a lighting device, the number of protrusions can be tens, and when the micro-LED device is used in a display device, the number of protrusions can be hundreds of thousands or even millions.

[0053] ​Further, etching the micro-LED epitaxial wafer from the second semiconductor layer until the first semiconductor layer is exposed, and continuing to etch the exposed first semiconductor layer to form a roughened surface of the first semiconductor layer, wherein the roughened surface is between every two adjacent posts in the array of posts and peripherally of the array of posts and comprises triangular protrusions.

[0054] Further, with reference to Figures 2-12 wherein Figure 3 A side view of a mesa structure 20 etched out of a micro-LED epitaxial wafer is shown. Specifically, a silicon oxide layer can first be deposited as a hard mask on the micro-LED epitaxial wafer by Plasma Enhanced Chemical Vapor Deposition (PECVD) in a PECVD apparatus with a mixture of silane (SiH4), nitrous oxide (N2O) and nitrogen (N2) gas. A pattern of the array of posts is then photolithographically defined by photoresist. Subsequently, the photolithographically defined pattern is etched into the silicon oxide layer by Inductively Coupled Plasma (ICP), wherein the silicon oxide layer is dry etched in an ICP etching instrument with a mixture of sulfur hexafluoride (SF6) and trifluoromethane (CHF3) and oxygen (O2) gas. After the photoresist is removed using acetone, the pattern of the silicon oxide layer is etched into the surface layer of the first semiconductor layer 103 by ICP using a mixture of chlorine (CL2), boron trichloride (BCl3) and argon (Ar) gas. The exposed first semiconductor layer 103 is then etched by adjusting the etching bias and gas composition to obtain a roughened surface of the first semiconductor layer 103 by a micro-trenching effect, which roughened surface comprises, for example, triangular protrusions 1031 as shown in Figure 3 The silicon oxide layer as a hard mask is then removed using a buffered oxide etch (BOE), thereby forming a mesa structure 20 as shown in Figure 3 The mesa structure 20 comprises an array of posts 21 with the triangular protrusions 1031 between every two adjacent posts 21 in the array of posts and peripherally of the array of posts.

[0055] It is noted that Figure 3 The number of posts 21 comprised by the array of posts in

[0056] like Figure 3 As shown, the roughened surface of the first semiconductor layer 103 includes only one triangular protrusion 1031 between every two adjacent protrusions 21 in the protrusion array, and only one triangular protrusion 1031 on each side of the periphery of the protrusion array. According to another embodiment, the roughened surface may include multiple smaller protrusions between every two adjacent protrusions 21 in the protrusion array and on each side of the periphery of the protrusion array. These protrusions may be, for example, triangular or other shapes, and the multiple smaller protrusions may form a serrated shape. After exposing the first semiconductor layer by etching as described above, multiple protrusions, such as triangular ones, can be formed by etching the surface of the exposed first semiconductor layer with a potassium hydroxide solution, thereby forming the roughened surface of the first semiconductor layer.

[0057] It is worth noting that, since the protrusion array corresponds to the micro LED light-emitting unit array, the lateral propagation of light emitted by the micro LED light-emitting unit in the first semiconductor layer 103 is disrupted by the rough surface of, for example, the triangular protrusion 1031 on the first semiconductor layer, thereby improving the light extraction efficiency and reducing light crosstalk.

[0058] In step S103, a first passivation layer, a first metal layer, and a second metal layer can be disposed on the mesa structure, such that the first metal layer passes through the first passivation layer and is disposed on the second semiconductor layer on the protrusion in the protrusion array, and the second metal layer passes through the first passivation layer and is disposed on the exposed first semiconductor layer, thereby obtaining the micro LED device.

[0059] According to the embodiments of this disclosure, a first passivation layer, a first metal layer, and a second metal layer can be disposed on the mesa structure in step S102, thus completing the fabrication of the micro LED device.

[0060] According to an embodiment of the present disclosure, providing a first passivation layer on the platform structure may include: providing a first passivation layer on the platform structure such that an isolation gap is formed between every two adjacent protrusions of the protrusion array and in the first passivation layer surrounding the protrusion array.

[0061] Further, the first passivation layer is disposed on the platform structure, such that an isolation gap is formed between every two adjacent bosses of the boss array and in the first passivation layer around the boss array, including: depositing the first passivation layer on the platform structure, and controlling the deposition rate of the first passivation layer at the top corner of the boss to form an isolation gap between every two adjacent bosses of the boss array and in the first passivation layer around the boss array.

[0062] According to an embodiment of the present disclosure, before the first passivation layer, the first metal layer and the second metal layer are disposed on the mesa structure, the method can further comprise: disposing a second passivation layer on the mesa structure, wherein the second passivation layer comprises a first contact hole exposing a preset exposed portion of the first semiconductor layer; and disposing a conductive layer on at least the preset exposed portion of the exposed first semiconductor layer. In this embodiment, the second passivation layer and the conductive layer can be disposed on the mesa structure in step S102 first.

[0063] Further, the disposing of the second passivation layer on the mesa structure, wherein the second passivation layer comprises a first contact hole exposing a preset exposed portion of the first semiconductor layer can comprise: disposing a second passivation layer with a predetermined thickness on the mesa structure along the profile of the mesa structure, and opening a first contact hole on the second passivation layer to expose the first semiconductor layer between the bosses in the boss array and the periphery of the boss array, wherein the predetermined thickness is equal to one quarter of the wavelength of the light emitted by the micro-LED unit corresponding to the boss. Therefore, the preset exposed portion can correspond to the positions between the bosses in the boss array and the periphery of the boss array.

[0064] Further, the disposing of the conductive layer on at least the preset exposed portion of the exposed first semiconductor layer can comprise: disposing a conductive layer integrally connected on the exposed first semiconductor layer and the second passivation layer on each side of the boss of the boss array.

[0065] Since the second passivation layer and the conductive layer are disposed on the mesa structure first, the disposing of the first passivation layer, the first metal layer and the second metal layer on the mesa structure, so that the first metal layer is disposed on the second semiconductor layer on the boss in the boss array through the first passivation layer, and the second metal layer is disposed on the conductive layer through the first passivation layer, to obtain the micro-LED device can comprise: disposing a first passivation layer, a first metal layer and a second metal layer on the mesa structure provided with the second passivation layer and the conductive layer, so that the first metal layer is disposed on the second semiconductor layer on the boss in the boss array through the first passivation layer and the second passivation layer, and the second metal layer is disposed on the conductive layer through the first passivation layer, to obtain the micro-LED device.

[0066] Further, the first passivation layer, the first metal layer and the second metal layer are arranged on the mesa structure provided with the second passivation layer and the conductive layer, so that the first metal layer is arranged on the second semiconductor layer on the pinnacles in the array of pinnacles through the first passivation layer and the second passivation layer, and the second metal layer is arranged on the conductive layer through the first passivation layer, and the micro-LED device can comprise: arranging the first passivation layer on the mesa structure provided with the second passivation layer and the conductive layer, and opening the second contact hole array corresponding to the array of pinnacles and a third contact hole from the first passivation layer, so that each second contact hole in the second contact hole array exposes a part of the second semiconductor layer on the corresponding pinnacles, and the third contact hole exposes a part of the conductive layer; arranging the first metal layer on the exposed part of the second semiconductor layer, and arranging the second metal layer on the exposed part of the conductive layer, thereby obtaining the micro-LED device.

[0067] Specifically, the first passivation layer is arranged on the mesa structure provided with the second passivation layer and the conductive layer, and the second contact hole array corresponding to the array of pinnacles and a third contact hole are opened from the second passivation layer, so that each second contact hole in the second contact hole array exposes a part of the second semiconductor layer on the corresponding pinnacles, and the third contact hole exposes a part of the conductive layer, which comprises: depositing the first passivation layer on the mesa structure provided with the second passivation layer and the conductive layer; performing grinding treatment on the first passivation layer, so that the surface of the first passivation layer is flat; opening the second contact hole array corresponding to the array of pinnacles and a third contact hole from the flat surface of the first passivation layer, so that each second contact hole in the second contact hole array exposes a part of the second semiconductor layer on the corresponding pinnacles, and the third contact hole exposes a part of the conductive layer on the first semiconductor layer at the periphery of the array of pinnacles. The surface of the first metal layer and the surface of the second metal layer can be flush with the flat surface of the first passivation layer.

[0068] Referring to Figures 2-12 , wherein Figure 4 A side view cross-sectional view of the second passivation layer 106 arranged on the mesa structure 20 is shown. As Figure 4 indicated, the second passivation layer 106 can be deposited on the mesa structure 20 by atomic layer deposition (ALD), so that the second passivation layer 106 is arranged along the contour of the mesa structure 20, the material of the second passivation layer 106 can be aluminum oxide or silicon dioxide for example, and the thickness of the second passivation layer 106 is equal to one quarter of the wavelength of the light emitted by the micro-LED unit corresponding to the pinnacles 21, thereby improving the reflectivity for the light emitted by the micro-LED unit.

[0069] Referring to Figures 2-12 , wherein Figure 5A side view cross-sectional view of the first contact hole 1061 opened on the second passivation layer 106 is shown. As shown in Figure 5 , a pattern of the first contact hole can be photoetched on the second passivation layer 106, and the first contact hole 1061 can be etched by an inductively coupled plasma (ICP) etching method through a mixed gas of SF6, CHF3 and O2, and a structure as shown in Figure 5 is formed after removing the photoresist. As shown in Figure 5 , the above-mentioned preset exposed portion corresponds to the first semiconductor layer between the protrusions 21 in the protrusion array and the periphery of the protrusion array, and thus the first contact hole 1061 exposes the first semiconductor layer between the protrusions 21 in the protrusion array and the periphery of the protrusion array, i.e. the second passivation layer 106 between the protrusions 21 in the protrusion array and the periphery of the protrusion array is removed. It is worth noting that the preset exposed portion of the first semiconductor layer can be determined according to the actual preparation scheme, which is not limited here.

[0070] Referring to Figures 2-12 , wherein Figure 6 , a conductive layer 107 integrated as one is arranged on the exposed first semiconductor layer 103 and on the second passivation layer 106 on the side of each protrusion 21 of the protrusion array. Specifically, as shown in Figure 6 , a pattern of the conductive layer can be photoetched by using a photoresist, and then the conductive layer 107 can be deposited by an electron beam evaporation method, and finally the photoresist and the excess material can be removed by a lift-off process using acetone or a stripping solution, to obtain a first intermediate structure 30 as shown in Figure 6 , i.e. a mesa structure provided with the second passivation layer 106 and the conductive layer 107. As described above, the second passivation layer 106 between the protrusions 21 in the protrusion array and the periphery of the protrusion array is removed, thereby exposing the preset exposed portion, and thus the second passivation layer on other parts except the protrusion array is removed in fact, which makes the preset exposed portion of the first semiconductor layer integrated as one, and thus the conductive layer arranged on the preset exposed portion is integrated as one, and because the conductive layer will act as a cathode layer in the case where the first semiconductor layer 103 is an n-GaN layer for example, the integrated cathode layer can form a common cathode structure. In addition, the conductive layer can include a third metal layer, and the material of the third metal layer can be any applicable material such as copper for example, and the conductive layer such as copper on the side of each protrusion of the protrusion array can reflect the light emitted by the micro-LED light emitting unit towards the protrusion side back to the micro-LED light emitting unit, thereby reducing the light cross talk between the micro-LED light emitting units. In addition, the conductive layer is arranged on the preset exposed portion of the first semiconductor layer and on the side of each protrusion of the protrusion array at the same time, to form the conductive layer integrated as one, which can simplify the preparation process.

[0071] It is worth noting that in another embodiment, the number of first contact holes opened on the second passivation layer can correspond to the number of the protrusions, and the preset exposed portions of the first semiconductor layer exposed by the first contact hole array can not be connected together, for example, in the case of the first semiconductor layer 103 being an n-GaN layer, the conductive layer will serve as a cathode layer, and therefore the cathode layer provided on the preset exposed portion is not connected together, that is, not a common cathode structure, thereby making each protrusion have a corresponding cathode layer.

[0072] Referring to Figures 2-12 wherein Figure 7 A side view cross-sectional view of the first passivation layer 108 provided on the first intermediate structure 30 is shown. As Figure 7 shown, the first passivation layer 108, for example, a silicon dioxide layer, can be first deposited on the first intermediate structure 30 using a plasma enhanced chemical vapor deposition method in a plasma enhanced chemical vapor deposition device. During the deposition of the first passivation layer 108, different deposition angles can be used according to different positions, so that the deposition rate of the first intermediate structure 30 at positions corresponding to the upper left and right corners of the protrusions 21 is faster, so that during the formation of the first passivation layer 108, the silicon dioxide layer deposited at positions corresponding to the adjacent corners of the adjacent two protrusions 21 will preferentially contact and close, and therefore an isolation gap 1081 will be formed between the two adjacent protrusions 21. In addition, next to the outermost protrusions in the array of protrusions, an isolation gap 1081 will also be formed next to the outermost protrusions due to the faster deposition rate at positions corresponding to the corners of the outermost protrusions. Thus, an isolation gap 1081 is formed in the first passivation layer 108 between every two protrusions 21 in the array of protrusions and at the periphery of the array of protrusions. Since the refractive indices of the first passivation layer 108 and the isolation gap 1081 differ greatly, a refractive index discontinuity can be formed between the first passivation layer 108 and the isolation gap 1081, thereby breaking the propagation of light between the two protrusions and further reducing the light crosstalk between the two micro-LED light emitting units.

[0073] Referring to Figures 2-12 wherein Figure 8 A side view cross-sectional view of the first passivation layer 108 after polishing to have a flat surface is shown. As Figure 8 shown, the first passivation layer 108 can be polished to have a flat surface by a chemical mechanical polishing method (CMP) using physical friction and chemical reaction. This method can obtain a very high flatness. The mechanical friction is mainly achieved by the polishing equipment and the abrasive particles (such as silicon oxide particles) added to the polishing liquid, and the smaller the particle size of the silicon oxide particles, the smaller the surface roughness obtained. The chemical reaction is mainly achieved by the solvent components in the polishing liquid, such as citric acid, hydrogen peroxide, etc. The polishing degree can be monitored in real time by the end point detection device of the polishing equipment.

[0074] Referring to Figures 2-12 wherein Figure 9 a side view cross-sectional view of the second contact holes 1082 and the third contact holes 1083 being opened from the first passivation layer 108 with a flat surface is shown. As Figure 9 shown, a pattern of the second contact holes 1082 and the third contact holes 1083 can be photoresist lithographed on the first passivation layer 108, and then etched by SF6, CHF3 and O2 mixed gas by an inductively coupled plasma (ICP) etching method, and after removing the photoresist, a structure as Figure 9 shown is formed. Wherein each of the second contact holes 1082 in the second contact hole array exposes a portion of the second semiconductor layer 105 on the corresponding boss, and each of the third contact holes 1083 exposes a portion of the conductive layer 107 on the first semiconductor layer 103 at the periphery of the boss array.

[0075] Referring to Figures 2-12 wherein Figure 10 a side view cross-sectional view of the first metal layer 1091 disposed on the exposed portion of the second semiconductor layer, and the second metal layer 1092 disposed on the exposed portion of the conductive layer is shown. Specifically, as Figure 10 shown, a pattern of the first metal layer 1091 and the second metal layer 1092 can be photoresist lithographed, and then the first metal layer 1091 and the second metal layer 1092 are deposited by an electron beam evaporation method, i.e. a TaN layer with a thickness of 100 nm, a Ta layer with a thickness of 100 nm and a Cu layer with a thickness of 0.5 um are sequentially deposited, and the photoresist and the excess metal are removed by a lift-off process using acetone or a stripping solution, and finally the deposited first metal layer and the second metal layer are polished by a chemical mechanical polishing method (CMP) so that the surface of the first metal layer 1091 and the surface of the second metal layer 1092 are flush with the flat surface of the first passivation layer 108, and a micro-LED chip 1 as Figure 10 shown is obtained.

[0076] According to embodiments of the present disclosure, the micro-LED device further comprises a driving substrate, and after the first metal layer disposed on the exposed portion of the second semiconductor layer and the second metal layer disposed on the exposed portion of the conductive layer, the method can further comprise: bonding the first metal layer and the second metal layer with the driving substrate.

[0077] Furthermore, the micro-LED epitaxial wafer further includes a substrate and a third semiconductor layer. The substrate is located on the side of the first semiconductor layer opposite to the multi-quantum-well structure, and the third semiconductor layer is located between the substrate and the first semiconductor layer. The driving substrate includes a first metal block and a second metal block. The surfaces of the first metal block and the second metal block are flush with the surface of the driving substrate. Bonding the first metal layer and the second metal layer to the driving substrate includes: bonding the first metal layer to the first metal block and bonding the second metal layer to the second metal block; and removing the substrate and the third semiconductor layer.

[0078] like Figure 2 As shown, the micro-LED epitaxial wafer 10 may further include a substrate 101 and a third semiconductor layer 102. The substrate 101 is located on the side of the first semiconductor layer 103 opposite to the multi-quantum well structure 104, and the third semiconductor layer 102 is located between the substrate 101 and the first semiconductor layer 103. The substrate 101 may include a transparent substrate, which may include a sapphire substrate. The third semiconductor layer 102 may be a u-GaN layer. Of course, the above-mentioned substrate and third semiconductor layer may be any other suitable substrate and semiconductor layer, which is not limited here.

[0079] Reference Figures 2-12 ,in Figure 11 A side cross-sectional view of the micro-LED chip 1 and the driving substrate 2 bonded together is shown. Specifically, the micro-LED chip 1 can be flip-chip bonded using a flip-chip bonding machine, and the first metal layer 1091 can be bonded to the first metal block 201 of the driving substrate 2, and the second metal layer 1092 can be bonded to the second metal block 202 of the driving substrate 2. Since the surfaces of the first metal layer 1091 and the second metal layer 1092 are flush with the flat surface of the first passivation layer 108, and the surfaces of the first metal block 201 and the second metal block 202 are flush with the surface of the driving substrate 2, the micro-LED chip 1 and the driving substrate 2 are bonded together in a close fit. The bonding pressure and temperature can be adjusted accordingly based on the size of the chip array.

[0080] Reference Figures 2-12 ,in Figure 12 It shows the results of the study on the topic of Figure 11 The diagram shows a side cross-sectional view of the micro-LED device 3 formed after removing the substrate. Specifically, when the substrate 101 is a transparent substrate, such as a sapphire substrate, a laser can be used to irradiate the interface between the third semiconductor layer 102 (e.g., a u-GaN layer) and the first semiconductor layer 103 (e.g., an n-GaN layer) through the sapphire substrate. This causes the interface to partially decompose and melt, thereby detaching the substrate 101 and the third semiconductor layer 102, resulting in the micro-LED device 3 formed after removing the substrate.Figure 12 The structure is as follows. It is worth noting that the substrate 101 can also be any other suitable type, for example, it can be an opaque substrate, in which case the substrate can be removed by a corresponding method.

[0081] As described above, since the surfaces of the first metal layer 1091 and the second metal layer 1092 are flush with the flat surface of the first passivation layer 108, and the surfaces of the first metal block 201 and the second metal block 202 are flush with the surface of the driving substrate 2, the micro LED chip 1 and the driving substrate 2 are bonded together in a close fit. Therefore, there is no need to fill the space between the bonded micro LED chip 1 and the driving substrate 2 with underfill. Furthermore, when removing the substrate by laser, there is no problem of the underfill irradiating with laser causing the underfill to bubble or carbonize, thus affecting the performance of the micro LED device, thereby improving the yield of the micro LED device.

[0082] Furthermore, as described above, a conductive layer 107, such as a third metal layer, is integrally formed on the exposed first semiconductor layer 103 and on the second passivation layer 106 on the side of each boss 21 of the boss array. When the substrate is removed by laser, the integral conductive layer 107, such as the third metal layer, prevents the laser from passing through and reaching the driving substrate 2, thereby preventing damage to the driving substrate by the laser.

[0083] Thus, the fabrication of the micro LED device is complete. Figure 12 The completed micro-LED device 3 is shown.

[0084] This disclosure also provides a micro LED device. This micro LED device can be manufactured using the micro LED device fabrication method described above.

[0085] like Figures 2-12 As shown, the micro LED device 3 includes a mesa structure 20, which includes a boss array and an exposed first semiconductor layer 103. Each boss 21 in the boss array includes, from bottom to top, a first semiconductor layer 103, a multi-quantum well structure 104, and a second semiconductor layer 105. The exposed first semiconductor layer 103 includes a roughened surface. The micro LED device 3 also includes: a first passivation layer 108 disposed on the mesa structure 20; a first metal layer 1091 and a second metal layer 1092. The first metal layer 1091 passes through the first passivation layer 108 and is disposed on the second semiconductor layer 105 on the boss 21 in the boss array, and the second metal layer 1092 passes through the first passivation layer 108 and is disposed on the exposed first semiconductor layer.

[0086] According to an embodiment of the present disclosure, the roughened surface is between every two adjacent bosses 21 in the boss array and on the periphery of the boss array and includes a triangular protrusion 1031.

[0087] According to an embodiment of this disclosure, the micro LED device 3 further includes: a second passivation layer 106 disposed on the mesa structure 20 and including a first contact hole 1061, the first contact hole 1061 exposing a predetermined exposed portion of the first semiconductor layer 103; and a conductive layer 107 disposed at least on the exposed predetermined exposed portion of the first semiconductor layer 103.

[0088] According to an embodiment of the present disclosure, the second passivation layer 106 is disposed along the contour of the boss 21 in the mesa structure 20 and has a predetermined thickness, and the first contact hole 1061 exposes a first semiconductor layer between the bosses 21 in the boss array and around the boss array, wherein the predetermined thickness is equal to one-quarter of the wavelength of the light emitted by the micro LED unit corresponding to the boss 21.

[0089] According to an embodiment of the present disclosure, the conductive layer 107 is integrally disposed on the exposed first semiconductor layer and on the second passivation layer 106 on the side of each boss 21 of the boss array, and the conductive layer 107 includes a third metal layer.

[0090] According to an embodiment of the present disclosure, the first passivation layer 108 includes isolation gaps 1081 between every two adjacent bosses 21 of the boss array and around the periphery of the boss array.

[0091] According to an embodiment of this disclosure, the isolation gap 1081 is formed by controlling the deposition rate of the first passivation layer 108 at the top corner of the boss.

[0092] According to an embodiment of the present disclosure, the first metal layer 1091 is disposed on the second semiconductor layer 105 on the boss 21 in the boss array through the first passivation layer 108 and the second passivation layer 106, and the second metal layer 1092 is disposed on the conductive layer 107 through the first passivation layer 108.

[0093] According to an embodiment of this disclosure, the first passivation layer 108 includes a first sub-contact hole array and a third contact hole 1083 corresponding to the boss array, and the second passivation layer 106 includes a second sub-contact hole array aligned with the first sub-contact hole array. The first sub-contact hole array and the second sub-contact hole array constitute a second contact hole array. Each second contact hole 1082 in the second contact hole array exposes a portion of the second semiconductor layer 105 on the corresponding boss. The third contact hole 1083 exposes a portion of the conductive layer 107. The first metal layer 1091 is disposed on the exposed portion of the second semiconductor layer 105, and the second metal layer 1092 is disposed on the exposed portion of the conductive layer 107.

[0094] According to an embodiment of the present disclosure, the first passivation layer 108 has a flat surface, and each of the third contact holes 1083 exposes a portion of the conductive layer on the first semiconductor layer located on the periphery of the boss array.

[0095] According to an embodiment of this disclosure, the surfaces of the first metal layer 1091 and the second metal layer 1092 are flush with the flat surface of the first passivation layer 108.

[0096] According to an embodiment of this disclosure, the micro LED device 3 further includes a driving substrate 2, wherein the first metal layer 1091 and the second metal layer 1092 are bonded to the driving substrate 2.

[0097] According to an embodiment of the present disclosure, the driving substrate 2 includes a first metal block 201 and a second metal block 202, the surfaces of the first metal block 201 and the second metal block 202 are flush with the surface of the driving substrate 2, and the first metal layer 1091 is bonded to the first metal block 201, and the second metal layer 1092 is bonded to the second metal block 202.

[0098] It is worth noting that any relevant descriptions of the micro-LED device structure in the above-mentioned micro-LED device fabrication method (including but not limited to technical features and their functions, explanations, etc.) can be applied to the micro-LED device disclosed herein.

[0099] This disclosure also provides a display device. The display device includes the aforementioned micro-LED device. This display device can be applied to electronic devices to realize technologies such as Augmented Reality (AR), Virtual Reality (VR), Extended Reality (XR), and Mixed Reality (MR). For example, the display device can be a projection component of an electronic device, such as a projector or a head-up display (HUD); or it can be a display component of an electronic device, such as a smartphone, smartwatch, laptop, tablet, dashcam, navigator, head-mounted device, or any device with a display screen.

[0100] It should be noted that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the exemplary embodiments according to this application. As used herein, the singular form is intended to include the plural form as well, unless the context clearly indicates otherwise. Furthermore, it should be understood that when the terms "comprising" and / or "including" are used in this specification, they indicate the presence of features, steps, operations, devices, components, and / or combinations thereof.

[0101] It should be understood that the phrase "one embodiment" or "an embodiment" throughout the specification means that a specific feature, structure, or characteristic related to the embodiment is included in at least one embodiment of this application. Therefore, "in one embodiment" or "in an embodiment" appearing throughout the specification does not necessarily refer to the same embodiment. Furthermore, these specific features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. It should be understood that in the various embodiments of this application, the sequence numbers of the above steps / processes do not imply a sequential order of execution; the execution order of each step / process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application. Moreover, the above embodiment numbers are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments.

[0102] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of this application described herein can be implemented, for example, in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0103] The above description is merely a preferred embodiment of this disclosure and is not intended to limit this disclosure. Various modifications and variations can be made to this disclosure by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this disclosure should be included within the scope of protection of this disclosure.

Claims

1. A method for fabricating a micro LED device, wherein, The method includes: A micro LED epitaxial wafer is provided, wherein the micro LED epitaxial wafer comprises, from bottom to top, a first semiconductor layer, a multi-quantum-well structure, and a second semiconductor layer; The micro-LED epitaxial wafer is etched starting from the second semiconductor layer until the first semiconductor layer is exposed, and the exposed first semiconductor layer is roughened to form a roughened surface, resulting in a mesa structure including a boss array. A first passivation layer, a first metal layer, and a second metal layer are disposed on the mesa structure, such that the first metal layer passes through the first passivation layer and is disposed on a second semiconductor layer on a protrusion in the protrusion array, and the second metal layer passes through the first passivation layer and is disposed on an exposed first semiconductor layer, thereby obtaining the micro LED device. The first passivation layer on the mesa structure includes: the first passivation layer is disposed on the mesa structure such that an isolation gap is formed between every two adjacent protrusions in the protrusion array and in the first passivation layer around the protrusion array.

2. The method for fabricating a micro LED device according to claim 1, wherein, The micro-LED epitaxial wafer is etched starting from the second semiconductor layer until the first semiconductor layer is exposed. The exposed first semiconductor layer is then roughened to form a roughened surface, resulting in a mesa structure including an array of bosses. The micro-LED epitaxial wafer is etched starting from the second semiconductor layer until the first semiconductor layer is exposed, and the exposed first semiconductor layer is further etched to form a roughened surface of the first semiconductor layer, wherein the roughened surface is between every two adjacent bosses in the boss array and on the periphery of the boss array and includes triangular protrusions.

3. The method for fabricating a micro LED device according to claim 1, wherein, Before depositing the first passivation layer, the first metal layer, and the second metal layer on the platform structure, the method further includes: A second passivation layer is provided on the platform structure, wherein the second passivation layer includes a first contact hole that exposes a predetermined exposed portion of the first semiconductor layer; a conductive layer is provided at least on the predetermined exposed portion of the exposed first semiconductor layer.

4. The method for fabricating a micro LED device according to claim 3, wherein, A second passivation layer is disposed on the mesa structure, wherein the second passivation layer includes a first contact hole, and the first contact hole exposes a predetermined exposed portion of the first semiconductor layer, including: A second passivation layer of predetermined thickness is provided on the mesa structure along the contour of the mesa structure, and a first contact hole is formed on the second passivation layer so that the first contact hole exposes the first semiconductor layer between the bosses in the boss array and the periphery of the boss array, wherein the predetermined thickness is equal to one-quarter of the wavelength of the light emitted by the micro LED unit corresponding to the boss.

5. The method for fabricating a micro LED device according to claim 3, wherein, Depositing a conductive layer at least on the predetermined exposed portion of the exposed first semiconductor layer includes: An integral conductive layer is provided on the exposed first semiconductor layer and on the second passivation layer on each side of the boss array.

6. The method for fabricating a micro LED device according to claim 1, wherein, A first passivation layer is provided on the platform structure, such that an isolation gap is formed between every two adjacent bosses of the boss array and in the first passivation layer surrounding the boss array, including: A first passivation layer is deposited on the platform structure. By controlling the deposition rate of the first passivation layer at the top corner of the boss, an isolation gap is formed between every two adjacent bosses in the boss array and in the first passivation layer around the boss array.

7. The method for fabricating a micro LED device according to claim 3, wherein, A first passivation layer, a first metal layer, and a second metal layer are disposed on the mesa structure, such that the first metal layer passes through the first passivation layer and is disposed on a second semiconductor layer on a protrusion in the protrusion array, and the second metal layer passes through the first passivation layer and is disposed on an exposed first semiconductor layer, thereby obtaining the micro LED device comprising: A first passivation layer, a first metal layer, and a second metal layer are disposed on a mesa structure having a second passivation layer and a conductive layer, such that the first metal layer passes through the first passivation layer and the second passivation layer and is disposed on a second semiconductor layer on a boss in the boss array, and the second metal layer passes through the first passivation layer and is disposed on the conductive layer, thereby obtaining the micro LED device.

8. The method for fabricating a micro LED device according to claim 7, wherein, A first passivation layer, a first metal layer, and a second metal layer are disposed on a mesa structure having a second passivation layer and a conductive layer, such that the first metal layer passes through the first passivation layer and the second passivation layer and is disposed on a second semiconductor layer on a protrusion in the protrusion array, and the second metal layer passes through the first passivation layer and is disposed on the conductive layer, thereby obtaining the micro LED device comprising: A first passivation layer is provided on a mesa structure having a second passivation layer and a conductive layer, and a second contact hole array and a third contact hole corresponding to the boss array are formed starting from the first passivation layer, so that each second contact hole in the second contact hole array exposes a portion of the second semiconductor layer on the corresponding boss, and the third contact hole exposes a portion of the conductive layer. A first metal layer is disposed on the exposed portion of the second semiconductor layer, and a second metal layer is disposed on the exposed portion of the conductive layer to obtain the micro LED device.

9. The method for fabricating a micro LED device according to claim 8, wherein, A first passivation layer is provided on a mesa structure having a second passivation layer and a conductive layer, and a second contact hole array and a third contact hole array corresponding to the boss array are formed starting from the second passivation layer, such that each second contact hole in the second contact hole array exposes a portion of the second semiconductor layer on the corresponding boss, and the third contact hole exposes a portion of the conductive layer including: A first passivation layer is deposited on a mesa structure having a second passivation layer and a conductive layer; the first passivation layer is polished to make its surface flat. Starting from the flat surface of the first passivation layer, a second contact hole array and a third contact hole corresponding to the boss array are formed, such that each second contact hole in the second contact hole array exposes a portion of the second semiconductor layer on the corresponding boss, and the third contact hole exposes a portion of the conductive layer on the first semiconductor layer located on the periphery of the boss array.

10. The method for fabricating a micro LED device according to claim 9, wherein, The surfaces of the first metal layer and the second metal layer are flush with the flat surface of the first passivation layer.

11. The method for fabricating a micro LED device according to claim 10, wherein, The micro-LED device includes a driving substrate, and after a first metal layer is disposed on the exposed portion of the second semiconductor layer, and a second metal layer is disposed on the exposed portion of the conductive layer, the method further includes: The first metal layer and the second metal layer are bonded to the driving substrate.

12. The method for fabricating a micro LED device according to claim 11, wherein, The micro-LED epitaxial wafer further includes a substrate and a third semiconductor layer. The substrate is located on the side of the first semiconductor layer opposite to the multi-quantum-well structure. The third semiconductor layer is located between the substrate and the first semiconductor layer. The driving substrate includes a first metal block and a second metal block. The surfaces of the first metal block and the second metal block are flush with the surface of the driving substrate. Bonding the first metal layer and the second metal layer to the driving substrate includes: The first metal layer is bonded to the first metal block, and the second metal layer is bonded to the second metal block; Remove the substrate and the third semiconductor layer.

13. A miniature LED device, wherein, The micro-LED device includes a mesa structure, which comprises an array of protrusions and an exposed first semiconductor layer. Each protrusion in the protrusion array, from bottom to top, includes a first semiconductor layer, a multiple quantum well structure, and a second semiconductor layer. The exposed first semiconductor layer includes a roughened surface. Furthermore, the micro LED device also includes: A first passivation layer is disposed on the platform structure, and the first passivation layer includes isolation gaps between every two adjacent bosses of the boss array and around the periphery of the boss array. A first metal layer and a second metal layer, wherein the first metal layer passes through the first passivation layer and is disposed on a second semiconductor layer on a boss in the boss array, and the second metal layer passes through the first passivation layer and is disposed on an exposed first semiconductor layer.

14. The micro LED device according to claim 13, wherein, The roughened surface is between every two adjacent bosses in the boss array and on the periphery of the boss array and includes triangular protrusions.

15. The micro LED device according to claim 13, wherein, The micro LED device also includes: A second passivation layer is disposed on the mesa structure and includes a first contact hole that exposes a predetermined exposed portion of the first semiconductor layer. A conductive layer is disposed at least on the predetermined exposed portion of the exposed first semiconductor layer.

16. The micro LED device according to claim 15, wherein, The second passivation layer is disposed along the contour of the boss in the mesa structure and has a predetermined thickness, and the first contact hole exposes a first semiconductor layer between the bosses in the boss array and around the periphery of the boss array, wherein the predetermined thickness is equal to one-quarter of the wavelength of the light emitted by the micro LED unit corresponding to the boss.

17. The micro LED device according to claim 15, wherein, The conductive layer is integrally disposed on the exposed first semiconductor layer and on the second passivation layer on each side of the boss array, and the conductive layer includes a third metal layer.

18. The micro LED device according to claim 13, wherein, The isolation gap is formed by controlling the deposition rate of the first passivation layer at the top corner of the boss.

19. The micro LED device according to claim 15, wherein, The first metal layer passes through the first passivation layer and the second passivation layer and is disposed on the second semiconductor layer on the boss in the boss array, and the second metal layer passes through the first passivation layer and is disposed on the conductive layer.

20. The micro LED device according to claim 19, wherein, The first passivation layer includes a first sub-contact hole array and a third contact hole corresponding to the boss array. The second passivation layer includes a second sub-contact hole array aligned with the first sub-contact hole array. The first sub-contact hole array and the second sub-contact hole array constitute a second contact hole array. Each second contact hole in the second contact hole array exposes a portion of the second semiconductor layer on the corresponding boss. The third contact hole exposes a portion of the conductive layer. The first metal layer is disposed on the exposed portion of the second semiconductor layer, and the second metal layer is disposed on the exposed portion of the conductive layer.

21. The micro LED device according to claim 20, wherein, The first passivation layer has a flat surface, and each of the third contact holes exposes a portion of the conductive layer on the first semiconductor layer located around the periphery of the boss array.

22. The micro LED device according to claim 21, wherein, The surfaces of the first metal layer and the second metal layer are flush with the flat surface of the first passivation layer.

23. The micro LED device according to claim 22, wherein, The micro LED device further includes a driving substrate, wherein the first metal layer and the second metal layer are bonded to the driving substrate.

24. The micro LED device according to claim 23, wherein, The driving substrate includes a first metal block and a second metal block, the surfaces of the first metal block and the second metal block are flush with the surface of the driving substrate, and the first metal layer is bonded to the first metal block and the second metal layer is bonded to the second metal block.

25. The micro LED device according to claim 13, wherein, The first semiconductor layer is an n-GaN layer, and the second semiconductor layer is a p-GaN layer.

26. A display device, wherein, The display device includes the micro LED device according to any one of claims 13 to 25.

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