Semiconductor structure and method for manufacturing semiconductor structure

Abstract

The present disclosure provides a semiconductor structure and a method for fabricating the semiconductor structure. The method comprises the following steps: providing a first substrate having a first surface, the first substrate having adjacent first and second regions in a direction parallel to the first surface, the first substrate comprising a metal pattern layer and an insulating layer covering the metal pattern layer, wherein a capacitor contact in the metal pattern layer is located in the first region; removing a portion of the insulating layer located in the first region near the first surface in a direction perpendicular to the first surface, leaving the remaining insulating layer in the first region without exposing the metal pattern layer, thereby obtaining a second substrate having a stepped structure, wherein the height of the second step surface of the stepped structure is greater than the height of the first step surface; forming a stacked structure on the second substrate, and forming an array of contact holes extending from the stacked structure to the stepped structure; and forming a lower electrode, a capacitor dielectric layer, and an upper electrode.

Description

Technical Field

[0001] The present disclosure relates to the field of memory technology, and in particular to a semiconductor structure and a method for manufacturing the semiconductor structure. Background Art

[0002] Currently, the process flow for Dynamic Random Access Memory (DRAM) typically requires forming capacitor holes and forming the bottom electrode of the capacitor structure within the capacitor holes. The capacitor holes can be formed using a patterning process, where a photoresist is used to divide the periphery area and the capacitor array area. The area covered by the photoresist is the periphery area. During the photolithography process, the periphery area is not etched due to being covered by the photoresist, leaving the capacitor holes in the capacitor array area.

[0003] However, due to the large pattern difference at the junction of the peripheral area and the capacitor array area, an etching loading effect is easily generated, which causes problems such as shape deformation at the edge of the capacitor array area, resulting in a large difference in the yield of the capacitor array area compared with other areas. Summary of the Invention

[0004] The main purpose of the present disclosure is to provide a semiconductor structure and a method for manufacturing the semiconductor structure.

[0005] To achieve the above-mentioned purpose, according to one aspect of the present disclosure, a method for manufacturing a semiconductor structure is provided, comprising the following steps: providing a first substrate having a first surface, wherein the first substrate has adjacent first and second regions in a direction parallel to the first surface, the first substrate comprises a metal pattern layer and an insulating layer covering the metal pattern layer, and the capacitor contact in the metal pattern layer is located in the first region; removing a portion of the insulating layer located in the first region close to the first surface in a direction perpendicular to the first surface, and the remaining insulating layer located in the first region does not expose the metal pattern layer, thereby obtaining a second substrate having a step structure, wherein the second substrate has adjacent third and fourth regions, and the step structure has a first step surface located in the third region and a second step surface located in the fourth region, and the height of the second step surface is greater than or equal to the height of the first step surface. The height is greater than the height of the first step surface; a stacking structure is formed on the second substrate, and a contact hole array is formed that penetrates the stacking structure to the step structure, the contact hole array includes a first contact hole located in the third area and a second contact hole located in the fourth area, the first contact hole exposes the capacitor contact located in the third area, and the second contact hole exposes the insulating layer located in the fourth area, thereby obtaining a third substrate, the third substrate having adjacent fifth and sixth areas, and the third substrate having a third step surface located in the fifth area and a fourth step surface located in the sixth area, the first contact hole is distributed on the third step surface, and the second contact hole is distributed on the fourth step surface; a lower electrode is formed in the first contact hole, and a capacitor dielectric layer and an upper electrode are formed in sequence so that the capacitor dielectric layer is located between the lower electrode and the upper electrode, thereby obtaining a capacitor structure.

[0006] Optionally, a portion of the insulating layer located in the first region close to the first surface is removed along a direction perpendicular to the first surface, and the remaining insulating layer located in the first region does not expose the metal pattern layer, thereby obtaining a second substrate having a step structure, comprising: setting a mask on the first surface located in the second region; etching the first substrate based on the mask to remove a portion of the insulating layer in the first region close to the first surface without exposing the capacitor contacts; and removing the mask.

[0007] Optionally, a stacking structure is formed on the second substrate, including: alternately forming sacrificial layers and supporting layers on the second substrate to form a stacking structure, the sacrificial layers and the supporting layers having different etching selectivities, wherein the sacrificial layers and the supporting layers are alternately formed on the second substrate, including: depositing sacrificial layer material on the surface of the second substrate to form a first sacrificial layer; depositing supporting layer material on the surface of the first sacrificial layer to form a first supporting layer; depositing sacrificial layer material on the surface of the first supporting layer to form a second sacrificial layer; and depositing supporting layer material on the surface of the second sacrificial layer to form a second supporting layer.

[0008] Optionally, the thickness of the insulating layer is 36-48 nm; and / or the height difference between the second step surface and the first step surface is 18-30 nm.

[0009] Optionally, forming a lower electrode in the first contact hole includes: depositing a conductive material in the contact hole array, partially covering the inner surface of the first contact hole to form the lower electrode, and partially covering the inner surface of the second contact hole to form a dummy electrode.

[0010] Optionally, after forming the lower electrode in the first contact hole and before sequentially forming the capacitor dielectric layer and the upper electrode, the manufacturing method further includes: patterning the second supporting layer to remove the portion of the second supporting layer corresponding to the sixth region, and the patterned second supporting layer has a fourth etching window corresponding to the fifth region; removing the second sacrificial layer; patterning the first supporting layer to remove the portion of the first supporting layer corresponding to the sixth region, and the patterned first supporting layer has a fifth etching window corresponding to the fourth etching window; removing the first sacrificial layer and the dummy electrode to obtain a supporting structure.

[0011] Optionally, the manufacturing method also includes: forming an initial insulating dielectric layer covering the capacitor structure on the third substrate, the initial insulating dielectric layer including a first initial insulating dielectric layer corresponding to the fifth area and a second initial insulating dielectric layer corresponding to the sixth area; forming a first contact structure that penetrates the first initial insulating dielectric layer and is connected to the capacitor structure, and obtaining a first insulating dielectric layer.

[0012] Optionally, the metal pattern layer also includes a metal connection located in the sixth area, and the manufacturing method also includes: forming a second contact structure that penetrates the second initial insulating dielectric layer and the remaining insulating layer located in the sixth area of ​​the third substrate and is connected to the metal connection, and obtaining a second insulating dielectric layer and a fourth substrate with a step structure, the first insulating dielectric layer and the second insulating dielectric layer constitute an insulating dielectric layer, wherein the fourth substrate includes a metal pattern layer and an insulating layer arranged on the metal pattern layer, and the insulating layer exposes the capacitor contacts and metal connections in the metal pattern layer; the fourth substrate has adjacent seventh and eighth areas, the capacitor contacts in the metal pattern layer are located in the seventh area, and the metal connections in the metal pattern layer are located in the eighth area, the step structure has a fifth step surface located in the seventh area and a sixth step surface located in the eighth area, the height of the sixth step surface is greater than the height of the fifth step surface, the fifth step surface includes a surface formed by the insulating layer and the capacitor contacts located in the seventh area, and the sixth step surface includes a surface formed by the insulating layer and the metal connection located in the eighth area.

[0013] According to another aspect of the present disclosure, a semiconductor structure is provided, comprising: a fourth substrate having a step structure, the fourth substrate comprising a metal pattern layer and an insulating layer arranged on the metal pattern layer, the insulating layer exposing a capacitor contact in the metal pattern layer; the fourth substrate having adjacent seventh and eighth regions, the capacitor contact in the metal pattern layer being located in the seventh region, the step structure having a fifth step surface located in the seventh region and a sixth step surface located in the eighth region, the height of the sixth step surface being greater than the height of the fifth step surface, the fifth step surface comprising a surface formed by the insulating layer and the capacitor contact located in the seventh region; a support structure located on the seventh region and a first contact hole penetrating the support structure, the first contact hole exposing the capacitor contact located in the seventh region; a capacitor structure comprising a lower electrode, a capacitor dielectric layer and an upper electrode, the lower electrode covering an inner wall of the first contact hole, the capacitor dielectric layer covering a surface of the lower electrode, and the upper electrode covering a surface of the capacitor dielectric layer.

[0014] Optionally, the insulating layer also exposes the metal wiring in the metal pattern layer, and the metal wiring in the metal pattern layer is located in the eighth region. The sixth step surface includes the surface formed by the insulating layer and the metal wiring located in the eighth region. The semiconductor structure also includes: an insulating dielectric layer located on the fourth substrate and covering the capacitor structure, the insulating dielectric layer includes a first insulating dielectric layer corresponding to the seventh region and a second insulating dielectric layer corresponding to the eighth region; a first contact structure, penetrating the first insulating dielectric layer and connected to the capacitor structure; a second contact structure, penetrating the second insulating dielectric layer and the insulating layer located in the eighth region of the fourth substrate, and connected to the metal wiring.

[0015] By applying the technical solution disclosed in the present invention, a method for manufacturing a semiconductor structure is provided. According to the method, after providing a first substrate having a first region and a second region at the bottom (the first substrate has adjacent first and second regions, the first substrate includes a metal pattern layer and an insulating layer covering the metal pattern layer, and the capacitor contact in the metal pattern layer is located in the first region), a portion of the insulating layer in the first region close to the first surface is first removed, and the remaining insulating layer in the first region does not expose the metal pattern layer, thereby obtaining a second substrate having a step structure (the second substrate has adjacent third and fourth regions, the step structure has a first step surface located in the third region and a second step surface located in the fourth region, and the height of the second step surface is greater than the height of the first step surface), and then a stack is formed on the second substrate. A stacked structure is provided, and a contact hole array is formed that penetrates the stacked structure to the step structure, so that before forming the contact hole array for setting the lower electrode, a thickness difference is first made between two adjacent areas of the substrate (i.e., the third area and the fourth area of ​​the second substrate). When etching to form the contact hole array, the etching overload effect generated at the junction of the areas corresponding to the third area and the fourth area in the stacked structure (e.g., the capacitor array area and the peripheral area) can be effectively eliminated, thereby avoiding the problem of graphic deformation of the contact holes formed by etching near the junction; at the same time, the above-mentioned thickness difference can ensure that the contact hole will not be etched into the metal pattern layer (metal wiring) located in the fourth area, thereby avoiding a short circuit caused by the contact between the lower electrode material and the metal wiring in the process of forming the lower electrode. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] The accompanying drawings, which constitute part of the present disclosure, are intended to provide a further understanding of the present disclosure. The exemplary embodiments of the present disclosure and their descriptions are intended to explain the present disclosure and do not constitute an improper limitation of the present disclosure. In the accompanying drawings:

[0017] Figure 1 A schematic cross-sectional structure diagram of a first substrate provided in a method for manufacturing a semiconductor structure according to an embodiment of the present disclosure is shown;

[0018] Figure 2 Shown in Figure 1 A schematic diagram of the cross-sectional structure of the substrate after a barrier layer is formed on the first substrate shown;

[0019] Figure 3 Shows the Figure 2 A schematic cross-sectional structure diagram of a second substrate having a stepped structure formed by etching the first substrate shown;

[0020] Figure 4 Shown in Figure 3 A schematic diagram of the cross-sectional structure of the substrate after a stacking structure is formed on the second substrate is shown;

[0021] Figure 5 Shown in Figure 4 A schematic cross-sectional structure diagram of a substrate after a first insulating material layer, a first patterned mask layer, a second insulating material layer, and a second patterned mask layer are formed on the stacked structure shown;

[0022] Figure 6 Shown Figure 5 A schematic top view of the structure of the first patterned mask layer is shown;

[0023] Figure 7 Shown Figure 5 A schematic top view of the structure of the second patterned mask layer is shown;

[0024] Figure 8 Shown Figure 5 The schematic cross-sectional structure diagram of the substrate after the first patterned mask layer and the second patterned mask layer are stacked;

[0025] Figure 9 Shown in Figure 5 A schematic diagram of the cross-sectional structure of the substrate after the contact hole array is formed in the stacked structure shown;

[0026] Figure 10 Shown in Figure 9 A schematic diagram of the cross-sectional structure of the substrate after the conductive material is deposited in the contact hole array shown;

[0027] Figure 11 Shown Figure 10 Schematic diagram of the cross-sectional structure of area A in the middle;

[0028] Figure 12 Shows the Figure 10 The schematic cross-sectional structure diagram of the substrate after the second supporting layer is patterned to form a fourth etching window is shown;

[0029] Figure 13 Shown by Figure 12 The schematic cross-sectional structure diagram of the substrate after the second sacrificial layer is removed by the fourth etching window shown;

[0030] Figure 14 Shown graphically Figure 13 The schematic cross-sectional structure diagram of the substrate after the first supporting layer is formed with the fifth etching window;

[0031] Figure 15 Shows the removal Figure 14 A schematic cross-sectional structure diagram of the substrate behind the first sacrificial layer and the dummy electrode is shown;

[0032] Figure 16 Shown in Figure 15 The cross-sectional structure diagram of the substrate in the XZ direction after the capacitor dielectric layer, the upper electrode and the insulating dielectric layer are formed is shown;

[0033] Figure 17 Shown Figure 16 Schematic diagram of the cross-sectional structure of area B in the middle;

[0034] Figure 18 Shown Figure 16 Schematic diagram of the cross-sectional structure of the middle C area;

[0035] Figure 19 Shown in Figure 16 A schematic cross-sectional structure diagram of the substrate after the first contact structure and the second contact structure are formed in the insulating dielectric layer shown;

[0036] Figure 20 Shown Figure 19 Schematic diagram of the cross-sectional structure of area D in the middle.

[0037] The above drawings include the following reference numerals:

[0038] 100, first substrate; 101, first region; 102, second region; 110, capacitor contact; 120, metal connection; 10, barrier layer; 200, second substrate; 201, third region; 202, fourth region; 210, first sacrificial layer; 220, second sacrificial layer; 30, support structure; 300, third substrate; 301, fifth region; 302, sixth region; 310, first support layer; 320, second support layer; 400, fourth substrate; 401, seventh region; 402, eighth region; 41 0. First insulating material layer; 420. First patterned mask layer; 421. First strip mask structure; 430. Second insulating material layer; 440. Second patterned mask layer; 441. Second strip mask structure; 450. Third patterned mask layer; 451. Third etching window; 50. Lower electrode; 510. Dummy electrode; 60. Capacitor dielectric layer; 70. Upper electrode; 80. Insulating dielectric layer; 810. First insulating dielectric layer; 820. Second insulating dielectric layer; 910. First contact structure; 920. Second contact structure. DETAILED DESCRIPTION

[0039] It should be noted that, in the absence of conflict, the embodiments and features of the embodiments in the present disclosure may be combined with each other. The present disclosure will be described in detail below with reference to the accompanying drawings and in combination with the embodiments.

[0040] In order to enable those skilled in the art to better understand the solutions of the present disclosure, the technical solutions in the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings in the embodiments of the present disclosure. Obviously, the embodiments described are only part of the embodiments of the present disclosure, not all of the embodiments. Based on the embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without making creative efforts should fall within the scope of protection of the present disclosure.

[0041] It should be noted that the terms "first," "second," and the like in the specification and claims of the present disclosure and the accompanying drawings are used to distinguish similar objects and are not necessarily used to describe a specific order or precedence. It should be understood that the terms used in this manner are interchangeable where appropriate for the embodiments of the present disclosure described herein. In addition, the terms "including" and "having," and any variations thereof, are intended to cover non-exclusive inclusions. For example, a process, method, system, product, or apparatus comprising a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units that are not explicitly listed or inherent to these processes, methods, products, or apparatus.

[0042] In some embodiments, the interface between the peripheral region and the capacitor array region in the DRAM process flow is prone to an etching loading effect due to large pattern differences, which can cause problems such as shape deformation at the edge of the capacitor array region, resulting in a significant difference in yield between the capacitor array region and other regions.

[0043] According to one embodiment of the present disclosure, a method for manufacturing a semiconductor structure is provided, comprising the following steps: providing a first substrate having a first surface, wherein the first substrate has adjacent first and second regions in a direction parallel to the first surface, the first substrate comprising a metal pattern layer and an insulating layer covering the metal pattern layer, and a capacitor contact in the metal pattern layer is located in the first region; removing a portion of the insulating layer located in the first region close to the first surface in a direction perpendicular to the first surface, leaving the remaining insulating layer located in the first region without exposing the metal pattern layer, to obtain a second substrate having a step structure, wherein the second substrate has adjacent third and fourth regions, and the step structure has a first step surface located in the third region and a second step surface located in the fourth region, wherein the height of the second step surface is greater than that of the first step surface. a height of a step surface; forming a stacking structure on the second substrate, and forming a contact hole array penetrating the stacking structure to the step structure, the contact hole array including a first contact hole located in the third area and a second contact hole located in the fourth area, the first contact hole exposing the capacitor contact located in the third area, the second contact hole exposing the insulating layer located in the fourth area, and obtaining a third substrate, the third substrate having adjacent fifth and sixth areas, and the third substrate having a third step surface located in the fifth area and a fourth step surface located in the sixth area, the first contact hole distributed on the third step surface, and the second contact hole distributed on the fourth step surface; forming a lower electrode in the first contact hole, and sequentially forming a capacitor dielectric layer and an upper electrode so that the capacitor dielectric layer is located between the lower electrode and the upper electrode, and obtaining a capacitor structure.

[0044] It should be noted that the first contact hole is located below the first step surface, and the capacitor contact located in the first area can be exposed through the first contact hole. The second contact hole is located below the second step surface, and the insulating layer located in the second area can be exposed through the second contact hole. That is, the layer formed by etching the insulating layer in the following text can also serve as a supporting layer or as part of the supporting structure. In addition, the third area of ​​the second substrate corresponds to the first area of ​​the first substrate, the fourth area of ​​the second substrate corresponds to the second area of ​​the first substrate, the fifth area of ​​the third substrate corresponds to the third area of ​​the second substrate, and the sixth area of ​​the third substrate corresponds to the fourth area of ​​the second substrate. The seventh area of ​​the fourth substrate in the following text corresponds to the fifth area of ​​the third substrate, and the eighth area of ​​the fourth substrate corresponds to the sixth area of ​​the third substrate.

[0045] In the above embodiment, since a thickness difference is first created between the first region and the second region of the first substrate before forming the contact hole array for setting the lower electrode, when etching to form the contact hole array, the etching overload effect generated at the junction of the regions corresponding to the first region and the second region (for example, the capacitor array region and the peripheral region) in the insulating layer can be effectively eliminated, thereby avoiding the problem of graphic deformation of the contact holes formed by etching near the junction; at the same time, the above-mentioned thickness difference can ensure that the contact holes will not be etched into the metal pattern layer (i.e., the metal connection) located in the second region, thereby avoiding a short circuit caused by the contact between the lower electrode material and the metal connection in the process of forming the lower electrode.

[0046] Exemplary embodiments of the method for fabricating a semiconductor structure provided herein will be described in more detail below with reference to the accompanying drawings. However, these embodiments may be implemented in a variety of different forms and should not be construed as being limited to the embodiments described herein. It should be understood that these embodiments are provided to make the disclosure of this application thorough and complete.

[0047] First, if Figure 1 As shown, a first substrate 100 having a first surface is provided. In a direction parallel to the first surface, the first substrate 100 has a first region 101 and a second region 102 adjacent to each other. The first substrate 100 includes a metal pattern layer 110 and an insulating layer covering the metal pattern layer. A capacitor contact 110 may be provided at the bottom of the first substrate 100. The region of the first substrate 100 having the capacitor contact 110 is the first region 101, and the portion of the first substrate 100 excluding the first region 101 is the second region 102.

[0048] Specifically, the insulating layer in the first substrate 100 may be formed of a silicon-containing material. Exemplarily, the insulating layer is made of silicon nitride.

[0049] In some optional embodiments, the thickness of the insulating layer is 36 to 48 nm. By ensuring that the insulating layer meets this thickness range, the height difference between the first step surface and the second step surface can be maintained in the subsequent step of forming the step structure, thereby further effectively ensuring that the subsequently formed contact holes will not etch into the metal pattern layer (i.e., metal wiring) located in the second region. At the same time, since the insulating layer can form a support layer for supporting the lower electrode after the subsequent step of forming the contact hole array, ensuring that the insulating layer meets this thickness range can provide better support.

[0050] like Figure 1 As shown, the bottom of the first substrate 100 may have a capacitor contact 110 and a metal connection line 120 . The capacitor contact 110 is located in the first area 101 , and the metal connection line 120 is located in the second area 102 .

[0051] Specifically, the steps for forming the capacitor contacts 110 and the metal wiring 120 may be various conventional steps for forming capacitor contacts and metal wiring in the art, and are not further described here. The wire materials forming the capacitor contacts 110 and the metal wiring 120 may be the same or different, and those skilled in the art may make appropriate selections based on actual needs, and this disclosure does not impose any specific limitations.

[0052] After the step of providing the first substrate 100, Figure 2 and Figure 3 As shown, a portion of the first surface of the first region 101 close to the first substrate 100 is removed, and the remaining insulating layer located in the first region 101 does not expose the metal pattern layer, thereby obtaining a second substrate 200 having a step structure. The second substrate 200 has adjacent third and fourth regions 201 and 202, and the step structure has a first step surface located in the third region 201 and a second step surface located in the fourth region 202.

[0053] In some optional embodiments, the height difference between the second step surface and the first step surface is 18 to 30 nm. By ensuring that the second step surface and the first step surface meet this height difference, it can be effectively ensured that the subsequently formed contact hole will not etch into the metal pattern layer (i.e., metal wiring) located in the second region.

[0054] In some optional embodiments, the step of removing a portion of the insulating layer in the first region 101 close to the first surface of the first substrate 100 includes: the step of removing the portion of the first region 101 close to the first surface may include: setting a mask on the local surface of the first surface of the first substrate 100 corresponding to the second region 102, the first surface having an exposed area not covered by the mask, and then etching the first substrate 100 through the exposed area to remove the portion of the first region 101 close to the first surface, and removing the mask before the step of forming the insulating layer.

[0055] In addition to the implementation method of using a mask to form the above-mentioned barrier layer 10 to etch away part of the insulating layer in the first region 101 close to the first surface of the first substrate 100, the present embodiment can also adopt an implementation method of forming a mask layer on the first surface of the first substrate 100 and etching. Specifically, the first surface of the first substrate 100 is covered with a mask material; the mask material is etched to expose a local surface corresponding to the first region in the first surface; the first substrate is etched through the local surface to remove the portion close to the first surface in the first region; before the step of forming the insulating layer, the remaining mask material is removed. Specifically, the mask material is etched to form a barrier layer 10 on the above-mentioned first surface, and the first surface has an exposed area not covered by the barrier layer 10, such as Figure 2The first substrate 100 is etched through the exposed area to remove the first region 101 near the first surface of the first substrate 100, as shown Figure 3 shown.

[0056] In the above optional embodiment, the mask material can be photoresist, and the blocking layer 10 can be a patterned photoresist layer. Specifically, the photoresist can be coated on the surface of the first substrate 100 to form a photoresist layer, and then the photoresist layer can be patterned by exposure and development to obtain the above-mentioned patterned photoresist layer. The area not covered by the photoresist can be etched to obtain the second substrate 200 having a stepped surface. It should be noted that the above-mentioned mask material can also be other materials that can achieve blocking etching, and this disclosure does not specifically limit it.

[0057] After the step of forming the second base 200 having the step structure, as shown in FIG. Figures 4 to 9 As shown, a stacking structure is formed on the second substrate 200, and a contact hole array is formed that penetrates the stacking structure to the step structure. The contact hole array includes a first contact hole located in the third area 201 and a second contact hole located in the fourth area 202. The first contact hole exposes the capacitor contact 110 located in the third area 201, and the second contact hole exposes the insulating layer located in the fourth area 202, thereby obtaining a third substrate 300. The third substrate 300 has adjacent fifth and sixth areas 301 and 302, and the third substrate 300 has a third step surface located in the fifth area 301 and a fourth step surface located in the sixth area 302. The first contact holes are distributed on the third step surface, and the second contact holes are distributed on the fourth step surface.

[0058] In some optional embodiments, the step of forming the stacked structure includes: alternately depositing a sacrificial layer and a supporting layer on the second substrate 200 to form a stacked structure, such as Figure 4 As shown, the sacrificial layer and the supporting layer have different etching selectivities.

[0059] In the above optional embodiment, after the sacrificial layer is removed in a subsequent process, the support layer can form a support structure, thereby playing a supporting role for the lower electrode in the capacitor structure. The sacrificial layer material and the support layer material can be insulating materials with different etching selectivities, so that the sacrificial layer material can be removed by etching in a subsequent process while retaining the support layer material. The sacrificial layer material can be silicon dioxide or other materials commonly used as sacrificial layers, and the support layer material can be silicon nitride or other materials commonly used as support layers. Those skilled in the art can make reasonable selections based on actual needs, and this disclosure does not impose specific limitations.

[0060] In the above optional embodiment, the number of alternating depositions of the sacrificial layer material and the supporting layer material can be reasonably set according to actual needs. In order to enable the subsequently formed supporting structure 30 to play a better supporting role, further optionally, the number of alternating depositions is greater than or equal to 2.

[0061] In the above optional embodiments, the deposition of the sacrificial layer material and the supporting layer material may be accomplished by any suitable process, such as chemical vapor deposition, physical vapor deposition (PVD), atomic layer deposition (ALD), molecular beam epitaxy (MBE), high-density plasma chemical vapor deposition (HDPCVD), metal organic chemical vapor deposition (MOCVD), remote plasma chemical vapor deposition (RPCVD), plasma enhanced chemical vapor deposition (PECVD), electroplating, other suitable methods and / or combinations of the foregoing.

[0062] Exemplarily, the steps of alternately depositing sacrificial layer materials and supporting layer materials may include: depositing sacrificial layer materials on the surface of the second substrate 200 to form a first sacrificial layer 210; depositing supporting layer materials on the surface of the first sacrificial layer 210 to form a first supporting layer 310; depositing sacrificial layer materials on the surface of the first supporting layer 310 to form a second sacrificial layer 220; and depositing supporting layer materials on the surface of the second sacrificial layer 220 to form a second supporting layer 320, wherein the remaining insulating layer in the second substrate 200 also serves as a supporting layer, as shown in FIG. Figure 4 shown.

[0063] In order to form a contact hole array in the insulating layer extending through the stepped structure, in some optional embodiments, the step of forming the contact hole array includes: performing a patterning process on the stacked structure to form a contact hole array extending through the stacked structure to the stepped structure. Furthermore, in order to reduce the size of each contact hole in the formed contact hole array, thereby increasing the array density, the stacked structure may further optionally be subjected to two self-aligned double patterning (SADP) processes to obtain the contact hole array.

[0064] Exemplarily, the steps of performing two self-aligned double patterning processes on the stacked structure may include: forming a mask layer on the stacked structure, and then sequentially forming a first insulating material layer 410, a first patterned mask layer 420, a second insulating material layer 430, and a second patterned mask layer 440 on the mask layer, wherein the second insulating material layer 430 is located on a side of the first insulating material layer 410 away from the insulating layer and wraps the first patterned mask layer 420, and the second patterned mask layer 440 is located on a side of the second insulating material layer 430 away from the first insulating material layer 410, and the second patterned mask layer 440 has a first etching window, such as Figures 5 to 8 As shown; the second insulating material layer 430 and the first patterned mask layer 420 are sequentially etched through the first etching window, and a second etching window is formed in the remaining first patterned mask layer 420; the portion of the first insulating material layer 410 corresponding to the second etching window is removed, and the remaining first insulating material layer 410 forms a third patterned mask layer 450 having a third etching window 451; the insulating layer is etched through the third etching window 451 to form a contact hole array, as shown Figure 9 shown.

[0065] In order to ensure that the contact holes in the formed contact hole array are small in size and have the same shape, the first patterned mask layer 420 may include a plurality of first strip mask structures 421 arranged at intervals, such as Figure 6 As shown, each first strip mask structure 421 extends along the first direction; the second patterned mask layer 440 may include a plurality of second strip mask structures 441 arranged at intervals, such as Figure 7 As shown, each second strip mask structure 441 extends along the second direction, and the second direction and the first direction have an angle, as shown in FIG. Figure 8 shown.

[0066] The first patterned mask layer 420 and the second patterned mask layer 440 can be formed by a patterning process. Specifically, after forming the first insulating material layer 410, a first mask material layer can be deposited and then etched using a patterning process to obtain a plurality of first strip-shaped mask structures 421 spaced apart from each other. Then, a second insulating material layer 430 is formed to wrap around the first strip-shaped mask structures 421, and a second mask material layer is deposited. Finally, a patterning process is used to etch the second mask material layer to obtain a plurality of second strip-shaped mask structures 441 spaced apart from each other.

[0067] In the above optional embodiment, the deposition of the first insulating material layer 410, the first mask material layer, the second insulating material layer 430 and the second mask material layer can be completed by any suitable process, such as chemical vapor deposition, physical vapor deposition (PVD), atomic layer deposition (ALD), molecular beam epitaxy (MBE), high density plasma chemical vapor deposition (HDPCVD), metal organic chemical vapor deposition (MOCVD), remote plasma chemical vapor deposition (RPCVD), plasma enhanced chemical vapor deposition (PECVD), electroplating, other suitable methods and / or combinations of the foregoing.

[0068] In the above optional embodiment, the material types of the first insulating material layer 410, the first mask material layer, the second insulating material layer 430 and the second mask material layer can be reasonably selected according to actual needs. For example, the above first insulating material layer 410 and the above second insulating material layer 430 can be SOH, etc., and the above first mask material layer and the second mask material layer can be SiON, etc. Those skilled in the art can make reasonable selections, and this disclosure does not make specific limitations.

[0069] After the step of forming the contact hole array penetrating the stacked structure to the step structure, as shown in FIG. Figures 10 to 15 As shown, a lower electrode 50 is formed in the first contact hole, and the stacked structure is etched to form a support structure 30 in contact with the lower electrode 50 .

[0070] In some optional embodiments, the step of forming the lower electrode 50 in the first contact hole includes: depositing a conductive material in the contact hole array, partially covering the inner surface of the first contact hole to form the lower electrode 50, and partially covering the inner surface of the second contact hole to form the dummy electrode 510, such as Figure 10 As shown, Figure 10 The cross-sectional diagram of area A is shown in Figure 11 As shown, the lower electrode 50 covers the bottom surface and sidewalls of the first contact hole.

[0071] In the above optional embodiment, the conductive material may include titanium nitride or the like.

[0072] In some optional embodiments, after forming the lower electrode 50 in the first contact hole and before sequentially forming the capacitor dielectric layer 60 and the upper electrode 70, the manufacturing method in this embodiment further includes the following steps: patterning the second supporting layer 320, wherein the patterned second supporting layer 320 has a fourth etching window, such as Figure 12 The second sacrificial layer 220 is removed by the fourth etching window, as shown Figure 13 As shown, the first supporting layer 310 is then patterned, and the patterned first supporting layer 310 has a fifth etching window corresponding to the fourth etching window, as shown in FIG. Figure 14 By removing the first sacrificial layer 210 and the dummy electrode 510 through the fifth etching window, a support structure 30 is obtained, as shown Figure 15 shown.

[0073] In the above optional embodiment, the second supporting layer 320 is patterned to remove the portion of the second supporting layer 320 corresponding to the sixth region 302, and the patterned second supporting layer 320 has a fourth etching window corresponding to the fifth region 301, so that the second sacrificial layer 220 located below can be partially exposed through the above fourth etching window, and the second sacrificial layer 220 can be etched away through the exposed portion; and the first supporting layer 310 is patterned to remove the portion of the first supporting layer 310 corresponding to the sixth region 302, and the patterned first supporting layer 310 has a fifth etching window corresponding to the fourth etching window, so that the first sacrificial layer 210 located below is partially exposed through the above fifth etching window, and the first sacrificial layer 210 can be etched away through the exposed portion. The patterned first supporting layer 310 and the second supporting layer 320 constitute a supporting structure 30 for supporting the lower electrode 50 (the supporting structure 30 may also include the remaining insulating layer on the substrate).

[0074] It should be noted that, in the process of removing the second sacrificial layer 220 and the first sacrificial layer 210, the dummy electrode 510 is also removed. Figure 15 As shown, the final support structure 30 includes the remaining second support layer 320 , the remaining first support layer 310 and the remaining insulation layer in the second base 200 .

[0075] In the above-mentioned process of etching and removing the second sacrificial layer 220 and the first sacrificial layer 210 , the etching process and its process conditions may be reasonably set according to the type of conductive material forming the dummy electrode 510 , and are not specifically limited in this disclosure.

[0076] After forming the lower electrode 50 and the supporting structure 30 in contact with the lower electrode 50, a capacitor dielectric layer 60 is formed to cover the surface of the lower electrode 50, and an upper electrode 70 is formed to cover the surface of the capacitor dielectric layer 60, thereby obtaining a capacitor structure. Figures 16 to 18 As shown, Figure 17 and Figure 18 They are Figure 16 In the cross-sectional structural diagram of the B region and the C region, the lower electrode 50 covers the inner surface of the first contact hole, the capacitor dielectric layer 60 wraps the lower electrode 50 , and the upper electrode 70 wraps the capacitor dielectric layer 60 .

[0077] In some optional embodiments, the capacitor dielectric layer 60 may be an aluminum oxide layer or a zirconium oxide layer (ZrO x ) or a stack of the two (such as an AZAZA layer) or other high-K dielectric layers, but is not limited to the above types. Those skilled in the art can make reasonable selections based on actual needs; the material of the above-mentioned upper electrode 70 may include titanium nitride, etc.

[0078] The deposition of the capacitor dielectric layer 60 and the top electrode 70 may be accomplished by any suitable process, such as chemical vapor deposition, physical vapor deposition (PVD), atomic layer deposition (ALD), molecular beam epitaxy (MBE), high-density plasma chemical vapor deposition (HDPCVD), metal organic chemical vapor deposition (MOCVD), remote plasma chemical vapor deposition (RPCVD), plasma enhanced chemical vapor deposition (PECVD), electroplating, other suitable methods, and / or combinations thereof.

[0079] It is understandable that after forming the upper electrode, a conductive layer such as a polysilicon layer may be deposited or filled to wrap the aforementioned capacitor structure.

[0080] After the step of forming the above-mentioned capacitor structure, the above-mentioned manufacturing method of this embodiment may further include: forming an initial insulating dielectric layer covering the capacitor structure (for example, a capacitor structure covered with a conductive layer such as a polysilicon layer deposited or filled) on the third substrate 300, the initial insulating dielectric layer 80 including a first initial insulating dielectric layer corresponding to the fifth region 301 and a second initial insulating dielectric layer corresponding to the sixth region 302; forming a first contact structure 910 penetrating the first initial insulating dielectric layer and contacting the capacitor structure, and obtaining the first insulating dielectric layer 810, as shown in FIG. Figure 19 shown.

[0081] In some optional embodiments, the metal pattern layer further includes a metal connection 120 located in the sixth region 302. The manufacturing method of this embodiment further includes: forming a second contact structure 920 that penetrates the second initial insulating dielectric layer and the remaining insulating layer located in the sixth region 302 of the third substrate 300 and is connected to the metal connection 120, and obtaining a second insulating dielectric layer 820 and a fourth substrate 400 having a step structure. The first insulating dielectric layer 810 and the second insulating dielectric layer 820 constitute an insulating dielectric layer 80, as shown in FIG. Figure 19 As shown, the fourth substrate 400 includes a metal pattern layer and an insulating layer arranged on the metal pattern layer, the insulating layer exposes the capacitor contact 110 and the metal connection 120 in the metal pattern layer; the fourth substrate 400 has an adjacent seventh region 401 and an eighth region 402, the capacitor contact 110 in the metal pattern layer is located in the seventh region 401, and the metal connection 120 in the metal pattern layer is located in the eighth region 402, the step structure has a fifth step surface located in the seventh region 401 and a sixth step surface located in the eighth region 402, the height of the sixth step surface is greater than the height of the fifth step surface, the fifth step surface includes a surface formed by the insulating layer and the capacitor contact 110 located in the seventh region 401, and the sixth step surface includes a surface formed by the insulating layer and the metal connection 120 located in the eighth region 402, the above-mentioned fifth step surface exposes the capacitor contact 110 in the metal pattern layer, and the above-mentioned sixth step surface exposes the metal connection 120 in the metal pattern layer.

[0082] In some optional embodiments, the first contact structure 910 and the second contact structure 920 are formed in the same etching process. Specifically, a patterned mask layer may be first provided on the insulating dielectric layer 80, and then the insulating dielectric layer 80 may be etched through the patterned mask layer to form lead holes. The lead holes are then filled with a conductive material, so that the first contact structure 910 is formed in the lead holes that penetrate the capacitor structure, and the second contact structure 920 is simultaneously formed in the lead holes that penetrate the metal connection 120.

[0083] According to another embodiment of the present disclosure, a semiconductor structure is provided. Figure 19As shown, it includes a fourth substrate 400 with a step structure and a capacitor structure, wherein: the fourth substrate 400 includes a metal pattern layer and an insulating layer arranged on the metal pattern layer, the insulating layer exposes the capacitor contact 110 in the metal pattern layer; the fourth substrate 400 has a seventh region 401 and an eighth region 402 adjacent to each other, the capacitor contact 110 in the metal pattern layer is located in the seventh region 401, the step structure has a fifth step surface located in the seventh region 401 and a sixth step surface located in the eighth region 402, the height of the sixth step surface is greater than the height of the fifth step surface, the fifth step surface includes a surface formed by the insulating layer and the capacitor contact 110 located in the seventh region 401; a support structure 30 located on the seventh region and a first contact hole penetrated through the support structure 30, the first contact hole exposing the capacitor contact 110 located in the seventh region 401; as shown Figure 20 As shown, the capacitor structure includes a lower electrode 50 , a capacitor dielectric layer 60 and an upper electrode 70 . The lower electrode 50 covers the inner wall of the first contact hole, the capacitor dielectric layer 60 covers the surface of the lower electrode 50 , and the upper electrode 70 covers the surface of the capacitor dielectric layer 60 .

[0084] It should be noted that the above semiconductor structure can also be manufactured by the method for manufacturing the semiconductor structure in the above embodiment.

[0085] In some optional embodiments, such as Figure 19 As shown, the insulating layer also exposes the metal connection 120 in the metal pattern layer, and the metal connection 120 in the metal pattern layer is located in the eighth region 402. The sixth step surface includes a surface formed by the insulating layer and the metal connection 120 located in the eighth region 402. The semiconductor structure also includes an insulating dielectric layer 80, a first contact structure 910 and a second contact structure 920, wherein: the insulating dielectric layer 80 is located on the fourth substrate 400 and covers the capacitor structure, the insulating dielectric layer 80 includes a first insulating dielectric layer 810 corresponding to the seventh region 401 and a second insulating dielectric layer 820 corresponding to the eighth region 402; the first contact structure 910 penetrates the first insulating dielectric layer 810 and is connected to the capacitor structure; the second contact structure 920 penetrates the second insulating dielectric layer 820 and the insulating layer located in the eighth region 402 of the fourth substrate 400, and is connected to the metal connection 120.

[0086] According to another embodiment of the present disclosure, a DRAM is provided, comprising the semiconductor structure in the above embodiment.

[0087] Exemplarily, the above-mentioned DRAM may include multiple memory cells, each memory cell including: a substrate, multiple semiconductor structures as in the above-mentioned embodiments, and transistors having a source region and a drain region, wherein the transistor is arranged in the substrate, and the capacitor structure in the semiconductor is in contact with the source region or the drain region.

[0088] In some optional embodiments, the transistor is a buried-gate transistor. In other optional embodiments, the transistor is a transistor with a planar gate structure or a ring-gate structure, which is not specifically limited in the present disclosure.

[0089] From the above description, it can be seen that the above embodiments of the present disclosure achieve the following technical effects:

[0090] Because a thickness difference is first created between the first region and the second region having the capacitor contacts before forming the contact hole array for setting the lower electrode, when etching to form the contact hole array, the etching overload effect generated at the junction of the regions corresponding to the first region and the second region (i.e., the capacitor array region and the peripheral region) in the insulating layer can be effectively eliminated, thereby avoiding the problem of graphic deformation of the contact holes formed by etching near the junction; at the same time, the above-mentioned thickness difference can ensure that the contact holes will not be etched into the metal wiring in the second region, thereby avoiding short circuits caused by contact between the lower electrode material and the metal wiring during the process of forming the lower electrode.

[0091] The foregoing description is merely a preferred embodiment of the present disclosure and is not intended to limit the present disclosure. Those skilled in the art will readily appreciate that various modifications and variations are possible. Any modifications, equivalent substitutions, or improvements made within the spirit and principles of the present disclosure shall be included within the scope of protection of the present disclosure.

Claims

1. A method for manufacturing a semiconductor structure, characterized in that: include: Providing a first substrate having a first surface, wherein the first substrate has a first region and a second region adjacent to each other in a direction parallel to the first surface, the first substrate comprising a metal pattern layer and an insulating layer covering the metal pattern layer, wherein a capacitor contact in the metal pattern layer is located in the first region; removing a portion of the insulating layer located in the first region and close to the first surface in a direction perpendicular to the first surface, with the remaining insulating layer in the first region not exposing the metal pattern layer, to obtain a second substrate having a stepped structure, wherein the second substrate has a third region and a fourth region adjacent to each other, the stepped structure having a first stepped surface located in the third region and a second stepped surface located in the fourth region, the height of the second stepped surface being greater than the height of the first stepped surface; forming a stacked structure on the second substrate, and forming a contact hole array penetrating the stacked structure to the step structure, the contact hole array including a first contact hole located in the third region and a second contact hole located in the fourth region, the first contact hole exposing the capacitor contact located in the third region, and the second contact hole exposing the insulating layer located in the fourth region, thereby obtaining a third substrate, the third substrate having adjacent fifth and sixth regions, and the third substrate having a third step surface located in the fifth region and a fourth step surface located in the sixth region, the first contact holes being distributed on the third step surface, and the second contact holes being distributed on the fourth step surface; A lower electrode is formed in the first contact hole, and a capacitor dielectric layer and an upper electrode are formed in sequence, so that the capacitor dielectric layer is located between the lower electrode and the upper electrode, thereby obtaining a capacitor structure.

2. The production method according to claim 1, characterized in that A second substrate having a stepped structure is obtained by removing a portion of the insulating layer located in the first region and close to the first surface in a direction perpendicular to the first surface, wherein the remaining insulating layer located in the first region does not expose the metal pattern layer. The second substrate comprises: Disposing a mask on the first surface located in the second area; etching the first substrate based on the mask to remove a portion of the insulating layer in the first region close to the first surface without exposing the capacitor contact; The mask is removed.

3. The production method according to claim 1, characterized in that forming a stacked structure on the second substrate, comprising: Alternatingly forming sacrificial layers and supporting layers on the second substrate to form the stacked structure, wherein the sacrificial layers and the supporting layers have different etching selectivities, wherein the alternatingly forming the sacrificial layers and the supporting layers on the second substrate comprises: depositing a sacrificial layer material on the surface of the second substrate to form a first sacrificial layer; depositing a support layer material on a surface of the first sacrificial layer to form a first support layer; Depositing the sacrificial layer material on the surface of the first supporting layer to form a second sacrificial layer; The supporting layer material is deposited on the surface of the second sacrificial layer to form a second supporting layer.

4. The production method according to any one of claims 1 to 3, characterized in that The thickness of the insulating layer is 36-48 nm; and / or A height difference between the second step surface and the first step surface is 18-30 nm.

5. The production method according to claim 3, characterized in that: forming a lower electrode in the first contact hole, comprising: Conductive material is deposited in the contact hole array, part of the conductive material covers the inner surface of the first contact hole to form the lower electrode, and part of the conductive material covers the inner surface of the second contact hole to form a dummy electrode.

6. The manufacturing method according to claim 5, characterized in that: After forming the lower electrode in the first contact hole and before sequentially forming the capacitor dielectric layer and the upper electrode, the manufacturing method further includes: Performing patterning on the second supporting layer to remove a portion of the second supporting layer corresponding to the sixth region, and the patterned second supporting layer has a fourth etching window corresponding to the fifth region; removing the second sacrificial layer; Performing a patterning process on the first supporting layer to remove a portion of the first supporting layer corresponding to the sixth region, and the patterned first supporting layer has a fifth etching window corresponding to the fourth etching window; The first sacrificial layer and the dummy electrode are removed to obtain a support structure.

7. The production method according to any one of claims 1 to 3, characterized in that: The production method further comprises: forming an initial insulating dielectric layer covering the capacitor structure on the third substrate, wherein the initial insulating dielectric layer includes a first initial insulating dielectric layer corresponding to the fifth region and a second initial insulating dielectric layer corresponding to the sixth region; A first contact structure is formed that penetrates the first initial insulating dielectric layer and is connected to the capacitor structure, thereby obtaining a first insulating dielectric layer.

8. The production method according to claim 7, characterized in that: The metal pattern layer further includes a metal connection line located in the sixth region, and the manufacturing method further includes: A second contact structure is formed that penetrates the second initial insulating dielectric layer and the remaining insulating layer located in the sixth region of the third substrate and is connected to the metal wiring, thereby obtaining a second insulating dielectric layer and a fourth substrate having a step structure, wherein the first insulating dielectric layer and the second insulating dielectric layer constitute an insulating dielectric layer, wherein: The fourth substrate includes a metal pattern layer and an insulating layer arranged on the metal pattern layer, the insulating layer exposes the capacitor contacts and metal connections in the metal pattern layer; the fourth substrate has adjacent seventh and eighth regions, the capacitor contacts in the metal pattern layer are located in the seventh region, and the metal connections in the metal pattern layer are located in the eighth region, the step structure has a fifth step surface located in the seventh region and a sixth step surface located in the eighth region, the height of the sixth step surface is greater than the height of the fifth step surface, the fifth step surface includes a surface formed by the insulating layer and the capacitor contacts located in the seventh region, and the sixth step surface includes a surface formed by the insulating layer and the metal connections located in the eighth region.

9. A semiconductor structure, characterized in that The semiconductor structure is manufactured by the manufacturing method according to claim 8, and the semiconductor structure comprises: A fourth substrate having a stepped structure, the fourth substrate comprising a metal pattern layer and an insulating layer disposed on the metal pattern layer, the insulating layer exposing a capacitor contact in the metal pattern layer; the fourth substrate having a seventh region and an eighth region adjacent to each other, the capacitor contact in the metal pattern layer being located in the seventh region, the stepped structure comprising a fifth step surface located in the seventh region and a sixth step surface located in the eighth region, the sixth step surface being greater in height than the fifth step surface, the fifth step surface comprising a surface formed by the insulating layer in the seventh region and the capacitor contact; a support structure located on the seventh region and a first contact hole penetrating the support structure, wherein the first contact hole exposes a capacitor contact located in the seventh region; The capacitor structure includes a lower electrode, a capacitor dielectric layer and an upper electrode, wherein the lower electrode covers the inner wall of the first contact hole, the capacitor dielectric layer covers the surface of the lower electrode, and the upper electrode covers the surface of the capacitor dielectric layer.

10. The semiconductor structure according to claim 9, wherein: The insulating layer further exposes the metal wiring in the metal pattern layer, the metal wiring in the metal pattern layer is located in the eighth region, the sixth step surface includes a surface formed by the insulating layer and the metal wiring located in the eighth region, and the semiconductor structure further includes: an insulating dielectric layer, located on the fourth substrate and covering the capacitor structure, the insulating dielectric layer comprising a first insulating dielectric layer corresponding to the seventh region and a second insulating dielectric layer corresponding to the eighth region; a first contact structure, penetrating the first insulating dielectric layer and connected to the capacitor structure; The second contact structure penetrates the second insulating dielectric layer and the insulating layer located in the eighth region of the fourth base, and is connected to the metal wiring.

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