A method for manufacturing a semiconductor structure

Abstract

The application provides a preparation method of a semiconductor structure, and is applied to the technical field of semiconductors. In the application, the stack layer (the first stack layer or the second stack layer) on the second region is removed before the formation of the alignment mark (the first alignment mark or the second alignment mark), and then the medium layer (the first medium layer or the second medium layer) is deposited, so that the quality of the alignment mark is improved by forming the alignment mark in the medium layer with the material being the isolation material, the quality of the alignment signal is ensured to meet the requirements, the recognizability of the alignment mark is improved, the misalignment of the first conductive column and the second conductive column is prevented, and finally the yield of the three-dimensional memory is improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor, and particularly relates to a preparation method of a semiconductor structure. BACKGROUND

[0002] With the continuous development of science and technology, the application of semiconductor devices is more and more wide. For example, a semiconductor device can include a transistor, which usually includes a source region, a drain region, a channel region between the source region and the drain region, a gate dielectric layer at least on the channel region, and a gate electrode on the gate dielectric layer. The transistor uses the electric field formed by the gate electrode to control the amount of induced charge in the channel region, thereby changing the state of the channel region, so as to achieve the effect of controlling the current of the drain region.

[0003] With the miniaturization of the feature size of semiconductor devices, the manufacturing cost of semiconductor devices is getting higher and higher, and the yield is getting lower and lower. The development of planar semiconductor devices has reached a bottleneck, and semiconductor devices with a three-dimensional structure, such as three-dimensional NAND flash memory, have become the mainstream development trend. However, the existing semiconductor devices still have many defects, and further improvement and effective improvement of the performance and reliability of related semiconductor devices are needed. SUMMARY

[0004] The purpose of the present application is to provide a preparation method of a semiconductor structure, which can improve the quality of the first alignment mark, prevent the misalignment of the first conductive pillar and the second conductive pillar, and improve the yield of the three-dimensional memory.

[0005] To solve the above technical problems, the present application provides a preparation method of a semiconductor memory, which can at least include:

[0006] A substrate is provided, which includes a first region and a second region;

[0007] A first stack layer is formed on the first region and the second region;

[0008] The first stack layer on the second region is removed to expose the substrate on the second region;

[0009] A first dielectric layer is formed on the second region;

[0010] A plurality of first conductive pillars separated from each other are formed in the first stack layer of the first region, and a plurality of first alignment marks are formed in the first dielectric layer of the second region.

[0011] In one optional example, the top surface of the first dielectric layer can be flush with the top surface of the first stack layer.

[0012] In one optional example, the material of the first dielectric layer can include an oxide.

[0013] In one optional example, after forming the first alignment mark, further comprising:

[0014] forming a second stack layer on the first stack layer of the first region and on the first dielectric layer of the second region;

[0015] etching part of the second stack layer of the second region to form a plurality of grooves in the second stack layer of the second region, the grooves exposing the first alignment mark at the bottom;

[0016] forming a second dielectric layer in the grooves.

[0017] In one optional example, a top surface of the second dielectric layer can be flush with a top surface of the second stack layer.

[0018] In one optional example, after forming the second dielectric layer, further comprising:

[0019] forming a plurality of second conductive pillars in the second stack layer of the first region and forming a second alignment mark in the second dielectric layer of the second region.

[0020] In one optional example, the step of forming the first alignment mark in the first dielectric layer or forming a second alignment mark in the second dielectric layer can comprise:

[0021] etching the first dielectric layer of the second region to form a plurality of first vias in the first dielectric layer, the first vias being arranged in a spaced-apart manner;

[0022] sequentially forming a metal oxide layer, a barrier layer and a metal layer in the first vias, the metal oxide layer, the barrier layer and the metal layer constituting the first alignment mark;

[0023] or,

[0024] etching the second dielectric layer of the second region to form a plurality of second vias in the second dielectric layer, the second vias being arranged in a spaced-apart manner;

[0025] sequentially forming a metal oxide layer, a barrier layer and a metal layer in the second vias, the metal oxide layer, the barrier layer and the metal layer constituting the second alignment mark.

[0026] In one optional example, projections of the first vias and the second vias in a first direction can not coincide, the first direction being a direction perpendicular to the surface of the substrate.

[0027] In one alternative example, the width of the groove in the second direction may be greater than the width of the first or second through hole in the second direction, which is parallel to the surface of the substrate.

[0028] In one alternative example, the first alignment mark and the second alignment mark may comprise grid-like mark bars.

[0029] In one alternative example, the first stacked layer and the second stacked layer may include alternating dielectric and conductive layers.

[0030] In one alternative example, the material of the first dielectric layer may be the same as the material of the second dielectric layer.

[0031] The present invention provides a method for fabricating a semiconductor structure, comprising: providing a substrate, the substrate including a first region and a second region; forming a first stacked layer on the first region and the second region; removing the first stacked layer on the second region to expose the substrate on the second region; forming a first dielectric layer on the second region; forming a plurality of mutually spaced first conductive pillars within the first stacked layer in the first region; and forming a plurality of first alignment marks within the first dielectric layer in the second region. In this invention, before forming the alignment marks (first alignment marks or second alignment marks), the stacked layer (first stacked layer or second stacked layer) on the second region is removed, and then the dielectric layer (first dielectric layer or second dielectric layer) is deposited. By forming the alignment marks in the dielectric layer, which is made of an insulating material, the quality of the alignment marks is improved, the alignment signal quality meets the requirements, the recognizability of the alignment marks is improved, and misalignment of the first conductive pillars and the second conductive pillars is prevented, ultimately improving the yield of the three-dimensional memory. Attached Figure Description

[0032] The accompanying drawings are provided to further illustrate the present application and form part of the specification. They are used together with the following detailed description to explain the present application, but do not constitute a limitation thereof. In the drawings:

[0033] Figure 1 This is a schematic flowchart of a method for fabricating a semiconductor structure according to an embodiment of the present invention;

[0034] Figures 2 to 11 The semiconductor structure fabrication method provided in one embodiment of the present invention follows the process of fabrication. Figure 12 The diagram shows the structure obtained by the direction of the tangent AA shown.

[0035] Figure 12 To utilize Figure 1A top view of the multiple first alignment marks and second alignment marks formed by the method of fabricating the semiconductor structure shown.

[0036] The attached figures are labeled as follows:

[0037] 100 - Substrate, 100A - First region of substrate, 100B - Second region of substrate, 110 - First etch stop layer, 120 - First stacked layer, 121 - Dielectric layer, 122 - Conductive layer, 130 - First photoresist layer, 140 - First dielectric layer, 150 - First hard mask layer, 160 - Second photoresist layer, 101 - First trench, OP1 - First via, 170 - First conductive pillar, 171 - Metal oxide layer, 172 - Barrier layer, 173 - Metal layer, Mark1 - First alignment mark, 180 - Second etch stop layer, 190 - Second stacked layer, 102 - Trench, 200 - Second dielectric layer, 210 - Second hard mask layer, 220 - Third photoresist layer, Mark2 - Second alignment mark.

[0038] In the accompanying drawings, the same parts are referred to by the same reference numerals, and the drawings are not drawn to scale. Detailed Implementation

[0039] To make the technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions of the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. Although exemplary implementation methods of the present invention are shown in the accompanying drawings, it should be understood that the present invention can be implemented in various forms and should not be limited to the embodiments described herein. Rather, these embodiments are provided to enable a more thorough understanding of the present invention and to fully convey the scope of the present invention to those skilled in the art.

[0040] In the embodiments of the present invention, the terms "first," "second," etc., are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be noted that the technical solutions described in the embodiments of the present invention can be arbitrarily combined without conflict.

[0041] For ease of understanding, a first direction and a second direction are defined below, where the first direction is perpendicular to the surface of the substrate 100; and the second direction is parallel to the surface of the substrate 100; while Figures 2 to 12 The code defines directions D1 and D2, where direction D2 corresponds to the horizontal direction and direction D1 corresponds to the vertical direction. Furthermore, directions D1 and D2, as well as the horizontal and vertical directions, are all perpendicular to each other.

[0042] Please refer to Figure 1 As shown, Figure 1 This is a schematic flowchart illustrating a method for fabricating a semiconductor structure according to an embodiment of the present invention.Figure 1 As shown, the method for preparing the semiconductor structure provided in this embodiment of the invention includes at least the following steps:

[0043] Step S101: Provide a substrate, the substrate including a first region and a second region;

[0044] Step S102: A first stacked layer is formed on the first region and the second region;

[0045] Step S103: Remove the first stacked layer on the second region to expose the substrate on the second region;

[0046] Step S104: A first dielectric layer is formed on the second region;

[0047] Step S105: A plurality of mutually separated first conductive pillars are formed within the first stacked layer of the first region, and a plurality of first alignment marks are formed within the first dielectric layer of the second region.

[0048] In the semiconductor structure fabrication method provided by the present invention, before forming alignment marks (first alignment marks or second alignment marks), the stacked layer (first stacked layer or second stacked layer) on the second region is removed, and then a dielectric layer (first dielectric layer or second dielectric layer) is deposited. By forming the alignment marks in the dielectric layer with the material being an isolation material, the quality of the alignment marks is improved, the quality of the alignment signal meets the requirements, the recognizability of the alignment marks is improved, and the misalignment of the first conductive pillar and the second conductive pillar is prevented, ultimately improving the yield of the three-dimensional memory.

[0049] To enable those skilled in the art to easily understand the semiconductor structure fabrication method in the embodiments of this invention, the following will further explain the semiconductor structure fabrication method proposed in this invention with reference to various structural schematic diagrams during the fabrication process. Among them, Figures 2 to 11 The semiconductor structure fabrication method provided in one embodiment of the present invention follows the process of fabrication. Figure 12 The schematic diagram shows the structure obtained by the direction of the tangent AA shown in the figure. Figure 12 To utilize Figure 1 The diagram shows a top view of the multiple first and second alignment marks formed by the fabrication method of the semiconductor structure. The following is a combination of... Figures 2 to 12 The method for fabricating the semiconductor structure provided in this embodiment will be described in detail.

[0050] Please refer to Figure 2Step S101 involves providing a substrate 100 and dividing the substrate 100 into a first region 100A, for example, a chip region for forming transistors, and a second region 100B, for example, a dicing region adjacent to the chip region. In one embodiment, the substrate 100 is any suitable substrate material known in the art, such as a silicon substrate, germanium substrate, silicon-germanium substrate, silicon carbide substrate, epitaxial silicon substrate, silicon-on-insulator (SOI) substrate, or germanium-on-insulator (GOI) substrate, or a substrate made of other suitable materials, but not limited thereto. Those skilled in the art will readily understand that various desired active and / or passive components, such as transistors and / or circuits (not shown), can be further formed on or within the substrate according to actual device requirements, but are not limited thereto.

[0051] Please continue to refer to Figure 2 Step S102: A first etch barrier layer 110 and a first stacked layer 120 are sequentially formed on the surface of the substrate 100 (including the substrate surfaces corresponding to the first region 100A and the second region 100B) using at least one deposition process such as physical vapor deposition, chemical vapor deposition, or atomic layer deposition. In one embodiment, the first etch barrier layer 110 may include a single layer or multiple layers of metal oxide material. Suitable metal oxide materials may include, for example, aluminum oxide, titanium oxide, tantalum oxide, tungsten oxide, or copper oxide, preferably aluminum oxide, but not limited thereto. The first stacked layer 120 includes a plurality of alternately arranged dielectric layers 121 and a plurality of conductive layers 122. Each dielectric layer 121 and the conductive layer 122 above it together form a dielectric-conductive layer pair. The specific number of dielectric-conductive layer pairs can be adjusted according to actual needs and is not limited to... Figure 2 The materials shown are for illustrative purposes only. The dielectric layer 121 may be, for example, a dielectric material such as silicon oxide, silicon nitride, silicon oxynitride, or any combination thereof, but is not limited thereto. The conductive layer 122 may be, for example, a metallic or non-metallic conductive material such as aluminum, titanium, tantalum, tungsten, copper, titanium nitride, titanium carbide, tantalum nitride, titanium tungsten, titanium and titanium nitride, polycrystalline silicon, doped silicon, metal silicides, or any combination thereof, preferably including tungsten, but is not limited thereto.

[0052] Please refer to Figure 3 Step S103: Using the deposition process described above, first form a layer that shields the top surface of the corresponding first stacked layer 120 on the first region 100A and exposes the top surface of the corresponding first stacked layer 120 on the second region 100B. The thickness of this layer is, for example, [missing information]. The left and right photoresist layers 130 are then removed using an etching process, such as at least one of dry etching or wet etching, with the photoresist layer 130 as a mask, to remove the corresponding first stacked layer 120 on the exposed second region 100B, so as to expose the corresponding substrate 100 on the second region 100B, and then the photoresist layer 130 is further removed.

[0053] Please refer to Figure 4 Step S104: A first dielectric layer 140 is formed on the substrate 100 of the second region 100B using at least one of the above deposition processes. In one embodiment, the top surface of the first dielectric layer 140 on the second region 100B is flush with the top surface of the first stacked layer 120 on the first region 100A, and the material of the first dielectric layer 140 is preferably an oxide, such as silicon dioxide. Obviously, in this embodiment of the invention, after forming the corresponding first stacked layer 120, the first alignment mark is not directly formed in the portion of the first stacked layer 120 in the first region 100A. Instead, the portion of the first stacked layer 120 in the second region 100B is removed first, and then the first dielectric layer 140 flush with the top surface of the first stacked layer 120 is formed, which prepares for the subsequent formation of the alignment mark in the dielectric layer.

[0054] Please refer to Figure 5 Following step S104, at least one of the above deposition processes can be used to form a first hard mask layer 150 and a second photoresist layer 160 stacked sequentially from bottom to top on the top surface of the first stacked layer 120 on the first region 100A and the first dielectric layer 140 on the second region 100B, and the second photoresist layer 160 has a plurality of via patterns. In one embodiment, the material of the first hard mask layer 150 may be, for example, a dielectric material such as silicon oxide, silicon nitride, silicon oxynitride, or any combination thereof, but is not limited thereto. The material of the second photoresist layer 160 may be the same as or different from that of the first photoresist layer 130. Furthermore, the size of the corresponding via pattern on the first region 100A and the size of the corresponding via pattern on the second region 100B of the second photoresist layer 160 may be different, for example, the width may be different along the second direction D2. For example, if the corresponding via pattern of the second photoresist layer 160 on the first region 100A is referred to as the first via pattern, and the corresponding via pattern of the second photoresist layer 160 on the second region 100B is referred to as the second via pattern, then the width of the first via pattern in the second direction D2 (for example, about 63 nm) is smaller than the width of the second via pattern in the second direction D2 (for example, about 240 nm), but is not limited thereto.

[0055] Please refer to Figure 6Following step S104, using the second photoresist layer 160 as a mask, the first hard mask layer 150 of the first region 100A and the first stacked layer 120 and the first etch barrier layer 110 below it, as well as the first hard mask layer 150 of the second region 100B and a portion of the first dielectric layer 140 below it, are etched along the first direction D1 to form a plurality of first deep trenches 101 on the first region 100A, and simultaneously form a plurality of first vias OP1 on the second region 100B. Then, the second photoresist layer 160 can be further removed. In one embodiment, the plurality of first deep trenches 101 are subsequently used to form first conductive pillars, and the plurality of first deep trenches 101 can be arranged at intervals along the second direction D2. The plurality of first vias OP1 are subsequently used to form first alignment marks, and the plurality of first vias OP1 can be arranged at intervals along the second direction D2, but are not limited thereto. Obviously, the width of the first deep trenches 101 in the second direction D2 is smaller than the width of the first vias OP1 in the second direction D2.

[0056] Please refer to Figure 7Step S105: Using at least one of the deposition processes described above, a first conductive pillar 170 is formed within the first deep trench 101, and a first alignment mark Mark1 is formed within the first through-hole OP1. Specifically, the first conductive pillar 170 may include a metal oxide layer 171, a barrier layer 172, and a metal layer 173 stacked sequentially. The metal oxide layer 171 is located on the sidewalls and part of the bottom of the first deep trench 101, exemplarily forming two opposing L-shaped structures. The barrier layer 172 is located on the surface of the metal oxide layer 171 and on the substrate 100 exposed at the bottom of the first deep trench 101. The metal layer 173 is located on the barrier layer 172 and fills the remaining space of the first deep trench 101. In one embodiment, the two corners at the bottom of the barrier layer 172 and the metal layer 173 are recessed in a direction close to each other. The material of the metal oxide layer 171 may include hafnium silicon oxide, hafnium oxide, zirconium oxide, tantalum oxide, titanium oxide, etc. Thus, the metal oxide layer 171 has a high dielectric constant, which can improve its insulation performance. The material of the barrier layer 22 may include titanium nitride, tantalum nitride, etc., to separate the metal oxide layer 171 from the metal layer 173, preventing metal ions in the metal layer 173 from diffusing into the metal oxide layer 171, thereby ensuring the insulation performance of the metal oxide layer 171. The material of the metal layer 173 is a metallic material, such as tungsten and its alloys, but not limited thereto. The shape of the first alignment mark Mark1 may be a grid-like mark bar, and it also includes the sequentially stacked metal oxide layer 171, barrier layer 172, and metal layer 173. The material, relative position, and structural shape of each layer of the metal oxide layer 171, barrier layer 172, and metal layer 173 are the same as those of the metal oxide layer 171, barrier layer 172, and metal layer 173 in the first conductive post 170, and will not be described again here.

[0057] Obviously, in this embodiment of the invention, the first alignment mark Mark1 is specifically formed in the first dielectric layer 140, which is an insulating material. Under this setting, the metal layer 170 (e.g., tungsten metal) in the first alignment mark Mark1 can be effectively isolated by the first dielectric layer 140 (e.g., silicon dioxide) to improve the quality of the alignment mark, ensure that the quality of the alignment signal meets the requirements, and improve the recognizability of the alignment mark.

[0058] Please refer to Figure 8Following step S105, the above deposition process can be further utilized to sequentially form a second etch stop layer 180 and a second stacked layer 190 on the top surface of the first stacked layer 120 where the first conductive pillar 170 is formed and on the top surface of the first dielectric layer 140 where the first alignment mark Mark1 is formed. In one embodiment, the material of the second etch stop layer 180 may be the same as the material of the first etch stop layer 110 (e.g., alumina), but is not limited thereto. The material and structure of the second stacked layer 190 may also be the same as the material and structure of the first stacked layer 120, for example, multiple sets of dielectric-conductive layer pairs composed of alternating dielectric layers and conductive layers, and the number of dielectric-conductive layer pairs included in the second stacked layer 190 and the first stacked layer 120 may be adjusted to be the same or different according to actual needs, without limitation. Figure 2 The examples shown are limited to those shown.

[0059] Please refer to Figure 9 Following step S105, an etching process is used to etch away a portion of the second stacked layer 190 and the underlying second etch barrier layer 180 of the second region 100B, thereby forming a plurality of grooves 102 within the second stacked layer 190 and the second etch barrier layer 180 of the second region 100B, with the bottom of the first alignment mark Mark1 exposed. In one embodiment, the width of the groove 102 in the second direction D2 is greater than the width of the first through-hole OP1 in the second direction D2, and also greater than the width of the first alignment mark Mark1 in the second direction D2, in preparation for the subsequent formation of a plurality of second alignment marks Mark2.

[0060] Please refer to Figure 10 Following step S105, the groove 102 is filled using a deposition process to form a second dielectric layer 200 whose top surface is flush with the top surface of the second stacked layer 190 on the first region 100A, and the second dielectric layer 200 is also flush with the top surface of the remaining second stacked layer 190 on the second region 100B. In one embodiment, the material of the second dielectric layer 190 may be the same as the material of the first dielectric layer 140 (e.g., oxide, silicon dioxide), but is not limited thereto.

[0061] Please refer to Figure 11 and combined Figure 12Following step S105, using a deposition process, a second hard mask layer 210 and a third photoresist layer 220 are further deposited sequentially on the first region 100A and the second region 100B. Utilizing the same process used to form the first conductive pillar 170 and the first alignment mark Mark1, a plurality of mutually spaced second conductive pillars (not shown) are further formed within the second stacked layer 190 of the first region 100A, and a plurality of mutually spaced second alignment marks Mark2 are formed within the second dielectric layer 200. Figure 11 (Not shown), the same manufacturing process will not be repeated here.

[0062] It should be specifically noted that the third photoresist layer 220 also contains a plurality of via patterns, some of which are located in the first region 100A and others in the second region 100B. The width of the via pattern in the first region 100A along the second direction D2 is also smaller than the width of the via pattern in the second region 100B along the second direction D2. Specifically, the via pattern in the first region 100A of the third photoresist layer 220 is used to form corresponding second conductive pillars, while the via pattern in the second region 100B is used to form corresponding second vias (not shown, located within the second dielectric layer 200) and a second alignment mark Mark2 filled within the second via. Furthermore, in conjunction with… Figure 12 As shown, the projections of the first through-hole OP1 with the first alignment mark Mark1 and the second through-hole with the second alignment mark Mark2 onto the first direction D1 do not coincide. Clearly, since both the first alignment mark Mark1 and the second alignment mark Mark2 in this embodiment are formed in a dielectric layer made of insulating material, the quality of both the first alignment mark Mark1 and the second alignment mark Mark2 is improved, thereby preventing misalignment of the first conductive post and the second conductive post formed based on the first alignment mark Mark1 and the second alignment mark Mark2.

[0063] In summary, the semiconductor structure fabrication method provided by the present invention includes: providing a substrate, the substrate including a first region and a second region; forming a first stacked layer on the first region and the second region; removing the first stacked layer on the second region to expose the substrate on the second region; forming a first dielectric layer on the second region; forming a plurality of mutually spaced first conductive pillars within the first stacked layer in the first region; and forming a plurality of first alignment marks within the first dielectric layer in the second region. In this invention, before forming the alignment marks (first alignment marks or second alignment marks), the stacked layer (first stacked layer or second stacked layer) on the second region is removed, and then the dielectric layer (first dielectric layer or second dielectric layer) is deposited. By forming the alignment marks in the dielectric layer, which is made of an insulating material, the quality of the alignment marks is improved, ensuring that the alignment signal quality meets the requirements, improving the recognizability of the alignment marks, thereby preventing misalignment of the first conductive pillars and the second conductive pillars, and ultimately improving the yield of the three-dimensional memory.

[0064] It should be noted that, in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0065] The various embodiments in this specification are described in a related manner. Similar or identical parts between embodiments can be referred to mutually. Each embodiment focuses on describing the differences from other embodiments. In particular, the embodiments of apparatus, electronic devices, and computer-readable storage media are basically similar to the method embodiments, and therefore the descriptions are relatively simple; relevant parts can be referred to the descriptions of the method embodiments.

[0066] The above description is merely a preferred embodiment of the present invention and is not intended to limit the scope of protection of the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention are included within the scope of protection of the present invention.

Claims

1. A method for fabricating a semiconductor structure, characterized in that, include: A substrate is provided, the substrate comprising a first region and a second region; A first stacked layer is formed on the first region and the second region; Remove the first stacked layer on the second region to expose the substrate on the second region; A first dielectric layer is formed on the second region; Multiple mutually spaced first conductive pillars are formed within the first stacked layer of the first region, and multiple first alignment marks are formed within the first dielectric layer of the second region; A second stacked layer is formed on the first stacked layer in the first region and on the first dielectric layer in the second region; Etch a portion of the second stacked layer in the second region to form a plurality of grooves with the bottom exposed by the first alignment mark within the second stacked layer in the second region; The second dielectric layer is formed within the groove; Multiple mutually spaced second conductive pillars are formed within the second stacked layer of the first region, and second alignment marks are formed within the second dielectric layer of the second region; The first stacked layer and the second stacked layer include alternating dielectric and conductive layers, and the materials of the first dielectric layer and the second dielectric layer include oxides.

2. The method for preparing the semiconductor structure according to claim 1, characterized in that, The top surface of the first dielectric layer is flush with the top surface of the first stacked layer.

3. The method for preparing the semiconductor structure as described in claim 1, characterized in that, The top surface of the second dielectric layer is flush with the top surface of the second stacked layer.

4. The method for preparing the semiconductor structure according to claim 1, characterized in that, The step of forming the first alignment mark in the first dielectric layer, or forming the second alignment mark in the second dielectric layer, includes: The first dielectric layer in the second region is etched to form a plurality of mutually spaced first vias within the first dielectric layer; A metal oxide layer, a barrier layer, and a metal layer are sequentially formed within the first via, and the metal oxide layer, the barrier layer, and the metal layer constitute the first alignment mark. or, The second dielectric layer in the second region is etched to form a plurality of mutually spaced second vias within the second dielectric layer; A metal oxide layer, a barrier layer, and a metal layer are sequentially formed within the second via, and the metal oxide layer, the barrier layer, and the metal layer constitute the second alignment mark.

5. The method for preparing the semiconductor structure as described in claim 4, characterized in that, The projections of the first through hole and the second through hole do not coincide in a first direction, which is a direction perpendicular to the surface of the substrate.

6. The method for preparing a semiconductor structure as described in claim 5, characterized in that, The width of the groove in the second direction is greater than the width of the first through hole or the second through hole in the second direction, which is parallel to the surface of the substrate.

7. The method for preparing a semiconductor structure as described in claim 4, characterized in that, The first alignment mark and the second alignment mark include grid-like mark bars.

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