Array substrate, display panel and display device

Abstract

The present application relates to an array substrate, a display panel, and a display device. The array substrate has a first region and a second region adjacent to each other, and includes a stacked drive circuit layer and a passivation layer. The drive circuit layer includes a first thin-film transistor located in the first region. The first thin-film transistor includes a first active layer and a first source-drain electrode electrically connected to each other, and the material of the first active layer is an oxide. The passivation layer is located in the first region and the second region and includes a first sub-passivation layer and a second sub-passivation layer. The first sub-passivation layer covers at least the first source-drain electrode and extends from the first region to the second region. The second sub-passivation layer covers the first sub-passivation layer located in the second region. The hydrogen atom content in the material of the first sub-passivation layer is less than the hydrogen atom content in the second sub-passivation layer, and the water penetration rate in the second sub-passivation layer is less than the water penetration rate in the first sub-passivation layer. The present application can effectively reduce the reliability risk of display products.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to an array substrate, a display panel, and a display device. Background Art

[0002] Among display solutions in recent years, organic light-emitting diodes (OLEDs) have been favored by more and more manufacturers due to their advantages such as high contrast, high brightness, high response speed, and low power consumption, which has also promoted the development of OLED in the display field.

[0003] Currently, the main backplane technologies for small-size OLED display products are low-temperature polycrystalline silicon (LTPS) thin-film transistor (TFT) backplane technology and oxide TFT backplane technology. However, due to the high carrier mobility of LTPS, which leads to high leakage current, and the difficulty in controlling the front uniformity of oxide, low-temperature polycrystalline oxide (LTPO) technology has emerged. Because LTPO technology combines the advantages of LTPS and oxides (such as indium gallium zinc oxide, IGZO), it forms an LTPO solution with fast response speed and lower power consumption.

[0004] However, compared with LTPS products, the IGZO thin-film transistors in LTPO products are more sensitive to the surrounding atmosphere (such as hydrogen, water, etc.). Therefore, it is necessary to provide a new LTPO structure to reduce the reliability risk of LTPO products. Summary of the Invention

[0005] The embodiments of the present application provide an array substrate, a display panel, and a display device, which can not only avoid or reduce the negative impact of hydrogen on the electrical properties of the first thin film transistor, but also effectively block the intrusion of water vapor, thereby effectively reducing the reliability risk of the display product.

[0006] To achieve the above-mentioned object, according to a first aspect of the present application, an array substrate is provided, wherein the array substrate has a first region and a second region adjacent to each other; the array substrate comprises:

[0007] a substrate layer, located in the first region and the second region;

[0008] a driving circuit layer, located on one side of the substrate layer and comprising a first thin film transistor located in the first region; the first thin film transistor comprising a first active layer and a first source-drain electrode electrically connected to each other, the first source-drain electrode being located on a side of the first active layer facing away from the substrate layer, the material of the first active layer being an oxide;

[0009] a passivation layer located in the first region and the second region and located on a side of the drive circuit layer facing away from the substrate layer; the passivation layer includes a first sub-passivation layer and a second sub-passivation layer; the first sub-passivation layer at least covers the first source and drain electrodes and extends from the first region to the second region; the second sub-passivation layer covers the first sub-passivation layer located in the second region;

[0010] The content of hydrogen atoms in the material of the first sub-passivation layer is less than that in the second sub-passivation layer, and the water penetration rate in the second sub-passivation layer is less than that in the first sub-passivation layer.

[0011] Optionally, the material of the first sub-passivation layer includes a silicon-oxygen compound, and the material of the second sub-passivation layer includes a silicon-nitride compound.

[0012] Optionally, the driving circuit layer further includes a stacked structure located on the substrate layer, the stacked structure being located in the first region and the second region; the first source-drain electrode being located on a side of the stacked structure facing away from the substrate layer, and the first sub-passivation layer covering the stacked structure and the first source-drain electrode;

[0013] The stacked structure includes multiple insulating layers stacked together, and the first active layer is located between two adjacent insulating layers. The insulating layer adjacent to the first active layer is made of a silicon oxide compound.

[0014] Optionally, the insulating layer disposed adjacent to the first sub-passivation layer is made of a silicon oxide compound.

[0015] Optionally, the first thin film transistor further includes a first gate and a second gate spaced apart from and aligned with the first active layer; the first gate is located on a side of the first active layer close to the substrate layer, and the second gate is located on a side of the first active layer away from the substrate layer;

[0016] At least one insulating layer in the stacked structure is located on the side of the second gate away from the first active layer, and the material of the insulating layer located on the side of the second gate away from the first active layer includes any one or more combinations of nitrogen silicon compounds, silicon oxide compounds, and nitrogen silicon oxide compounds.

[0017] Optionally, the driving circuit layer further includes a first conductor portion located in the second region, the first conductor portion being located between two adjacent insulating layers in the stacked structure; a first opening is provided on a side of the stacked structure facing away from the substrate layer, and the first conductor portion is at least partially exposed in the first opening;

[0018] The driving circuit layer also includes a first transfer electrode, which is located on the side wall of the first opening and the first conductor portion exposed in the first opening, and extends from the side wall of the first opening to the side of the stacking structure away from the substrate layer; the first transfer electrode and the first source-drain electrode are arranged in the same layer; the first sub-passivation layer and the second sub-passivation layer are also stacked in sequence on the first transfer electrode located on the side of the stacking structure away from the substrate layer.

[0019] Optionally, the first transfer electrode forms a second opening in the first opening, and the first sub-passivation layer and the second sub-passivation layer located in the second area are arranged around the second opening; the driving circuit layer also includes a second transfer electrode, which is located on the first transfer electrode exposed by the second opening and extends from the side wall of the second opening to the side of the second sub-passivation layer facing away from the substrate layer.

[0020] Optionally, the array substrate further includes a first flat layer, a second conductor portion, and a second flat layer located in the first region and stacked on a side of the passivation layer facing away from the substrate layer; the first flat layer covers the first source-drain electrode and the first sub-passivation layer, and extends from the first region to cover a portion of the second sub-passivation layer; the second conductor portion is located on the first flat layer and electrically connected to the drive circuit layer; the second flat layer covers the second conductor portion and the first flat layer; the second transfer electrode and the second conductor portion are provided on the same layer;

[0021] The array substrate also includes a third area arranged adjacent to the first area and a third opening located in the third area; the third opening at least penetrates the stacked structure and the first sub-passivation layer; the first flat layer also extends from the first area to the third area and fills the third opening; the second flat layer also extends from the first area to the third area.

[0022] Optionally, the driving circuit layer also includes a second thin film transistor located in the first area, and the second thin film transistor and the first thin film transistor are arranged at intervals from each other; the second thin film transistor includes a second active layer and a second source-drain electrode, the second source-drain electrode and the first source-drain electrode are arranged in the same layer and are electrically connected to the second active layer, and the material of the second active layer includes polycrystalline silicon; the first sub-passivation layer also covers the second source-drain electrode.

[0023] Optionally, the second thin film transistor further includes a third gate and a fourth gate spaced apart from and aligned with the second active layer, the third gate being located on a side of the second active layer close to the substrate layer, and the fourth gate being located on a side of the third gate away from the substrate layer;

[0024] The first thin film transistor includes a gate electrode provided in the same layer as the third gate electrode or the fourth gate electrode.

[0025] According to a second aspect of the present application, a display panel is provided, comprising the array substrate described above, and further comprising a light-emitting layer and an encapsulation layer stacked on the array substrate;

[0026] The light emitting layer is located in the first area and is electrically connected to the driving circuit layer; the encapsulation layer covers the light emitting layer and extends from the first area to cover at least a portion of the array substrate located in the second area.

[0027] Optionally, the display panel also includes a touch layer located on the side of the encapsulation layer away from the light-emitting layer; the touch layer includes at least one touch insulation layer located on the side of the encapsulation layer away from the light-emitting layer, and the touch insulation layer extends from the first area to cover the second sub-passivation layer located in the second area; the material of the touch insulation layer is the same as the material of the second sub-passivation layer.

[0028] According to a third aspect of the present application, a display device is provided, wherein the display device includes the array substrate described above, or the display device includes the display panel described above.

[0029] In the array substrate, display panel and display device of the present application, the passivation layer on the driving circuit layer is divided into two layers, so that the passivation layer includes a first sub-passivation layer close to the driving circuit layer and a second sub-passivation layer away from the driving circuit layer; since the first sub-passivation layer is arranged in the first area and the second area, and the hydrogen content of the material of the first sub-passivation layer is low, the release of hydrogen from the first sub-passivation layer can be avoided or reduced in the high-temperature process, and the first sub-passivation layer can block the hydrogen released by the second sub-passivation layer from diffusing toward the first thin-film transistor, thereby avoiding or reducing the negative impact of hydrogen on the electrical properties of the first thin-film transistor; at the same time, since the second sub-passivation layer is arranged in the second area, and the water penetration rate in the second sub-passivation layer is lower than the water penetration rate in the first sub-passivation layer, when a tiny crack is generated in the second area, the second sub-passivation layer located on the outer layer of the second area can effectively block the invasion of water vapor, thereby preventing water vapor from affecting the threshold voltage of the first thin-film transistor. Therefore, the combination of the first sub-passivation layer and the second sub-passivation layer provided in the present application can not only avoid or reduce the negative impact of hydrogen on the electrical properties of the first thin film transistor, but also effectively block the invasion of water vapor, thereby effectively reducing the reliability risk of the display product.

[0030] Other features and advantages of the present application will be described in detail in the subsequent detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] To more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for describing the embodiments. Obviously, the drawings described below are only some embodiments of the present application. Those skilled in the art can also derive other drawings based on these drawings without inventive effort.

[0032] In order to more completely understand the present application and its beneficial effects, the following description will be given in conjunction with the accompanying drawings, wherein the same drawing numbers represent the same parts in the following description.

[0033] Figure 1 is a schematic cross-sectional structural diagram of an exemplary display panel provided in an embodiment of the present application;

[0034] Figure 2 is a schematic diagram of the cross-sectional structure of an array substrate provided in an embodiment of the present application;

[0035] Figure 3 yes Figure 2 Schematic diagram of the process of preparing the array substrate shown;

[0036] Figures 4 to 10 1 is a schematic structural diagram of a method for preparing an array substrate provided in an embodiment of the present application;

[0037] Figure 11 Schematic diagram of the cross-sectional structure of a display panel provided in an embodiment of the present application. DETAILED DESCRIPTION

[0038] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the embodiments described are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present application.

[0039] like Figure 1 As shown, an exemplary display panel 1 has a display area AA and a non-display area NAA. The display panel 1 includes an array substrate 2, a light-emitting layer 3, an encapsulation layer 4 and a touch layer 5 from bottom to top; the array substrate 2 is located in the display area AA and the non-display area NAA, the light-emitting layer 3 is located in the display area AA, the encapsulation layer 4 is located in the display area AA and part of the non-display area NAA, and the touch layer 5 is located in the display area AA and the non-display area NAA.

[0040] The display panel 1 is manufactured using LTPO backplane technology. The array substrate 2 includes a substrate layer 38, a first barrier layer 6 stacked on the substrate layer 38, a light shielding layer 7, a second barrier layer 8, a buffer layer 9, a first active layer 10, a first gate insulating layer 11, a first metal layer 12, a second gate insulating layer 13, a second metal layer 14, a first interlayer insulating layer 15, a second active layer 16, a third gate insulating layer 17, a third metal layer 18, a second interlayer insulating layer 19, a fourth metal layer 20, a passivation layer 21, a first planarizing layer 22, a fifth metal layer 23, and a second planarizing layer 24. Among them, the first metal layer 12 includes a first gate GE1 located in the display area AA and aligned with the first active layer 10; the second metal layer 14 includes a second gate GE2 aligned with the first gate GE1, a third gate GE3 located in the display area AA and spaced apart from the second gate GE2, and a first conductor portion 25 located in the non-display area NAA, and the third gate GE3 is aligned with the second active layer 16; the third metal layer 18 includes a fourth gate GE4 aligned with the second active layer 16; the fourth metal layer 20 includes a first source-drain electrode SD1 located in the display area AA and electrically connected to the first active layer 10, a second source-drain electrode SD2 located in the display area AA and electrically connected to the second active layer 16, and a first transfer electrode 26 located in the non-display area NAA and electrically connected to the first conductor portion 25; the fifth metal layer 23 includes a second conductor portion 27 located in the display area AA and electrically connected to the first source-drain electrode SD1, and a second transfer electrode 28 located in the non-display area NAA and electrically connected to the first transfer electrode 26.

[0041] The first active layer 10 is made of polycrystalline silicon (Poly), and the second active layer 16 is made of indium gallium zinc oxide (IGZO). The first active layer 10, the first gate electrode GE1, the second gate electrode GE2, and the first source-drain electrode SD1 constitute the LTPS thin-film transistor T1. The third gate electrode GE3, the second active layer 16, the fourth gate electrode GE4, and the second source-drain electrode SD2 constitute the IGZO thin-film transistor T2. A passivation layer 21 overlies the second interlayer insulating layer 19, the first source-drain electrode SD1, and the second source-drain electrode SD2. A light shielding layer 7 is provided corresponding to the LTPS thin-film transistor T1.

[0042] The light-emitting layer 3 includes an anode layer 29 and a pixel definition layer 30 located on the second planar layer 24, and a light-emitting functional layer 31 and a cathode layer 32 located on the anode layer 29. The pixel definition layer 30 is provided with a pixel opening exposing the anode layer 29, and the light-emitting functional layer 31 is located within the pixel opening. The encapsulation layer 4 covers the light-emitting layer 3 and a portion of the array substrate 2. The touch layer 5 includes a first touch insulating layer 33, a first touch electrode layer 34, a second touch insulating layer 35, a second touch electrode layer 36, and a protective layer 37, which are stacked in sequence on the encapsulation layer 4. The first and second touch insulating layers 33 and 35 extend from the display area AA to the non-display area NAA and are stacked on the passivation layer 21 in the non-display area NAA. The array substrate 2 also includes a third transfer electrode 39 located in the non-display area NAA and co-located with the second touch electrode layer 36. The third transfer electrode 39 covers the second transfer electrode 28 and the second touch insulating layer 35.

[0043] Since the active layer of the IGZO thin film transistor T2 is made of IGZO, which is sensitive to hydrogen (H), the passivation layer 21 above the IGZO active layer can only be made of silicon oxide (SiO x However, the inventors have found through research that the contact interface between the passivation layer 21 and the first touch insulating layer 33 in the non-display area NAA is a weak area for water vapor intrusion. The water vapor intrusion route is as follows: Figure 1 As shown in the schematic diagram of the route of area A in FIG; when there are tiny cracks in the non-display area NAA, water vapor will enter the contact interface between the first touch insulating layer 33 and the array substrate 2 (i.e., the contact interface between the first touch insulating layer 33 and the passivation layer 21) along the cracks; and, due to the SiO x The texture of the film is relatively loose, resulting in the SiO x The film layer has a weak inhibitory effect on water vapor intrusion. If SiO x If the film layer is used as the passivation layer 21 , a channel for water vapor to invade will be formed in the passivation layer 21 , thereby causing reliability failure of the display panel 1 .

[0044] In order to solve the above technical problems, the embodiments of the present application provide an array substrate, a display panel and a display device, wherein the passivation layer in the array substrate is divided into layers and zones, so that the non-display area is made of SiO x -SiN x The stacked structure is used as the passivation layer, and the display area uses SiO x The single-layer structure is used as the passivation layer, and the SiO x The film layer is arranged in the same layer; at this time, the passivation layer close to the IGZO thin film transistor side extends from the display area to the non-display area, and its material is silicon oxide compound (SiO x ), can effectively avoid SiN x The hydrogen in the IGZO diffuses into the channel of the IGZO active layer, causing the IGZO to become conductive, thereby avoiding the negative impact of hydrogen on the electrical properties of the IGZO thin film transistor; and the passivation layer away from the side of the IGZO thin film transistor is located in the non-display area, and its material is a nitride silicon compound (SiN x ), due to SiN x The film layer has a denser texture and a stronger inhibitory effect on water vapor intrusion, which can effectively block water vapor intrusion, thereby greatly reducing the reliability risk of the display panel.

[0045] like Figure 2 As shown, an embodiment of the present application provides an array substrate 40 having a first region 41 and a second region 42 arranged adjacent to each other. The array substrate 40 includes a substrate layer 43 and a drive circuit layer 44 and a passivation layer 45 stacked on the substrate layer 43. The substrate layer 43 is located in the first region 41 and the second region 42; the drive circuit layer 44 is located on one side of the substrate layer 43 and includes a first thin film transistor 46 located in the first region 41. The first thin film transistor 46 includes a first active layer 47 and a first source-drain electrode 48 electrically connected to each other. The first source-drain electrode 48 is located on a side of the first active layer 47 facing away from the substrate layer 43. The material of the first active layer 47 is an oxide. The passivation layer 45 is located in the first region 41 and the second region 42, and is located on the side of the drive circuit layer 44 facing away from the substrate layer 43. The passivation layer 45 includes a first sub-passivation layer 45a and a second sub-passivation layer 45b; the first sub-passivation layer 45a at least covers the first source-drain electrode 48 and extends from the first region 41 to the second region 42; the second sub-passivation layer 45b covers the first sub-passivation layer 45a located in the second region 42.

[0046] The hydrogen content of the first sub-passivation layer 45a is less than that of the second sub-passivation layer 45b, and the water penetration rate in the second sub-passivation layer 45b is less than that in the first sub-passivation layer 45a.

[0047] It should be noted that, in the embodiment of the present application, the first area 41 corresponds to the effective display area (AA area) of the display panel 80 , and the second area 42 corresponds to the non-display area (NAA area) of the display panel 80 .

[0048] In some embodiments, the second region 42 is a bonding area used to electrically connect the driver IC to the traces in the driver circuit layer. Since pressure is applied to the second region 42 of the array substrate 40 during the bonding process, this process may cause microcracks in the second region 42, thereby allowing moisture intrusion.

[0049] Because the material of the first active layer 47 is oxide, the first thin-film transistor 46 is an oxide thin-film transistor. Oxide thin-film transistors are relatively sensitive to ambient atmospheres (such as hydrogen and water). If hydrogen diffuses into the channel of the first active layer 47, it will cause the first active layer 47 to become conductive, thereby affecting the electrical properties of the first thin-film transistor 46. If water vapor intrudes, it will cause the threshold voltage of the first thin-film transistor 46 to shift, causing the first thin-film transistor 46 to fail.

[0050] Because the hydrogen content of the material of the first sub-passivation layer 45a is lower than that of the second sub-passivation layer 45b, and because the first sub-passivation layer 45a is located on the side of the second sub-passivation layer 45b closer to the first thin-film transistor 46, hydrogen release from the first sub-passivation layer 45a can be prevented or reduced during high-temperature processes. Furthermore, the first sub-passivation layer 45a can block the diffusion of hydrogen released from the second sub-passivation layer 45b toward the first thin-film transistor 46, thereby preventing or reducing the negative impact of hydrogen on the electrical properties of the first thin-film transistor 46. Furthermore, because the water permeability in the second sub-passivation layer 45b is lower than that in the first sub-passivation layer 45a, and the second sub-passivation layer 45b is located in the second region 42 and on the side of the first sub-passivation layer 45a away from the first thin-film transistor 46, when a microcrack forms in the second region 42, the second sub-passivation layer 45b, located outside the second region 42, can effectively block the intrusion of water vapor, preventing it from affecting the threshold voltage of the first thin-film transistor 46.

[0051] Therefore, the combination of the first sub-passivation layer 45a and the second sub-passivation layer 45b can not only prevent or reduce the negative impact of hydrogen on the electrical properties of the first thin-film transistor 46, but also effectively block the intrusion of water vapor, thereby effectively reducing the reliability risk of the display substrate. In addition, the provision of the first sub-passivation layer 45a in the second region 42 can also prevent excessive etching of the insulating layer in the underlying drive circuit layer 44 when etching the second sub-passivation layer 45b, thereby improving the electrical insulation performance of the underlying insulating layer.

[0052] In some embodiments, the material of the first sub-passivation layer 45 a is a silicon oxide compound, such as silicon oxide, but not limited thereto; the material of the second sub-passivation layer 45 b is a silicon nitrogen compound, such as silicon nitride, but not limited thereto.

[0053] Because the hydrogen content in silicon oxides is lower than that in silicon nitrides, the silicon oxide first sub-passivation layer 45a is positioned in the first region 41 and the second region 42 to effectively block hydrogen, preventing the hydrogen in the silicon nitride from negatively impacting the electrical properties of the first thin-film transistor 46. Furthermore, because silicon nitrides are denser than silicon oxides, the silicon nitride second sub-passivation layer 45b is positioned in the second region 42, where cracks are more likely to form, and further away from the first thin-film transistor 46. This effectively blocks water vapor intrusion at the initial location, preventing it from negatively impacting the threshold voltage of the first thin-film transistor 46.

[0054] In some embodiments, the substrate layer 43 may be a flexible substrate layer or a rigid substrate layer, which is not limited here.

[0055] In a specific embodiment, the substrate layer 43 is a flexible substrate layer, and in this case, the substrate layer 43 can be a single-layer flexible substrate layer or a double-layer flexible substrate layer. The material of the flexible substrate layer includes polyimide (PI), but is not limited thereto.

[0056] In some embodiments, the driving circuit layer 44 further includes a stacked structure 49 located on the substrate layer 43, and the stacked structure 49 is located in the first region 41 and the second region 42. A first source-drain electrode 48 is located on a side of the stacked structure 49 facing away from the substrate layer 43, and a first sub-passivation layer 45a covers the stacked structure 49 and the first source-drain electrode 48. The stacked structure 49 includes multiple insulating layers stacked together, with a first active layer 47 located between two adjacent insulating layers; the insulating layer adjacent to the first active layer 47 is made of a silicon oxide compound.

[0057] Since the first active layer 47 is sensitive to hydrogen, when the material of the insulating layer arranged adjacent to the first active layer 47 is a silicon oxide compound, it can more effectively block hydrogen on the basis of playing an electrical insulating role, thereby further preventing hydrogen from affecting the electrical properties of the first thin film transistor 46.

[0058] In some embodiments, the insulating layer disposed adjacent to the first sub-passivation layer 45a is made of a silicon oxide compound. Typically, the insulating layer disposed adjacent to the first sub-passivation layer 45a is an interlayer insulating layer, and the first drain electrode is disposed on the interlayer insulating layer. The interlayer insulating layer electrically insulates the first source-drain electrode 48 from the gate of the first thin-film transistor 46. When the insulating layer disposed adjacent to the first sub-passivation layer 45a is made of a silicon oxide compound, it can effectively block hydrogen while providing electrical insulation between the first source-drain electrode and the gate of the first thin-film transistor 46, thereby further preventing hydrogen from affecting the electrical properties of the first thin-film transistor 46.

[0059] In some embodiments, the first thin film transistor 46 further includes a first gate 50 and a second gate 51 spaced apart from and aligned with the first active layer 47; the first gate 50 is located on the side of the first active layer 47 close to the substrate layer 43, and the second gate 51 is located on the side of the first active layer 47 away from the substrate layer 43; at least one insulating layer in the stacked structure 49 is located on the side of the second gate 51 away from the first active layer 47, and the material of the insulating layer located on the side of the second gate 51 away from the first active layer 47 includes any one or more combinations of nitrogen silicon compounds, silicon oxide compounds, and nitrogen silicon oxide compounds.

[0060] It can be understood that when a second gate 51 is provided above the first active layer 47, the second gate 51 protects the first active layer 47 and can prevent hydrogen from diffusing into the channel of the first active layer 47. At this time, the material of the insulating layer located on the side of the second gate 51 away from the first active layer 47 is more selective. For example, the material of the insulating layer can be a nitrogen silicon compound, a silicon oxide compound, a nitrogen silicon oxide compound or a combination thereof.

[0061] In some embodiments, the driving circuit layer 44 further includes a first conductor portion 52 located in the second region 42. The first conductor portion 52 is located between two adjacent insulating layers in the stacked structure 49. A first opening 53 is provided on a side of the stacked structure 49 facing away from the substrate layer 43, with the first conductor portion 52 at least partially exposed in the first opening 53. The driving circuit layer 44 further includes a first transfer electrode 54. The first transfer electrode 54 is located on the sidewalls of the first opening 53 and on the first conductor portion 52 exposed in the first opening 53, and extends from the sidewalls of the first opening 53 to the side of the stacked structure 49 facing away from the substrate layer 43. The first transfer electrode 54 and the first source-drain electrode 48 are disposed in the same layer. The first sub-passivation layer 45a and the second sub-passivation layer 45b are also stacked in sequence on the first transfer electrode 54 located on the side of the stacked structure 49 facing away from the substrate layer 43.

[0062] It can be understood that the first switching electrode 54 is used to transmit the electrical signal on the driving circuit located in the first area 41 through the first conductor portion 52, or the first switching electrode 54 is used to input the electrical signal to the driving circuit located in the first area 41 through the first conductor portion 52.

[0063] The presence of the first opening 53 in the stacked structure 49 in the second region 42 increases the risk of cracks forming in the second region 42, thereby increasing the risk of water vapor intrusion. In the embodiment of the present application, the first sub-passivation layer 45a and the second sub-passivation layer 45b in the second region 42 are stacked on the first transfer electrode 54 located on the side of the stacked structure 49 facing away from the substrate layer 43. This increases the path for water vapor intrusion, which helps enhance the water vapor barrier effect of the passivation layer 45, thereby reducing the risk of water vapor intrusion.

[0064] In some embodiments, the first transfer electrode 54 forms a second opening 55 in the first opening 53, and the first sub-passivation layer 45a and the second sub-passivation layer 45b located in the second region 42 are disposed around the second opening 55. The driving circuit layer 44 further includes a second transfer electrode 56, which is located on the first transfer electrode 54 exposed by the second opening 55 and extends from the sidewall of the second opening 55 to the side of the second sub-passivation layer 45b facing away from the substrate layer 43.

[0065] As can be understood, the second transfer electrode 56 is electrically connected to the first transfer electrode 54, and the second transfer electrode 56 covers the edge of the second sub-passivation layer 45b disposed around the second opening 55. This design sandwiches the edges of the first sub-passivation layer 45a and the second sub-passivation layer 45b between the first transfer electrode 54 and the second transfer electrode 56, thereby preventing the edges of the first sub-passivation layer 45a and the second sub-passivation layer 45b near the second opening 55 from being exposed. This also extends the path for water vapor intrusion, thereby further enhancing the water vapor barrier effect.

[0066] In some embodiments, the array substrate 40 further includes a first planar layer 57, a second conductor portion 58, and a second planar layer 59 located in the first region 41 and stacked on the side of the passivation layer 45 facing away from the substrate layer 43. The first planar layer 57 covers the first source-drain electrode 48 and the first sub-passivation layer 45a and extends from the first region 41 to cover a portion of the second sub-passivation layer 45b. The second conductor portion 58 is located on the first planar layer 57 and is electrically connected to the drive circuit layer 44. The second planar layer 59 covers the second conductor portion 58 and the first planar layer 57. The second transfer electrode 56 and the second conductor portion 58 are provided on the same layer.

[0067] It can be understood that the first planar layer 57 covers the side of the second sub-passivation layer 45 b close to the first region 41 , which can prevent moisture from invading from the side of the second sub-passivation layer 45 b close to the first region 41 .

[0068] The array substrate 40 also includes a third region 60 arranged adjacent to the first region 41 and a third opening 61 located in the third region 60; the third opening 61 at least penetrates the stacking structure 49 and the first sub-passivation layer 45a; the first flat layer 57 also extends from the first region 41 to the third region 60 and fills the third opening 61; the second flat layer 59 also extends from the first region 41 to the third region 60.

[0069] Specifically, the third region 60 may be a foldable region, for example, a bending region in the non-display area, but is not limited thereto. When the third region 60 is a foldable region, the first planar layer 57 is made of a flexible material, such as an organic planar material. Filling the third opening 61 with the first planar layer 57 can improve the bending performance of the third region 60.

[0070] Of course, the third region 60 can also be a non-bending region in the effective display area, and the third region 60 is located between two adjacent second regions 42. In order to improve the transmittance of the third region 60, a material with high transmittance can be selected as the material of the first flat layer 57.

[0071] It can be understood that the third area 60 can be located in the effective display area or in the non-display area, and this application does not limit this. Moreover, the embodiment of this application does not specifically limit the function of the third area 60 and the material of the first flat layer 57. Those skilled in the art can select suitable materials as the material of the first flat layer 57 according to actual needs.

[0072] In some embodiments, the bottom of the third opening 61 may further extend toward the interior of the substrate layer 43 .

[0073] In some embodiments, as Figure 2 As shown, the driving circuit layer 44 also includes a second thin film transistor 62 located in the first area 41, and the second thin film transistor 62 and the first thin film transistor 46 are arranged at intervals from each other; the second thin film transistor 62 includes a second active layer 63 and a second source-drain electrode 64, and the second source-drain electrode 64 and the first source-drain electrode 48 are arranged in the same layer and are electrically connected to the second active layer 63, and the material of the second active layer 63 includes polycrystalline silicon; the first sub-passivation layer 45a also covers the second source-drain electrode 64.

[0074] It can be understood that the second thin film transistor 62 can be an LTPS thin film transistor, that is, the array substrate 40 in the embodiment of the present application is an LTPO array substrate.

[0075] In some embodiments, the second thin-film transistor 62 further includes a third gate 65 and a fourth gate 66 spaced apart from and aligned with the second active layer 63. The third gate 65 is located on a side of the second active layer 63 close to the substrate layer 43, and the fourth gate 66 is located on a side of the third gate 65 facing away from the substrate layer 43. The first thin-film transistor 46 includes a gate disposed on the same layer as the third gate 65 or the fourth gate 66. This design saves a metal layer, simplifies the manufacturing process of the array substrate 40, and reduces manufacturing costs.

[0076] In a specific embodiment, the stacked structure 49 includes a first blocking layer 67, a second blocking layer 68, a buffer layer 69, a first gate insulating layer 70, a second gate insulating layer 71, a first interlayer insulating layer 72, a third gate insulating layer 73 and a second interlayer insulating layer 74 stacked on the substrate layer 43.

[0077] Specifically, the second active layer 63 is located between the buffer layer 69 and the first gate insulating layer 70, the third gate 65 is located between the first gate insulating layer 70 and the second gate insulating layer 71, the first gate 50, the fourth gate 66 and the first conductor portion 52 are located between the second gate insulating layer 71 and the first interlayer insulating layer 72, the first active layer 47 is located between the first interlayer insulating layer 72 and the third gate insulating layer 73, the second gate 51 is located between the third gate insulating layer 73 and the second interlayer insulating layer 74, and the first source-drain electrode 48 and the second source-drain electrode 64 are located between the second interlayer insulating layer 74 and the first sub-passivation layer 45a.

[0078] Specifically, the first opening 53 penetrates the first interlayer insulating layer 72 , the third gate insulating layer 73 , and the second interlayer insulating layer 74 , and exposes at least a portion of the first conductor portion 52 .

[0079] In some embodiments, the driving circuit layer 44 further includes a light shielding layer 75 located between the first barrier layer 67 and the second barrier layer 68 and corresponding to the second thin film transistor 62. The light shielding layer 75 is used to block external light from entering the second thin film transistor 62 from the bottom. The material of the light shielding layer 75 can be made of a black light shielding material, such as a black light shielding metal or a black organic material.

[0080] In some embodiments, the first active layer 47 includes a first channel portion and first ohmic contacts located on opposite sides of the first channel portion and disposed in the same layer. The source and drain electrodes in the first source-drain electrode are electrically connected to the first ohmic contacts located on opposite sides of the first channel portion, respectively. The second active layer 63 includes a second channel portion and second ohmic contacts located on opposite sides of the second channel portion and disposed in the same layer. The source and drain electrodes in the second source-drain electrode are electrically connected to the second ohmic contacts located on opposite sides of the second channel portion, respectively.

[0081] In some embodiments, the materials of the first interlayer insulating layer 72 and the third gate insulating layer 73 are silicon oxide compounds, which can effectively prevent hydrogen from diffusing into the first active layer 47 .

[0082] In some embodiments, the material of the second interlayer insulating layer 74 is silicon oxide, which can enhance the barrier effect against hydrogen.

[0083] In some embodiments, the materials of the first blocking layer 67 , the second blocking layer 68 , the buffer layer 69 , the first gate insulating layer 70 and the second gate insulating layer 71 may be silicon nitride, silicon oxide, silicon nitride oxide or a combination thereof, but are not limited thereto.

[0084] In one specific embodiment, the buffer layer 69 and the first gate insulating layer 70 disposed adjacent to the second active layer 63 may be made of a silicon nitride compound. Because silicon nitride compounds have a high hydrogen content, they can release hydrogen at high temperatures. This allows hydrogen replenishment of the second active layer 63 fabricated using low-temperature polysilicon technology, thereby meeting the requirements of low-temperature polysilicon technology and ensuring the performance of the second active layer 63. Furthermore, because the first gate 50 and the second gate insulating layer 71, made of a silicon oxide compound, are disposed between the first active layer 47 and the first gate insulating layer 70, the use of a silicon nitride compound as the material for the first gate insulating layer 70 does not negatively impact the first active layer 47.

[0085] In some embodiments, the materials of the first gate 50, the second gate 51, the third gate 65 and the fourth gate 66 can be molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti), etc., or an alloy of at least two or more metals, or a multilayer thin film structure composed of at least two or more metals.

[0086] In some embodiments, the materials of the first source-drain electrode and the second source-drain electrode may be copper, molybdenum, molybdenum-titanium alloy, or titanium-aluminum-titanium triple-layer metal, but are not limited thereto.

[0087] In the embodiment of the present application, the passivation layer 45 on the driving circuit layer 44 is divided into two layers, so that the passivation layer 45 includes a first sub-passivation layer 45a close to the driving circuit layer 44 and a second sub-passivation layer 45b away from the driving circuit layer 44. Since the first sub-passivation layer 45a is arranged in the first area 41 and the second area 42, and the hydrogen content of the material of the first sub-passivation layer 45a is low, the release of hydrogen from the first sub-passivation layer 45a can be avoided or reduced during the high-temperature process, and the first sub-passivation layer 45a can block the release of hydrogen from the second sub-passivation layer 45b. The released hydrogen diffuses toward the first thin-film transistor 46, thereby avoiding or reducing the negative impact of hydrogen on the electrical properties of the first thin-film transistor 46. At the same time, because the second sub-passivation layer 45b is disposed in the second region 42, and the water penetration rate in the second sub-passivation layer 45b is lower than the water penetration rate in the first sub-passivation layer 45a, when a microcrack forms in the second region 42, the second sub-passivation layer 45b located outside the second region 42 can effectively block the intrusion of water vapor, thereby preventing the water vapor from affecting the threshold voltage of the first thin-film transistor 46. Therefore, the combination of the first sub-passivation layer 45a and the second sub-passivation layer 45b provided in the embodiment of the present application can not only avoid or reduce the negative impact of hydrogen on the electrical properties of the first thin-film transistor 46, but also effectively block the intrusion of water vapor, thereby effectively reducing the reliability risk of the display substrate.

[0088] like Figure 3 As shown, the embodiment of the present application further provides a method for preparing the array substrate 40 described in the above embodiment, and the preparation method includes steps S301 to S307.

[0089] S301: forming a driving circuit layer on a substrate layer; wherein the substrate layer includes a first region and a second region adjacent to each other, the driving circuit layer includes a first thin film transistor and a second thin film transistor located in the first region, and a first conductor portion, a first opening and a first transfer electrode located in the second region, the first conductor portion being exposed in the first opening, the first transfer electrode being located at least on a side wall and a bottom of the first opening, and being electrically connected to the first conductor portion.

[0090] like Figure 4 As shown, the substrate layer 43 includes a first area 41 and a second area 42 arranged adjacent to each other, the driving circuit layer 44 includes a first thin film transistor 46 and a second thin film transistor 62 located in the first area 41, and a first conductor portion 52, a first opening 53 and a first transfer electrode 54 located in the second area 42, the first conductor portion 52 is exposed in the first opening 53, and the first transfer electrode 54 is located at least on the side wall and bottom of the first opening 53, and is electrically connected to the first conductor portion 52.

[0091] The driving circuit layer 44 further includes a stacked structure 49 located in the first region 41 and the second region 42. The source and drain electrodes of the first thin-film transistor 46 and the second thin-film transistor 62 are located on the stacked structure 49. The first opening 53 is formed on a side of the stacked structure 49 away from the substrate layer 43. The first transfer electrode 54 is disposed on the same layer as the source and drain electrodes of the first thin-film transistor 46 and the second thin-film transistor 62.

[0092] The specific structure of the driving circuit layer 44 can be referred to the description of the aforementioned embodiment and will not be repeated here.

[0093] S302: forming a first sub-passivation layer and a second sub-passivation layer on the entire surface of the driving circuit layer; the first sub-passivation layer continuously covers the first thin film transistor, the second thin film transistor and the first transfer electrode, and the second sub-passivation layer completely covers the first sub-passivation layer, the material of the first sub-passivation layer is a silicon oxide compound, and the material of the second sub-passivation layer is a nitrogen silicon compound.

[0094] like Figure 5 As shown, the first sub-passivation layer 45a and the second sub-passivation layer 45b sequentially cover the entire surface. Figure 4 On the driving circuit layer 44 shown.

[0095] S303: using a half-tone mask to form a photoresist layer on the surface of the second sub-passivation layer; the photoresist layer includes a fourth opening corresponding to the first opening, and the thickness of the photoresist layer in the first area is less than the thickness of the photoresist layer in the second area.

[0096] like Figure 6 As shown, the photoresist layer 76 is located on the second sub-passivation layer 45 b . The photoresist layer 76 includes a fourth opening 77 corresponding to the first opening 53 . The thickness of the photoresist layer 76 in the first region 41 is smaller than that in the second region 42 .

[0097] S304: performing an etching process on the second sub-passivation layer located in the first opening to remove the second sub-passivation layer located in the first opening.

[0098] like Figure 7 As shown, through the first etching process, the second sub-passivation layer 45b located in the first opening 53 is etched away to expose the first sub-passivation layer 45a.

[0099] S305: performing an ashing process on the photoresist layer to remove the photoresist layer located in the first region.

[0100] like Figure 8 As shown, during the ashing process of the photoresist layer 76 , the thickness of the photoresist layer 76 decreases as a whole until the photoresist layer 76 located in the first region 41 is completely removed, and only the photoresist layer 76 located in the second region 42 remains.

[0101] S306 : performing an etching process on the first sub-passivation layer in the first opening and the second sub-passivation layer in the first region simultaneously to remove the first sub-passivation layer in the first opening and the second sub-passivation layer in the second region.

[0102] like Figure 9 As shown, through the second etching process, the first sub-passivation layer 45a located in the first opening 53 and the second sub-passivation layer 45b located in the second region 42 are removed, exposing the first switching electrode 54 located in the first opening 53 and the first sub-passivation layer 45a located in the first region 41.

[0103] S307: removing the photoresist layer located in the second region, forming a first sub-passivation layer located in the first region and the second region, and a second sub-passivation layer located in the second region.

[0104] like Figure 10 As shown, after the photoresist layer 76 is removed, a first sub-passivation layer 45 a located in the first region 41 and the second region 42 and a second sub-passivation layer 45 b located in the second region 42 are formed, and the first sub-passivation layer 45 a and the second sub-passivation layer 45 b constitute the passivation layer 45 .

[0105] Combine Figure 2 It can be seen that after step S307, the preparation method further includes the following steps:

[0106] Performing a patterning process on the driving circuit layer 44 and the passivation layer 45 , removing the stacked structure 49 and the first sub-passivation layer 45 a in a predetermined area (corresponding to the third area), and forming a third opening 61 ;

[0107] The first flat layer 57 is laid on the entire surface, and the first flat layer 57 is filled in the third opening 61;

[0108] Performing a patterning process on the first planarization layer 57 to remove a portion of the first planarization layer 57 in the second region 42 , so that the first planarization layer 57 covers an edge of the second sub-passivation layer 45 b in the second region 42 ;

[0109] forming a second conductor portion 58 on the first flat layer 57 and a second via electrode 56 in the second opening 55; and

[0110] A patterned second flat layer 59 is formed so that the second flat layer 59 covers the first flat layer 57; the resulting array substrate 40 is as shown in FIG. Figure 2 shown.

[0111] In the embodiment of the present application, the use of a half-tone mask process to manufacture the double-layer passivation layer 45 in the array substrate 40 can save one photomask process, which is beneficial to simplifying the manufacturing process of the array substrate 40 .

[0112] like Figure 11 As shown, an embodiment of the present application further provides a display panel 80, which includes the array substrate 40 described in the aforementioned embodiment, and a light-emitting layer 78 and an encapsulation layer 79 stacked on the array substrate 40; wherein the light-emitting layer 78 is located in the first area 41 and is electrically connected to the driving circuit layer 44; the encapsulation layer 79 covers the light-emitting layer 78 and extends from the first area 41 to cover at least a portion of the array substrate 40 located in the second area 42.

[0113] Specifically, the display panel 80 includes a display area and a non-display area, wherein the display area at least covers the first area 41, and the non-display area at least covers the second area 42. In other words, the second area 42 may be a portion of the non-display area or the entire non-display area.

[0114] In some embodiments, the light-emitting layer 78 includes an anode layer 81 and a pixel definition layer 82 located on the array substrate 40 , and a light-emitting functional layer 83 and a cathode layer 84 located on the anode layer 81 .

[0115] In some embodiments, the anode layer 81 , the light-emitting functional layer 83 , and the cathode layer 84 in the light-emitting functional layer 83 constitute a plurality of light-emitting devices, and the light-emitting devices include, but are not limited to, OLED devices.

[0116] Specifically, a plurality of pixel openings are provided on the pixel definition layer 82 , and the light-emitting functional layer 83 and the cathode layer 84 are stacked on the anode layer 81 in the pixel openings.

[0117] In some embodiments, a support layer is provided on the pixel definition layer 82 , and the support layer and the pixel definition layer 82 can be formed in the same process, for example, by using a halftone mask to form the pixel definition layer 82 and the support layer.

[0118] In some embodiments, the pixel definition layer 82 and the anode layer 81 are arranged on the side of the second planar layer 59 away from the first planar layer 57, and the anode layer 81 is electrically connected to the second conductor portion 58 through a via hole passing through the second planar layer 59, thereby achieving electrical connection with the second source and drain electrode 64 of the second thin film transistor 62.

[0119] In some embodiments, the encapsulation layer 79 covers the second planar layer 59 and the light-emitting layer 78 . The encapsulation layer 79 is located in the first region 41 and extends from the first region 41 to the second region 42 .

[0120] In some embodiments, the encapsulation layer 79 includes a thin film encapsulation (TFE) layer, but is not limited thereto.

[0121] In some embodiments, the edges of the first planar layer 57 and the second planar layer 59 in the second region 42 are aligned, and the edge of the encapsulation layer 79 in the second region 42 is also aligned with the edge of the second planar layer 59. This design allows the patterning of the first planar layer 57, the second planar layer 59, and the encapsulation layer 79 to be completed in the same process.

[0122] In some embodiments, the display panel 80 also includes a touch layer 85 located on the side of the encapsulation layer 79 away from the light-emitting layer 78; the touch layer 85 includes at least one touch insulation layer located on the side of the encapsulation layer 79 away from the light-emitting layer 78, and the touch insulation layer extends from the first area 41 to cover the second sub-passivation layer 45b located in the second area 42; the material of the touch insulation layer is the same as the material of the second sub-passivation layer 45b.

[0123] In a specific embodiment, the touch layer 85 includes a first touch insulation layer 86, a first touch electrode layer 87, a second touch insulation layer 88, a second touch electrode layer 89 and a protective layer 90 stacked on the encapsulation layer 79; wherein the first touch insulation layer 86 and the second touch insulation layer 88 extend from the first area 41 to the second area 42, and are stacked and covered on the second sub-passivation layer 45b located in the second area 42; the first touch electrode layer 87 and the second touch electrode layer 89 are located in the first area 41, and the second touch electrode layer 89 is electrically connected to the first touch electrode layer 87 through a via hole penetrating the second touch insulation layer 88.

[0124] It is understandable that the embodiments of the present application do not limit the touch type, and the above description of the structure of the touch electrode is only for illustrative purposes.

[0125] In some embodiments, the first touch insulating layer 86 and the second touch insulating layer 88 are made of a silicon nitride compound. Because the first touch insulating layer 86 and the second touch insulating layer 88 are located above the passivation layer 45 in the second region 42 and are made of a silicon nitride compound, which has a better water barrier effect, this design can more effectively block water vapor intrusion.

[0126] In some embodiments, the display panel 80 further includes a third transfer electrode 91 located in the second region 42. The third transfer electrode 91 covers the second transfer electrode 56 and a portion of the second touch insulation layer 88. The third transfer electrode 91 is provided on the same layer as either the first touch electrode layer 87 or the second touch electrode layer 89. This design ensures that the edges of the first and second touch insulation layers 86 and 88 near the second opening 55 are covered by the third transfer electrode 91. Furthermore, the edges of the first and second touch insulation layers 86 and 88 near the second opening 55 are sandwiched between the second transfer electrode 56 and the third transfer electrode 91, further extending the water vapor intrusion path and helping to further prevent water vapor intrusion.

[0127] In the embodiment of the present application, since the first touch insulating layer 86 and the second touch insulating layer 88 of the second area 42 (i.e., the non-display area) of the display panel 80 are stacked in sequence on the second sub-passivation layer 45b, and the materials of the first touch insulating layer 86, the second touch insulating layer 88, and the second sub-passivation layer 45b are the same, the materials of the three are all strong water-insulating materials, which can effectively prevent water vapor from entering the drive circuit layer 44, avoiding the negative impact of water vapor on the reliability of the oxide thin film transistor. In addition, the first sub-passivation layer 45a is located on the side of the second sub-passivation layer 45b close to the drive circuit layer 44, and the material of the first sub-passivation layer 45a is a hydrogen-isolating material, which can effectively avoid the negative impact of hydrogen on the electrical properties of the oxide thin film transistor. Therefore, the electrical stability of the oxide thin film transistor in the display panel 80 provided in the embodiment of the present application can be greatly improved, and the reliability risk of the panel can be greatly reduced.

[0128] The present application further provides a display device, which includes the array substrate 40 described in the above embodiment, or the display device includes the display panel 80 described in the above embodiment.

[0129] In some embodiments, the display device further includes a housing, which is at least located on the side of the substrate layer 43 of the array substrate 40 away from the driving circuit layer 44 , or at least located on the side of the substrate layer 43 of the display panel 80 away from the driving circuit.

[0130] In the embodiment of the present application, since the array substrate 40 and the display panel 80 provided in the aforementioned embodiment have strong barrier capabilities against hydrogen and water vapor, the performance and reliability of the display device can be effectively improved.

[0131] In the description of this application, the terms "first" and "second" are used for descriptive purposes only and should not be understood to indicate or imply relative importance or implicitly specify the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more features. In the description of this application, "plurality" means two or more, unless otherwise specifically defined.

[0132] In the above embodiments, the description of each embodiment has its own focus. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0133] The embodiments, implementation methods and related technical features of the present application can be combined and replaced with each other unless there is any conflict.

[0134] The above are merely preferred embodiments of the present application and do not constitute any form of limitation to the present application. However, any simple modifications, equivalent changes, and modifications made to the above embodiments based on the technical essence of the present application without departing from the content of the technical solution of the present application are still within the scope of the technical solution of the present application.

Claims

1. An array substrate, characterized in that: The array substrate has a first area and a second area adjacent to each other; the array substrate includes: a substrate layer, located in the first region and the second region; a driving circuit layer, located on one side of the substrate layer and comprising a first thin film transistor located in the first region; the first thin film transistor comprising a first active layer and a first source-drain electrode electrically connected to each other, the first source-drain electrode being located on a side of the first active layer facing away from the substrate layer, the material of the first active layer being an oxide; a passivation layer located in the first region and the second region and located on a side of the drive circuit layer facing away from the substrate layer; the passivation layer includes a first sub-passivation layer and a second sub-passivation layer; the first sub-passivation layer at least covers the first source and drain electrodes and extends from the first region to the second region; the second sub-passivation layer covers the first sub-passivation layer located in the second region; The content of hydrogen atoms in the material of the first sub-passivation layer is less than that in the second sub-passivation layer, and the water penetration rate in the second sub-passivation layer is less than that in the first sub-passivation layer.

2. The array substrate according to claim 1, wherein: The material of the first sub-passivation layer includes silicon oxide compound, and the material of the second sub-passivation layer includes silicon nitrogen compound.

3. The array substrate according to claim 1, wherein: The driving circuit layer further includes a stacked structure located on the substrate layer, the stacked structure being located in the first region and the second region; the first source-drain electrode being located on a side of the stacked structure away from the substrate layer, and the first sub-passivation layer covering the stacked structure and the first source-drain electrode; The stacked structure includes multiple insulating layers stacked together, and the first active layer is located between two adjacent insulating layers; The insulating layer disposed adjacent to the first active layer is made of a material including silicon oxide.

4. The array substrate according to claim 3, wherein: The insulating layer disposed adjacent to the first sub-passivation layer is made of a material comprising silicon oxide.

5. The array substrate according to claim 3, wherein: The first thin film transistor further includes a first gate and a second gate spaced apart from and aligned with the first active layer; the first gate is located on a side of the first active layer close to the substrate layer, and the second gate is located on a side of the first active layer away from the substrate layer; At least one insulating layer in the stacked structure is located on the side of the second gate away from the first active layer, and the material of the insulating layer located on the side of the second gate away from the first active layer includes any one or more combinations of nitrogen silicon compounds, silicon oxide compounds, and nitrogen silicon oxide compounds.

6. The array substrate according to claim 3, wherein: The driving circuit layer further includes a first conductor portion located in the second region, the first conductor portion being located between two adjacent insulating layers in the stacked structure; a first opening is provided on a side of the stacked structure facing away from the substrate layer, and the first conductor portion is at least partially exposed in the first opening; The driving circuit layer further includes a first switching electrode, which is located on a sidewall of the first opening and on the first conductor portion exposed in the first opening, and extends from the sidewall of the first opening to a side of the stacked structure facing away from the substrate layer; The first transfer electrode and the first source-drain electrode are arranged in the same layer; The first sub-passivation layer and the second sub-passivation layer are stacked in sequence on the first switching electrode located on a side of the stack structure away from the substrate layer.

7. The array substrate according to claim 6, wherein: The first transfer electrode forms a second opening in the first opening, and the first sub-passivation layer and the second sub-passivation layer located in the second area are arranged around the second opening; the driving circuit layer also includes a second transfer electrode, which is located on the first transfer electrode exposed by the second opening and extends from the side wall of the second opening to the side of the second sub-passivation layer facing away from the substrate layer.

8. The array substrate according to claim 7, wherein: The array substrate further includes a first flat layer, a second conductor portion, and a second flat layer located in the first region and stacked on a side of the passivation layer facing away from the substrate layer; the first flat layer covers the first source-drain electrode and the first sub-passivation layer and extends from the first region to cover a portion of the second sub-passivation layer; the second conductor portion is located on the first flat layer and electrically connected to the drive circuit layer; the second flat layer covers the second conductor portion and the first flat layer; the second transfer electrode and the second conductor portion are provided on the same layer; The array substrate also includes a third area arranged adjacent to the first area and a third opening located in the third area; the third opening at least penetrates the stacked structure and the first sub-passivation layer; the first flat layer also extends from the first area to the third area and fills the third opening; the second flat layer also extends from the first area to the third area.

9. The array substrate according to any one of claims 1 to 8, wherein: The driving circuit layer also includes a second thin film transistor located in the first area, and the second thin film transistor and the first thin film transistor are arranged to be spaced apart from each other; the second thin film transistor includes a second active layer and a second source-drain electrode, the second source-drain electrode and the first source-drain electrode are arranged in the same layer and are electrically connected to the second active layer, and the material of the second active layer includes polycrystalline silicon; the first sub-passivation layer also covers the second source-drain electrode.

10. The array substrate according to claim 9, wherein: The second thin film transistor further includes a third gate and a fourth gate spaced apart from and aligned with the second active layer, the third gate being located on a side of the second active layer close to the substrate layer, and the fourth gate being located on a side of the third gate away from the substrate layer; The first thin film transistor includes a gate electrode provided in the same layer as the third gate electrode or the fourth gate electrode.

11. A display panel, characterized in that: The display panel comprises the array substrate according to any one of claims 1 to 10, wherein the display panel further comprises a light-emitting layer and an encapsulation layer stacked on the array substrate; The light emitting layer is located in the first area and is electrically connected to the driving circuit layer; The encapsulation layer covers the light emitting layer and extends from the first area to cover at least a portion of the array substrate located in the second area.

12. The display panel according to claim 11, wherein: The display panel also includes a touch layer located on the side of the encapsulation layer away from the light-emitting layer; the touch layer includes at least one touch insulation layer located on the side of the encapsulation layer away from the light-emitting layer, and the touch insulation layer extends from the first area to cover the second sub-passivation layer located in the second area; the material of the touch insulation layer is the same as the material of the second sub-passivation layer.

13. A display device, characterized in that: The display device includes the array substrate according to any one of claims 1 to 10, or the display device includes the display panel according to claim 11 or 12.

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