Semiconductor device

Abstract

A semiconductor device (1) includes: a semiconductor layer (40); a first vertical MOS transistor (10) and a second vertical MOS transistor (20) formed in the semiconductor layer (40); a metal layer (30) in contact with the back surface side of the semiconductor layer (40) over the entire surface; and a support body (42) joined to the back surface side of the metal layer (30) via an adhesive (41); in plan view, the support body (42) is larger in area than the semiconductor layer (40) and contains the semiconductor layer (40) therein; the thickness of the support body (42) is larger than the thickness of the semiconductor layer (40); in a cross section of the semiconductor device (1) including the center of the semiconductor layer (40) and the outer periphery of the semiconductor layer (40) in plan view, the height of the adhesive (41) along the side surface of the semiconductor layer (40) is lower than the upper surface of the semiconductor layer (40); and in the cross section, the semiconductor chip (2) excluding the support body (42) and the adhesive (41) from the semiconductor device (1) is curved in a convex shape toward the direction of the support body (42).

Description

TECHNICAL FIELD

[0001] The present disclosure relates to a semiconductor device. BACKGROUND

[0002] For the purpose of protecting a lithium ion battery from overcharge or / and overdischarge, a vertical MOS transistor of a dual structure capable of controlling bidirectional conduction with one chip is used.

[0003] PRIOR ART DOCUMENTS

[0004] PATENT DOCUMENTS

[0005] Patent Document 1: US Patent No. 4616413 Specification SUMMARY

[0006] PROBLEMS TO BE SOLVED BY THE INVENTION

[0007] In order to reduce the on-resistance of the vertical MOS transistor of the dual structure, the vertical MOS transistor of the dual structure (hereinafter, the vertical MOS transistor of the dual structure will also be referred to as "semiconductor chip") is preferably configured to have a larger area in planar view and a thinner semiconductor substrate. However, in such a configuration, the warpage of the semiconductor chip becomes large, and in addition, the strength of the semiconductor chip decreases. In Patent Document 1, a configuration in which a printed circuit board is adhered to a rigid metal plate via a conductive adhesive is disclosed.

[0008] Therefore, an object of the present disclosure is to provide a semiconductor device that, in a configuration in which a rigid metal plate is adhered via a conductive adhesive, has a vertical MOS transistor of a dual structure that can make the area of the rigid metal plate in planar view as small as possible.

[0009] MEANS FOR SOLVING THE PROBLEMS

[0010] To solve the above problems, as a semiconductor device capable of being mounted face down, characterized by comprising: a semiconductor substrate; a low-concentration impurity layer formed on the surface side of the semiconductor substrate; a first vertical MOS transistor formed in a first region of a semiconductor layer in which the semiconductor substrate and the low-concentration impurity layer are taken together as the semiconductor layer; a second vertical MOS transistor formed in a second region adjacent to the first region in a planar view of the semiconductor layer; a metal layer in contact with the back surface side of the semiconductor substrate; and a support body joined to the back surface side of the metal layer via an adhesive; in the planar view, the support body is larger in area than the semiconductor layer and includes the semiconductor layer; the thickness of the support body is greater than the thickness of the semiconductor layer; in a cross section of the semiconductor device including the center of the semiconductor layer and the outer periphery of the semiconductor layer in the planar view, the height of the adhesive along the side surface of the semiconductor layer is lower than the upper surface of the semiconductor layer; when the semiconductor chip other than the support body and the adhesive in the semiconductor device is observed in the cross section, the semiconductor chip is curved in a convex shape toward the direction of the support body.

[0011] According to the above structure, in the double-structure vertical MOS transistor, the warping of the semiconductor chip can be reduced while reducing the on-resistance, and the strength of the semiconductor chip can be increased.

[0012] Effects of Invention

[0013] The present disclosure aims to provide a semiconductor device having a double-structure vertical MOS transistor that reduces the on-resistance of a semiconductor chip while reducing the warping of the semiconductor chip, and further increases the strength of the semiconductor chip. BRIEF DESCRIPTION OF DRAWINGS

[0014] Figure 1 is a cross-sectional schematic view showing an example of the configuration of the semiconductor device of Embodiment 1.

[0015] Figure 2A is a planar schematic view showing an example of the configuration of the semiconductor device of Embodiment 1.

[0016] Figure 2B is a cross-sectional schematic view showing the main current flowing in the semiconductor device of Embodiment 1.

[0017] Figure 3A is a planar schematic view showing an example of the configuration of the semiconductor device of Embodiment 1.

[0018] Figure 3B is a three-dimensional schematic view showing an example of the configuration of the semiconductor device of Embodiment 1.

[0019] Figure 4A is a flowchart showing part of a manufacturing process of the semiconductor device of Embodiment 1.

[0020] Figure 4B is a cross-sectional schematic view showing a process of mounting the semiconductor device of Embodiment 1 face down.

[0021] Figure 5A is a cross-sectional SEM image showing an example of the configuration of the semiconductor device of Embodiment 1.

[0022] Figure 5B is a cross-sectional SEM image showing an example of the configuration of the semiconductor device of Embodiment 1.

[0023] Figure 5C is a cross-sectional SEM image showing an example of the configuration of the semiconductor device of Embodiment 1.

[0024] Figure 6A is a cross-sectional SEM image showing an example of the configuration of the semiconductor device of Comparative Example 1 of Embodiment 1.

[0025] Figure 6B is a cross-sectional SEM image showing an example of the configuration of the semiconductor device of Comparative Example 1 of Embodiment 1.

[0026] Figure 7 is a graph showing the relationship between the warpage amount of the semiconductor chip and the length of the bottom side of the fillet of the conductive adhesive of Embodiment 1.

[0027] Figure 8A is a cross-sectional SEM image showing an example of the configuration of the semiconductor device of Comparative Example 2 of Embodiment 1.

[0028] Figure 8B is a cross-sectional SEM image showing an example of the configuration of the semiconductor device of Comparative Example 2 of Embodiment 1.

[0029] Figure 9 is a cross-sectional SEM image showing an example of the configuration of the semiconductor device of Embodiment 1.

[0030] Figure 10A is a cross-sectional schematic view showing an example of the configuration of the semiconductor device of Modified Example 1 of Embodiment 1.

[0031] Figure 10B is a cross-sectional schematic view showing an example of the configuration of the semiconductor device of Modified Example 2 of Embodiment 1.

[0032] Figure 11 is a cross-sectional schematic view showing an example of the configuration of the semiconductor device of Embodiment 2.

[0033] Figure 12 is a flowchart showing a part of a manufacturing process of a semiconductor device of Embodiment 2. DETAILED DESCRIPTION

[0034] Hereinafter, a specific example of a semiconductor device of one aspect of the present disclosure will be described with reference to the drawings. The embodiments shown here each represent one specific example of the present disclosure. Thus, the numerical values, shapes, constituent elements, arrangement and connection modes of the constituent elements represented in the following embodiments are merely examples and are not intended to limit the present disclosure. Further, each drawing is a schematic view and is not necessarily strictly to scale. In each drawing, the same reference signs are assigned to substantially identical structures, and overlapping description is omitted or simplified.

[0035] (Embodiment 1)

[0036] [1. Configuration of Semiconductor Device]

[0037] Figure 1 is a cross-sectional view showing one example of the configuration of a semiconductor device. Figure 2A is a plan view thereof, and the semiconductor device is one example in size and shape other than being rectangular (square or rectangular). Further, the size and shape and arrangement of the pads are also one example. Figure 2B is a cross-sectional view schematically showing a main current flowing in the semiconductor device. Figure 1 and Figure 2B are cross-sectional views when the semiconductor device is cut along Figure 2A I-I.

[0038] As shown in Figure 1 and Figure 2B , the semiconductor device 1 has a semiconductor substrate 32, a metal layer 30, and a low-concentration impurity layer 33 formed on the semiconductor substrate 32. In the present disclosure, the semiconductor substrate 32 and the low-concentration impurity layer 33 are collectively referred to as a semiconductor layer 40.

[0039] The semiconductor substrate 32 is arranged on the back surface side of the semiconductor layer 40 and is composed of silicon of the first conductivity type containing impurities of the first conductivity type. The low-concentration impurity layer 33 is arranged on the surface side of the semiconductor layer 40, is formed in contact with the semiconductor substrate 32, contains impurities of the first conductivity type at a lower concentration than the concentration of impurities of the first conductivity type of the semiconductor substrate 32, and is of the first conductivity type. The low-concentration impurity layer 33 can be formed on the semiconductor substrate 32, for example, by epitaxial growth.

[0040] As shown in Figure 1 and Figure 2AAs shown, the semiconductor device 1 has a first vertical MOS transistor 10 (hereinafter also referred to as "transistor 10") formed in a first region A1 within the semiconductor layer 40 and a second vertical MOS transistor 20 (hereinafter also referred to as "transistor 20") formed in a second region A2 within the semiconductor layer 40.

[0041] Here, as Figure 2A As shown, the first region A1 and the second region A2 are adjacent to each other in a planar view of the semiconductor layer 40, and divide the semiconductor layer 40 into two equal parts in terms of area. Figure 2A In FIG, the imaginary boundary line 90 between the first region A1 and the second region A2 is indicated by a dotted line (for ease of understanding, the dotted line indicating the boundary line 90 is extended to the outside of the semiconductor layer 40 and the semiconductor device 1). Figure 2A In the figure, the dotted lines representing the first area A1 and the second area A2 are not strictly aligned with the semiconductor layer 40 and the boundary line 90 for ease of understanding, but are slightly left blank and represented on the inside. However, in essence, the outer periphery of the first area A1 and the outer periphery of the second area A2 are aligned with the outer periphery of the semiconductor layer 40 and the boundary line 90.

[0042] The metal layer 30 is formed in contact with the back side of the semiconductor layer 40 (semiconductor substrate 32) and is composed of, for example, silver (Ag) or copper (Cu). The metal layer 30 may also contain trace amounts of elements other than metals that have been introduced as impurities during the manufacturing process of the metal material. Furthermore, the metal layer 30 is formed entirely on the back side of the semiconductor layer 40 (semiconductor substrate 32), and the thickness of the metal layer 30 is preferably 10 μm or greater.

[0043] The support 42 is formed by indirectly contacting the back side of the metal layer 30 via the adhesive 41. Typically, the support 42 is at least twice the thickness of the semiconductor layer 40, for example, a flat metal plate with a thickness of 200 [μm] uniform across the surface. The support 42 may be referred to as a thick-film metal plate 42 hereinafter. The thick-film metal plate 42 preferably has the same degree of electrical conductivity as the metal layer 30, for example, a conductivity of 30×10 6 [S / m] or more, and is typically made of a metal material mainly composed of copper (Cu). In addition, the adhesive 41 is conductive, and is typically a silver paste. Hereinafter, the adhesive 41 may also be referred to as a conductive adhesive 41.

[0044] like Figure 1 As shown in FIG. 1 , in this disclosure, the structure after the support body 42 and the adhesive 41 are removed from the semiconductor device 1 is referred to as a semiconductor chip 2. The semiconductor chip 2 is as shown in FIG. Figure 1As shown, the curved shape is convex in the direction approaching the support body 42. The curved shape is, for example, a shape resulting from warping. The amount of warping of the semiconductor chip 2 is the difference between the highest position and the lowest position in the Z direction among the upper surface or the lower surface of the semiconductor layer 40 or the lower surface of the metal layer 30 when the semiconductor chip 2 is sectioned. In the case where the warping occurring in the semiconductor chip 2 is warping that is convex in the direction approaching the support body 42, the highest position is the outer periphery of the semiconductor layer 40 in plan view, particularly the corner portion, and the lowest position is the center of the semiconductor layer 40 in plan view.

[0045] In addition, the center of the semiconductor layer 40 in plan view refers to the intersection of the diagonals of the semiconductor layer 40 in plan view. Furthermore, the sectioning of the semiconductor device 1 in the present disclosure refers to the case where the cross section of the semiconductor device 1 is observed with a plane that simultaneously includes the center of the semiconductor layer 40 in the semiconductor chip 2 and the outer periphery of the semiconductor layer 40 in the semiconductor chip 2. The outer periphery of the semiconductor layer 40 at this time can be an arbitrary position on the outer periphery of the semiconductor layer 40.

[0046] As shown in Figs. 1 and 2, the semiconductor device 1 includes a semiconductor chip 2, a support body 42, a first source electrode 11, a first gate conductor 15, and a first gate insulating film 16. Figure 1 Figure 2A As shown, in the first region Al of the semiconductor layer 40 (low-concentration impurity layer 33), a first body region 18 including an impurity of a second conductivity type different from the first conductivity type is formed. In the first body region 18, a first source region 14, the first gate conductor 15, and the first gate insulating film 16 including an impurity of the first conductivity type are formed.

[0047] The first gate insulating film 16 is formed inside a plurality of first gate trenches 17 that penetrate the first source region 14 and the first body region 18 from the upper surface of the semiconductor layer 40 to a depth reaching a portion of the low-concentration impurity layer 33, and the first gate conductor 15 is formed on the first gate insulating film 16 inside the first gate trenches 17. The first gate conductor 15 is a buried gate electrode that is buried inside the semiconductor layer 40 and is electrically connected to the first gate pad 119.

[0048] The first source electrode 11 is composed of a portion 12 and a portion 13, and the portion 12 is connected to the first source region 14 and the first body region 18 via the portion 13. The portion 12 of the first source electrode 11 is a layer that is joined with solder at the time of reflow in face-down mounting, and can be composed of a metal material including one or more of nickel, titanium, tungsten, and palladium, for example, as an example not limited thereto. A plating layer of gold or the like can be applied to the surface of the portion 12.

[0049] ​The portion 13 of the first source electrode 11 is a layer that connects the portion 12 and the semiconductor layer 40, and can be composed of a metal material including at least one of aluminum, copper, gold, and silver, for example, without being limited thereto.

[0050] The thickness of the first source electrode 11 is, for example, 2 [μm] or more and 8 [μm] or less when the portion 12 and the portion 13 are added together.

[0051] In the second region A2 of the low-concentration impurity layer 33, a second body region 28 including an impurity of the second conductivity type is formed. In the second body region 28, a second source region 24 including an impurity of the first conductivity type, a second gate conductor 25, and a second gate insulating film 26 are formed.

[0052] The second gate insulating film 26 is formed inside a plurality of second gate trenches 27 that penetrate the second source region 24 and the second body region 28 of the semiconductor layer 40 to a depth reaching a portion of the low-concentration impurity layer 33, and the second gate conductor 25 is formed on the second gate insulating film 26 inside the second gate trenches 27. The second gate conductor 25 is a buried gate electrode that is buried inside the semiconductor layer 40 and is electrically connected to the second gate pad 129.

[0053] The second source electrode 21 is composed of a portion 22 and a portion 23, and the portion 22 is connected to the second source region 24 and the second body region 28 via the portion 23. The portion 22 of the second source electrode 21 is a layer that is joined to solder at the time of reflow in face-down mounting, and can be composed of a metal material including at least one of nickel, titanium, tungsten, and palladium, for example, without being limited thereto. A plating layer of gold or the like can be applied to the surface of the portion 22.

[0054] The portion 23 of the second source electrode 21 is a layer that connects the portion 22 and the semiconductor layer 40, and can be composed of a metal material including at least one of aluminum, copper, gold, and silver, for example, without being limited thereto.

[0055] The thickness of the second source electrode 21 is, for example, 2 [μm] or more and 8 [μm] or less when the portion 22 and the portion 23 are added together.

[0056] With the above-described structure of the transistor 10 and the transistor 20, the semiconductor substrate 32 functions as a common drain region that is common to the first drain region of the transistor 10 and the second drain region of the transistor 20. A portion of the side of the low-concentration impurity layer 33 that is in contact with the semiconductor substrate 32 also functions as the common drain region. In addition, the low-concentration impurity layer 33 is also a drift layer that is common to the transistor 10 and the transistor 20, and is also referred to as the drift layer 33 in this specification.

[0057] Further, the metal layer 30 functions as a common drain electrode that makes the drain electrode of the transistor 10 and the drain electrode of the transistor 20 common. In the case where the adhesive 41 is silver paste and the support 42 is a thick film metal plate, not only the metal layer 30 but also the conductive adhesive 41 and the thick film metal plate 42 function as the common drain electrode.

[0058] As shown in FIG. 1, the first body region 18 and the first source region 14 are covered with the interlayer insulating layer 34 having an opening, and are connected to the portion 13 of the first source electrode 11 via the opening of the interlayer insulating layer 34. The interlayer insulating layer 34 and the portion 13 of the first source electrode 11 are covered with the passivation layer 35 having an opening, and are connected to the portion 12 via the opening of the passivation layer 35. Figure 1 The second body region 28 and the second source region 24 are covered with the interlayer insulating layer 34 having an opening, and are connected to the portion 23 of the second source electrode 21 via the opening of the interlayer insulating layer 34. The interlayer insulating layer 34 and the portion 23 of the second source electrode 21 are covered with the passivation layer 35 having an opening, and are connected to the portion 22 via the opening of the passivation layer 35.

[0059] Thus, the plurality of first source pads 111 and the plurality of second source pads 121 each refer to a region where the first source electrode 11 and the second source electrode 21, respectively, partially protrude on the surface of the semiconductor device 1, a so-called terminal. Likewise, the one or more first gate pads 119 and the one or more second gate pads 129 each refer to a region where the first gate electrode 19 (not shown in FIG. 1) and the second gate electrode 29 (not shown in FIG. 1), respectively, partially protrude on the surface of the semiconductor device 1, a so-called terminal.

[0060]

[0060] Figure 1 Figure 2A Figure 2B Figure 1 Figure 2A Figure 2B

[0061] Further, in the present disclosure, it is assumed that only the structure constituting the first vertical MOS transistor 10 is provided in the first region Al and only the structure constituting the second vertical MOS transistor 20 is provided in the second region A2 in planar observation. Further, the boundary line 90 can also be understood as an imaginary line along the center position of the interval between the portion 13 of the first source electrode 11 and the portion 23 of the second source electrode 21. Further, it can also be understood as the interval itself although it is of a limited width (even in the case of the interval, it can be recognized as a line in the appearance under the naked eye or low magnification). ​​​​​

[0062] In the semiconductor device 1, for example, the first conductivity type can be set to N type, the second conductivity type can be set to P type, the first source region 14, the second source region 24, the semiconductor substrate 32, and the low-concentration impurity layer 33 are N type semiconductors, and the first body region 18 and the second body region 28 are P type semiconductors.

[0063] Further, in the semiconductor device 1, for example, the first conductivity type can be set to P type, the second conductivity type can be set to N type, the first source region 14, the second source region 24, the semiconductor substrate 32, and the low-concentration impurity layer 33 are P type semiconductors, and the first body region 18 and the second body region 28 are N type semiconductors.

[0064] [2. Operation of the vertical MOS transistor of the double structure]

[0065] In the following description, it is assumed that the transistor 10 and the transistor 20 are so-called N-channel transistors in which the first conductivity type is set to N type and the second conductivity type is set to P type, and the on operation of the semiconductor device 1 is described.

[0066] Figure 3A and Figure 3B are plan views and perspective views of the substantially unit structure of the transistor 10 (or the transistor 20) repeatedly formed in the X direction and the Y direction of the semiconductor device 1, respectively. In Figure 3A and Figure 3B In the plan views and the perspective views of the substantially unit structure of the transistor 10 (or the transistor 20) in Figs. 1 and 2, the semiconductor substrate 32 and the metal layer 30, the conductive adhesive 41, the thick film metal plate 42, and the passivation layer 35 and the first source electrode 11 (or the second source electrode 21), the interlayer insulating layer 34 are not illustrated for easy understanding.

[0067] The configuration of the transistor 10 and the configuration of the transistor 20 are the same. Therefore, the substantially unit structure is described below using the reference numerals of the transistor 10.

[0068] The Y direction is a direction parallel to the upper surface of the semiconductor layer 40 and in which the first gate trench 17 extends. Further, the X direction refers to a direction parallel to the upper surface of the semiconductor layer 40 and orthogonal to the Y direction. The Z direction refers to a direction orthogonal to both the X direction and the Y direction, indicating the height direction of the semiconductor device 1. In the present disclosure, there are cases in which the Y direction is denoted as the first direction, the X direction is denoted as the second direction, and the Z direction is denoted as the third direction.

[0069] As Figure 3A and Figure 3BAs shown, the transistor 10 has a first connecting portion 18a that electrically connects the first body region 18 and the first source electrode 11. The first connecting portion 18a is a region of the first body region 18 in which the first source region 14 is not formed, and contains impurities of the same second conductivity type as the first body region 18. The first source region 14 and the first connecting portion 18a are alternately and periodically arranged along the Y direction. The same applies to the transistor 20.

[0070] In the semiconductor device 1, if a high voltage is applied to the first source electrode 11 and a low voltage is applied to the second source electrode 21, and a voltage exceeding the threshold value is applied to the second gate electrode 29 (the second gate conductor 25) with the second source electrode 21 as a reference, a conduction channel is formed in the vicinity of the second gate insulating film 26 in the second body region 28. As a result, a main current flows through a path of the first source electrode 11 - the first connecting portion 18a - the first body region 18 - the low-concentration impurity layer 33 - the semiconductor substrate 32 - the metal layer 30 - the conductive adhesive 41 - the thick metal plate 42 - the conductive adhesive 41 - the metal layer 30 - the semiconductor substrate 32 - the low-concentration impurity layer 33 - the conduction channel formed in the second body region 28 - the second source region 24 - the second source electrode 21, and the semiconductor device 1 becomes in an on state. A PN junction exists at the contact surface between the second body region 28 and the low-concentration impurity layer 33 in the conduction path, and functions as a body diode.

[0071] Likewise, in the semiconductor device 1, if a high voltage is applied to the second source electrode 21 and a low voltage is applied to the first source electrode 11, and a voltage exceeding the threshold value is applied to the first gate electrode 19 (the first gate conductor 15) with the first source electrode 11 as a reference, a conduction channel is formed in the vicinity of the first gate insulating film 16 in the first body region 18. As a result, a main current flows through a path of the second source electrode 21 - the second connecting portion 28a - the second body region 28 - the low-concentration impurity layer 33 - the semiconductor substrate 32 - the metal layer 30 - the conductive adhesive 41 - the thick metal plate 42 - the conductive adhesive 41 - the metal layer 30 - the semiconductor substrate 32 - the low-concentration impurity layer 33 - the conduction channel formed in the first body region 18 - the first source region 14 - the first source electrode 11, and the semiconductor device 1 becomes in an on state. A PN junction exists at the contact surface between the first body region 18 and the low-concentration impurity layer 33 in the conduction path, and functions as a body diode.

[0072] In Figure 2BThe flow of the main current in both directions is schematically indicated by arrows. The flow of the main current in the horizontal direction (X direction) occurs in each of the metal layer 30, the conductive adhesive 41, the thick film metal plate 42, and the semiconductor substrate 32. Since the specific resistance of the metal layer 30 and the thick film metal plate 42 is lower than that of the other layers, by making the metal layer 30 or the thick film metal plate 42 thicker, the cross-sectional area of the main current path is enlarged, and the on-resistance of the semiconductor device 1 can be reduced.

[0073] [3. Method of manufacturing semiconductor device]

[0074] A method of manufacturing the semiconductor device 1 will be described.

[0075] Figure 4A is a diagram simply showing a part of the manufacturing process of the semiconductor device 1 of Embodiment 1. The configuration of each double-structure vertical MOS transistor to be singulated later is formed in a grid shape on a silicon wafer until the process 501.

[0076] Next, in the process 502, the back surface side of the silicon wafer (corresponding to the semiconductor substrate 32 in view of each double-structure vertical MOS transistor to be singulated later) is thinned. In the thinning in the process 502, the thickness of the semiconductor layer 40 is preferably controlled to be 15 [μm] or more and 100 [μm] or less, and more preferably 15 [μm] or more and 75 [μm] or less.

[0077] Next, in the process 503, the metal layer 30 is formed on the entire back surface side of the silicon wafer after the thinning. The metal layer 30 can be, for example, a multilayer structure including a plurality of metal layers, but the surface to be in contact with the conductive adhesive 41 in the following process 504 is preferably mainly made of silver (Ag) or copper (Cu). The plurality of metal layers can be formed individually by a method such as evaporation, sputtering, or plating. In the metal layer formation in the process 503, the thickness of the metal layer 30 is preferably 10 [μm] or more.

[0078] Next, in the process 504, the silicon wafer is sliced using a blade, and each double-structure vertical MOS transistor is singulated. The double-structure vertical MOS transistor singulated is in a state where the thick film metal plate 42 is not yet joined, and is in the state described above as the semiconductor chip 2.

[0079] In the process 504, the metal layer 30 formed on the back surface side of the silicon wafer in the process 503 is also cut off together with the silicon wafer, but the metal layer 30 physically pushed by the blade extends along the side surface of the semiconductor chip 2. Therefore, a protrusion (so-called burr) extending toward the lower side (-Z direction) of the back surface side of the semiconductor chip 2 is formed at the outer periphery of the metal layer 30 of the singulated semiconductor chip 2.

[0080] In addition, the dicing by the blade is an example, and the singulation of the vertical MOS transistor of the double structure can also be a method other than the blade dicing, for example, can be dicing using a laser. However, in the dicing using a laser, it is difficult to form a protrusion.

[0081] Next, in the process 505, a thick film metal plate 42 on which a conductive adhesive 41 such as silver paste is applied is prepared in advance, and the back surface side of the metal layer 30 of the semiconductor chip 2 is bonded. In general, the amount of the conductive adhesive 41 pushed in is set to, for example, 5 [μm] to 10 [μm], and further the thickness of the conductive adhesive 41 after hardening and bonding is calculated as a target value (for example, 20 [μm] to 60 [μm]), and the conductive adhesive 41 is applied to the surface of the thick film metal plate 42.

[0082] The conductive adhesive 41 is an adhesive for bonding the back surface side of the metal layer 30 to the thick film metal plate 42. It is preferable that, when observed in a state after hardening and bonding of the thick film metal plate 42, the back surface side of the metal layer 30 is completely covered with the conductive adhesive 41.

[0083] For the thick film metal plate 42, a structure in which the area exceeds the area of the semiconductor substrate 32 in planar observation is selected, and in bonding, alignment is performed so that a blank is provided in planar observation at a substantially equal width from the outer periphery of the metal layer 30 to the outer periphery of the closest thick film metal plate 42. As an example, as shown in FIG. 6, the thick film metal plate 42 is a similar shape to the semiconductor layer 40. By the semiconductor layer 40 and the thick film metal plate 42 being similar shapes, it means that the semiconductor layer 40 and the thick film metal plate 42 are the same shape in planar observation, and only the areas are different. Figure 2A

[0084] Further, regarding the thick film metal plate 42, it is preferable for bonding of the semiconductor layer 40 that the thickness is uniform in-plane from a macroscopic point of view, and is a so-called flat plate which does not have a step difference or a concave-convex shape. In the present embodiment 1, the description is made assuming that the thick film metal plate 42 is a flat plate.

[0085] ​At the time of joining, generally, the thick film metal plate 42 of a relatively large area is taken as the receiving side, and the semiconductor chip 2 of a relatively small area is aligned. The conductive adhesive 41 can also be made to protrude from the back of the metal layer 30 in plan view. Whether the amount of protrusion of the conductive adhesive 41 is uniform along the outer periphery of the semiconductor layer 40 in plan view is also possible. In Figure 2A , the case where the protrusion of the conductive adhesive 41 is uniform is shown as an example. Alternatively, the protruding conductive adhesive 41 can be made to rise along the side surface of the semiconductor chip 2 as shown in Figure 1 , forming a substantially triangular-shaped chamfer.

[0086] In the step 505, in order to harden the conductive adhesive 41 such as silver paste, the thick film metal plate 42 is heat-treated at a high temperature in a state where the semiconductor chip 2 is aligned. The temperature of the heat treatment is preferably 200 [°C] or less, for example, 170 [°C]. The conductive adhesive 41 starts to harden from around 170 [°C], and the metal layer 30 is joined to the thick film metal plate 42 to become the semiconductor device 1.

[0087] In addition, at the time of heat treatment of the thick film metal plate 32 to a high temperature of 170 [°C], the semiconductor chip 2 warps. As described above, the thickness of the semiconductor layer 40 is preferably 15 [μm] or more and 75 [μm] or less, and the thickness of the first source electrode 11 and the second source electrode 21 is 2 [μm] or more and 8 [μm] or less. The thickness of the metal layer 30 is preferably 10 [μm] or more, and in this thickness structure, the semiconductor chip 2 at 170 [°C] warps convex in the direction close to the thick film metal plate 42 (in the -Z direction in the cross section in Figure 1 .

[0088] Figure 4B is a schematic view at the time of mounting the semiconductor device 1 with the face down.

[0089] [4. Investigation]

[0090] Hereinafter, the effects of the semiconductor device 1 of the present embodiment 1 will be described.

[0091] In a vertical MOS transistor of a double structure, in order to reduce the on-resistance at the time of conduction, it is required to make the semiconductor substrate 32 (semiconductor layer 40) thin and the metal layer 30 thick. The semiconductor chip 2 of such a structure easily warps convex in the -Z direction at a high temperature. The thinner the semiconductor layer 40 is made and the thicker the metal layer 30 is made, the greater the warp at a high temperature becomes.

[0092] In particular, in the case of a vertical MOS transistor of a double structure which requires a low on-resistance, it is effective to increase the area of the semiconductor chip 2 in plan view for the purpose of increasing the total gate width of the channel. However, if the area is large, warping occurring on the semiconductor chip 2 significantly increases.

[0093] When the semiconductor device 1 is mounted face down to a mounting substrate, reflow processing is required in which the solder material is subjected to high-temperature treatment at around 240 [°C]. It is known that if the warping amount of the semiconductor chip 2 at 240 [°C] exceeds 40 [μm], mounting failure is likely to occur regardless of the direction of warping, and it is required to suppress the warping amount of the semiconductor chip 2 to be lower than 40 [μm].

[0094] In the semiconductor device 1 of Embodiment 1, the semiconductor chip 2 is joined to the thick-film metal plate 42 at around 170 [°C] which is lower than 240 [°C], so it is possible to fix the warping amount of the semiconductor chip 2 to the extent of warping occurring at around 170 [°C]. As the conductive adhesive 41, if a material which does not melt again, such as silver paste, is selected, as shown in FIG. 6, in reflow processing (240 [°C]) when the semiconductor device 1 is mounted face down to a mounting substrate, the warping of the semiconductor chip 2 which has been joined to the thick-film metal plate 42 does not increase. Figure 4B

[0095] Thus, the structure of the semiconductor device 1 of Embodiment 1 is particularly effective for a configuration in which the warping amount of the semiconductor chip 2 increases, that is, particularly effective for a semiconductor chip 2 in which the thickness of the semiconductor layer 40 is thin and the area in plan view of the semiconductor chip 2 is large, and further, the thickness of the metal layer 30 is thick. Further, if the thick-film metal plate 42 is sufficiently thick, the thick-film metal plate 42 functions as a support for the semiconductor chip 2, so it is possible to compensate for the decrease in strength of the semiconductor chip 2 due to the thinning of the semiconductor layer 40.

[0096] However, in the semiconductor device 1 of Embodiment 1, when the semiconductor chip 2 is attached to the thick-film metal plate 42 via the conductive adhesive 41, as schematically shown in FIG. 7, a part of the conductive adhesive 41 exposed from the semiconductor chip 2 rises at the side surface of the semiconductor chip 2, and forms a substantially triangular chamfer in cross section. Therefore, in plan view, if the area of the thick-film metal plate 42 is not sufficiently large compared to the area of the semiconductor layer 40, the exposure of the conductive adhesive 41 can not be contained in the inside of the thick-film metal plate 42. Figure 1

[0097] ​​Moreover, in a cross section, if the exposed conductive adhesive 41 rises to the upper surface of the semiconductor chip 2, the semiconductor device 1 can possibly short-circuit, so the height by which the conductive adhesive 41 rises from the surface of the thick-film metal plate 42 along the side surface of the semiconductor chip 2 (the height of the chamfer of the conductive adhesive 41) must be smaller than the upper surface of the semiconductor layer 40.

[0098] Thus, in the semiconductor device 1 of Embodiment 1, it is necessary to (1) prepare the area of the thick-film metal plate 42 in plan view in consideration of the presence of the exposed conductive adhesive 41 corresponding to the length of the bottom edge of the chamfer of the conductive adhesive 41, and (2) adjust the thickness of the semiconductor chip 2 in consideration of the presence of the rise of the conductive adhesive 41 corresponding to the height of the chamfer of the conductive adhesive 41.

[0099] The semiconductor device 1 of Embodiment 1 can define an appropriate size of the thick-film metal plate 42 in plan view with respect to the above (1) and prevent short-circuit of the semiconductor chip 2 due to the exposure (chamfer) of the conductive adhesive 41 with respect to the above (2) by controlling the bending of the semiconductor chip 2.

[0100] First, the above (1) is described.

[0101] As described above, in the semiconductor device 1 of Embodiment 1, the thick-film metal plate 42 needs to be the size including the semiconductor chip 2 and the conductive adhesive 41 exposed from the semiconductor chip 2 in plan view. Therefore, by joining the semiconductor chip 2 and the thick-film metal plate 42, the area of the semiconductor device 1 must be larger than the area of the semiconductor chip 2 in plan view.

[0102] In order to make the area of the semiconductor device 1 as small as possible in plan view compared with the area of the semiconductor chip 2, it is necessary to make the area of the thick-film metal plate 42 as small as possible, and for this purpose, it is important to suppress the length by which the conductive adhesive 41 is exposed.

[0103] Therefore, the semiconductor device 1 of Embodiment 1 sets the thickness of the metal layer 30 to 10 [μm] or more and controls the warping of the semiconductor chip 2 at 170 [°C] to be convex in the direction close to the support 42 (-Z direction).

[0104] As Figure 1As shown, if the back surface of the metal layer 30 viewed from the thick film metal plate 42 is warped in a convex manner toward the approaching direction (-Z direction), the outer periphery of the semiconductor chip 2 is bent in a convex manner toward the relatively distant direction (+Z direction) from the support body 42 by the warping. If the semiconductor chip 2 becomes such a bent shape, the pressing of the conductive adhesive 41 is alleviated at the outer periphery of the semiconductor chip 2, so the conductive adhesive 41 can achieve the effect of suppressing the length exposed from the semiconductor chip 2.

[0105] Thus, for the semiconductor device 1, when observing the semiconductor chip 2 in the semiconductor device 1 except for the thick film metal plate 42 and the conductive adhesive 41 in a cross section of the semiconductor device 1, the semiconductor chip 2 is preferably in a bent shape convex toward the thick film metal plate 42. In other words, it is preferable that the thickness of the conductive adhesive 41 directly below the semiconductor layer 40 at the outer periphery of the semiconductor layer 40 in a plan view be thicker than the thickness of the conductive adhesive 41 directly below the semiconductor layer 40 at the center of the semiconductor layer 40 in the plan view.

[0106] In Figure 5A , Figure 5B , Figure 5C is a cross-sectional SEM image when the semiconductor device 1 of Embodiment 1 is mounted face down on a mounting substrate. Figure 5B is Figure 5A an enlarged cross-sectional SEM image of the portion surrounded by the broken line in Figure 5C is Figure 5B an enlarged cross-sectional SEM image of the portion surrounded by the broken line in In Figure 5A , Figure 5B , Figure 5C the semiconductor device 1 shown in

[0107] Figure 5B the horizontal line A in Figure 5C is a line extending the interface position between the semiconductor layer 40 and the metal layer 30 at the center of the semiconductor layer 40 in a plan view to the outer periphery of the semiconductor layer 40 in the plan view. Further, Figure 5C the horizontal line B in

[0108] In Figure 5CIn the figure, horizontal line A is closer to thick-film metal plate 42 (in the -Z direction) than horizontal line B, and the distance between horizontal line A and horizontal line B in the Z direction is 10 μm. Therefore, semiconductor chip 2 is warped in a convex shape toward thick-film metal plate 42 (in the -Z direction), with a warpage of 10 μm.

[0109] like Figure 5C As shown, when the warping amount of the semiconductor chip 2 is 10 [μm], the exposed length of the conductive adhesive 41 (the length of the bottom edge of the chamfer of the conductive adhesive 41) is 128 [μm], and the thick film metal plate 42 needs to maintain a blank space of more than 128 [μm] from the periphery of the semiconductor chip 2.

[0110] Here, in Figure 6A 、 Figure 6B 9 shows a cross-sectional SEM image of Comparative Example 1 of the first embodiment. Figure 6B yes Figure 6A An enlarged cross-sectional SEM image of the portion surrounded by the dotted line. Figure 6A 、 Figure 6B In the semiconductor device 1 shown, the semiconductor layer 40 has a thickness of 53 μm, the first source electrode 11 and the second source electrode 21 have a thickness of 4 μm, the metal layer 30 has a thickness of 3 μm, and the thick metal plate 42 has a thickness of 200 μm. With these thicknesses, the semiconductor chip 2 has a convex, warped shape away from the thick metal plate 42 (in the +Z direction), with the warpage amount being 2 μm.

[0111] like Figure 6B As shown, when the semiconductor chip 2 is warped by 2 [μm] in the +Z direction, the exposed length of the conductive adhesive 41 (the length of the bottom side of the chamfer of the conductive adhesive 41) is 150 [μm]. It can be seen that it is larger than the length of the bottom side of the chamfer of the conductive adhesive 41 of 128 [μm] formed when the semiconductor chip 2 is warped by 10 [μm] in the -Z direction in the semiconductor device 1 of this embodiment 1.

[0112] That is, the semiconductor chip 2 warps in a convex manner in the -Z direction, thereby reducing the pressure of the conductive adhesive 41 on the outer periphery of the semiconductor chip 2, and thus having the effect of reducing the length of the conductive adhesive 41 exposed from the semiconductor chip 2 when viewed in plan. Therefore, with the aim of determining the appropriate size of the thick-film metal plate 42, the inventors studied the relationship between the amount of warpage of the semiconductor chip 2 and the exposed length of the conductive adhesive 41 (the length of the bottom side of the chamfer of the conductive adhesive 41) in the semiconductor device 1 of the first embodiment.

[0113] exist Figure 7The figure shows a plot showing the relationship between the length of the base of the chamfer of conductive adhesive 41 and the amount of warpage of semiconductor chip 2. The horizontal axis represents the warpage w [μm] of semiconductor chip 2, and the vertical axis represents the length b [μm] of the base of the chamfer formed by the exposed conductive adhesive 41. The thickness of semiconductor layer 40 is 53 μm. By adjusting the thickness of metal layer 30, semiconductor chips 2 with varying amounts of warpage were fabricated. The length of the base of the chamfer of conductive adhesive 41 for each warpage amount is plotted.

[0114] The plot marked with a circle (⊥) shows the relationship between the length b of the bottom edge of the chamfer of the conductive adhesive 41 and the warpage w of the semiconductor chip 2 when the amount of conductive adhesive 41 pushed in is 5 μm. The relationship between b and w is b = -0.75 × w + 135.3. The plot marked with a circle (□) shows the relationship between the length b of the bottom edge of the chamfer of the conductive adhesive 41 and the warpage w of the semiconductor chip 2 when the amount of conductive adhesive 41 pushed in is 10 μm. The relationship between b and w is b = -1.5 × w + 270.6.

[0115] The amount of conductive adhesive 41 pushed in is to ensure the close adhesion between the metal layer 30 and the conductive adhesive 41 during the bonding in step 505, and to further push the semiconductor chip 2 toward the thick film metal plate 42 after the entire back side of the metal layer 30 is completely covered with the conductive adhesive 41.

[0116] When the area of ​​the semiconductor layer 40 in plan view is S [μm 2 ], assuming that the pushing amount of the conductive adhesive 41 is P [μm], the exposed amount of the conductive adhesive 41 is S×P [μm 3 ], so as the amount of conductive adhesive 41 pushed in increases, the amount of conductive adhesive 41 exposed increases. In order to minimize the amount of conductive adhesive 41 exposed and stably ensure the close contact between the metal layer 30 and the conductive adhesive 41, the amount of conductive adhesive 41 pushed in is preferably in the range of 5 [μm] to 10 [μm].

[0117] In the semiconductor device 1 of Embodiment 1, in order to include the exposed amount of the conductive adhesive 41 in the thick film metal plate 42 in planar observation, it is sufficient to secure a blank corresponding to the length of the base of the chamfer of the conductive adhesive 41 when the push-in amount of the conductive adhesive 41 is in the range of 5 [μm] to 10 [μm]. Thus, if the minimum length in the closest distance from the outer periphery of the semiconductor layer 40 to the outer periphery of the thick film metal plate 42 in planar observation is M [μm], it is sufficient that the relationship of -0.75 x w + 135.3 (plotting line of O-mark) ≤ M ≤ -1.5 x w + 270.6 (plotting line of □-mark) is satisfied, and it is not necessary to enlarge the area of the thick film metal plate 42 beyond this range. By adjusting the direction and the amount of warping w of the semiconductor chip 2, the area of the thick film metal plate 42 can be reduced.

[0118] In addition, the minimum length in the closest distance from the outer periphery of the semiconductor layer 40 to the outer periphery of the thick film metal plate 42 in planar observation is referred to as M, which means the blank described in the explanation of the step 504. That is, as an example, it means the minimum length in the blank provided at a substantially equal width from the outer periphery of the metal layer 30 to the outer periphery of the closest thick film metal plate 42 in planar observation.

[0119] However, as a result of the research by the inventors, if the amount of warping of the semiconductor chip 2 at 170 [°C] is higher than 30 [μm], the physical adhesion of the metal layer 30 to the conductive adhesive 41 is deteriorated at the outer periphery of the semiconductor chip 2, and there is a case where the conductive adhesive 41 and the metal layer 30 are peeled.

[0120] In Figure 8A , Figure 8B the cross-sectional SEM image of Comparative Example 2 of Embodiment 1 is shown. Figure 8B is Figure 8A the enlarged cross-sectional SEM image of the portion surrounded by the broken line in FIG. 12. In Figure 8A , Figure 8B the semiconductor device 1 shown in FIG. 13, the thickness of the semiconductor layer 40 is 40 [μm], the thickness of the first and second source electrodes 11 and 21 is 4 [μm], the thickness of the metal layer 30 is 25 [μm], and the thickness of the thick film metal plate 42 is 200 [μm]. In this thickness structure, the semiconductor chip 2 is convex in the direction close to the thick film metal plate 42 (-Z direction) and is warped, and the amount of warping is 35 [μm].

[0121] As Figure 8BAs shown, when the warpage amount of the semiconductor chip 2 is 35 [μm], a space is generated between the metal layer 30 and the conductive adhesive 41 at the outer periphery of the semiconductor chip 2, and the metal layer 30 and the conductive adhesive 41 are not in close contact. If the warpage amount is thus too large, the conductive adhesive 41 can peel off near the outer periphery of the metal layer 30 in plan view. Thus, in order to reduce the exposed amount of the conductive adhesive 41 while stably ensuring the close contact of the metal layer 30 and the thick film metal plate 42, the warpage amount of the semiconductor chip 2 at 170 [°C] is preferably 30 [μm] or less.

[0122] The direction of the warpage of the semiconductor chip 2 at high temperature (also referred to as the direction of the bending) and the warpage amount (also referred to as the bending amount) are determined by the relationship between the physical values such as the linear expansion coefficients and Young's moduli of the semiconductor layer 40, the first and second source electrodes 11 and 21, and the metal layer 30, and the thicknesses thereof.

[0123] Since the linear expansion coefficients of the metal types constituting the first and second source electrodes 11 and 21 and the metal type constituting the metal layer 30 are close to each other in many cases, the direction of the warpage of the semiconductor chip 2 is determined by the relationship between the thicknesses of the metal layer 30 and the first and second source electrodes 11 and 21 in many cases.

[0124] The thicknesses of the first and second source electrodes 11 and 21 are typically 2 [μm] or more and 8 [μm] or less, respectively, and thus in order to control the warpage to be convex in the -Z direction, the thickness of the metal layer 30 is preferably set to 10 [μm] or more. This is because, by making the thickness of the metal layer 30 thicker than the thicknesses of the first and second source electrodes 11 and 21, a greater thermal stress is generated in the metal layer 30 at high temperature, and the semiconductor chip 2 becomes a bent shape that is convex in the direction in which the metal layer 30 is provided (the -Z direction).

[0125] In addition, regarding the warpage amount, the warpage amount is greater as the semiconductor layer 40 is thinner and the metal layer 30 is thicker, which is determined by the relative relationship between the thicknesses of the semiconductor layer 40 and the metal layer 30. Thus, by adjusting the thicknesses of the semiconductor layer 40 and the metal layer 30, the warpage amount of the semiconductor chip 2 at 170 [°C] can be controlled to be 30 [μm] or less.

[0126] Further, in the semiconductor device 1 of this Embodiment 1, when the amount of the conductive adhesive 41 applied on the surface of the thick film metal plate 42 and the push-in amount of the conductive adhesive 41 are constant, and the tightness of the joining of the metal layer 30 and the thick film metal plate 42 via the conductive adhesive 41 is stably ensured, the volume of the conductive adhesive 41 exposed from the semiconductor chip 2 (the volume of the chamfer of the conductive adhesive 41) is constant. During the volume of the chamfer of the conductive adhesive 41 is constant, the height of the chamfer of the conductive adhesive 41 (the amount of the conductive adhesive 41 rising from the surface of the thick film metal plate 42 along the side surface of the semiconductor chip 2) varies depending on the length of the base of the chamfer of the conductive adhesive 41.

[0127] Next, the above (2) is described.

[0128] In the semiconductor device 1 of this Embodiment 1, when the length of the long side of the semiconductor layer 40 in planar observation is set to Ll [μm], and the length of the short side is set to L2 [μm] (Ll = L2 in the case where the semiconductor layer 40 is a square), the amount of the conductive adhesive 41 exposed from the semiconductor chip 2 is Ll x L2 x P [μm 3 ]. Further, the conductive adhesive 41 exposed from the semiconductor chip 2 forms a substantially triangular chamfer in cross section, so if the height of the chamfer of the conductive adhesive 41 is set to ht [μm], the volume of the chamfer of the conductive adhesive 41 is (b x ht / 2) x 2 x (Ll + L2) [μm 3 ]. Here, it is assumed that the amount of the conductive adhesive 41 exposed in planar observation is uniform along the outer periphery of the semiconductor layer 40.

[0129] Since the amount of the conductive adhesive 41 exposed from the semiconductor chip 2 Ll x L2 x P [μm 3 ] is equal to the volume of the chamfer of the conductive adhesive 41 (b x ht / 2) x 2 x (Ll + L2) [μm 3 ], the height of the chamfer of the conductive adhesive 41 is ht = P x Ll x L2 / {b x (Ll + L2)}. Further, it is premised that the warpage amount of the semiconductor chip 2 is 30 [μm] or less, and the conductive adhesive 41 does not peel off between the metal layer 30 and the thick film metal plate 42.

[0130] If the conductive adhesive 41 rises to the upper surface of the semiconductor chip 2, the semiconductor device 1 can possibly short-circuit, so the amount of the conductive adhesive 41 rising from the surface of the thick film metal plate 42 along the side surface of the semiconductor chip 2 (the height of the chamfer of the conductive adhesive 41) must be smaller than the upper surface of the semiconductor layer 40.

[0131] In the semiconductor device 1 of Embodiment 1, the semiconductor chip 2 is controlled to be convex toward the direction (−Z direction) in which the support body 42 is approached, and the outer periphery of the semiconductor chip 2 is bent in the direction (+Z direction) in which the support body 42 is relatively distanced by warping. If the semiconductor chip 2 is in such a bent shape, the distance from the surface of the thick metal plate 42 to the upper surface of the semiconductor chip 2 is lengthened in the outer periphery of the semiconductor chip 2 in plan view, so that the effect of preventing the conductive adhesive 41 exposed from the semiconductor chip 2 from rising to the upper surface of the semiconductor chip 2 can be obtained.

[0132] In the semiconductor device 1 of Embodiment 1, when the thickness of the semiconductor chip 2 at the center of the semiconductor chip 2 in plan view is H [μm] and the thickness of the conductive adhesive 41 is T [μm], if the relationship ht < H + T + w is satisfied, the conductive adhesive 41 will not rise to the upper surface of the semiconductor layer 40.

[0133] That is, by controlling the direction and amount of warping of the semiconductor chip 2, the length of the conductive adhesive 41 exposed from the semiconductor chip 2 in plan view can be controlled, and the conductive adhesive 41 exposed from the semiconductor chip 2 in cross section can be prevented from rising to the upper surface of the semiconductor chip 2.

[0134] Further, Figure 9 is a cross-sectional SEM image of the outer periphery of the semiconductor device 1 of Embodiment 1. As shown in Figure 9 , the metal layer 30 has a case in which a protrusion is present in the face bonded to the conductive adhesive 41 in the direction (−Z direction) toward the thick metal plate 42. As an example, the protrusion is a burr formed when the metal layer 30 is physically stretched when the semiconductor chip 2 is singulated from a wafer state by a blade, and in the case of a burr, a case in which the burr is continuously formed along the outer periphery of the metal layer 30 in plan view is more common.

[0135] In the semiconductor device 1 of Embodiment 1, if a portion in which the height of the burr is 5 [μm] or more from the back surface of the metal layer 30 is present locally in the outer periphery of the semiconductor chip 2, the metal layer 30 and the conductive adhesive 41 are bonded, and the effect of improving the adhesion to the conductive adhesive 41 is obtained as an anchoring effect.

[0136] Further, according to the results of the inventors' research, it was found that in terms of the adhesion of the metal layer 30 to the conductive adhesive 41, the face of the metal layer 30 bonded to the conductive adhesive 41 is preferably a metal type other than nickel (Ni), and typically, if silver (Ag) or copper (Cu) is used as the main material, the adhesion of the metal layer 30 to the conductive adhesive 41 can be stably ensured.

[0137] Next, a modification of the semiconductor device 1 of Embodiment 1 will be described.

[0138] In Figure 10A FIG. 6 is a cross-sectional schematic view showing a modification 1 of the semiconductor device 1 of Embodiment 1. In the semiconductor device 1 of the modification 1, the support body 42 has a curved shape convex toward the direction of the semiconductor chip 2. The curved shape of the support body 42 is, for example, a shape generated due to warping of the support body 42 at the time of heat treatment when the metal layer 30 is joined with the support body 42 via the conductive adhesive 41. The warping amount of the support body 42 is a difference between the highest position and the lowest position in the Z direction in the upper surface or the lower surface of the support body 42 when the support body 42 is sectioned. In the case where the warping of the support body 42 is warping convex toward the direction of the semiconductor chip 2, the highest position is the center of the support body 42 in plan view, and the lowest position is the outer periphery of the support body 42 in plan view, particularly, the corner portion at the outer periphery.

[0139] As for the direction of the warping of the support body 42 and the warping amount, the direction and the warping amount of the warping of the support body 42 can be controlled by adjusting the warping amount of the semiconductor chip 2 at 170 [°C], the thickness or / and the material of the support body 42, and the thickness or / and the material of the conductive adhesive 41, or the conditions of joining. The easiest adjustment is to make the thickness of the support body 42 thinner. If the thickness of the support body 42 is made thinner, the warping amount of the support body 42 at the time when the semiconductor device 1 is completed can be increased, but the rigidity of the semiconductor device 1 is decreased. Therefore, as a reference, it is preferable that the thickness of the support body 42 is designed so that the warping amount of the support body 42 is smaller than the warping amount of the semiconductor chip 2.

[0140] As Figure 10A shown in FIG. 6, in the semiconductor device 1 in which the warping amount of the support body 42 is smaller than the warping amount of the semiconductor chip 2 and the support body 42 has a curved shape convex toward the direction of the semiconductor chip 2, the pressing of the conductive adhesive 41 is alleviated compared to the case where the support body 42 is not curved, so the length of the conductive adhesive 41 exposed from the semiconductor layer 40 in plan view can be suppressed.

[0141] In Figure 10B FIG. 7 is a cross-sectional schematic view showing a modification 2 of the semiconductor device 1 of Embodiment 1. In the semiconductor device 1 of the modification 2, the support body 42 has a curved shape convex away from the semiconductor chip 2. As Figure 10BAs shown, in the semiconductor device 1, in a case where the amount of bending of the support body 42 is smaller than the amount of bending of the semiconductor chip 2 and the support body 42 has a curved shape convex in a direction away from the semiconductor chip 2, compared with a case where the support body 42 is not curved, it is possible to prevent a void from being generated between the semiconductor chip 2 and the conductive adhesive 41 in the vicinity of the center of the semiconductor layer 40 in plan view.

[0142] (Embodiment 2)

[0143] Hereinafter, a semiconductor device 100 of Embodiment 2, which is a modification of the semiconductor device 1 of Embodiment 1, will be described.

[0144] The semiconductor device 100 of Embodiment 2 is an example in which the thick metal plate, i.e., the support body 42 of Embodiment 1 is changed to an insulating support body 420.

[0145] Here, regarding the semiconductor device 100 of Embodiment 2, for the same constituent elements as those of the semiconductor device 1 of Embodiment 1, it is considered that the same has been described and the same reference numerals are assigned and detailed description thereof is omitted, and description will be made focusing on the points different from the semiconductor device 1.

[0146] [1. Structure of Semiconductor Device]

[0147] In Figure 11 , a cross-sectional schematic view of the semiconductor device 100 of Embodiment 2 is shown. The point different from the semiconductor device 1 of Embodiment 1 is that the support body 42 is changed to the insulating support body 420.

[0148] [2. Manufacturing Method of Semiconductor Device]

[0149] In Figure 12 , a part of the manufacturing process of the semiconductor device 100 of Embodiment 2 is simply shown. The steps 501 to 504 are the same as the manufacturing process of the semiconductor device 1 of Embodiment 1. The step 506 is a step corresponding to the step 505 in Embodiment 1.

[0150] In this Embodiment 2, in the step 506, the semiconductor chip 2 is bonded to the insulating support body 420. In the step 506, the conductive adhesive 41 is applied to the upper surface of the insulating support body 420 in advance. The conductive adhesive 41 is, for example, a silver paste, which is hardened by being subjected to high temperature of 170 [°C] to bond the semiconductor chip 2 to the insulating support body 420.

[0151] [3. Investigation]

[0152] In the semiconductor device 100 of this embodiment, since the insulating support 420 is used, rigidity can be increased compared to the thick film metal plate of Embodiment 1. As a raw material with good rigidity, for example, a silicon substrate is available. In the case where a silicon substrate is used as the insulating support 420, the same effect as when the thick film metal plate is used in the semiconductor device 1 of Embodiment 1 can be achieved with a thinner size.

[0153] Further, the semiconductor device of the present disclosure can achieve a sufficiently low on-resistance as an on-path since it is provided with the metal layer 30. Thus, the semiconductor device 100 of Embodiment 2 is practical in the case where the semiconductor chip 2 is provided with the metal layer 30 on the back surface side of the semiconductor layer 40.

[0154] As with the semiconductor device 1 of Embodiment 1, in the semiconductor device 100 of Embodiment 2, the metal layer 30 in the semiconductor chip 2 is present, so the direction of the warping of the semiconductor chip 2 at 170[°C] is convex toward the support 42.

[0155] The semiconductor device of the technical solution of the present disclosure has been described based on Embodiments 1 to 2 and Modified Examples 1 to 2 above, but the present disclosure is not limited to these embodiments and modified examples. As long as the gist of the present disclosure is not deviated from, the configurations obtained by various modifications that can be thought of by those skilled in the art with respect to these embodiments, or the configurations constructed by combining the constituent elements of different embodiments and modified examples can also be included in the scope of one or more technical solutions of the present disclosure.

[0156] Industrial applicability

[0157] The semiconductor device provided with the vertical MOS transistor of the present application can be widely used as a device that controls the on state of a current path.

[0158] Explanation of reference numerals

[0159] 1, 100 semiconductor device

[0160] 2 semiconductor chip

[0161] 10 transistor (1st vertical MOS transistor)

[0162] 11 1st source electrode

[0163] 12, 13 portions

[0164] 14 1st source region

[0165] 15 1st gate conductor

[0166] 16 1st gate insulating film

[0167] 17 first gate trench

[0168] 18 first body region

[0169] 18a first connection region

[0170] 19 first gate electrode

[0171] 20 transistor (second vertical MOS transistor)

[0172] 21 second source electrode

[0173] 22, 23 portion

[0174] 24 second source region

[0175] 25 second gate conductor

[0176] 26 second gate insulating film

[0177] 27 second gate trench

[0178] 28 second body region

[0179] 28a second connection region

[0180] 29 second gate electrode

[0181] 30 metal layer

[0182] 32 semiconductor substrate

[0183] 33 low-concentration impurity layer (drift layer)

[0184] 34 interlayer insulating layer

[0185] 35 passivation layer

[0186] 40 semiconductor layer

[0187] 41 adhesive (conductive adhesive)

[0188] 42 support body (thick film metal plate)

[0189] 90 boundary line

[0190] 111 first source pad

[0191] 119 first gate pad

[0192] 121 second source pad

[0193] 129 second gate pad

[0194] 420 insulating support body

[0195] A1 first region

[0196] A2 2nd region

Claims

1. A semiconductor device, which is a semiconductor device capable of being mounted face down, is characterized in that it includes: a semiconductor substrate; a low-concentration impurity layer formed on the surface side of the semiconductor substrate; a first vertical MOS transistor formed in a first region of the semiconductor layer when the semiconductor substrate and the low-concentration impurity layer are taken together as the semiconductor layer; a second vertical MOS transistor formed in a second region adjacent to the first region in a plan view of the semiconductor layer; a metal layer in surface contact connection with the back side of the semiconductor substrate; and a support body bonded to the back side of the metal layer via an adhesive; in the plan view, the support body is larger in area than the semiconductor layer and includes the semiconductor layer; the thickness of the support body is larger than the thickness of the semiconductor layer; in a cross-section of the semiconductor device including the center and the outer periphery of the semiconductor layer in the plan view, the height of the adhesive along the side surface of the semiconductor layer is lower than the upper surface of the semiconductor layer; when observing the semiconductor chip other than the support body and the adhesive in the semiconductor device in the cross-section, the semiconductor chip is in a curved shape convex in the direction approaching the support body; when the bending amount of the semiconductor chip is w in μm and the minimum length among the closest distances from the outer periphery of the semiconductor layer to the outer periphery of the support body in the plan view is M in μm, the relationship of -0.75×w + 135.3 ≤ M ≤ -1.5×w + 270.6 holds.

2. The semiconductor device according to claim 1, wherein in the plan view, the semiconductor layer is rectangular; the thickness of the adhesive directly below the semiconductor layer at the outer periphery of the semiconductor layer in the plan view is greater than the thickness of the adhesive directly below the semiconductor layer at the center of the semiconductor layer in the plan view.

3. The semiconductor device according to claim 1, wherein in the plan view, let the length of the side of the semiconductor layer along the first direction be L1 in μm, let the length of the side of the semiconductor layer along the second direction orthogonal to the first direction be L2 in μm, and let the length of the adhesive exposed from the outer periphery of the semiconductor chip be b in μm, in the plan view, at the center of the semiconductor chip, when the thickness of the semiconductor chip is H in μm and the thickness of the adhesive is T in μm, the relationship of P×L1×L2 / {b×(L1 + L2)} < H + T + w (5 μm ≤ P ≤ 10 μm) holds.

4. The semiconductor device according to claim 1, wherein in the cross-section, the support body is in a curved shape convex in the direction towards the semiconductor chip; the bending amount of the support body is smaller than the bending amount of the semiconductor chip.

5. The semiconductor device according to claim 1, wherein In the cross-sectional view, the support body is convex and curved in a direction away from the semiconductor chip; The amount of curvature of the support body is smaller than the amount of curvature of the semiconductor chip.

6. The semiconductor device according to claim 1, wherein In the above-mentioned planar view, a protrusion protruding toward the above-mentioned adhesive is provided on the outer periphery of the above-mentioned metal layer; In the cross-section of the protrusion, the protrusion includes a portion where the height is 5 μm or greater.

7. The semiconductor device according to claim 1, wherein The metal layer has a multi-layer structure, and the surface in contact with the adhesive does not contain nickel.

8. The semiconductor device according to claim 1, wherein The adhesive is a conductive adhesive containing conductive particles and is composed of a resin that is thermosetting at 200° C. or lower.

9. The semiconductor device according to claim 1, wherein The supporting body is made of metal; The electrical conductivity of the support body is equivalent to that of the metal layer.

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