Chips, chip testing methods

Abstract

This disclosure provides a chip comprising: multiple identical multiplexing modules, each multiplexing module having a module input terminal and a module output terminal; a detection input pin connected to the module input terminal of each multiplexing module for inputting a detection signal to the module input terminal; a comparison module having an input terminal and an output terminal, the input terminal of the comparison module being connected to the module output terminal of each multiplexing module, the comparison module receiving and comparing the result signals output by each multiplexing module at its respective module output terminal in response to the detection signal, and outputting a comparison result at its output terminal indicating whether the result signals of all connected module output terminals are completely identical; and a comparison output pin connected to the output terminal of the comparison module for outputting a signal indicating the comparison result. This disclosure also provides a method for chip detection.

Description

Technical Field

[0001] This disclosure relates to the field of chip testing technology, and in particular to a chip and a method for chip testing. Background Technology

[0002] As chip manufacturing processes evolve, the number of devices in chips is increasing, their size is decreasing, and their scale is increasing. This increases the probability of defects. To screen out faulty chips and improve product quality, chip testing is necessary.

[0003] However, when testing chips that include a large number of multiplexed modules (such as multiplexed cores), the number of pins required by the chip is still large, and the testing process is complex. Summary of the Invention

[0004] This disclosure provides a chip and a method for chip testing.

[0005] In a first aspect, embodiments of this disclosure provide a chip comprising:

[0006] Multiple reusable modules with identical structures, each of the multiplexed modules having a module input terminal and a module output terminal;

[0007] A detection input pin is provided, which is connected to the module input terminal of each of the multiplexing modules, and is used to input the detection signal to the module input terminal.

[0008] A comparison module has an input terminal and an output terminal. The input terminal of the comparison module is connected to the output terminal of each of the multiplexing modules. The comparison module is used to receive and compare the result signals output by each of the multiplexing modules in response to the detection signal at their respective output terminals, and output a comparison result at the output terminal of the comparison module that indicates whether the result signals of all the output terminals of the connected modules are completely identical.

[0009] The comparison output pin is connected to the output terminal of the comparison module and is used to output a signal characterizing the comparison result.

[0010] Secondly, embodiments of this disclosure provide a method for detecting the above-mentioned chips, wherein the chip includes multiple multiplexed modules with identical structures, each multiplexed module having a module input terminal and a module output terminal, and the method includes:

[0011] Acquire the detection signal and synchronously transmit the detection signal to the module input terminal of each of the multiplexing modules;

[0012] Each of the multiplexing modules outputs a result signal at its respective module output terminal in response to the detection signal;

[0013] The result signals at the output terminals of each of the multiplexing modules are compared, and a comparison result is generated to indicate whether the result signals are completely identical.

[0014] Output a signal characterizing the comparison result.

[0015] The chip in this embodiment has a comparison module that compares the signals generated by multiple multiplexing modules and obtains a comparison result representing whether all signals are the same. Since the multiplexing modules have the same structure, when the same detection signal is input to them through the detection input pin, the resulting signals they generate should theoretically be the same. If they are different, it indicates that there are multiplexing modules with different structures. Therefore, by analyzing the comparison results, it is possible to determine to some extent whether the chip is faulty (for example, if the comparison results show that the resulting signals generated by the multiplexing modules are different, it means that at least some multiplexing modules are faulty), without necessarily outputting the result signals of all multiplexing modules. Therefore, the chip requires fewer pins, has a simpler structure, and the detection process is simple and fast. Attached Figure Description

[0016] In the accompanying drawings of the embodiments disclosed herein:

[0017] Figure 1 A block diagram of a chip provided in an embodiment of this disclosure;

[0018] Figure 2 A block diagram illustrating the composition of a multiplexing module in a chip, provided as an embodiment of this disclosure;

[0019] Figure 3 A block diagram of another chip provided in an embodiment of this disclosure;

[0020] Figure 4 A block diagram of another chip provided in an embodiment of this disclosure;

[0021] Figure 5 A circuit diagram of a comparison module in a chip provided in an embodiment of this disclosure;

[0022] Figure 6 A circuit diagram of another comparison module in a chip provided in an embodiment of this disclosure;

[0023] Figure 7 A flowchart of a chip detection method provided in this embodiment of the disclosure;

[0024] Figure 8 A flowchart of another chip detection method provided in this disclosure embodiment;

[0025] Figure 9 A schematic diagram of a specific chip detection logic process provided in an embodiment of this disclosure;

[0026] The meanings of the reference numerals in the attached figures include:

[0027] 11. First AND gate unit; 12. First OR gate unit; 13. First XOR gate unit; 14. Second OR gate unit; 15. Second AND gate unit; 21. Second XOR gate unit; 22. Third OR gate unit; 23. Multiplexer unit. Detailed Implementation

[0028] To enable those skilled in the art to better understand the technical solutions of this disclosure, the chip and chip testing method provided in the embodiments of this disclosure will be described in detail below with reference to the accompanying drawings.

[0029] The present disclosure will be described more fully below with reference to the accompanying drawings; however, the embodiments shown may be embodied in different forms, and the present disclosure should not be construed as limited to the embodiments set forth below. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will enable those skilled in the art to fully understand the scope of the disclosure.

[0030] The accompanying drawings of the embodiments disclosed herein are provided to further illustrate the embodiments of this disclosure and form part of the specification. They are used together with the detailed embodiments to explain this disclosure and do not constitute a limitation thereof. The above and other features and advantages will become more apparent to those skilled in the art from the description of the detailed embodiments with reference to the accompanying drawings.

[0031] This disclosure may be described with reference to plan and / or cross-sectional views using the ideal schematic diagrams of this disclosure. Therefore, the example illustrations may be modified according to manufacturing techniques and / or tolerances.

[0032] Where there is no conflict, the various embodiments of this disclosure and the features thereof in the embodiments may be combined with each other.

[0033] The terminology used in this disclosure is for the purpose of describing particular embodiments only and is not intended to limit the disclosure. The term "and / or" as used in this disclosure includes any and all combinations of one or more of the associated enumerated entries. The singular forms "a" and "the" as used in this disclosure are also intended to include the plural forms, unless the context clearly indicates otherwise. The terms "comprising," "made of," etc., as used in this disclosure specify the presence of the stated feature, integral, step, operation, element, and / or component, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or groups thereof.

[0034] Unless otherwise specified, all terms used in this disclosure (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art. It will also be understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and this disclosure, and will not be interpreted as having an idealized or overly formal meaning, unless expressly so defined in this disclosure.

[0035] This disclosure is not limited to the embodiments shown in the accompanying drawings, but includes modifications to the configuration based on the manufacturing process. Therefore, the areas illustrated in the drawings are schematic, and the shapes of the areas shown illustrate specific shapes of the areas of an element, but are not intended to be limiting.

[0036] As chip manufacturing processes (such as logic chips and network chips) evolve, the number of devices (such as transistors) in chips increases, their size decreases, and their scale increases. This increases the probability of defects (faults). For example, defects may include short circuits caused by sticking between circuits, circuits being incorrectly connected to unwanted locations (such as high or low levels), and delays caused by circuit defects.

[0037] To screen out faulty chips and improve product quality, it is essential to test the chips.

[0038] However, the integrated circuits within a chip are very large, and their combinational and sequential logic is extremely complex, making it difficult to directly test or observe the components. Therefore, specific detection signals can be input into the chip, and the resulting signals can be analyzed to determine if there are any structural faults in the chip.

[0039] Specifically, detection vectors (a series of signals consisting of 0s and 1s) can be generated through Automatic Test Pattern Generation (ATPG) technology and input into the chip through the input pin. At the same time, the result vector generated by the chip can be obtained through the output pin. The Automatic Test Equipment (ATE) compares the standard vector when there is no fault with the actual result vector to determine whether the chip is faulty.

[0040] In large-scale chips, multiple structurally identical parts, or multiple "multiplexed modules," such as multiple logic cores (multiplexed cores), are often included. Because these multiplexed modules have the same structure, they can be detected using the same detection signal (such as a detection vector). Therefore, a shared-input technique can be used, where the same detection signal is simultaneously input to multiple multiplexed modules through a single input pin of the chip, reducing the number of input pins and simplifying the input of the detection signal.

[0041] However, although the input detection signals can be shared, the different multiplexing modules operate independently. Therefore, the result signals (such as result vectors) generated by their respective operations still need to be read out through different output pins and compared with standard results (such as standard vectors) to determine whether each multiplexing module is faulty. Thus, the above method still requires a large number of output pins on the chip, and each multiplexing module still needs to be detected and analyzed separately. Therefore, the total number of pins on the chip remains large, the structure remains complex, and the detection process remains complex.

[0042] Moreover, testing costs are a significant component of chip costs, and the time spent on the testing process can delay the chip's time to market. Therefore, a complex testing process can also increase chip costs and affect its marketability.

[0043] Firstly, referring to Figures 1 to 6 This disclosure provides a chip.

[0044] This disclosure provides a chip with data processing capabilities that is packaged relatively independently, including but not limited to logic chips, network chips, etc.

[0045] Reference Figure 1 The chip in this embodiment of the disclosure includes:

[0046] Multiple reusable modules with identical structures, each having a module input terminal and a module output terminal;

[0047] The detection input pin is connected to the module input terminal of each multiplexing module and is used to input the detection signal to the module input terminal.

[0048] The comparison module has an input terminal and an output terminal. The input terminal of the comparison module is connected to the output terminal of each multiplexing module. The comparison module is used to receive and compare the result signals output by each multiplexing module in response to the detection signal at its respective module output terminal, and outputs a comparison result at the output terminal of the comparison module to indicate whether the result signals of all the module output terminals connected to it are completely identical.

[0049] The comparison output pin is connected to the output terminal of the comparison module and is used to output a signal representing the comparison result.

[0050] The chip in this embodiment can be divided into multiple modules, some of which have the same structure and function. These modules are called multiplexed modules.

[0051] For example, in a multi-core chip, multiple identical logical cores can be formed through wrapper chain technology, which are multiple reused cores (reuse modules).

[0052] The chip also has multiple pins (i.e. I / O ports, such as Pin) for external information exchange. Some of these pins are detection input pins for receiving detection signals. These detection input pins are connected to the module input terminal to transmit the received detection signals to the module input pins, so that the multiplexing module can operate according to the received detection signals and generate corresponding result signals at its own module output terminal.

[0053] In some embodiments, each detection input pin is connected to the module input terminal at the same location of each multiplexing module, and is used to synchronously input the same detection signal to each module input terminal to which it is connected.

[0054] Reference Figure 1 As one embodiment of this disclosure, each detection input pin can be connected to the same module input terminal of multiple multiplexing modules simultaneously, that is, the shared-input technology is adopted. Thus, inputting a detection signal to one detection input pin can enable the same detection signal to be received synchronously at the same position of the module input terminal of all multiplexing modules, thereby enabling each multiplexing module to operate synchronously and generate result signals synchronously.

[0055] It should be understood that it is also feasible to connect each detection input pin to only one module input instead of using shared input technology; in this case, when performing detection, the same detection signal needs to be input simultaneously to multiple detection input pins of the corresponding multiplexing modules.

[0056] Specifically, the detection signal can be a detection vector generated by Automatic Test Pattern Generation (ATPG) technology, which is a signal composed of a series of 0s and 1s; correspondingly, based on the detection vector, each multiplexing module will also generate a result vector, which is also a signal composed of a series of 0s and 1s.

[0057] When the multiplexing module is fault-free, the resulting vector it produces "should" be a standard signal, i.e., a standard vector; however, if the multiplexing module is faulty, the resulting vector it produces may differ from the standard vector in one or more positions.

[0058] Furthermore, ATPG-based detection can employ scan chains technology, which can be designed according to Design for Test (DFT) requirements. A scan chain is a structure where function registers are replaced with scan registers and connected in series. A multiplexer (MUX) is added, allowing for efficient input of detection signals and reception of output signals from the device under test (DUT), thus achieving detection. Under the control of the scan register's MUX selection signal (scan_enable), the scan chain typically operates in two modes: functional mode and detection mode. In functional mode, the scan register performs the functions of a register, storing combinational logic data and operating according to its original structure. In detection mode, the detection signal is sequentially shifted and input through the scan register, the detection result is acquired, and then shifted and output from the scan chain.

[0059] Furthermore, as chip sizes increase, the time and cost of chip testing also increase. Therefore, scan chain compression technology, such as EDT compression in Tessent tools, can be used. EDT compression can transform a large scan chain into multiple short scan chains to shorten testing time and reduce testing costs.

[0060] Reference Figure 1 The chip in this embodiment of the present disclosure also includes a comparison module. Each comparison module is connected to the module output terminal of each multiplexing module, so that it can receive the result signal generated by these multiplexing modules according to the detection signal, compare whether all result signals are completely the same, and generate the corresponding comparison result (such as using 0 to indicate that all result signals are completely the same, and using 1 to indicate that at least one of the result signals is different), and then output it from the comparison output pin.

[0061] Since all multiplexing modules should theoretically have the same structure, when multiple multiplexing modules receive the same detection signal at the same time, if all multiplexing modules are fault-free, the result signals generated by the output terminals of all multiplexing modules should also be exactly the same. If these result signals are not exactly the same, it means that the structures of all multiplexing modules are not exactly the same, that is, there is at least one faulty (different structure) multiplexing module.

[0062] It should be understood that each multiplexing module may actually have multiple module input terminals and multiple module output terminals. Different module input terminals of the same multiplexing module may need different detection signals, and the result signals generated by different module output terminals of the same multiplexing module may also be different.

[0063] Therefore, each of the above detection input pins should be connected to the same module input terminal of each multiplexing module (e.g., all connected to the input terminal of the a-th module), and each comparison module should also be connected to the same module output terminal of each multiplexing module (e.g., all connected to the output terminal of the b-th module), and the result signals of these module output terminals at the same location should be compared.

[0064] For example, refer to Figure 2 Each multiplexed module can have (n+1) module inputs, i.e., shared_dft_edt_in[n:0], and (m+1) module outputs, i.e., dft_edtout_i[m:0]. Therefore, referring to... Figure 3 The chip has n detection input pins (such as EDT input pins), (m+1) comparison modules and comparison output pins, and may also have (m+1) detection output pins (such as EDT output pins), multiplexer modules, etc., which will be described later.

[0065] Reference Figure 3 There can be a total of (j+1) multiplexing modules in the chip. Therefore, the output terminals of all multiplexing modules are from dft_edtout_i_0[m:0] to dft_edtout_i_j[m:0]. The k-th comparison module, comparison output pin, detection output pin, and multiplexer module are connected to the output terminals from dft_edtout_i_0[k] to dft_edtout_i_j[k].

[0066] It should be understood that, in addition to connecting the detection input pins and comparison modules, the module input and output terminals of each multiplexing module can also be connected to other conventional results in the chip; moreover, the chip may also include other pins for inputting and outputting signals during normal operation.

[0067] The chip in this embodiment has a comparison module that compares the signals generated by multiple multiplexing modules and obtains a comparison result representing whether all signals are the same. Since the multiplexing modules have the same structure, when the same detection signal is input to them through the detection input pin, the resulting signals they generate should theoretically be the same. If they are different, it indicates that there are multiplexing modules with different structures. Therefore, by analyzing the comparison results, it is possible to determine to some extent whether the chip is faulty (for example, if the comparison results show that the resulting signals generated by the multiplexing modules are different, it means that at least some multiplexing modules are faulty), without necessarily outputting the result signals of all multiplexing modules. Therefore, the chip requires fewer pins, has a simpler structure, and the detection process is simple and fast.

[0068] In some embodiments, the chip of this disclosure further includes: a detection output pin, which is connected to the output terminal of the module and is used to output the result signal of the module output terminal.

[0069] As before, comparing the results can determine whether all reused modules are completely identical, but it cannot determine whether a single reused module is functioning correctly; therefore, refer to... Figure 3 The chip in this embodiment may also be provided with a detection output pin, which can directly output the result (result signal) generated by the operation of the multiplexing module itself, so that the failure of the corresponding multiplexing module itself can be directly determined by analyzing the result signal.

[0070] In some embodiments, the multiplexer module has multiple input terminals, output terminals, and a control terminal; the multiple input terminals of the multiplexer module are connected to multiple module output terminals, and the control terminal of the multiplexer module is connected to an output selection signal terminal. The multiplexer module is used to select the module output terminal connected to the output terminal of the multiplexer module according to the signal of the output selection signal terminal.

[0071] In some embodiments, when the chip further includes a detection output pin, the detection output pin is connected to the output of the multiplexer module.

[0072] Reference Figure 3 , Figure 4 As one embodiment of this disclosure, the chip may also include a multiplexer (MUX) module. By outputting the selection signal (dft_edtout_sel[j:0]), the multiplexer module can "select" one of the multiple module outputs connected to it to conduct with its own output, that is, select a result signal as its own output.

[0073] Furthermore, refer to Figure 3 When the above detection output pins are available, the detection output pins can be connected to the output of the multiplexer module. That is, the multiplexer module can select which multiplexing module's result signal to output from the detection output pin.

[0074] As before, the number of multiplexer modules and detection output pins should correspond to the number of module outputs of a single multiplexing module, which is (m+1). At the same time, the output selection signal (dft_edtout_sel[j:0]) should usually cause the multiplexer module and detection output pins to output the result signal of one of the multiplexing modules in (j+1) multiplexing modules.

[0075] For example, it could be a reference. Figure 9First, select a multiplexing module and obtain the result signals generated by the output terminals of each module. If the result signal of the multiplexing module is correct, it can be determined that the multiplexing module is correct (e.g., Golden core). Then, by comparing the results, it can be determined whether all multiplexing modules are the same. If they are the same, it means that all multiplexing modules are correct and the chip is fault-free. Otherwise, it means that at least one other multiplexing module is different from the Golden core and the chip is faulty.

[0076] It should be understood that it is also feasible if only the output terminals of some multiplexing modules (such as a selected multiplexing module) are directly connected to the corresponding detection output pins.

[0077] Among them, reference Figure 3 As one embodiment of this disclosure, the detection output pin and the comparison output pin can be two physically independent pins, so that they can output result signals and comparison results separately (including simultaneously).

[0078] In some embodiments, the chip of this disclosure further includes: a processing module, the processing module having an input terminal and an output terminal, the input terminal of the processing module being connected to the output terminal of a multiplexer module and the output terminal of a comparison module respectively, the output terminal of the processing module being connected to a comparison output pin, and the processing module being used to process the result signal output by the output terminal of the multiplexer module to which it is connected and the comparison result output by the output terminal of the comparison module to which it is connected, and then output the result to the comparison output pin.

[0079] As one embodiment of this disclosure, refer to Figure 3 , Figure 4 The output of the multiplexer module (i.e., the result signal, which is also the module output) and the output of the comparison module (i.e., the comparison result) can be connected to the comparison output pin through the processing module, so that the processing module can perform certain processing on the above result signal and comparison result, and then send the processed result to the comparison output pin.

[0080] In some embodiments, the processing module includes a selection submodule, which is used to select a signal or result signal representing the comparison result to be output from the comparison output pin.

[0081] Reference Figure 4 As another embodiment of this disclosure, the processing module may specifically include a selection submodule, which controls the comparison output pin to specifically output a signal representing the comparison result, or output a result signal; that is, the processing module performs a "selection" process between the result signal and the comparison result.

[0082] Therefore, the number of pins on the chip can be further reduced by using a single "common" physical pin (compare output pin) to output the comparison result and the result signal in a "time-division" manner.

[0083] The specific forms of the above-mentioned selection sub-modules are diverse.

[0084] For example, in the simplest way, the output of the module (such as the output of the multiplexer module mentioned above) and the output of the comparator module can each be connected to the comparator output pin through a transistor (selection submodule). By controlling one transistor to be turned on and the other transistor to be turned off, the selected signal can be output.

[0085] For example, you can also refer to Figure 4 The selection submodule is an AND gate, with its two inputs connected to the output of the corresponding comparison module and the control terminal of the selection submodule, respectively. Its output is connected to the control terminal of the multiplexer (MUX) in the corresponding conversion submodule (described later). The module output (such as the output of the multiplexer module mentioned above) is connected to the comparison output pin via the multiplexer. Therefore, by setting the signal (dft_edtout_uncomp) at the control terminal of the selection submodule to 0, the output of the AND gate is guaranteed to be 0, meaning the signal at the control terminal of the multiplexer is 0, thus allowing the multiplexer to continuously output the signal from the module output terminal, which in turn causes the comparison output pin to output the result signal. Conversely, by setting the signal (dft_edtout_uncomp) at the control terminal of the selection submodule to 1, the AND gate can actually output the comparison result signal, or the comparison result can be loaded onto the control terminal of the multiplexer, ultimately outputting a signal representing the comparison result at the comparison output pin (described later).

[0086] In some embodiments, the processing module includes:

[0087] The conversion submodule is used to generate a conversion comparison result based on the comparison result and the result signal, which serves as a signal characterizing the comparison result. Specifically, when the comparison result characterizes the result signals at all module outputs in the same way, the conversion comparison result is the same as the signal at the module output. When the comparison result characterizes the result signals at all module outputs in different ways, the conversion comparison result is the opposite of the signal at the module output.

[0088] As mentioned before, the detection signal can be the detection vector generated by ATPG technology, and the signal output by the corresponding module is the result vector. The analysis process of the result vector is to compare the result vector with the preset standard vector.

[0089] However, the comparison result directly generated by the comparison module is entirely determined by whether the signals of the multiplexing module are the same, and has nothing to do with the original form of the result vector and the standard vector, so it is not convenient to analyze it.

[0090] Therefore, it can be referred to Figure 3 , Figure 4 A conversion submodule is set up to transform the comparison result into a "converted comparison result" format. In other words, the processing module performs the process of "converting" the comparison result format based on the result signal. The characteristics of the resulting converted comparison result are:

[0091] (1) If the comparison result at a certain moment indicates that the signals of all multiplexing modules are the same, then the corresponding bit of the conversion comparison result is the same as the corresponding bit of the result signal at the output of the module;

[0092] (2) If the comparison result at a certain moment indicates that the signals of all multiplexed modules are different, then the corresponding bit of the conversion comparison result is the inversion of the corresponding bit of the result signal at the output of the module.

[0093] Therefore, a similar approach to analyzing result vectors in related technologies can be used to analyze the transformation comparison result (which represents the comparison result). That is, the transformation comparison result is compared with the standard vector. If a certain bit is different from the standard vector, it can be determined that there is an error in the signal of at least one multiplexing module at the corresponding time.

[0094] The specific forms of the above conversion sub-modules are varied.

[0095] For example, refer to Figure 3 , Figure 4 The conversion submodule may include the multiplexer mentioned above. The module output (such as the output of the multiplexer module) is directly connected to and inverted (such as through a NOT gate) to the two inputs of the multiplexer. The control terminal of the multiplexer is connected to the output of the comparator module (including the reference). Figure 3 Direct link, or refer to Figure 4 By connecting the above submodules using AND gates, thus:

[0096] (1) When the comparison result is 0 (the signals of all multiplexing modules are the same), the comparison result control multiplexer directly outputs the result signal;

[0097] (2) When the comparison result is 1 (the signals of at least one multiplexed module are different), the comparison result controls the multiplexer to output the inverted result signal.

[0098] It should be understood, with reference Figure 4 When both a selection submodule and a conversion submodule are present, if the selection submodule controls the output signal of the comparison output pin, the conversion submodule will not function; however, if the selection submodule controls the output signal of the comparison output pin, the actual output will be the conversion comparison result generated by the conversion submodule.

[0099] It should be understood that the specific form of the processing module is diverse. For example, it may contain only one of the selection submodule and the transformation submodule, or both of them, or other submodules. Moreover, the selection submodule, transformation submodule, etc., may also take other specific forms, which will not be described in detail here.

[0100] It should be understood that selecting submodules, converting submodules, etc., can also take other specific forms, which will not be described in detail here.

[0101] In some embodiments, the comparison module includes:

[0102] The first AND gate unit 11 includes multiple input terminals that correspond one-to-one with the output terminals of each module connected to the comparison module, and each input terminal is connected to its corresponding module output terminal.

[0103] The first OR gate unit 12 includes multiple input terminals that correspond one-to-one with the output terminals of each module connected to the comparison module, and each input terminal is connected to its corresponding module output terminal.

[0104] The first XOR gate unit 13 includes two input terminals that are respectively connected to the output terminal of the first AND gate unit 11 and the output terminal of the first OR gate unit 12.

[0105] Reference Figure 5 As one embodiment of this disclosure, each comparison module may specifically include a first AND gate unit 11 and a first OR gate unit 12, and all module output terminals (such as the (j+1) segments) corresponding to the comparison module are respectively connected to the inputs of the first AND gate unit 11 and the first OR gate unit 12, and the outputs of the first AND gate unit 11 and the first OR gate unit 12 are simultaneously connected to the input of the first XOR gate unit 13.

[0106] Therefore, if the signals at the output terminals of all modules are the same (all 1 or all 0), then the outputs of the first AND gate unit 11 and the first OR gate unit 12 must also be the same (all 1 or all 0), so the comparison result generated by the first XOR gate unit 13 after their outputs are passed through the first XOR gate unit 13 is 0; however, as long as the signals at the output terminals of all modules are not completely the same (some are 1 and some are 0), then the output of the first AND gate unit 11 must be 0 and the output of the first OR gate unit 12 must be 1, so the comparison result generated by the first XOR gate unit 13 after their outputs are passed through the first XOR gate unit 13 is 1.

[0107] In some embodiments, the comparison module further includes a second OR gate unit 14 and a second AND gate unit 15 corresponding to at least a portion of the module output terminals;

[0108] Each second OR gate unit 14 includes two input terminals that are respectively connected to its corresponding module output terminal and the first shielded signal terminal, and an output terminal that is connected to the input terminal of the first AND gate unit 11;

[0109] Each second AND gate unit 15 includes two inverted input terminals connected to its corresponding module output terminal and the first shielded signal terminal, respectively, and an output terminal connected to the input terminal of the first OR gate unit 12.

[0110] The second OR gate unit 14 and the second AND gate unit 15, which correspond to the output terminals of the same module, are connected to the same first shielded signal terminal.

[0111] In some cases, it may be desirable not to compare certain reused modules, which requires "masking" the information of the relevant reused modules so that they do not affect the comparison modules.

[0112] For example, if a fault has been identified in a multiplexing module, the signal of that multiplexing module can be blocked to further analyze whether other multiplexing modules are faulty.

[0113] Therefore, it can be referred to Figure 5 In the comparison module, a second OR gate unit 14 is provided between each module output terminal and the corresponding first AND gate unit 11, and a second AND gate unit 15 is provided between each module output terminal and the corresponding first OR gate unit 12. Moreover, the other output terminal of the second OR gate unit 14 and the second AND gate unit 15 corresponding to the same module output terminal is respectively connected to the same first shielded signal terminal and its inverted phase.

[0114] It should be understood that "inverted" in the embodiments of this disclosure means that the signals ultimately connected at the two positions are inverted, and its specific implementation is diverse, as can be found in the following references. Figure 5 A NOT gate unit can be set between the first shielded signal terminal and the second AND gate unit 15, or the two positions can be connected to different ports respectively, and the signals provided by the two ports are always out of phase.

[0115] At the same time, the out-of-phase nature of two signals is a relative concept rather than an absolute one; for example, referring to... Figure 5 The NOT gate unit can also be located between the first shielded signal terminal and the second OR gate unit 14. In this case, it is only necessary to invert the signal provided by the first shielded signal terminal.

[0116] When it is necessary to shield the signal at the output terminal of a certain module, the signal (dft_comp_mask_en[j:0]) of the corresponding first shielding signal terminal can be set to 1, so that the output of the second OR gate unit 14 is always 1, and 1 "does not affect" the output of the subsequent first AND gate unit 11; at the same time, the inversion of the signal at the first shielding signal terminal is 0, so the output of the second AND gate unit 15 is always 0, and 0 also "does not affect" the output of the subsequent first OR gate unit 12.

[0117] For module outputs that do not need to be shielded, the signal of the corresponding first shielding signal terminal is set to 1, which means that the presence of the second AND gate unit 15 and the second OR gate unit 14 "does not affect" the result signal of the module output.

[0118] In other words, when the signal (dft_comp_mask_en[j:0]) of the first shielding signal terminal corresponding to the module output terminal is set to 1, the first AND gate unit 11 and the first OR gate unit 12 can work only according to the signal of the "other" module output terminal, and are not affected by the signal of the module output terminal, that is, the signal of the corresponding module output terminal is "shielded".

[0119] In some embodiments, the comparison module includes:

[0120] Multiple second XOR gate units 21, one of the output terminals of each module connected to the comparison module is simultaneously connected to one input terminal of all second XOR gate units 21, and each other module output terminal is connected to the other input terminal of each second XOR gate unit 21 respectively;

[0121] The third OR gate unit 22 includes multiple input terminals that are respectively connected to the output terminals of each of the second XOR gate units 21.

[0122] Reference Figure 6 As another embodiment of this disclosure, the comparison module may also include multiple (j) second XOR gate units 21, with one input terminal of all second XOR gate units 21 connected to the same module output terminal. Figure 6 Taking module output j as an example, while the outputs of each of the other modules ( Figure 6 Taking module output terminals 0 to j-1 as an example, each is connected to the other input terminal of a second XOR gate unit 21. Thus, multiple second XOR gate units 21 are equivalent to comparing the signal of a selected module output terminal (module output terminal j) with the signal of each other module output terminal. If the results are all the same, the output of all second XOR gate units 21 is 0, and the comparison result 0 can be generated by the third OR gate unit 22. If the results are not all the same, the output of the second XOR gate unit 21 will be 1, and the comparison result 1 can be generated by the third OR gate unit 22.

[0123] In some embodiments, the comparison module further includes a multiplexer unit 23 corresponding to at least some of the module outputs; the module outputs are directly connected to and inverted connected to the two inputs of their respective multiplexer units 23, the output of the multiplexer unit 23 is connected to the corresponding second XOR gate unit 21, and the control terminal of the multiplexer unit 23 is connected to the second shielding signal terminal.

[0124] For reference Figure 6 The comparison module also includes a multiplexer (MUX) unit 23 that acts as a shield. Each module output is directly connected to and inverted connected to the multiplexer unit 23 (e.g., by setting a NOT gate unit). Therefore, the signal (dft_comp_mask_en[j:0]) at the second shielding signal terminal can be used to select the original signal or its inverted signal at the output of the output module of the multiplexer unit 23.

[0125] Therefore, when it is determined that the output signal of a certain module is incorrect at a certain time, the signal of the second shielding signal terminal can be used to control the output of the corresponding multiplexer unit 23 to output its inverted signal. This ensures that the signal entering the second XOR gate unit 21 from the output of the module is always correct, thus shielding the influence of the signal at the output of the module.

[0126] It should be understood that the chip may also include other structures, such as a timing logic module located before the detection output pin (including the shared comparison output pin), a register module directly connected to the output of each module, and a compression / decompression unit located in the multiplexing module, etc., which will not be described in detail here.

[0127] The effects of the chip implementation in the embodiments of this disclosure will be described in detail below.

[0128] For example, suppose a chip has 32 multiplexed cores, each multiplexed core has 6 output terminals, and the chip has 36 output pins.

[0129] Therefore, according to the ATPG detection method in the relevant technology, a maximum of 36 / 6 = 6 multiplexed nuclei can be detected each time on the ATE device, so a total of 32 / 6≈6 detections are required, and the detection time is approximately 6T (the time for a single detection is T).

[0130] If the method of this disclosure embodiment is adopted, only one detection is required (if the comparison result and the result signal can be output simultaneously) or two detections are required (if the comparison result and the result signal are output separately). The detection time is approximately T or 2T, which is 1 / 6 or 1 / 3 of the related technology.

[0131] Moreover, if the method of this disclosure embodiment is adopted, only 6 output pins are actually required (if the comparison result and the result signal are output in a time-division manner through the comparison output pin) or 12 (if the comparison result and the result signal are output through different pins), which can greatly reduce the number of output pins to be used and save I / O resources.

[0132] Secondly, referring to Figures 1 to 9 This disclosure provides a method for detecting the above-mentioned chips.

[0133] The chip detected by the method of this disclosure includes multiple multiplexed modules with identical structures, each multiplexed module having a module input terminal and a module output terminal.

[0134] It should be understood that the chip detection method of this disclosure can be used to detect any kind of chip of this disclosure.

[0135] Reference Figure 7 The chip detection method of this disclosure includes:

[0136] S201. Acquire the detection signal and synchronously transmit the detection signal to the module input terminal of each multiplexing module.

[0137] S202. Each multiplexing module outputs a result signal at its respective module output terminal for the detection signal.

[0138] S203. Compare the result signals at the output terminals of each multiplexing module and generate a comparison result indicating whether the result signals are completely identical.

[0139] S204. Output the signal representing the comparison result.

[0140] In the chip detection method of this disclosure embodiment, the chip first acquires a detection signal (e.g., received through a detection input terminal) and synchronously transmits it to the module input terminals of each multiplexing module within it. Thus, each multiplexing module will work synchronously according to the detection signal and output a result signal at its respective module output terminal. Afterward, the chip can compare the result signals at the module output terminals of each multiplexing module to generate a comparison result indicating whether they are all the same (e.g., generated in a comparison module). Finally, the chip can output a signal characterizing the comparison result (e.g., output through a comparison output pin).

[0141] Therefore, by analyzing the signal of the comparison result, it can be determined whether the multiplexing modules of the chip are completely consistent (i.e., the consistency of the multiplexing modules is determined).

[0142] In some embodiments, the detection signal includes a detection vector generated based on ATPG technology.

[0143] In some embodiments, the chip further includes detection input pins, each detection input pin being connected to the module input terminal at the same location of each multiplexing module; see reference. Figure 8 Acquiring the detection signal and synchronously transmitting the detection signal to the module input terminal of each multiplexing module (S201) includes:

[0144] S2011. Obtain the detection signal through the detection input pin and transmit the detection signal synchronously to the input terminals of each module connected to the detection input pin.

[0145] When the chip adopts the above shared-input technology, the detection signal obtained through a detection input pin can be synchronously transmitted to the module input terminal at the same position of each multiplexing module.

[0146] It should be understood that it is also feasible not to use the shared input terminal technology. In this case, it is necessary to provide the same detection signal to multiple detection input pins of the corresponding multiplexing module at the same time.

[0147] In some embodiments, refer to Figure 8 After each multiplexing module outputs a result signal at its respective module output terminal for the detection signal (S202), the method further includes:

[0148] S205, Output result signal.

[0149] During chip testing, the chip can also output (e.g., through detection output pins or comparison output pins in a time-division manner) the result signal (e.g., result vector) of a specific multiplexing module. By analyzing the result signal (e.g., by comparing the result vector with a standard vector), it can be determined whether the corresponding multiplexing module is faulty, that is, the correctness of the multiplexing module can be determined.

[0150] It should be understood that the process of determining the consistency of reused modules and the process of determining the correctness of reused modules are relatively independent, and there is no necessary execution order or relationship between the two.

[0151] For example, the process of determining the consistency and correctness of the reuse module is carried out in two steps: the detection signal is input twice, and the comparison result and the result signal are obtained by comparing the output key, and there is no necessary order in which the two are obtained.

[0152] Alternatively, when the chip has separate comparison output pins and detection output pins, the comparison result and the result signal can be acquired simultaneously with a single input test signal.

[0153] For example, you can refer to Figure 9First, a multiplexing module (multiplexing core) is randomly selected, and its result signal (result vector) is obtained. This result is compared with the standard result (standard vector). If they are the same, the multiplexing module is determined to be normal (e.g., it is determined to be the Golden core). Then, the result signals of all multiplexing modules are input to the comparison module. The comparison result is analyzed to be 0 or 1. If it is 0, it means that all multiplexing modules have the same structure (i.e., the same as the Golden core), so the chip can be determined to be fault-free. If it is 1, it means that the multiplexing modules have different structures (i.e., different from the Golden core), so the chip can be determined to be faulty.

[0154] Alternatively, one could first check if all reused modules are identical, and then proceed with different subsequent steps based on the results:

[0155] (1) If they are the same, it can be assumed that the chip is fault-free; or, a multiplexed module can be selected for correctness testing. If the multiplexed module is normal, the chip is confirmed to be fault-free.

[0156] (2) If they are different, the chip can be directly identified as faulty and the process can be terminated (if fault location is not required); or, the correctness of one or more of the multiplexing modules can be further checked to achieve fault location.

[0157] Those skilled in the art will understand that all or some of the steps, systems, and devices disclosed above, as functional modules / units, can be implemented as software, firmware, hardware, or suitable combinations thereof.

[0158] In hardware implementations, the division between functional modules / units mentioned in the above description does not necessarily correspond to the division of physical components; for example, a physical component may have multiple functions, or a function or step may be executed by several physical components working together.

[0159] This disclosure has disclosed exemplary embodiments, and although specific terminology has been used, it is for general illustrative purposes only and should not be construed as limiting. In some instances, it will be apparent to those skilled in the art that features, characteristics, and / or elements described in conjunction with particular embodiments may be used alone, or in combination with features, characteristics, and / or elements described in conjunction with other embodiments, unless otherwise expressly indicated. Therefore, those skilled in the art will understand that various changes in form and detail may be made without departing from the scope of this disclosure as set forth by the appended claims.

Claims

1. A chip, wherein, include: Multiple reusable modules with identical structures, each of the multiplexed modules having a module input terminal and a module output terminal; A detection input pin is provided, which is connected to the module input terminal of each of the multiplexing modules, and is used to input the detection signal to the module input terminal. A comparison module has an input terminal and an output terminal. The input terminal of the comparison module is connected to the output terminal of each of the multiplexing modules. The comparison module is used to receive and compare the result signals output by each of the multiplexing modules in response to the detection signal at their respective output terminals, and output a comparison result at the output terminal of the comparison module that indicates whether the result signals of all the output terminals of the connected modules are completely identical. The comparison output pin is connected to the output terminal of the comparison module and is used to output a signal characterizing the comparison result. A multiplexer module has multiple input terminals, output terminals, and a control terminal; the multiple input terminals of the multiplexer module are connected to multiple output terminals of the module, and the control terminal of the multiplexer module is connected to an output selection signal terminal; the multiplexer module is used to select the output terminal of the module connected to the output terminal of the multiplexer module according to the signal of the output selection signal terminal. The processing module has an input terminal and an output terminal. The input terminal of the processing module is connected to the output terminal of the multiplexer module and the output terminal of the comparison module, respectively. The output terminal of the processing module is connected to the comparison output pin. The processing module is used to process the result signal output from the output terminal of the multiplexer module and the comparison result output from the output terminal of the comparison module and output the result to the comparison output pin.

2. The chip according to claim 1, wherein, Each of the detection input pins is connected to the module input terminal at the same position of each of the multiplexing modules, and is used to synchronously input the same detection signal to each of the connected module input terminals.

3. The chip according to claim 1, wherein, Also includes: The detection output pin is connected to the output terminal of the module and is used to output the result signal of the module output terminal.

4. The chip according to claim 1, wherein, Also includes: The detection output pin is connected to the output terminal of the multiplexer module.

5. The chip according to claim 1, wherein, The processing module includes: The selection submodule is used to select whether to output a signal characterizing the comparison result or the result signal from the comparison output pin.

6. The chip according to claim 1, wherein, The processing module includes: A conversion submodule is configured to generate a conversion comparison result based on the comparison result and the result signal, which serves as a signal characterizing the comparison result. Specifically, when the comparison result characterizes all the result signals at the output terminals of the modules to be completely identical, the conversion comparison result is the same as the signal at the output terminal of the module; when the comparison result characterizes all the result signals at the output terminals of the modules to be not completely identical, the conversion comparison result is opposite to the signal at the output terminal of the module.

7. The chip according to claim 1, wherein, The comparison module includes: The first AND gate unit includes a plurality of input terminals that correspond one-to-one with the output terminals of each of the modules connected to the comparison module, and each input terminal is connected to its corresponding module output terminal. The first OR gate unit includes a plurality of input terminals that correspond one-to-one with the output terminals of each of the comparison modules, and each input terminal is connected to its corresponding module output terminal. The first XOR gate unit includes two input terminals that are respectively connected to the output terminal of the first AND gate unit and the output terminal of the first OR gate unit.

8. The chip according to claim 7, wherein, The comparison module further includes a second OR gate unit and a second AND gate unit corresponding to at least some of the module outputs; Each of the second OR gate units includes two input terminals that are respectively connected to its corresponding module output terminal and the first shielded signal terminal, and an output terminal that is connected to the input terminal of the first AND gate unit; Each of the second AND gate units includes two inverted input terminals respectively connected to its corresponding module output terminal and the first shielded signal terminal, and an output terminal connected to the input terminal of the first OR gate unit: The second OR gate unit and the second AND gate unit corresponding to the same output terminal of the module are connected to the same first shielded signal terminal.

9. The chip according to claim 1, wherein, The comparison module includes: Multiple second XOR gate units, wherein one of the output terminals of each module connected to the comparison module is simultaneously connected to one input terminal of all the second XOR gate units, and each of the other module output terminals is respectively connected to the other input terminal of each of the second XOR gate units; The third OR gate unit includes multiple input terminals that are respectively connected to the output terminals of each of the second XOR gate units.

10. The chip according to claim 9, wherein, The comparison module also includes a multiplexer unit corresponding to at least some of the module outputs; The output terminals of the module are directly connected to and inverted connected to the two input terminals of their corresponding multiplexer units, respectively. The output terminal of the multiplexer unit is connected to the corresponding second XOR gate unit, and the control terminal of the multiplexer unit is connected to the second shielding signal terminal.

11. A method for chip detection, wherein, The chip is the chip according to any one of claims 1 to 10, and the method includes: Acquire the detection signal and synchronously transmit the detection signal to the module input terminal of each of the multiplexing modules; Each of the multiplexing modules outputs a result signal at its respective module output terminal in response to the detection signal; The result signals at the output terminals of each of the multiplexing modules are compared, and a comparison result is generated to indicate whether the result signals are completely identical. Output a signal characterizing the comparison result.

12. The method according to claim 11, wherein, The step of acquiring the detection signal and synchronously transmitting the detection signal to the input terminal of each of the multiplexing modules includes: The detection signal is acquired through the detection input pin and synchronously transmitted to the input terminals of each module connected to the detection input pin.

13. The method according to claim 11, wherein, After each of the multiplexing modules outputs a result signal at its respective module output terminal in response to the detection signal, the method further includes: Output the resulting signal.

14. The method according to claim 11, wherein, The detection signal includes a detection vector generated based on the Automatic Detection Vector Generation (ATPG) technology.

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