Display module, manufacturing method and display device

Abstract

The application discloses a display module, a manufacturing method and a display device. The display module of one embodiment comprises a substrate, a gate signal line arranged on the substrate, a data signal line arranged in insulation with the gate signal line, a plurality of pixel areas formed by the intersection of the orthographic projection of the gate signal line and the data signal line, the gate signal line comprising a first conductive layer extending along a first direction and arranged in sequence in a second direction perpendicular to the first direction, and a first oxide layer in the orthographic projection of the substrate located in the part of the orthographic projection of the substrate of the first conductive layer, the data signal line comprising a second conductive layer extending along the second direction and arranged in sequence in the first direction, and a second oxide layer in the orthographic projection of the substrate coinciding with the orthographic projection of the second conductive layer in the substrate, and the first oxide layer not overlapping with the second oxide layer in the orthographic projection of the substrate.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of display. More particularly, it relates to a display module, a manufacturing method and a display device. BACKGROUND

[0002] In the related art, the contrast ratio (CR) of a display product is affected by many factors, one of which is the reflection of metal in the wiring layer. The metal used in the current wiring layer is copper, which has strong reflectivity.

[0003] Light from the backlight is incident on the metal wire through scattering, reflection, refraction and other ways of other materials in the box, and then reflected to the front of the screen through the metal wire, which reduces the contrast ratio of the product. In addition, the display product also has a display defect of uneven green and red color, which is mainly affected by film layer interference. For a thin film transistor liquid crystal display (TFT-LCD display), the backlight needs to penetrate through insulating films such as insulating layer and passivation layer. Since the refractive index of light is different for different film layers, film layer interference is easily generated, which in turn causes the uneven green and red color phenomenon. SUMMARY

[0004] The present application aims to provide a display module, a manufacturing method and a display device to solve at least one of the problems in the prior art.

[0005] To achieve the above-mentioned purpose, the present application adopts the following technical solutions:

[0006] The present application provides a display module in a first aspect, which comprises:

[0007] a substrate;

[0008] a gate signal line arranged on the substrate;

[0009] a data signal line arranged in insulation with the gate signal line, the gate signal line and the data signal line intersecting in orthographic projection of the substrate to form a plurality of pixel areas;

[0010] wherein,

[0011] the gate signal line comprises:

[0012] a first conductive layer extending in a first direction and arranged in sequence in a second direction perpendicular to the first direction; and

[0013] a first oxide layer in orthographic projection of the substrate located in a part of the orthographic projection of the first conductive layer in orthographic projection of the substrate;

[0014] the data signal line comprises:

[0015] a second conductive layer extending in the second direction and arranged in sequence in the first direction; and

[0016] a second oxide layer, a projection of the second oxide layer on the substrate does not overlap with a projection of the second conductive layer on the substrate,

[0017] a projection of the first oxide layer on the substrate does not overlap with a projection of the second oxide layer on the substrate.

[0018] In an optional embodiment, the first oxide layer is obtained by oxidizing the first conductive layer, the first oxide layer has a reflectivity lower than that of the first conductive layer;

[0019] the second oxide layer is obtained by oxidizing the second conductive layer, the second oxide layer has a reflectivity lower than that of the second conductive layer.

[0020] In an optional embodiment, the display module further comprises a driving transistor disposed on the substrate in the pixel region, the driving transistor comprises:

[0021] a gate layer disposed on the substrate;

[0022] a gate insulating layer covering the gate layer, the gate insulating layer is further used for insulating the gate signal line and the data signal line;

[0023] an active layer disposed on a side of the gate insulating layer away from the substrate;

[0024] a source-drain electrode layer covering the active layer and at least partially disposed on a surface of the gate insulating layer away from the substrate.

[0025] In an optional embodiment, the source-drain electrode layer comprises:

[0026] a source conductive layer connected to one end of the active layer and covering at least part of a surface of the active layer away from the substrate;

[0027] a drain conductive layer connected to the other end of the active layer and covering at least part of a surface of the active layer away from the substrate; and

[0028] a third oxide layer covering surfaces of the source conductive layer and the drain conductive layer away from the substrate.

[0029] In an optional embodiment, the third oxide layer is obtained by oxidizing the source conductive layer and the drain conductive layer, the third oxide layer has a reflectivity lower than that of the source conductive layer and lower than that of the drain conductive layer.

[0030] In an alternative embodiment, a projection of the gate insulating layer on the substrate covers a projection of the second conductive layer on the substrate, and covers a combined projection of the source conductive layer and the drain conductive layer on the substrate, in a projection of the first conductive layer on the substrate, the gate insulating layer is not disposed at a non-overlapping position of the first conductive layer and the second conductive layer on the substrate.

[0031] In an alternative embodiment, a surface of the gate layer distal to the substrate is completely covered by the gate insulating layer;

[0032] a projection of the gate insulating layer on the substrate covers a projection of the gate layer on the substrate, and covers a combined projection of the source conductive layer and the drain conductive layer on the substrate,

[0033] a surface of the source conductive layer proximal to the substrate is completely disposed at a surface of the gate insulating layer distal to the substrate;

[0034] a surface of the drain conductive layer proximal to the substrate is completely disposed at a surface of the gate insulating layer distal to the substrate.

[0035] In an alternative embodiment, in a projection of the first conductive layer on the substrate, the first oxide layer is disposed at a non-overlapping position of the first conductive layer and the second conductive layer on the substrate;

[0036] the second oxide layer is disposed at a position of the second conductive layer on the substrate;

[0037] the third oxide layer covers a combined projection of the source conductive layer and the drain conductive layer on the substrate.

[0038] In an alternative embodiment, a projection of the gate insulating layer on the substrate covers a combined projection of the first conductive layer and the second conductive layer on the substrate,

[0039] in a projection of the first conductive layer on the substrate, the gate insulating layer is not disposed at a non-overlapping position of the first conductive layer and the second conductive layer on the substrate;

[0040] in a projection of the second conductive layer on the substrate, the gate insulating layer is not disposed at a non-overlapping position of the first conductive layer and the second conductive layer on the substrate.

[0041] In an alternative embodiment, a surface of the gate layer distal to the substrate is completely covered by the gate insulating layer, a projection of the gate insulating layer on the substrate covers a projection of the gate layer on the substrate,

[0042] A projection of the gate insulating layer on the substrate overlaps a projection of the source conductive layer and the drain conductive layer on the substrate,

[0043] A surface portion of the source conductive layer near a side of the substrate facing away from the substrate is disposed on a surface of the gate insulating layer facing away from the substrate and on a surface of the substrate;

[0044] A surface portion of the drain conductive layer near a side of the substrate facing away from the substrate is disposed on a surface of the gate insulating layer facing away from the substrate and on a surface of the substrate.

[0045] In an optional embodiment, the display module comprises:

[0046] In a projection of the first conductive layer on the substrate, a projection of the first oxide layer on the substrate is disposed at a position where a projection of the second conductive layer on the substrate does not overlap a projection of the first conductive layer on the substrate;

[0047] A projection of the second oxide layer on the substrate is disposed at a position where a projection of the second conductive layer on the substrate is disposed;

[0048] The third oxide layer covers surfaces of the source conductive layer and the drain conductive layer facing away from the substrate.

[0049] The second aspect of the present application provides a display device comprising the display module of the first aspect of the present application.

[0050] The third aspect of the present application provides a method for manufacturing the display module of the first aspect of the present application, the method comprising:

[0051] forming a metal material layer of a gate signal line on a substrate, the metal material layer extending in a first direction and arranged in a second direction perpendicular to the first direction;

[0052] forming a material layer of a gate insulating layer on the gate signal line;

[0053] forming a metal material layer of a data signal line on the material layer of the gate insulating layer, the metal material layer extending in the second direction and arranged in the first direction, a projection of the gate signal line and a projection of the data signal line on the substrate intersecting to form a plurality of pixel regions;

[0054] oxidizing the metal material layers of the gate signal line and the data signal line to form a first conductive layer, a second conductive layer, a first oxide layer and a second oxide layer,

[0055] wherein the oxidizing the metal material layers of the gate signal line and the data signal line further comprises:

[0056] treating a surface of the metal material layer of the gate signal line away from the substrate with an oxidizing gas, the oxidized surface forming a first oxide layer, and the unoxidized metal layer material forming a first conductive layer,

[0057] treating a surface of the metal material layer of the data signal line away from the substrate with an oxidizing gas, the oxidized surface forming a second oxide layer, and the unoxidized metal layer material forming a second conductive layer, the first oxide layer not overlapping the second oxide layer in a projection on the substrate.

[0058] In an optional embodiment, before the oxidizing of the metal material layers of the gate signal line and the data signal line, the method further comprises forming a driving transistor on the substrate in the pixel region, and further comprising:

[0059] forming a gate layer on the substrate, the gate layer being electrically connected with the gate signal line;

[0060] forming a material layer of a gate insulating layer on the gate layer, the material layer of the gate insulating layer covering the gate layer;

[0061] forming an active layer on a surface of the material layer of the gate insulating layer away from the substrate;

[0062] forming a source-drain electrode layer on a surface of the active layer away from the substrate, the source-drain electrode layer covering the active layer and being at least partially disposed on a surface of the gate insulating layer away from the substrate;

[0063] the method further comprising oxidizing a metal surface of the source-drain electrode layer away from the substrate, an oxidized surface of the source-drain electrode layer forming a third oxide layer, and unoxidized metal layer material connected to one end of the active layer forming a source conductive layer, and unoxidized metal layer material connected to another end of the active layer forming a drain conductive layer.

[0064] In an optional embodiment, before the oxidizing of the metal material layers of the gate signal line and the data signal line, the method further comprises:

[0065] etching the material layer of the gate insulating layer in the pixel region, and etching the gate signal line at a non-overlapping position of the gate signal line and the data signal line,

[0066] retaining the material layer of the gate insulating layer at a corresponding position of the second conductive layer, retaining the material layer of the gate insulating layer at an overlapping position of the first conductive layer and the second conductive layer, and retaining the material layer of the gate insulating layer at corresponding positions of the source conductive layer, the drain conductive layer, and the active layer.

[0067] In an alternative embodiment, before forming the metal material layer of the data signal line on the material layer of the gate insulating layer, the method further comprises:

[0068] Etching the material layer of the gate insulating layer in the pixel region, etching the gate signal line at the non-overlapping position of the gate signal line and the data signal line, and etching the data signal line at the non-overlapping position of the gate signal line and the data signal line, leaving the material layer of the gate insulating layer at the overlapping position of the gate signal line and the data signal line,

[0069] The forming of the material layer of the gate insulating layer covering the gate layer further comprises etching the material layer of the gate insulating layer covering the gate layer, leaving the material layer of the gate insulating layer at the corresponding positions of the source conductive layer, the drain conductive layer and the active layer.

[0070] The forming of the source-drain electrode layer away from the substrate side of the active layer further comprises:

[0071] The forming of the source conductive layer on the surface of the substrate, the surface of the gate insulating layer away from the substrate side and the surface of the substrate away from the substrate side of the active layer further comprises:

[0072] The beneficial effects of the present application are as follows:

[0073] The display module of the embodiment of the present application, by designing the layer structure of the gate signal line and the data signal line, setting the gate signal line to have a first conductive layer and a first oxide layer, and setting the data signal line to have a second conductive layer and a second oxide layer, oxidizing the signal line, and using the weak light reflection performance of the first oxide layer and the second oxide layer after oxidation to weaken the metal light reflection, thereby improving the contrast of the display module. BRIEF DESCRIPTION OF DRAWINGS

[0074] The specific embodiments of the present application will be further described in detail below with reference to the accompanying drawings.

[0075] Figure 1 The arrangement of the signal line of the embodiment of the present application is shown;

[0076] Figure 2 The layer structure of the driving transistor of the embodiment of the present application is shown;

[0077] Figure 3 The layer structure of the driving transistor of an alternative embodiment of the present application is shown;

[0078] Figure 4 A schematic diagram of the arrangement of signal lines in one alternative embodiment of the present application is shown;

[0079] Figure 5 A schematic diagram of the arrangement of signal lines in one alternative embodiment of the present application is shown; Figure 4 A schematic diagram of the layer structure in which a cross-section extending in the first direction is located at the overlapping position of the gate signal line and the data signal line is shown;

[0080] Figure 6 A schematic diagram of the layer structure in which a cross-section extending in the first direction is located at the overlapping position of the gate signal line and the data signal line is shown; Figure 4 A schematic diagram of the layer structure in which a cross-section extending in the second direction is located at the overlapping position of the gate signal line and the data signal line is shown;

[0081] Figure 7 A schematic diagram of the layer structure of the drive transistor in another alternative embodiment of the present application is shown;

[0082] Figure 8 A schematic diagram of the arrangement of signal lines in another alternative embodiment of the present application is shown;

[0083] Figure 9 A schematic diagram of the arrangement of signal lines in another alternative embodiment of the present application is shown; Figure 8 A schematic diagram of the layer structure in which a cross-section extending in the first direction is located at the overlapping position of the gate signal line and the data signal line is shown;

[0084] Figure 10 A schematic diagram of the layer structure in which a cross-section extending in the first direction is located at the overlapping position of the gate signal line and the data signal line is shown; Figure 8 A schematic diagram of the layer structure in which a cross-section extending in the second direction is located at the overlapping position of the gate signal line and the data signal line is shown;

[0085] Figure 11 A schematic diagram of the flow of manufacturing the display module in another embodiment of the present application is shown;

[0086] Figure 12a A schematic diagram of the flow of manufacturing the display module in another embodiment of the present application is shown; Figure 3 A process flow diagram of the drive transistor shown is shown;

[0087] Figure 12b A process flow diagram of the signal line shown is shown; Figure 4 A process flow diagram of the signal line shown is shown;

[0088] Figure 13a A process flow diagram of the drive transistor shown is shown; Figure 7 A process flow diagram of the drive transistor shown is shown;

[0089] Figure 13b A process flow diagram of the signal line shown is shown. Figure 8 A process flow diagram of the signal line shown is shown. DETAILED DESCRIPTION

[0090] In order to more clearly illustrate the present application, the present application will be further described below with reference to the embodiments and drawings. Like components are denoted by the same reference numerals in the drawings. Those skilled in the art should understand that the following specific description is illustrative rather than limiting and should not be construed as limiting the scope of the present application.

[0091] In the related art, the contrast ratio (CR) of a display product is affected by many factors, in which the reflection of metal in the wiring layer is an important factor. The metal mainly used in the current wiring layer is copper, which has strong reflection.

[0092] The light of the backlight is incident on the metal wire through scattering, reflection, refraction and other ways of other materials in the box, and then is reflected to the front of the screen through the metal wire, so that the contrast ratio of the product is reduced. Moreover, the display product also has a display defect of uneven green and red, which is mainly affected by film layer interference. For a thin film transistor liquid crystal display (TFT-LCD display), the backlight needs to penetrate through insulating films such as an insulating layer and a passivation layer, and since the refractive indexes of light are different for different film layers, the film layer interference is easily generated and then causes the uneven green and red phenomenon.

[0093] Therefore, the present application provides a display module, a manufacturing method and a display device to solve at least one of the above problems.

[0094] The present application provides a display module, a manufacturing method and a display device to solve at least one of the above problems. Figures 1 to 10 As shown in the drawings, the display module comprises:

[0095] a substrate 10,

[0096] a gate signal line 20 disposed on the substrate 10;

[0097] a data signal line 30 disposed in insulation with the gate signal line 20, the gate signal line 20 and the data signal line 30 intersecting in orthographic projection of the substrate 10 to form a plurality of pixel regions Pix;

[0098] The gate signal line 20 comprises:

[0099] a first conductive layer 21 extending in a first direction and arranged in sequence in a second direction perpendicular to the first direction; and

[0100] a first oxide layer 22 located in orthographic projection of the substrate 10 in a part of the orthographic projection of the substrate 10 of the first conductive layer 21;

[0101] The data signal line 30 comprises:

[0102] a second conductive layer 31 extending in the second direction and arranged in sequence in the first direction; and

[0103] a second oxide layer 32, a projection of the second oxide layer 32 on the substrate 10 does not overlap with a projection of the second conductive layer 31 on the substrate 10,

[0104] the first oxide layer 22 on the substrate 10 does not overlap with the second oxide layer 32 on the substrate 10.

[0105] The gate signal line 20 is closer to the substrate 10, and the data signal line 30 is farther from the substrate 10 than the gate signal line 20, that is, in the layering relationship of the layer structure, the substrate 10, the gate signal line 20 and the data signal line 30 are sequentially arranged from bottom to top. Figure 1 As shown, the gate signal line 20 and the data signal line 30 have overlapping projections in the projection direction. In the structure design of the double-layer structure of the gate signal line 20 and the data signal line 30 according to the embodiment of the present application, the second oxide layer 32 of the data signal line 30 located at the upper side completely covers the second conductive layer 31, and the first oxide layer 22 is not arranged at the overlapping position of the gate signal line 20 and the data signal line 30. That is, the first oxide layer 22 does not completely cover the first conductive layer 21, so as to improve the process efficiency.

[0106] The display module according to the embodiment of the present application improves the contrast of the display module by designing the layer structure of the gate signal line 20 and the data signal line 30, arranging the gate signal line 20 to have the first conductive layer 21 and the first oxide layer 22, arranging the data signal line 30 to have the second conductive layer 31 and the second oxide layer 32, and oxidizing the signal lines, so as to weaken the metal reflection of the first oxide layer 22 and the second oxide layer 32 after oxidation.

[0107] In an optional embodiment, the first oxide layer 22 is obtained by oxidizing the first conductive layer 21, and the reflectivity of the first oxide layer 22 is lower than that of the first conductive layer 21; the second oxide layer 32 is obtained by oxidizing the second conductive layer 31, and the reflectivity of the second oxide layer 32 is lower than that of the second conductive layer 31. The reflectivity of the first oxide layer 22 and the second oxide layer 32 after oxidation is weakened, so as to weaken the metal reflection of the conductive layer, thereby improving the contrast of the display module.

[0108] In an optional embodiment, the materials of the first conductive layer 21 and the second conductive layer 31 are copper, and the materials of the first oxide layer 22 and the second oxide layer 32 are cuprous oxide. The reflectivity of the cuprous oxide is lower than that of the copper, so as to reduce the light intensity of the reflected light reflected to the front of the screen, thereby improving the contrast of the display product.

[0109] In an optional embodiment, as shown in Figure 1 and Figure 2As shown, the display module further comprises a driving transistor 40 disposed on the substrate 10 within the pixel region Pix, the driving transistor 40 being configured to form a driving circuit for driving the sub-pixels within the pixel region Pix. In the present embodiment, the driving transistor 40 comprises:

[0110] a gate layer 41 disposed on the substrate 10;

[0111] a gate insulating layer 42 covering the gate layer 41, the gate insulating layer 42 being further configured to insulate the gate signal line 20 and the data signal line 30;

[0112] an active layer 43 disposed on the gate insulating layer 42 away from the substrate 10;

[0113] a source-drain electrode layer 44 covering the active layer 43 and at least partially disposed on the surface of the gate insulating layer 42 away from the substrate 10; and

[0114] a passivation layer 45 covering the source-drain electrode layer 44 away from the substrate 10.

[0115] In an alternative embodiment, as shown in Figure 3 and another embodiment of the present application, Figure 7 the source-drain electrode layer 44 comprises:

[0116] a source conductive layer 441 connected to one end of the active layer 43 and covering at least part of the surface of the active layer 43 away from the substrate 10;

[0117] a drain conductive layer 442 connected to the other end of the active layer 43 and covering at least part of the surface of the active layer 43 away from the substrate 10; and

[0118] a third oxide layer 443 covering the surfaces of the source conductive layer 441 and the drain conductive layer 442 away from the substrate 10.

[0119] The source-drain electrode layer 44 of the present embodiment is designed to form a double-layer structure through oxidation, i.e., the source conductive layer 441 is provided with the third oxide layer 443, the drain conductive layer 442 is provided with the third oxide layer 443, and the active layer 43 is not provided with the third oxide layer 443. In other words, the layer structure at the corresponding position of the source conductive layer 441 is a double-layer structure, the layer structure at the corresponding position of the drain conductive layer 442 is a double-layer structure, and the layer structure at the position of the active layer 43 is a single-layer structure.

[0120] In an alternative embodiment, the third oxide layer 443 is obtained by oxidizing the source conductive layer 441 and the drain conductive layer 442, and the reflectivity of the third oxide layer 443 is lower than the reflectivity of the source conductive layer 441 and the drain conductive layer 442. The reflectivity of the conductive layer is reduced by using the characteristic that the reflectivity of the conductive layer is reduced after oxidation, so that the metal reflection of the conductive layer is reduced, and the contrast of the display module is improved.

[0121] In an alternative embodiment, the material of the source conductive layer 441 and the drain conductive layer 442 is copper, and the material of the third oxide layer 443 is cuprous oxide. The reflectivity of the cuprous oxide is lower than the reflectivity of the copper, so that the intensity of the light reflected to the front of the screen is reduced by reducing the reflected light, and the contrast of the display product is improved.

[0122] In the embodiment, the active layer 43 is also supplemented with oxygen in the process of oxidizing the surface of the source conductive layer 441 and the drain conductive layer 442 away from the substrate 10 by using the oxidizing gas, so that the surface of the active layer 43 is not oxidized.

[0123] The gate insulating layer 42 of the driving transistor 40 of the embodiment has a different structure design,

[0124] In an alternative embodiment, as shown in Figure 3 The surface of the gate layer 41 away from the substrate 10 is completely covered by the gate insulating layer 42;

[0125] The orthogonal projection of the gate insulating layer 42 on the substrate 10 covers the orthogonal projection of the gate layer 41 on the substrate 10, and covers the combined orthogonal projection of the source conductive layer 441 and the drain conductive layer 442 on the substrate 10,

[0126] The surface of the source conductive layer 441 close to the substrate 10 is completely arranged on the surface of the gate insulating layer 42 away from the substrate 10, and the surface of the drain conductive layer 442 close to the substrate 10 is completely arranged on the surface of the gate insulating layer 42 away from the substrate 10.

[0127] In other words, the length of the gate insulating layer 42 in the second direction is greater than the length of the combined orthogonal projection of the source conductive layer 441, the drain conductive layer 442 and the active layer 43 on the substrate 10 along the second direction.

[0128] As shown in Figure 3 The gate insulating layer 42 of the embodiment completely covers the gate layer 41, and provides a bearing surface for the source-drain electrode layer 44 and the active layer 43, so that the source-drain electrode layer 44 and the active layer 43 are completely arranged on the surface of the gate insulating layer 42 away from the substrate 10.

[0129] In the embodiment, to save the process steps, the gate insulating layer 42 of the driving transistor 40 is not only arranged between the gate layer 41 and the active layer 43, but also arranged between the gate signal line 20 and the data signal line 30, that is, the gate insulating layer 42 is used to simultaneously realize the insulation between the gate signal line 20 and the data signal line 30. The gate insulating layer 42 of the embodiment can have different arrangements, which will be described in the following embodiments.

[0130] For the arrangement design of the gate insulating layer 42 insulating the gate signal line 20 and the data signal line 30, in an alternative embodiment, as shown in Figures 4 to 6

[0131] The orthogonal projection of the gate insulating layer 42 on the substrate 10 covers the orthogonal projection of the second conductive layer 31 on the substrate 10, and covers the overlapping projection of the first conductive layer 21 and the second conductive layer 31 on the substrate 10.

[0132] In the orthogonal projection of the first conductive layer 21 on the substrate 10, the gate insulating layer 42 is not arranged at the non-overlapping position of the orthogonal projection of the first conductive layer 21 and the second conductive layer 31 on the substrate 10.

[0133] That is, the gate insulating layer 42 of the embodiment is not arranged in the non-pixel area, but arranged below the entire data signal line 30, that is, arranged at the position of the frame line surrounded by the dashed line as shown in Figure 4 In addition to the overlapping position of the projection of the gate signal line 20 and the data signal line 30, the gate insulating layer 42 of the embodiment is also not arranged above the gate signal line 20, that is, there is no dashed frame above the gate signal line 20 as shown in Figure 4 Through the position design of the above-mentioned gate insulating layer 42, the gate insulating layer 42 is not arranged in the pixel area Pix, so that the pixel area Pix will not form a flat interference with the passivation layer 45 above the source-drain electrode layer 44, effectively improving the problem of uneven blue and red of the display module.

[0134] As shown in Figure 4 and Figure 5 Figure 5 Figure 4 ​​​A schematic diagram of the layer structure at the cross-sectional position extending along the second direction at the location of the data signal line 30. In an optional embodiment, at the signal line position of the second conductive layer 31, the length of the gate insulating layer 42 in the second direction is greater than or equal to the length of the second conductive layer 31 in the second direction. That is, the gate insulating layer 42 is a strip structure disposed below the second conductive layer 31 of the data signal line 30. The length of the gate insulating layer 42 in the second direction is at least equal to or greater than the length of the second conductive layer 31 in the second direction. The gate insulating layer 42 completely covers the second conductive layer 31 to completely insulate the gate signal line 20 and the second conductive layer 31.

[0135] At the overlap of the first conductive layer 21 and the second conductive layer 31, in an optional embodiment, the length of the gate insulating layer 42 in the second direction is greater than the length of the first conductive layer 21 in the second direction. That is, the length of the gate insulating layer 42 at the overlap location in the second direction is greater than the overall width of the first conductive layer 21. The gate insulating layer 42 forms complete insulation between the second conductive layer 31 and the gate signal line 20 at the overlap location.

[0136] like Figure 4 and Figure 6 As shown, Figure 6 It shows Figure 4 A schematic diagram of the layer structure at the overlapping position of the gate signal line 20 and the data signal line 30, extending along the first direction. In an optional embodiment, at the overlapping position of the first conductive layer 21 and the second conductive layer 31, the length of the gate insulating layer 42 along the first direction is greater than the length of the second conductive layer 31 along the first direction. That is, the length of the gate insulating layer 42 at the overlapping position in the first direction is greater than the overall width of the second conductive layer 31. The gate insulating layer 42 completely insulates the second conductive layer 31 and the gate signal line 20 at the overlapping position.

[0137] In an optional embodiment, based on Figures 3 to 6 As shown, under the signal line routing structure and the structure of the driving transistor 40, the positions of the first oxide layer 22, the second oxide layer 32, and the third oxide layer 443 are designed as follows:

[0138] In the orthographic projection of the first conductive layer 21 onto the substrate 10, the first oxide layer 22 is disposed at the non-overlapping position of the first conductive layer 21 and the second conductive layer 31 in the orthographic projection of the substrate 10.

[0139] The second oxide layer 32 is disposed at the position of the second conductive layer 31 as the orthogonal projection of the second conductive layer 31 onto the substrate 10;

[0140] The third oxide layer 443 covers the combined orthographic projection of the source conductive layer 441 and the drain conductive layer 442 on the substrate 10.

[0141] That is, the first oxide layer 22 of the present embodiment covers the first conductive layer 21, the second oxide layer 32 covers the second conductive layer 31, and the third oxide layer 443 covers the source conductive layer 441 and the drain conductive layer 442. Based on the above structure, the present embodiment etches away the gate insulating layer 42 above the gate signal line 20 and in the pixel region Pix, and only retains the gate insulating layer 42 below the driving transistor 40 and the data signal line 30, so that each signal line and the driving transistor 40 are away from the reflectivity of the surface of the side of the substrate 10, and the present embodiment does not set the gate insulating layer 42 in the pixel region Pix, and does not form a flat panel interference with the passivation layer 45 of the data signal line 30 away from the side of the substrate 10. Therefore, the above setting can effectively improve the unevenness of blue and red in the display state.

[0142] In an optional embodiment, as shown in Figure 7 The surface of the side of the gate layer 41 away from the substrate 10 is completely covered by the gate insulating layer 42, and the orthographic projection of the gate insulating layer 42 on the substrate 10 covers the orthographic projection of the gate layer 41 on the substrate 10,

[0143] The orthographic projection of the gate insulating layer 42 on the substrate 10 has an overlapping projection with the combined orthographic projection of the source conductive layer 441 and the drain conductive layer 442 on the substrate 10,

[0144] The surface of the side of the source conductive layer 441 close to the substrate 10 is partially disposed on the surface of the side of the gate insulating layer 42 away from the substrate 10, and partially disposed on the surface of the substrate 10;

[0145] The surface of the side of the drain conductive layer 442 close to the substrate 10 is partially disposed on the surface of the side of the gate insulating layer 42 away from the substrate 10, and partially disposed on the surface of the substrate 10.

[0146] In other words, as shown in Figure 7 The length of the gate insulating layer 42 in the second direction of the present embodiment is less than the length of the combined orthographic projection of the source conductive layer 441, the drain conductive layer 442 and the active layer 43 on the substrate 10 along the second direction.

[0147] As shown in Figure 7 The gate insulating layer 42 of the present embodiment completely covers the gate layer 41 and provides a complete bearing surface for the active layer 43, while the gate insulating layer 42 provides a partial bearing surface for the source conductive layer 441 and a partial bearing surface for the drain conductive layer 442.

[0148] For example, the surface portion of the source conductive layer 441 near the substrate 10 side includes:

[0149] a first source portion on the top surface of the gate insulating layer 42 away from the substrate 10 side and covering a part of the surface of the active layer 43 away from the substrate 10 side;

[0150] a second source portion on the side inclined surface of the gate insulating layer 42 away from the substrate 10 side, and a third source portion on the substrate 10,

[0151] For example, the surface portion of the drain conductive layer 442 near the substrate 10 side includes:

[0152] a first drain portion on the top surface of the gate insulating layer 42 away from the substrate 10 side and covering a part of the surface of the active layer 43 away from the substrate 10 side, the first drain portion and the first source portion being located at both ends of the active layer 43;

[0153] a second drain portion on the side inclined surface of the gate insulating layer 42 away from the substrate 10 side, and a third drain portion on the substrate 10.

[0154] Based on the above arrangement, the source conductive layer 441 and the drain conductive layer 442 of the present embodiment are not completely arranged on the gate insulating layer 42, which can reduce the occupied area of the driving transistor 40 and improve the display performance.

[0155] For the arrangement design of the gate insulating layer 42 of the insulating gate signal line 20 and the data signal line 30, in an alternative embodiment, as shown in Figures 7 to 10

[0156] The orthogonal projection of the gate insulating layer 42 on the substrate 10 covers the overlapping projection of the first conductive layer 21 and the second conductive layer 31 on the substrate 10, that is, the gate insulating layer 42 completely insulates the overlapping position of the gate signal line 20 and the data signal line 30,

[0157] In the orthogonal projection of the first conductive layer 21 on the substrate 10, the gate insulating layer 42 is not arranged at the non-overlapping position of the orthogonal projection of the first conductive layer 21 and the second conductive layer 31 on the substrate 10;

[0158] In the orthogonal projection of the second conductive layer 31 on the substrate 10, the gate insulating layer 42 is not arranged at the non-overlapping position of the orthogonal projection of the first conductive layer 21 and the second conductive layer 31 on the substrate 10.

[0159] ​That is, for the position of the gate signal line 20 and the data signal line 30, the gate insulating layer 42 of the embodiment is not provided in the non-pixel area, nor is it provided below the entire data signal line 30, but is only provided at the position where the gate signal line 20 and the data signal line 30 projectively overlap, that is, at the position of the frame line enclosed by the dashed line as shown in Figure 8 , except that the overlapping position of the data signal line 30 and the gate signal line 20 is provided with a dashed frame, the upper side of the gate signal line 20 at the non-overlapping position is not provided with a dashed frame, and the upper side of the data signal line 30 at the non-overlapping position is also not provided with a dashed frame. And for the position of the driving transistor 40, the gate insulating layer 42 is provided, that is, at the position of the frame line enclosed by the dashed line as shown in Figure 8 , through the position design of the above-mentioned gate insulating layer 42, the gate insulating layer 42 is not provided in the pixel area Pix, so that the pixel area Pix will not form a flat interference with the passivation layer 45 above the source-drain electrode layer 44, effectively improving the problem of unevenness of blue and red of the display module.

[0160] In an optional embodiment, as shown in Figure 9 , Figure 9 shows Figure 8 the layer structure schematic diagram of the cross section along the first direction at the overlapping position of the gate signal line 20 and the data signal line 30 in

[0161] As shown in the cross-sectional position as shown in Figure 9 , the extension length of the gate insulating layer 42 along the first direction is greater than the extension length of the second conductive layer 31 along the first direction, that is, the extension length of the gate insulating layer 42 along the first direction is greater than the overall width of the second conductive layer 31.

[0162] In an optional embodiment, as shown in Figure 10 , Figure 10 shows Figure 8 the layer structure schematic diagram of the cross section along the second direction at the overlapping position of the gate signal line 20 and the data signal line 30 in

[0163] As shown in the cross-sectional position as shown in Figure 10 , the extension length of the gate insulating layer 42 along the second direction is greater than the extension length of the first conductive layer 21 along the first direction, that is, the gate insulating layer 42 covers the gate signal line 20 and the extension length of the gate insulating layer 42 along the second direction is greater than the overall width of the first conductive layer 21.

[0164] In an optional embodiment, the display module comprises:

[0165] In the orthographic projection of the first conductive layer 21 on the substrate 10, the first oxide layer 22 is arranged at a non-overlapping position of the first conductive layer 21 and the second conductive layer 31 in the orthographic projection of the substrate 10, that is, the first oxide layer 22 covers the first conductive layer 21 of the gate signal line 20 at the non-overlapping position;

[0166] The second oxide layer 32 is arranged at the position of the second conductive layer 31 in the orthographic projection of the substrate 10, that is, the second oxide layer 32 covers the entire second conductive layer 31 of the data signal line 30, including the second conductive layer 31 at the overlapping position;

[0167] The third oxide layer 443 covers the surfaces of the source conductive layer 441 and the drain conductive layer 442 away from the substrate 10, that is, the third oxide layer 443 covers the entire source conductive layer 441 and the drain conductive layer 442. Through the above arrangement, the weak light reflection performance of the oxidized first oxide layer 22 and the second oxide layer 32 weakens the metal reflection, thereby improving the contrast of the display module.

[0168] Therefore, based on the display module of the above embodiment, by designing the layer structure of the gate signal line 20 and the data signal line 30, the gate signal line 20 is arranged to have the first conductive layer 21 and the first oxide layer 22, and the data signal line 30 is arranged to have the second conductive layer 31 and the second oxide layer 32. The signal line is oxidized, the weak light reflection performance of the oxidized first oxide layer 22 and the second oxide layer 32 weakens the metal reflection, thereby improving the contrast of the display module. And the above embodiment also designs the position of the gate insulating layer 42, and the gate insulating layer 42 is not arranged in the pixel area Pix, therefore, the pixel area Pix will not form a flat panel interference with the passivation layer 45 above the source-drain electrode layer 44, effectively improving the problem of uneven blue and red of the display module.

[0169] Another embodiment of the present application provides a display device comprising the display module of the above embodiment of the present application. The display device can be applied to any product or component with display function, such as electronic paper, mobile phone, tablet computer, television, display, notebook computer, digital photo frame, navigator, etc., which is not limited in the present embodiment.

[0170] Another embodiment of the present application provides a method for manufacturing the above display module, as shown in Figure 11 The method comprises:

[0171] S10, forming a metal material layer of the gate signal line 20 on the substrate 10, extending in a first direction and arranged in sequence in a second direction perpendicular to the first direction;

[0172] S30, forming a material layer of a gate insulating layer 42 on the gate signal line 20;

[0173] S50, forming a metal material layer of a data signal line 30 on the material layer of the gate insulating layer 42, extending along a second direction and arranged in sequence in the first direction, the gate signal line 20 and the data signal line 30 intersecting the orthographic projection of the substrate 10 to form a plurality of pixel regions Pix;

[0174] S70, oxidizing the metal material layer of the gate signal line 20 and the data signal line 30 to form a first conductive layer 21, a second conductive layer 31, a first oxide layer 22 and a second oxide layer 32,

[0175] The step S70 of oxidizing the metal material layer of the gate signal line 20 and the data signal line 30 further comprises:

[0176] S71, treating the surface of the metal material layer of the gate signal line 20 away from the substrate 10 side with an oxidizing gas, the oxidized surface forming a first oxide layer 22, and the unoxidized metal layer material forming a first conductive layer 21,

[0177] S73, treating the surface of the metal material layer of the data signal line 30 away from the substrate 10 side with an oxidizing gas, the oxidized surface forming a second oxide layer 32, and the unoxidized metal layer material forming a second conductive layer 31, the orthographic projection of the first oxide layer 22 on the substrate 10 and the orthographic projection of the second oxide layer 32 on the substrate 10 not overlapping.

[0178] In the process of forming the data signal line 30 and the gate signal line 20, the signal line is oxidized to form the gate signal line 20 with the first conductive layer 21 and the first oxide layer 22, and the second conductive layer 31 and the second oxide layer 32, and the weak light reflection performance of the first oxide layer 22 and the second oxide layer 32 after oxidation weakens the metal light reflection, thereby improving the contrast of the display module.

[0179] In an optional embodiment, before the step S70 of oxidizing the metal material layer of the gate signal line 20 and the data signal line 30, the method further comprises a step S60 of forming a driving transistor 40 on the substrate 10 in the pixel region Pix, and the step S60 further comprises:

[0180] S61, forming a gate layer 41 on the substrate 10, the gate layer 41 being electrically connected to the gate signal line 20;

[0181] S63, forming a material layer of a gate insulating layer 42 on the gate layer 41, the material layer of the gate insulating layer 42 covering the gate layer 41;

[0182] S65, forming an active layer 43 on the material layer of the gate insulating layer 42 away from the substrate 10;

[0183] S67, forming a source-drain electrode layer 44 on the active layer 43 away from the substrate 10, the source-drain electrode layer 44 covering the active layer 43 and at least partially disposed on the surface of the gate insulating layer 42 away from the substrate 10;

[0184] The method further comprises a step S80 of "oxidizing the metal surface of the source-drain electrode layer 44 away from the substrate 10". Based on the oxidation step, the surface of the oxidized source-drain electrode layer 44 forms a third oxide layer 443, the metal layer material connected to one end of the active layer 43 which is not oxidized forms a source conductive layer 441, and the metal layer material connected to the other end of the active layer 43 which is not oxidized forms a drain conductive layer 442.

[0185] This step oxidizes the source-drain electrode layer 44 during the process of manufacturing the drive transistor 40 of the display module, and forms the third oxide layer 443 on the source conductive layer 441 and the drain conductive layer 442. The third oxide layer 443 formed after oxidation has weaker light reflection performance, which reduces metal light reflection, thereby improving the contrast of the display module.

[0186] When forming Figures 3 to 6 The structure of the signal lines and the drive transistor 40 of the embodiment shown, in an alternative embodiment, before the step S70 of "oxidizing the metal material layer of the gate signal line 20 and the data signal line 30", the method further comprises:

[0187] S68, etching the material layer of the gate insulating layer 42 in the pixel area Pix, and etching the gate signal line 20 at the non-overlapping positions of the gate signal line 20 and the data signal line 30, retaining the material layer of the gate insulating layer 42 at the corresponding positions of the second conductive layer 31, retaining the material layer of the gate insulating layer 42 at the overlapping positions of the first conductive layer 21 and the second conductive layer 31, and retaining the material layer of the gate insulating layer 42 at the corresponding positions of the source conductive layer 441, the drain conductive layer 442 and the active layer 43.

[0188] Manufacturing Figures 3 to 6 The method of manufacturing the signal lines and the drive transistor 40 of the embodiment shown is exemplified as follows, referring to the schematic diagrams shown in Figure 12a and Figure 12b The method of manufacturing the signal lines and the drive transistor 40 of the embodiment shown is exemplified as follows, referring to the schematic diagrams shown in

[0189] First, the gate signal line 20, the data signal line 30 and the drive transistor 40 are formed according to the normal process steps S10, S30, S50, S60. For example, the metal lines of the signal lines can be formed by etching using a wet etching method.

[0190] For example, as shown in Figure 12a and Figure 12b , the material layers of the gate layer 41 and the gate signal line 20 are formed on the substrate 10 in the same process, the material layers of the gate layer 41 and the gate signal line 20 are covered by the gate insulating layer 42, then the material layer of the data signal line 30 is formed on the gate insulating layer 42 at the position corresponding to the data signal line 30, and the active layer 43 and the source-drain electrode layer 44 are formed at the position corresponding to the drive transistor 40, until step S67 is completed.

[0191] In the etching step of step S68, the insulating film mask is added, the material layers of the gate insulating layer 42 on the gate signal line 20 and in the pixel area Pix are etched away by the process of coating photoresist, exposing, developing and dry etching, and only the device area of the drive transistor 40 and the gate insulating layer 42 under the SD line are reserved.

[0192] Then in step S70, the metal material layers of the gate signal line 20 and the data signal line 30 are oxidized to form the first conductive layer 21, the second conductive layer 31, the first oxide layer 22 and the second oxide layer 32 as shown in Figure 12a and Figure 12b .

[0193] For example, in this step S70, the surfaces of the metal material layers of the gate signal line 20, the data signal line 30 and the source-drain electrode layer 44 are treated with an oxidizing gas such as N2O to oxidize the surfaces of the metal of the gate signal line 20 and the data signal line 30 and the source-drain electrode layer 44, form the first oxide layer 22, the second oxide layer 32 and the third oxide layer 443, reduce the reflection of the metal, improve the contrast of the display product, and the pixel area Pix is free of the gate insulating layer 42, so that the flat interference between the pixel area Pix and the passivation layer 45 above the source-drain electrode layer 44 is avoided, and the problem of unevenness of cyan and red is effectively improved.

[0194] When the structure of the signal lines and the drive transistor 40 of the embodiment shown in Figures 7 to 10 is formed, in an alternative embodiment, before the step S50 "forming the metal material layer of the data signal line 30 on the material layer of the gate insulating layer 42", the method further comprises:

[0195] S40. Etch the material layer of the gate insulating layer 42 in the pixel region Pix, etch the gate signal line 20 at the non-overlapping position of the gate signal line 20 and the data signal line 30, and etch the data signal line 30 at the non-overlapping position of the gate signal line 20 and the data signal line 30, while retaining the material layer of the gate insulating layer 42 at the overlapping position of the gate signal line 20 and the data signal line 30.

[0196] The step S63, "forming a material layer on the gate layer 41 covering the gate insulating layer 42", further includes etching the material layer covering the gate insulating layer 42, while retaining the material layer of the gate insulating layer 42 at the corresponding positions of the source conductive layer 441, the drain conductive layer 442, and the active layer 43.

[0197] Step S67, "forming a source / drain electrode layer 44 on the side of the active layer 43 away from the substrate 10", further includes:

[0198] S671, a source conductive layer 441 is formed on the end surface of the active layer 43 away from the substrate 10, on the surface of the gate insulating layer 42 away from the substrate 10, and on the surface of the substrate 10.

[0199] S673, a source conductive layer 441 is formed on the other end surface of the active layer 43 away from the substrate 10, on the surface of the gate insulating layer 42 away from the substrate 10, and on the surface of the substrate 10.

[0200] Production Figures 7 to 10 The method of signal lines and driving transistor 40 in the illustrated embodiment is exemplified as follows, see below. Figure 13a and Figure 13b The diagram shown is as follows:

[0201] After forming the material layer of the gate signal line 20 and the material layer of the gate insulating layer 42 according to the process flow steps S10 and S30, in step S40, an insulating film photomask is added. Through the process flow of coating photoresist, exposure, development and dry etching, the material layer of the gate insulating layer 42 above the gate signal line 20 outside the preset overlapping position, as well as the material layer of the gate insulating layer 42 of the pixel area Pix, are etched away, leaving only the device area of ​​the driving transistor 40 and the gate insulating layer 42 at the overlapping position of the data signal line 30 and the gate signal line 20.

[0202] Then, following step S50, data signal lines 30 are formed on the material layer of the gate insulating layer 42. Figure 13a The second layer structure diagram shown is as follows.

[0203] According to the processes of steps S61, S63, S65 and S67, each component of the driving transistor 40 is formed on the substrate 10 in the pixel region Pix, and the Figure 13b The second layer structure schematic diagram is shown in the figure,

[0204] Then, in the step of S70, the metal material layers of the gate signal line 20 and the data signal line 30 are oxidized. For example, the surfaces of the metal material layers of the gate signal line 20, the data signal line 30 and the source-drain electrode layer 44 are treated by using an oxidizing gas such as N2O, so that the surfaces of the gate signal line 20 and the data signal line 30 and the source-drain electrode layer 44 are all oxidized, and a layer structure schematic diagram as shown in the figure is formed. Figure 13a and Figure 13b The first oxide layer 22, the second oxide layer 32 and the third oxide layer 443 can reduce the reflection of metal and improve the contrast of the display product, and the pixel region Pix does not have the gate insulating layer 42, so that the flat interference between the pixel region Pix and the passivation layer 45 above the source-drain electrode layer 44 is avoided, and the problem of unevenness of cyan and red can be effectively improved.

[0205] It is worth mentioning that the specific embodiments of the manufacturing method of the display module of the embodiment of the present application can refer to the display module of the foregoing embodiment, which will not be described here.

[0206] In the description of the present application, the relationship terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between the entities or operations. Moreover, the terms "include", "contain" or any other variants thereof are intended to cover non-exclusive inclusion, so that the process, method, article or equipment including a series of elements not only includes those elements, but also includes other elements not explicitly listed or inherent to such process, method, article or equipment. Without more limitation, the element defined by the statement "including a…" does not exclude the presence of other identical elements in the process, method, article or equipment including the element.

[0207] Obviously, the above embodiments of the present application are only examples for clearly illustrating the present application, and are not limitations on the embodiments of the present application. For those skilled in the art, other different forms of changes or variations can be made on the basis of the above description, and it is impossible to enumerate all the embodiments here. Any obvious changes or variations derived from the technical solutions of the present application still fall within the protection scope of the present application.

Claims

1. A method of manufacturing a display module, characterized by, The method comprises: forming a metal material layer of a gate signal line on a substrate, extending along a first direction and arranged in sequence in a second direction perpendicular to the first direction; forming a material layer of a gate insulating layer on the gate signal line; forming a metal material layer of a data signal line on the material layer of the gate insulating layer, extending along the second direction and arranged in sequence in the first direction, the gate signal line and the data signal line intersecting in the orthographic projection of the substrate to form a plurality of pixel regions; oxidizing the metal material layers of the gate signal line and the data signal line to form a first conductive layer, a second conductive layer, a first oxide layer and a second oxide layer, wherein the oxidizing the metal material layers of the gate signal line and the data signal line further comprises: treating the surface of the metal material layer of the gate signal line away from the substrate side with an oxidizing gas, the oxidized surface forming a first oxide layer, and the unoxidized metal layer material forming a first conductive layer; treating the surface of the metal material layer of the data signal line away from the substrate side with an oxidizing gas, the oxidized surface forming a second oxide layer, and the unoxidized metal layer material forming a second conductive layer, the first oxide layer not overlapping with the second oxide layer in the orthographic projection of the substrate; The display module comprises: a substrate; a gate signal line disposed on the substrate; a data signal line disposed in insulation with the gate signal line, the gate signal line and the data signal line intersecting in the orthographic projection of the substrate to form a plurality of pixel regions; wherein the gate signal line comprises: a first conductive layer extending along a first direction and arranged in sequence in a second direction perpendicular to the first direction; and a first oxide layer in the orthographic projection of the substrate located in part of the orthographic projection of the first conductive layer in the orthographic projection of the substrate; the data signal line comprises: a second conductive layer extending along a second direction and arranged in sequence in the first direction; and a second oxide layer coinciding with the second conductive layer in the orthographic projection of the substrate, the first oxide layer not overlapping with the second oxide layer in the orthographic projection of the substrate; the reflectivity of the first oxide layer is lower than the reflectivity of the first conductive layer; the reflectivity of the second oxide layer is lower than the reflectivity of the second conductive layer.

2. The method of claim 1, wherein, Before the oxidizing the metal material layers of the gate signal line and the data signal line, the method further comprises forming a driving transistor on the substrate within the pixel region, further comprising: forming a gate layer on the substrate, the gate layer being electrically connected with the gate signal line; forming a material layer of a gate insulating layer covering the gate layer on the gate layer; forming an active layer on the material layer of the gate insulating layer away from the substrate side; forming a source-drain electrode layer on the active layer away from the substrate side, the source-drain electrode layer covering the active layer and being at least partially disposed on the surface of the gate insulating layer away from the substrate side; The method further comprises oxidizing the metal surface of the source-drain electrode layer away from the substrate side, forming a third oxide layer on the surface of the oxidized source-drain electrode layer, and forming a source conductive layer from the metal layer material connected to one end of the active layer which is not oxidized, and forming a drain conductive layer from the metal layer material connected to the other end of the active layer which is not oxidized.

3. The method of claim 2, wherein, Before the oxidizing of the metal material layer of the gate signal line and the data signal line, the method further comprises: etching the material layer of the gate insulating layer in the pixel area, etching the gate signal line at the non-overlapping position of the gate signal line and the data signal line, and retaining the material layer of the gate insulating layer at the corresponding position of the second conductive layer, retaining the material layer of the gate insulating layer at the overlapping position of the first conductive layer and the second conductive layer, and retaining the material layer of the gate insulating layer at the corresponding position of the source conductive layer, the drain conductive layer and the active layer.

4. The method of claim 2, wherein, Before the forming of the metal material layer of the data signal line on the material layer of the gate insulating layer, the method further comprises: etching the material layer of the gate insulating layer in the pixel area, etching the gate signal line at the non-overlapping position of the gate signal line and the data signal line, and etching the data signal line at the non-overlapping position of the gate signal line and the data signal line, and retaining the material layer of the gate insulating layer at the overlapping position of the gate signal line and the data signal line; The forming of the material layer of the gate insulating layer covering the gate layer further comprises etching the material layer of the gate insulating layer covering the gate layer, and retaining the material layer of the gate insulating layer at the corresponding position of the source conductive layer, the drain conductive layer and the active layer; The forming of the source-drain electrode layer away from the substrate side of the active layer further comprises: forming the source conductive layer on the surface of the one side end surface of the surface away from the substrate side of the active layer, on the surface away from the substrate side of the gate insulating layer and on the surface of the substrate, and forming the source conductive layer on the surface of the other side end surface of the surface away from the substrate side of the active layer, on the surface away from the substrate side of the gate insulating layer and on the surface of the substrate.

5. A display module prepared by the method of any one of claims 1-4, wherein: the first oxide layer is obtained by oxidizing the first conductive layer; the second oxide layer is obtained by oxidizing the second conductive layer.

6. The display module of claim 5, wherein, The display module further comprises a driving transistor disposed on the substrate in the pixel area, and the driving transistor comprises: a gate layer disposed on the substrate; a gate insulating layer covering the gate layer, the gate insulating layer being further used for insulating the gate signal line and the data signal line; an active layer disposed on the side of the gate insulating layer away from the substrate; a source-drain electrode layer covering the active layer and at least partially disposed on the surface of the side of the gate insulating layer away from the substrate.

7. The display module of claim 6, wherein, The source-drain electrode layer comprises: a source conductive layer connected to one end of the active layer and covering at least part of the surface of the active layer away from the substrate; a drain conductive layer connected to the other end of the active layer and covering at least part of the surface of the active layer away from the substrate; and a third oxide layer covering the surfaces of the source conductive layer and the drain conductive layer away from the substrate.

8. The display module of claim 7, wherein, The third oxide layer is obtained by oxidizing the source conductive layer and the drain conductive layer, and the reflectivity of the third oxide layer is lower than that of the source conductive layer and the drain conductive layer.

9. The display module of claim 7, wherein, The orthogonal projection of the gate insulating layer on the substrate covers the orthogonal projection of the second conductive layer on the substrate and the overlapping projection of the first conductive layer and the second conductive layer on the substrate, In the orthogonal projection of the first conductive layer on the substrate, the gate insulating layer is not arranged at the non-overlapping position of the orthogonal projection of the first conductive layer and the orthogonal projection of the second conductive layer on the substrate.

10. The display module of claim 9, wherein, The surface of the gate layer away from the substrate is completely covered by the gate insulating layer, The orthogonal projection of the gate insulating layer on the substrate covers the orthogonal projection of the gate layer on the substrate and the combined orthogonal projection of the source conductive layer and the drain conductive layer on the substrate, The surface of the source conductive layer close to the substrate is completely arranged on the surface of the gate insulating layer away from the substrate, The surface of the drain conductive layer close to the substrate is completely arranged on the surface of the gate insulating layer away from the substrate.

11. The display module of claim 10, wherein In the orthogonal projection of the first conductive layer on the substrate, the orthogonal projection of the first oxide layer on the substrate is arranged at the non-overlapping position of the orthogonal projection of the first conductive layer and the orthogonal projection of the second conductive layer on the substrate; The orthogonal projection of the second oxide layer on the substrate is arranged at the position of the orthogonal projection of the second conductive layer on the substrate; The third oxide layer covers the combined orthogonal projection of the source conductive layer and the drain conductive layer on the substrate.

12. The display module of claim 7, wherein, The orthogonal projection of the gate insulating layer on the substrate covers the overlapping projection of the first conductive layer and the second conductive layer on the substrate, In the orthogonal projection of the first conductive layer on the substrate, the gate insulating layer is not arranged at the non-overlapping position of the orthogonal projection of the first conductive layer and the orthogonal projection of the second conductive layer on the substrate; In the orthogonal projection of the second conductive layer on the substrate, the gate insulating layer is not arranged at the non-overlapping position of the orthogonal projection of the first conductive layer and the orthogonal projection of the second conductive layer on the substrate.

13. The display module of claim 12, wherein, The surface of the gate layer away from the substrate is completely covered by the gate insulating layer, and the orthogonal projection of the gate insulating layer on the substrate covers the orthogonal projection of the gate layer on the substrate, The orthogonal projection of the gate insulating layer on the substrate has an overlapping projection with the combined orthogonal projection of the source conductive layer and the drain conductive layer on the substrate, The surface of the source conductive layer close to the substrate is partially arranged on the surface of the gate insulating layer away from the substrate and partially arranged on the surface of the substrate; The surface of the drain conductive layer close to the substrate is partially arranged on the surface of the gate insulating layer away from the substrate and partially arranged on the surface of the substrate.

14. The display module of claim 13, wherein, The display module comprises: In the orthographic projection of the first conductive layer on the substrate, the orthographic projection of the first oxide layer on the substrate is arranged at a non-overlapping position of the first conductive layer and the second conductive layer in the orthographic projection of the substrate; The orthographic projection of the second oxide layer on the substrate is arranged at the position of the second conductive layer in the orthographic projection of the substrate; The third oxide layer covers the surfaces of the source conductive layer and the drain conductive layer away from the substrate side.

15. A display device comprising: The display device comprises the display module according to any one of claims 5-14.

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