Electronic device and method with hardware optimized compilation

Abstract

An electronic device and method with hardware optimized compilation are provided. The operation method of the electronic device includes generating a mapping by mapping hardware components represented in a hardware representation of a target device to one or more hardware component characteristics and one or more drivers based on the hardware representation of the target device; and generating, on the basis of the hardware representation, topology information representing a connection relationship and dependency between hardware components of the target device represented in the hardware representation, the hardware representations include representations of the hardware components tagged with the one or more hardware component characteristics and representations of the one or more drivers and a hierarchical structure between the hardware components.

Description

[0001] This application claims the benefit of Korean Patent Application No. 10-2023-0073600 filed on June 8, 2023, in the Korean Intellectual Property Office, and Korean Patent Application No. 10-2023-0101276 filed on August 2, 2023, in the Korean Intellectual Property Office, the disclosures of which are incorporated herein by reference in their entirety for all purposes. Technical Field

[0002] The present disclosure relates to an electronic device and method with hardware optimized compilation. Background Art

[0003] A compiler is a software tool that converts a code written in a programming language into another generally lower-level form of code (e.g., machine executable code or bytecode). The compiler typically parses and analyzes the code to generate target code based on the analysis. In order to optimize the efficiency of the code output from the compiler, compiler optimization techniques are used. Compiler optimizations can typically be used to increase the execution speed of a program, to minimize the size of the memory used by the program when the program is executed, or to improve other aspects of performance. Summary of the invention

[0004] This Summary is provided to introduce a selection of concepts in a simplified form that are further described below in the Detailed Description. This Summary is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to be used as an aid in determining the scope of the claimed subject matter.

[0005] In one general aspect, a method for operating an electronic device includes: generating a mapping based on a hardware representation of a target device by mapping hardware components represented in the hardware representation of the target device to one or more hardware component characteristics and one or more drivers; and generating topology information based on the hardware representation, the topology information representing connection relationships and dependencies between hardware components of the target device represented in the hardware representation, wherein the hardware representation includes representations of hardware components marked with representations of the one or more hardware component characteristics and the one or more drivers, and a hierarchical structure between hardware components.

[0006] The one or more hardware component characteristics may be indicative of software executable by the hardware component.

[0007] The one or more hardware component characteristics may be included in a first set, in which the characteristics of the standardized hardware components are standardized; the one or more drivers may be included in a second set, in which the operations that can be performed by the standardized hardware components are standardized, and a combination of the operations of the corresponding drivers in the second set may be included in a third set.

[0008] The mapping may include: a first mapping table that maps between the one or more hardware component characteristics and the hardware components, and a second mapping table that maps between the one or more drivers and the hardware components.

[0009] The operating method may also include: receiving a query about a hardware component from a compiler, the compiler compiling a target application for execution on a target device; generating a response to the query based on the first container and / or the second container; sending the response to the compiler; and optimizing the compilation of the target application based on the response by the compiler for execution on the target device.

[0010] The query may be a query as to whether one of the hardware components includes a predetermined hardware component characteristic, a query as to whether one of the hardware components includes a predetermined driver, or a query as to whether one of the hardware components is included in a predetermined topology.

[0011] Generating a response to the query may be based on the mapping or a hardware representation including the topology information, the mapping including: a first mapping table mapping between the one or more hardware component characteristics and the hardware components, and a second mapping table including mapping information between the one or more drivers and the hardware components.

[0012] Generating the mapping and the topology information may be performed based on compiling a target application for execution on a target device, and wherein compiling optimizes the target application for execution on the target device based on the mapping and the topology information.

[0013] In another general aspect, a method for operating an electronic device includes: receiving a target application and a hardware representation of the target device; generating, by a compiler, a query for a mapping table and / or topology information; and compiling, by the compiler, the target application for execution on the target device based on a response to the query, wherein the mapping table is based on the hardware representation and indicates which hardware components included in the target device are mapped to (i) which hardware component characteristics and (ii) which drivers, and the topology information is based on the hardware representation and indicates connection relationships and dependencies between hardware components.

[0014] The hardware representation may include hardware components labeled with hardware component properties and drivers, and a hierarchical structure between hardware components.

[0015] Hardware component characteristics may indicate software that is executable by the hardware component.

[0016] Hardware component characteristics may be included in a first set in which the characteristics of the hardware components are standardized, drivers may be included in a second set in which the operations that can be performed by the hardware components are standardized, and indications of combinations of operations that can be performed by the drivers may be included in a third set.

[0017] In another general aspect, an electronic device includes: one or more host processors configured to: generate mapping information based on a hardware representation of a target device by mapping each hardware component included in the hardware representation of the target device to one or more hardware component characteristics and one or more drivers, and generate topology information representing connection relationships and dependencies between hardware components based on the hardware representation, wherein the hardware representation includes indications of hardware components marked with indications of the one or more hardware component characteristics and the one or more drivers and a hierarchical structure between the hardware components.

[0018] The one or more hardware component characteristics may be related to software executable by the hardware component.

[0019] The one or more hardware component characteristics may be included in a first set, in which the characteristics of the hardware components are standardized, the one or more drivers may be included in a second set, in which the operations that can be performed by the hardware components are standardized, and each of the one or more drivers may be a combination of one or more of the multiple operations included in the third set.

[0020] The mapping information may include a first mapping table including mappings between the one or more hardware component characteristics and hardware components, and a second mapping table including mappings between the one or more drivers and hardware components.

[0021] The one or more host processors may also be configured to receive a query about a hardware component from a compiler and send a response to the query to the compiler based on the mapping information and / or the topology information, wherein the compiler is configured to compile a target application to execute the target application on a target device.

[0022] The query may be a query as to whether one of the hardware components has a predetermined hardware component characteristic, a query as to whether one of the hardware components has a predetermined driver, or a query as to whether one of the hardware components is included in a predetermined topology.

[0023] The one or more host processors may also be configured to: determine the response to the query based on one of: a first mapping table that maps information between the one or more hardware component characteristics and hardware components, a second mapping table that maps between the one or more drivers and hardware components, and the topology information; and send the determined response to a compiler.

[0024] The compiler may use the response to the query when performing an optimization pass for compiling a target application.

[0025] Other features and aspects will be apparent from the following detailed description, drawings, and claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1 An example of an electronic device according to one or more embodiments is shown.

[0027] Figure 2 An example of the operation of a compiler according to one or more embodiments is shown.

[0028] Figure 3 A compiler according to one or more embodiments is shown.

[0029] Figure 4A A multi-level hardware representation and a software stack for the multi-level hardware representation are shown according to one or more embodiments.

[0030] Figure 4B Shows an example of a hardware representation in accordance with one or more embodiments.

[0031] Figure 5 An example of generating a container in accordance with one or more embodiments is shown.

[0032] Figure 6 Examples of queries in accordance with one or more embodiments are shown.

[0033] Figure 7 An example method of operating an electronic device according to one or more embodiments is illustrated.

[0034] Figure 8 Another example method of operating an electronic device according to one or more embodiments is illustrated.

[0035] Fig. 9 and Fig.10 Examples of electronic devices and target devices according to one or more embodiments are shown.

[0036] Throughout the drawings and detailed description, unless otherwise described or provided, the same reference numerals will be understood to refer to the same elements, features, and structures. The drawings may not be to scale, and the relative sizes, proportions, and depictions of the elements in the drawings may be exaggerated for clarity, illustration, and convenience. DETAILED DESCRIPTION

[0037] The following detailed description is provided to help the reader obtain a comprehensive understanding of the method, device and / or system described herein. However, after understanding the disclosure of the present application, various changes, modifications and equivalents of the method, device and / or system described herein will be clear. For example, the order of operations described herein is only an example, and is not limited to those orders set forth herein, but can be changed as it will be clear after understanding the disclosure of the present application, except for the operations that must occur in a specific order. In addition, for greater clarity and simplicity, the description of known features after understanding the disclosure of the present application can be omitted.

[0038] The features described herein can be implemented in different forms and should not be interpreted as being limited to the examples described herein. On the contrary, the examples described herein have been provided only to illustrate some of the many possible ways to implement the methods, devices and / or systems described herein that will be clear after understanding the disclosure of the present application.

[0039] The terms used herein are only used to describe various examples and will not be used to limit the disclosure. Unless the context clearly indicates otherwise, the singular form is also intended to include the plural form. As used herein, the term "and / or" includes any one or any combination of any two or more of the associated listed items. As non-limiting examples, the terms "include", "comprise" and "have" indicate the presence of stated features, quantities, operations, components, elements and / or combinations thereof, but do not exclude the presence or addition of one or more other features, quantities, operations, components, elements and / or combinations thereof.

[0040] Throughout the specification, when a component or element is described as being "connected to," "coupled to," or "engaged to" another component or element, the component or element may be directly "connected to," "coupled to," or "engaged to" the other component or element, or there may reasonably be one or more other components or elements in between. When a component or element is described as being "directly connected to," "directly coupled to," or "directly engaged to" another component and element, there may not be other elements in between. Similarly, expressions such as "between" and "immediately between," and "adjacent to" and "immediately adjacent to" may also be interpreted as described in the foregoing.

[0041] Although terms such as "first", "second" and "third" or A, B, (a), (b), etc. may be used to describe various components, components, regions, layers or parts, these components, components, regions, layers and parts should not be limited by these terms. For example, each of these terms is not used to define the nature, order or sequence of the corresponding component, component, region, layer or part, but is only used to distinguish the corresponding component, component, region, layer or part from other components, components, regions, layers or parts. Therefore, without departing from the teaching of the example, the first component, first component, first region, first layer or first part referred to in the example described herein may also be referred to as the second component, second component, second region, second layer or second part.

[0042] Unless otherwise defined, all terms (including technical terms and scientific terms) used herein have the same meaning as those generally understood by a person of ordinary skill in the art to which the present disclosure belongs based on an understanding of the disclosure of the present application. Unless explicitly defined as such herein, terms (such as terms defined in a general dictionary) should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and the disclosure of the present application, and should not be interpreted in an idealized or overly formal sense. The use of the term "may" with respect to an example or embodiment herein (e.g., with respect to what an example or embodiment may include or implement) indicates that there is at least one example or embodiment that includes or implements such a feature, but all examples are not limited thereto.

[0043] Figure 1 An example of an electronic device according to one or more embodiments is shown.

[0044] Reference Figure 1 , the electronic device 100 may include a host processor 110, a memory 120, and an accelerator 130. The host processor 110, the memory 120, and the accelerator 130 may communicate with each other through a bus, a network on chip (NoC), a peripheral component interconnect express (PCIe), etc. Figure 1 In the example of FIG. 1 , only components related to the example described herein are shown as being included in the electronic device 100. Therefore, except Figure 1 In addition to the components shown in , the electronic device 100 may further include other general components.

[0045] The host processor 110 may perform an overall function for controlling the electronic device 100. The host processor 110 may generally control the electronic device 100 by executing a program and / or an instruction stored in the memory 120. The host processor 110 may be implemented as a central processing unit (CPU), a graphics processing unit (GPU), an application processor (AP), etc. included in the electronic device 100, however, examples are not limited thereto. According to an example, the host processor 110 may use a compiler to convert a programming language into an intermediate language (intermediate representation (IR)) and a machine language (e.g., binary code).

[0046] The memory 120 is a hardware component for storing data processed in the electronic device 100 and data to be processed. In addition, the memory 120 may store applications, drivers, etc. to be driven by the electronic device 100. The memory 120 may include a volatile memory (e.g., a dynamic random access memory (DRAM)) and / or a nonvolatile memory.

[0047] The electronic device 100 may include an accelerator 130 for performing operations. The accelerator 130 is a separate device that processes tasks more efficiently than a general-purpose processor or a central processing unit (CPU) (e.g., a general-purpose host processor 110) due to the characteristics of a specific task. Here, one or more processing elements (PEs) included in the accelerator 130 may be used to perform specific tasks. The accelerator 130 may be, for example, a neural processing unit (NPU), a tensor processing unit (TPU), a digital signal processor (DSP), a GPU, a neural engine, etc. that can perform operations according to a neural network. According to an example, the accelerator 130 may execute some of the binary codes converted by a compiler.

[0048] The host processor 110 may use a compiler to convert a target application represented by a "source code in a programming language stored in the memory 120" into an IR, or into a binary code that can be executed by a target device and a hardware component included in the target device. The target device may be a device for executing a target application. The target device may include an electronic device 100 and another electronic device. In other words, the target (e.g., binary) code generated using a compiler may be used by the electronic device 100, or may be sent to be used by another electronic device. The host processor 110 may promote compiler optimization when converting (compiling) by using a query about the hardware component of the target device. The query about the hardware component may be about the structural characteristics of the hardware component and the characteristics and capabilities (e.g., driver characteristics) that are not related to the structural characteristics. In other words, even if the exact type of the hardware component (e.g., NPU, GPU, etc.) is unknown, the host processor 110 may also optimize the compilation of the target application based on the characteristics and capabilities of the hardware component (some of the characteristics and capabilities of the hardware component may be changeable).

[0049] Figure 2 An example of the operation of a compiler according to one or more embodiments is shown.

[0050] Reference Figure 2 , showing a compiler 200 and a multi-level hardware representation (MLHR) manager 220. The compiler 200 and the MLHR manager 220 may be software (in the form of instructions) executed by a host processor (e.g., the host processor 110 of the electronic device 100). The compiler 200 may use information from the MLHR manager 220 to optimize the compilation of the target application. However, this is merely an example. In some embodiments, the compiler 200 may perform the operations of the MLHR manager 220 (i.e., the functionality of the MLHR manager 220 may be included in the compiler 200). When the MLHR manager 220 is implemented separately from the compiler 200, the compiler 200 may interact with the MLHR manager 220 through an application programming interface (API) exposed by the MLHR manager 220.

[0051] In operation 201, the compiler 200 initializes the MLHR manager 220 after receiving a target application and a hardware representation of a target device on which compilation of the target application is to be executed. The target application may include a deep learning model (e.g., a neural network) represented in a predetermined programming language (e.g., Python), and the compiler 200 may be a deep learning compiler (e.g., a compiler that can convert high-level deep learning constructs (e.g., initialization / configuration, training, and execution of a neural network)). However, this is only an example, and the compilation prior art described herein may be used for any type of application or compiler.

[0052] The compiler 200 may cause the MLHR manager 220 to generate a first container and a second container. Although a virtualized type of container may be used, "container" as used herein does not mean such a virtualized type of container. Instead, a container is any data structure or memory arrangement for encapsulating information. The compiler 200 may send a hardware representation of the target device to the MLHR manager 220 to generate a first container and a second container. The hardware representation is a representation of the hardware components included in the target device that will execute the target application. The hardware representation may include a representation of a hierarchical structure of the hardware components of the target device, that is, the hardware representation may represent the relationship between the hardware components of the target device (a complete hierarchical representation of the target device is not required). The hardware representation may include a representation of the hardware components marked with hardware characteristics of the hardware components and drivers of the hardware components. For brevity, the phrase "hardware characteristics" is used herein as an abbreviation for "hardware component characteristics" to represent the characteristics of the hardware components. Refer to Figure 4A and Figure 4BThe hardware representation is further described.

[0053] As described below, in operation 203 , the MLHR manager 220 may generate a first container and a second container based on a hardware representation.

[0054] The MLHR manager 220 may map the hardware component to one or more hardware characteristics of the hardware component based on the hardware representation. "Hardware characteristics" refers to any characteristics of the hardware and is not limited to the hardware information itself (i.e., "hardware characteristics" may be any characteristics of the corresponding hardware). For example, in addition to the physical structure of the hardware component, the hardware characteristics may also be characteristics related to the software that can be executed by the hardware component (or driver, etc.). The hardware characteristics may include characteristics in addition to the physical structure / characteristics of the hardware component. For example, the hardware characteristics of the hardware component (represented in the hardware representation) may be related to the type of software that can be executed by the hardware component.

[0055] The MLHR manager 220 may map the hardware components to one or more corresponding drivers, for example, based on the hardware representation. The driver mapping may indicate operations that may be performed by the hardware component via the driver. For example, the driver record may indicate whether the corresponding hardware component is capable of performing convolution operations or matrix operations.

[0056] The first container may include a first mapping table and a second mapping table. The first mapping table may indicate, for each of the hardware components in the hardware representation, which hardware component is mapped to which hardware characteristics of the one or more corresponding hardware characteristics. The second mapping table may indicate which hardware components of the hardware components are mapped to which drivers of the one or more drivers. Figure 5 The first mapping table and the second mapping table are further described.

[0057] In addition, the MLHR manager 220 may generate a second container based on the hardware representation. The second container may include topology information representing connection relationships and dependencies between hardware components.

[0058] MLHR manager 220 may use containers to model not only structural characteristics, but also characteristics and capabilities of hardware components.

[0059] In operation 205, compiler 200 may execute Figure 2A pass pipeline is shown in the figure with a dotted box marked as "Pass pipeline". The pass pipeline can be a sequence of compiler passes, and the compiler passes optimize the target application during the compilation process so that when the target application is executed on the target device, the hardware components of the target device can be used to execute the target application. For example, based on compiling the target application to execute the target application on the target device, the steps of generating mapping tables (e.g., first mapping tables and second mapping tables) and topology information are performed. For example, the compilation can optimize the target application to execute the target application on the target device based on the mapping tables (e.g., first mapping tables and second mapping tables) and topology information. For example, the pass pipeline can be a sequence of Pass A, Pass B, and Pass C. Each pass of the compiler 200 can be configured to optimize the target application and convert the target application into target code. In Figure 2 In the embodiment, operations 207 to 215 may be performed through one pass. Figure 2 The operations shown in are relevant to the present disclosure; except Figure 2 In addition to the operations shown in , the delivery pipeline may also include other operations.

[0060] In operation 207, individual passes of the pass pipeline begin to be executed. For example, if the pass pipeline is a sequence of passes such as pass A, pass B, and pass C, then pass A may be executed first.

[0061] In operation 209, the compiler 200 may query information about the hardware component. The query may be initiated by generating a query for verifying or obtaining information about the hardware component. The query may be used to verify information about the hardware component for which the first container and the second container will be generated. The query may include a query as to whether one of the hardware components includes a predetermined hardware characteristic (i.e., a query for a specific hardware characteristic). The query may be a query as to whether one of the hardware components includes a predetermined / specific driver. The query may be a query as to topology information related to one of the hardware components. For example, the query may be a query as to whether one of the hardware components is included in predetermined topology information.

[0062] Although for ease of description, Figure 2 Only a single operation of verifying / obtaining information about a hardware component is shown, but one or more operations of verifying information about a hardware component may be included in one transfer.

[0063] In addition, the query may include a subordinate query. A query including a subordinate query may be referred to as a high-level query. A subordinate query may be a query that queries for more specific information based on a response to a high-level query for more specific information. If the response to the high-level query is "yes", the subordinate query may be a query that performs an additional query related to the high-level query.

[0064] In operation 211 , the MLHR manager 220 receives the generated query and executes the query to generate a response to the query. The MLHR manager 220 may generate a response to the query (or referred to as a query response) based on the first container and the second container and send the generated response to the compiler 200 .

[0065] In operation 213, the compiler 200 receives the query response and performs an operation corresponding to the response. The compiler 200 performs optimization based on the response. The compiler 200 may map the operation of the target application to a predetermined hardware component based on the response. Figure 6 Operation 213 is further described and referenced Figure 7 It is further described that operations corresponding to the responses are performed by compiler 200. For example, compiler 200 uses the responses to the queries when performing an optimization pass for compiling a target application.

[0066] In operation 215, compiler 200 determines whether the transfer pipeline is terminated. That is, compiler 200 can determine whether all transfers of the transfer pipeline have been executed. In operation 217, after all transfers have been executed, compiler 200 terminates compilation and generates optimized target code. Binary code can be sent to be used in the target device. The target code can be a code optimized by the compiler considering the software characteristics (i.e., a subset of hardware characteristics) and capabilities (i.e., drivers) and structural characteristics (i.e., topology) of the target device.

[0067] Compiler 200 may repeatedly perform operation 207 to execute subsequent passes until all passes are executed. For example, in a pass pipeline, pass A may be terminated and pass B may be executed.

[0068] According to the above operation, the compiler 200 can obtain information about the hardware components by responding to the query, and perform operations based on the response. That is, the information about the hardware components can be decoupled from the compiler kernel algorithm, and the optimization decision can be made by the compiler based on the information about the hardware components obtained at compile time. In other words, the compiler 200 can optimize the compilation by receiving information about the hardware components via a query. Thus, even if the compiler 200 is provided for public use, the information about the hardware components that "may be sensitive or proprietary" may not be disclosed with the compiler itself.

[0069] Furthermore, according to the above operations, the information about the hardware component may include characteristics related to the software (i.e., may include characteristics other than the physical structure) and / or operations that may be performed by the hardware component. Therefore, even if the type of the hardware component is unknown, the compiler 200 may perform optimization using only the information about the hardware component, wherein the information is not necessarily about the physical structure of the hardware component. As a result, the compiler 200 may be configured to be able to perform optimization for a variety of arbitrary hardware components, and thus may be more widely used.

[0070] Next, a compiler for performing optimization through different delivery pipelines corresponding to different types of hardware components, respectively, is described.

[0071] Figure 3 A compiler according to one or more embodiments is shown. Figure 3 The compiler 300 in can be contrasted with a compiler (described later) that uses non-architectural (non-hardware) properties or "hardware component properties" of hardware components.

[0072] The compiler 300 may receive a target application (source code) and a hardware representation of a target device. In operation 310, after receiving the target application and the hardware representation, the compiler 300 may determine which type of hardware component (of the target device) will execute the target application. Depending on the type of hardware component that will execute the target application in the target device, the compiler 300 may perform compilation according to different optimized pass-through pipelines. That is, an optimized pass-through pipeline that matches the type of hardware component determined in operation 310 may be selected.

[0073] For example, if the type of hardware component is an NPU, the compiler 300 may perform compilation according to an NPU-specific delivery pipeline 320. If the type of hardware component is a GPU, the compiler 300 may perform compilation according to a GPU-specific delivery pipeline 330. If the type of hardware component is a process-in-memory (PIM), the compiler 300 may perform compilation according to a PIM-specific delivery pipeline 340. Since different optimized delivery pipelines may be used for each type of hardware component, the need to extend the compiler 300 may be reduced. In this example, the type of hardware component may be generic in the sense that the type of hardware component is not limited to a specific model, manufacturer, etc. In addition, a given delivery pipeline may be optimized in a manner specific to a type of hardware component corresponding to a given delivery pipeline.

[0074] Transfer pipelines 320, 330, and 340 may also be used as references. Figure 2 Describes the delivery pipeline.

[0075] Even if the compiler 300 uses different pass-through pipelines for hardware components of different types of representations, the compiler 300 may generate a query for "getting information about the hardware component" in any of the pass-through pipelines. The compiler 300 may receive a response to the query. In one example, the query may be configured to get only structural information of the hardware component. If software features and capabilities (information other than structural information of the hardware component) are hard-coded in the pass-through pipeline, the pass-through pipeline is generally difficult to reuse, and therefore, a different pass-through pipeline may be needed for each of the various hardware components.

[0076] When with Figure 2 The compiler 200 compares, Figure 3 The compiler 300 may lack reusability and may be difficult to extend to new hardware components. Figure 2 In the compiler 200, software features and capabilities (information other than structural information of hardware components) are decoupled from the delivery pipeline.

[0077] Next is a description of a hardware representation that can be input into a compiler and the software used to generate the hardware representation.

[0078] Figure 4A A multi-level hardware representation (MLHR) and a software stack for the MLHR (or MLHR software stack) are shown according to one or more embodiments.

[0079] like Figure 4A As shown in , a hardware representation can be generated using a list of hardware characteristics (Htrait), a list of capabilities (drivers), and a topology (lower layers). This approach can be different from a high-level hardware description language (HDL) approach, which is typically written to synthesize hardware and is intended to describe detailed parts for synthesizing hardware. On the other hand, the techniques described herein can use a hardware representation language that is configured to provide abstract information to software (such as a compiler) without having to represent detailed parts of the hardware.

[0080] As noted above, a topology may correspond to hardware and at the same time may be an element to be included in other hardware as a topology, thereby enabling the representation of a hierarchical structure of hardware.

[0081] The hardware features and capabilities (drivers) list associated with the hardware / topology may include a table / set of standard hardware features, a table / set of drivers, and those present in the capability set. The hardware representation represented using this method can be processed by the MLHR layer software stack with a multi-level hardware representation (MLHR) manager 420 as information to be used by other software.

[0082] The MLHR manager 420 may implement an MLHR syntax for abstracting and representing hardware. Descriptions (e.g., declarative) that conform to the MLHR syntax may be used to specify hardware representations. Sets of standard hardware feature / capability / driver information may be stored in corresponding standard hardware feature / capability / driver containers via a standard hardware feature / capability / driver set importer. Associations may exist between items in different sets. These sets of information may be provided to be queried by other software using the MLHR manager 420 (e.g., via an MHLR interface / API).

[0083] The representable hardware can be input through the MLHR importer and stored in the hardware container through the MLHR builder. This information can be provided to be queried by other software using the MLHR manager. Data structured hardware information can be received through the MLHR importer, and the topological information of the hardware can be abstracted into a structure convenient for software use through the topology abstraction builder, and then stored in the hardware container after the topology abstraction. The information can be provided to be queried by other software using the MLHR manager 420 (i.e., through the MHLR interface / API of the MLHR manager 420).

[0084] The hardware modeling method can remove the compiler's dependency on multiple specific hardware, which can achieve high versatility and reusability. The hardware representation / modeling technology can be used for other applications besides compiler optimization (for example, for implementing advanced simulators for various hardware).

[0085] Figure 4B Shows an example of a hardware representation in accordance with one or more embodiments.

[0086] Reference Figure 4B , a hardware representation 400 of a target device is shown. The target device may be a device intended to execute a target application. The target device may include hardware components. Figure 4B , "ht" stands for "hardware characteristics," "cap" stands for "capability" (operational capability), and "drv" stands for "driver." The example hardware representation 400 may include links to sets of information such as a first set 450 of predefined hardware characteristics, a second set 460 of predefined drivers, and a third set 470 of operational capabilities.

[0087] The hardware representation 400 may include a hierarchical structure between the hardware components included in the target device (although the hierarchical structure is not required). The hardware representation 400 may use a topology to represent the hierarchical structure between the hardware components. Each of the hardware components included in the target device may itself be a topology. The topology may be a topology of a first hardware component and may be included in a topology of a second hardware component that includes the first hardware component. Thus, the topology information may be information representing the relationships and dependencies between the hardware components. For example, the supercomputer representation 410 is an example of the hardware representation 400 representing a supercomputer. The supercomputer representation 410 may be the largest hardware unit represented by the example of the hardware representation 400. The deep learning graphics card (DGX) representation 420 may represent a corresponding hardware component (e.g., a DGX card) in the represented supercomputer. The CPU representation 430 may represent a corresponding hardware component (CPU) and be included in a DGX card of a supercomputer. For example, the CPU representation 430 may include a core and a DRAM. The GPU representation 440 may represent a corresponding hardware component (GPU) included in a DGX of a supercomputer. For example, the GPU representation 440 may include a stream multiprocessor (SM) and a high bandwidth memory (HBM). In summary, supercomputer representation 410 may include DGX card representation 420 with GPU representation 440, and CPU representation may represent a corresponding DGX card of the supercomputer.

[0088] The hardware representation may be marked with one or more hardware component characteristics (i.e., hardware characteristics) in the hardware representation 400. Hardware characteristics may be characteristics other than characteristics of the physical structure of the hardware component being represented. Hardware characteristics may be software characteristics of the hardware component (e.g., variable characteristics that may be known / unknown only based on the hardware itself). In other words, the hardware characteristics may include characteristics related to the viewpoint of the software viewing the hardware component. The hardware characteristics may be about what type of software can be executed by the hardware component. The hardware characteristics may be standardized and predefined. The set of predefined hardware characteristics may be referred to as the first set 450. In one example, the standardized characteristics of the standardized hardware components may be predefined in the first set 450. For example, in the first set 450, the characteristics of the standardized hardware components are standardized. One or more hardware characteristics with which the hardware components are marked in the hardware representation 400 may be included in the first set 450 (and extracted from the first set 450). For example, the hardware characteristics ht1 and ht2 with which the supercomputer representation 410 is marked may be included in the first set 450.

[0089] The hardware representation can be marked with a driver record in the available hardware representation 400. The driver record can be about operations that can be performed by the driver in conjunction with the corresponding driven hardware component. One or more driver records can indicate (the corresponding driver's) operations (such as, convolution operations, matrix operations, vector operations, etc.). Drivers / driver records can be standardized and predefined. A set of predefined drivers / driver records can be included in the second set 460 (and extracted from the second set 460). In other words, standard operations that can be performed by standard hardware components (or standardized hardware components) can be predefined in the second set 460. For example, in the second set 460, operations that can be performed by standardized hardware components are standardized. One or more driver records with which hardware components are marked in the hardware representation 400 can be included in the second set 460.

[0090] The driver records included in the second set 460 may be a combination of one or more operations (or capabilities) included in the third set 470. For example, the convolution operation included in the second set 460 may be a combination of one or more operations included in the third set 470. For example, drv0 included in the second set 460 may be a combination of cap0 and cap1 in the third set 470. The third set 470 may include indications of operations constituting the driver included in the second set 460. The third set 470 may include indications of operations such as addition, subtraction, multiplication, and division. In other words, the third set 470 may be a set of capabilities of the smallest unit including the driver. The driver included in the second set 460 may have a combination of operations / capabilities included in the third set 470.

[0091] Since the first set 450 , the second set 460 , and the third set 470 are later used to generate a mapping table, the first set 450 , the second set 460 , and the third set 470 may be provided to a compiler.

[0092] According to an example, a specific target device may not be described using information in the first set 450, the second set 460, and the third set 470. For example, when one of the hardware components of the specific target device is capable of performing a convolution operation but the convolution operation is not included in the second set 460, the target device may not be describable. When the target device having the hardware representation 400 cannot be described using the first set 450 and the second set 460, the compiler developer may add new hardware features, driver records, and / or operations / capabilities. The new hardware feature may be a combination of one or more of the hardware features included in the first set 450. Alternatively, the new hardware feature may be a completely new hardware feature defined by the compiler developer. The new driver record may be a combination of one or more of the driver records included in the second set 460 and / or a combination of one or more of the operations included in the third set 470. Alternatively, the new driver may be a completely new driver defined by the compiler developer.

[0093] Next, a method of generating a container using the hardware representation 400 , the first set 450 , the second set 460 , and the third set 470 is described.

[0094] Figure 5 An example of generating a container in accordance with one or more embodiments is shown.

[0095] Reference Figure 5 , Figure 5 A method of generating a first container 590 and a second container 580 by receiving a hardware representation 540 through the MLHR manager 500 is shown.

[0096] MLHR manager 500 may receive a hardware representation 540 of a target device. Figure 4B For ease of description, assume that hardware representation 540 is Figure 4B The MLHR manager 500 may include a topology abstraction manager 510, a hardware property manager 520, and a driver manager 530.

[0097] The MLHR manager 500 may first use a parser to parse the received hardware representation 540. The hardware representation 540 may be a code that conforms to the MLHR syntax, and the content / meaning of the hardware representation 540 may be obtained from the parser configured to parse the MLHR syntax. The MLHR manager 500 may include a combiner that combines the parsed hardware representation 540 with the hardware features and drivers included in the hardware representation 540. The hardware features and drivers included in the hardware representation 540 may be loaded from the first set 550 and the second set 560. Description of the first set 550 and the second set 560 in general and with reference to Figure 4BSame description provided.

[0098] The hardware feature manager 520 may use an instantiator and a mapper to map each of the hardware components in the hardware representation 540 to one or more corresponding hardware features. Each of the hardware components included in the represented target device may be mapped to one or more hardware features. A first mapping table 521 may be generated in which each of the hardware components included in the target device is mapped to one or more hardware features. The first mapping table 521 may include mapping information in which the hardware components are mapped to one or more hardware features based on the hardware representation 540.

[0099] For example, a supercom component may be labeled with ht1 and ht2 in the hardware representation 540. In the first mapping table 521, ht1 may be mapped with a supercom component. In the first mapping table 521, ht2 may be mapped with a hardware component that is a DGX.

[0100] The driver manager 530 may map each (or some) of the hardware components of the hardware representation 540 to one or more drivers using an instantiator and a mapper. Each of the hardware components included in the target device may be mapped to one or more drivers. A second mapping table 531 may be generated in which each of the hardware components included in the target device is mapped to one or more drivers. The second mapping table 531 may include mapping information in which the hardware components are mapped to one or more drivers based on the hardware representation 540.

[0101] For example, a supercomputer may be marked with drv0 in the hardware representation 540. In the second mapping table 531, drv0 may be mapped with a supercomputer (not shown). In the second mapping table 531, drv0 may also be mapped with a DGX.

[0102] The first container 590 may include a first mapping table 521 and a second mapping table 531. The first mapping table 521 and the second mapping table 531 stored in the first container 590 may be provided (accessed) through a query received from other software (eg, a compiler).

[0103] The topology abstraction manager 510 may generate an original hardware diagram representing the physical connection relationship between the hardware components of the hardware representation 540. The topology abstraction manager 510 may generate an accompanying hardware diagram obtained by abstracting the original hardware diagram. The accompanying hardware diagram may be a diagram obtained by simplifying the original hardware diagram. The accompanying hardware diagram may be a diagram obtained by abstracting the original hardware diagram downward into hardware units recognizable by software. The topology abstraction manager 510 may convert the accompanying hardware diagram into a hardware view using a view builder. The hardware view may be obtained by abstracting the accompanying hardware diagram so that the software recognizes the structural characteristics of the hardware components. For example, the hardware view may abstract the accompanying hardware diagram in a tree form (e.g., of a standard subgraph set) and a grid form (e.g., of a standard subgraph set). The hardware view may be topology information that enables the software to recognize the structural characteristics of the hardware components. The hardware view may be implemented as a view set, which may be a code suitable for being queried (e.g., a code in a markup language).

[0104] The second container 580 may include a hardware view. For example, the second container 580 may include a hardware view abstracted in a tree form and a hardware view abstracted in a grid form. In other words, the second container 580 may include topological information of hardware components represented by hardware. The topological information stored in the second container 580 may be provided (e.g., provided to a compiler) through a query received from other software (e.g., a compiler).

[0105] Hereinafter, a query and a response to the query according to an example will be described.

[0106] Figure 6 Examples of queries in accordance with one or more embodiments are shown.

[0107] As reference Figure 2 As described, in the delivery pipeline, compiler 600 may generate query 620 when hardware information is needed (or available). Query 620 may be sent to MLHR manager 610. For ease of description, Figure 6 Only operations related to query 620 are shown.

[0108] The query 620 may be one of a first query 621 , a second query 623 , or a third query 625 .

[0109] The first query 621 may be a query about whether one of the hardware components includes a predetermined hardware characteristic. The predetermined hardware characteristic being queried may be one of the hardware characteristics included in the first set. The first query 621 may include one or more queries about hardware characteristics. For example, the first query 621 may include a query about whether any of the hardware components (in the hardware representation) includes the hardware characteristic ht0. If any of the hardware components does not include ht0, the first query 621 may include a query about whether any of the hardware components includes ht1.

[0110] The second query 623 may be a query about whether any of the hardware components includes a predetermined driver. The predetermined driver may be any driver included in the second set. The second query may include one or more queries about the driver. For example, the second query 623 may include a query about whether any of the hardware components includes drv0. If any of the hardware components does not include drv0, the second query 623 may include a query about whether any of the hardware components includes drv1.

[0111] The third query 625 may be a query as to whether any of the hardware components is included in a predetermined topology. The third query 625 may include one or more queries about the topology. For example, the third query 625 may include a query as to whether "one of the hardware components corresponds to layer L0 in the hardware view in tree form." If one of the hardware components does not correspond to layer L0, the third query 625 may include a query as to whether "one of the hardware components corresponds to layer L1."

[0112] The MLHR manager 610 may send a response 630 to the query 620 to the compiler 600. The MLHR manager 610 may send the response 630 to the query 620 to the compiler 600 based on the first container and / or the second container. For example, the MLHR manager 610 may determine the response to the query based on one of: a first mapping table including mappings between one or more hardware component characteristics and hardware components, a second mapping table including mappings between one or more drivers and hardware components, and topology information.

[0113] Upon receiving the first query 621, the MLHR manager 610 may send a response 630 to the first query 621 based on the first container to the compiler 600. Upon receiving the first query 621, the MLHR manager 610 may send a response 630 to the first query 621 based on a first mapping table including mapping information between one or more hardware characteristics and hardware components to the compiler 600. The MLHR manager 610 may send the response 630 to the first query 621 to the compiler 600 by referring to the first mapping table.

[0114] Upon receiving the second query 623, the MLHR manager 610 may send a response 630 to the second query 623 based on the first container to the compiler 600. Upon receiving the second query 623, the MLHR manager 610 may send a response 630 to the second query 623 to the compiler 600 based on a second mapping table including mapping information between one or more drivers and hardware components.

[0115] Upon receiving the third query 625, the MLHR manager 610 may send a response 630 to the third query 625 based on the second container to the compiler 600. Upon receiving the third query 625, the MLHR manager 610 may send a response 630 to the third query 625 based on the second container including the topology information.

[0116] Compiler 600 may receive response 630 from MLHR manager 610 and perform an operation corresponding to response 630 .

[0117] The response 630 to the first query 621 may be a response that “one of the hardware components includes a predetermined hardware characteristic.” The compiler 600 may compile a target application to be optimized for the corresponding hardware characteristic as a task corresponding to the response.

[0118] The response 630 to the second query 623 may be a response of “one of the hardware components includes a predetermined driver.” The compiler 600 may map the predetermined driver to the hardware component so that the hardware component including the predetermined driver may execute the predetermined driver as a task corresponding to the response.

[0119] The response 630 to the third query 625 may be a response that one of the hardware components is included in the predetermined topology. The compiler 600 may perform a transfer corresponding to the predetermined topology as a task corresponding to the response.

[0120] Even if the type of the hardware component is unknown, compiler 600 can verify the characteristics and capabilities of the hardware component (represented by the hardware representation) of the target device through the above query. Compiler 600 can optimize the compilation of the target application through tasks corresponding to the response to the query.

[0121] Figure 7 An example of an operating method of an electronic device according to one or more embodiments is shown.

[0122] In the following examples, the operations may be performed sequentially, but need not be performed sequentially. For example, the operations may be performed in a different order, and at least two of the operations may be performed in parallel.

[0123] In operation 710 , the electronic device may generate a first container by mapping each of hardware components included in the target device to one or more hardware characteristics and one or more drivers based on a hardware representation of the target device.

[0124] In operation 720 , the electronic device may generate a second container including topology information representing connection relationships and dependencies between hardware components based on the hardware representation.

[0125] The hardware representation may include hardware components labeled with one or more hardware characteristics and one or more drivers (eg, representations or indications of one or more drivers) and a hierarchy between the hardware components.

[0126] Figure 8 An example of an operating method of an electronic device according to one or more embodiments is shown.

[0127] In the following examples, the operations may be performed sequentially, but need not be performed sequentially. For example, the operations may be performed in a different order, and at least two of the operations may be performed in parallel.

[0128] In operation 810 , the electronic device may receive a target application and a hardware representation of a target device.

[0129] In operation 820 , the electronic device may perform a query about the first container and / or the second container through a compiler configured to compile a target application to execute the target application on a target device.

[0130] The first container may include a mapping table in which each of the hardware components included in the target device is mapped to one or more hardware characteristics and one or more drivers based on the hardware representation. The second container may include topology information representing connection relationships and dependencies between the hardware components based on the hardware representation.

[0131] In operation 830 , the electronic device may compile a target application based on a response to the query.

[0132] Fig. 9 and Fig.10 Examples of electronic devices and target devices according to one or more embodiments are shown.

[0133] Reference Fig. 9 , the electronic device may be implemented as a server 900. The server 900 may be a separate device distinguished from a user terminal controlled by a user, and may communicate with one or more user terminals via a wired and / or wireless network. The server 900 may receive requests sent simultaneously from multiple users via their user terminals. The server 900 may compile a target application via a host processor 910 to generate a binary code. The server 900 may send the binary code to the user terminal (i.e., the target device). Optionally, the server 900 may execute the binary code via an accelerator 920. The user terminal may be a device capable of executing binary code, and may include various computing devices (such as smart phones, tablet computers, laptops, and personal computers), various wearable devices (such as smart watches and smart glasses), various home appliances (such as smart speakers, smart televisions (TVs), and smart refrigerators), smart cars, smart self-service terminals, and Internet of Things (IoT) devices.

[0134] Reference Fig.10 , the target device may be implemented as the user terminal 1000. Fig.10 In the embodiment, for ease of description, the user terminal 1000 is shown as a smart phone. However, any device capable of executing binary code may be applied herewith without limitation. The user terminal 1000 may execute the binary code received from the server. When the binary code is used for the host processor 1010, the user terminal 1000 may use the host processor 1010 to execute the binary code. When the binary code is used for the accelerator 1020, the user terminal 1000 may use the accelerator 1020 to execute the binary code. However, according to the example, the host processor 1010 of the user terminal 1000 may compile the target application. In other words, the user terminal 1000 may be an electronic device configured to compile the target application. The user terminal 1000 may send the compiled binary code to a separate target device and cause the target device to execute the binary code.

[0135] Here about Figures 1 to 10The computing devices, electronic devices, processors, memories, displays, information output systems and hardware, storage devices and other devices, devices, units, modules and components described are implemented by hardware components or represent hardware components. Examples of hardware components that can be used to perform the operations described in this application include, where appropriate, controllers, sensors, generators, drivers, memories, comparators, arithmetic logic units, adders, subtractors, multipliers, dividers, integrators, and any other electronic components configured to perform the operations described in this application. In other examples, one or more hardware components in the hardware components that perform the operations described in this application are implemented by computing hardware (e.g., by one or more processors or computers). A processor or computer may be implemented by one or more processing elements (such as logic gate arrays, controllers and arithmetic logic units, digital signal processors, microcomputers, programmable logic controllers, field programmable gate arrays, programmable logic arrays, microprocessors, or any other device or combination of devices configured to respond and execute instructions in a limited manner to achieve the desired result). In one example, a processor or computer includes or is connected to one or more memories storing instructions or software executed by a processor or computer. The hardware components implemented by a processor or a computer can execute instructions or software (such as, an operating system (OS) and one or more software applications running on the OS) to perform the operations described in the present application. The hardware components can also access, manipulate, process, create and store data in response to the execution of instructions or software. For simplicity, the singular term "processor" or "computer" can be used in the description of the examples described in the present application, but in other examples, multiple processors or computers can be used, or the processor or computer can include multiple processing elements, or multiple types of processing elements, or both. For example, a single hardware component, or two or more hardware components can be implemented by a single processor, or two or more processors, or a processor and a controller. One or more hardware components can be implemented by one or more processors, or a processor and a controller, and one or more other hardware components can be implemented by one or more other processors, or another processor and another controller. One or more processors, or a processor and a controller can implement a single hardware component, or two or more hardware components. The hardware components may have any one or more of different processing configurations, examples of which include: a single processor, independent processors, parallel processors, single instruction single data (SISD) multiprocessing, single instruction multiple data (SIMD) multiprocessing, multiple instruction single data (MISD) multiprocessing, and multiple instruction multiple data (MIMD) multiprocessing.

[0136] Figures 1 to 10The method for performing the operations described in the present application shown in the embodiment is performed by computing hardware (e.g., by one or more processors or computers), which is implemented as executing instructions or software as described above to perform the operations performed by the method described in the present application. For example, a single operation, or two or more operations may be performed by a single processor, or two or more processors, or a processor and a controller. One or more operations may be performed by one or more processors, or a processor and a controller, and one or more other operations may be performed by one or more other processors, or another processor and another controller. One or more processors, or a processor and a controller may perform a single operation, or two or more operations.

[0137] Instructions or software for controlling computing hardware (e.g., one or more processors or computers) to implement hardware components and perform methods as described above may be written as computer programs, code segments, instructions, or any combination thereof to individually or collectively instruct or configure one or more processors or computers to operate as a machine or special-purpose computer to perform operations performed by the hardware components and methods as described above. In one example, the instructions or software include machine code (such as machine code generated by a compiler) directly executed by one or more processors or computers. In another example, the instructions or software include high-level code executed by one or more processors or computers using an interpreter. The instructions or software may be written in any programming language based on the block diagrams and flow charts shown in the accompanying drawings and the corresponding descriptions herein, which disclose algorithms for performing operations performed by the hardware components and methods as described above.

[0138] Instructions or software for controlling computing hardware (e.g., one or more processors or computers) to implement hardware components and perform the methods described above, and any associated data, data files, and data structures, may be recorded, stored, or fixed in or on one or more non-transitory computer-readable storage media. Examples of non-transitory computer-readable storage media include: read-only memory (ROM), random access programmable read-only memory (PROM), electrically erasable programmable read-only memory (EEPROM), random access memory (RAM), dynamic random access memory (DRAM), static random access memory (SRAM), flash memory, non-volatile memory, CD-ROM, CD-R, CD+R, CD-RW, CD+RW, DVD-ROM, DVD-R, DVD+R, DVD-RW, DVD+RW, DVD-RAM, BD-ROM, BD-R, BD-R LTH, BD-RE, Blu-ray or optical disk storage device, hard disk drive (HDD), solid state drive (SSD), card memory (such as, multimedia card or micro card (for example, secure digital (SD) or extreme digital (XD))), magnetic tape, floppy disk, magneto-optical data storage device, optical data storage device, hard disk, solid state disk and any other device, any other device is configured to store instructions or software and any associated data, data files and data structures in a non-temporary manner, and provide instructions or software and any associated data, data files and data structures to one or more processors or computers so that one or more processors or computers can execute the instructions. In one example, the instructions or software and any associated data, data files and data structures are distributed on a networked computer system so that the instructions and software and any associated data, data files and data structures are stored, accessed and executed by one or more processors or computers in a distributed manner.

[0139] Although the present disclosure includes specific examples, it will be clear after understanding the disclosure of the present application that various changes in form and detail may be made in these examples without departing from the spirit and scope of the claims and their equivalents. The examples described herein should be considered to be descriptive only, not for limiting purposes. The description of the features or aspects in each example should be considered to be applicable to similar features or aspects in other examples. If the described techniques are performed in a different order, and / or if the components in the described system, architecture, device, or circuit are combined in a different manner, and / or replaced or supplemented by other components or their equivalents, suitable results may be achieved.

[0140] Therefore, the scope of the disclosure may be defined by the claims and their equivalents in addition to the above disclosure, and all variations within the scope of the claims and their equivalents are to be construed as being included in the disclosure.

Claims

1. A method for operating an electronic device, the operating method include: generating a mapping based on the hardware representation of the target device by mapping hardware components represented in the hardware representation of the target device to one or more hardware component characteristics and one or more drivers; and generating topology information based on the hardware representation, the topology information representing connection relationships and dependencies between hardware components of the target device represented in the hardware representation, The hardware representation includes representations of hardware components marked with the one or more hardware component characteristics and representations of the one or more drivers, and a hierarchical structure between hardware components.

2. The operating method according to claim 1, in, The one or more hardware component characteristics indicate software executable by the hardware component.

3. The operating method according to claim 1, wherein The one or more hardware component characteristics are included in a first set in which the standardized hardware component characteristics are standardized, The one or more drivers are included in a second set, in which operations that can be performed by the standardized hardware components are standardized, and in, Each of the one or more drivers in the second set is a combination of one or more of the plurality of operations included in the third set.

4. The operating method according to claim 1, in, The mapping includes a first mapping table, comprising mapping information between the one or more hardware component characteristics and the hardware components, and The second mapping table includes mapping information between the one or more drivers and hardware components.

5. The operating method according to claim 1, further comprising: include: receiving a query about the hardware component from a compiler, the compiler compiling a target application to execute the target application on a target device; generating a response to the query based on a first container including the mapping and / or a second container including the topology information; sending the response to a compiler; as well as Compilation of the target application is optimized, by the compiler, based on the response to execute the target application on the target device.

6. The operating method according to claim 5, in, The query is a query as to whether one of the hardware components of the target device includes a predetermined hardware component characteristic, a query as to whether one of the hardware components of the target device includes a predetermined driver, or a query as to whether one of the hardware components of the target device is included in a predetermined topology.

7. The operating method according to claim 6, wherein generating the response to the query based on the mapping or the topology information, The mapping include: A first mapping table includes mapping information between the one or more hardware component characteristics and the hardware components, The second mapping table includes mapping information between the one or more drivers and hardware components.

8. The operating method according to any one of claims 1 to 7, in, Compiling optimizes a target application based on the mapping and the topology information to execute the target application on a target device.

9. A method for operating an electronic device, the operating method include: receiving a hardware representation of a target application and a target device; Generate, by a compiler, a query for a mapping table and / or topology information; as well as compiling, by a compiler, a target application based on a response to the query to execute the target application on a target device, wherein the mapping table is based on a hardware representation and indicates which hardware components included in the target device are mapped to which hardware component characteristics and which drivers, and The topology information is based on a hardware representation and indicates connection relationships and dependencies between hardware components.

10. The operating method according to claim 9, in, The hardware representation includes hardware components labeled with hardware component properties and drivers, and the hierarchical structure between hardware components.

11. The operating method according to claim 9, in, The hardware component characteristics indicate the software that can be executed by the hardware component.

12. The operating method according to claim 9, wherein The hardware component characteristics are included in a first set, in which the characteristics of the hardware components are standardized, The driver is included in a second set in which operations that can be performed by the hardware component are standardized, and Indications of operations that can be performed by the driver are included in the third set.

13. An electronic device, include: One or more host processors, configured to: generating mapping information based on a hardware representation of the target device by mapping each hardware component included in the hardware representation of the target device to one or more hardware component characteristics and one or more drivers, and generating topology information representing connection relationships and dependencies between the hardware components based on the hardware representation, The hardware representation includes indications of hardware components marked with the one or more hardware component characteristics and indications of the one or more drivers, and a hierarchical structure between the hardware components.

14. The electronic device according to claim 13, in, The one or more hardware component characteristics are related to software executable by the hardware component.

15. The electronic device according to claim 13, wherein The one or more hardware component characteristics are included in a first set in which characteristics of hardware components are standardized, The one or more drivers are included in a second set in which operations that can be performed by the hardware component are standardized, and Each of the one or more drivers is a combination of one or more of the plurality of operations included in the third set.

16. The electronic device according to claim 13, in, The mapping information includes a first mapping table and a second mapping table, the first mapping table includes mappings between the one or more hardware component characteristics and the hardware components, and the second mapping table includes mappings between the one or more drivers and the hardware components.

17. The electronic device according to claim 13, in, The one or more host processors are further configured to receive a query about hardware components from a compiler and send a response to the query to the compiler based on the mapping information and / or the topology information, wherein the compiler is configured to compile a target application to execute the target application on a target device.

18. The electronic device according to claim 17, in, The query is a query as to whether one of the hardware components of the target device has a predetermined hardware component characteristic, a query as to whether one of the hardware components of the target device has a predetermined driver, or a query as to whether one of the hardware components of the target device is included in a predetermined topology.

19. The electronic device according to claim 18, in, The one or more host processors are further configured to: determining the response to the query based on one of: a first mapping table including mappings between the one or more hardware component characteristics and hardware components, a second mapping table including mappings between the one or more drivers and hardware components, and the topology information, and The determined response is sent to the compiler.

20. The electronic device according to claim 18, in, The compiler uses the response to the query when performing an optimization pass for compiling a target application.

Images