Attack detection device and method and processor

Abstract

The invention provides an attack detection device and method and a processor, the device comprises a signal amplifier, a burr detection circuit and an early warning circuit, the burr detection circuit comprises an edge detection sub-circuit and a matching sub-circuit, and the output end of the signal amplifier is electrically connected with the input end of the early warning circuit through the edge detection sub-circuit and the matching sub-circuit. According to the device, the burr detection sensitivity can be improved, so that the possibility that the chip is attacked is reduced, and the burr detection application range is widened.

Description

Technical Field

[0001] The present application relates to the field of information security technology, and in particular to an attack detection device and method, and a processor. Background Art

[0002] In fault attacks (FA), attackers may exploit key signals in the chip's operation process through laser injection, power failure, or electromagnetic interference to induce the chip to produce predictable errors, thereby obtaining sensitive information or tampering with the chip's expected behavior.

[0003] In the related art, the pulse width of the chip system clock can be monitored by a glitch fault detection circuit to determine whether the chip is under attack. However, the measurement sensitivity of this glitch detection technology is not high, resulting in limited applicability of the glitch detection technology. Summary of the invention

[0004] The purpose of the present application is to provide an attack detection device, method and processor, wherein the attack detection device can improve the sensitivity of glitch detection, thereby reducing the possibility of a chip being attacked and increasing the scope of application of glitch detection.

[0005] In a first aspect, the present application provides an attack detection device, including: a signal amplifier, a glitch detection circuit, and an early warning circuit, the glitch detection circuit including an edge detection subcircuit and a matching subcircuit, the output end of the signal amplifier is electrically connected to the input end of the early warning circuit through the edge detection subcircuit and the matching subcircuit;

[0006] The signal amplifier is used to receive the target pulse, amplify the target pulse, and transmit the obtained amplified signal of the target pulse to the edge detection subcircuit;

[0007] The edge detection subcircuit is used to receive the amplified signal, perform target edge detection on the amplified signal using a reference clock within a preset time length, and obtain a target edge counting result of the amplified signal within the preset time length. The operating frequency of the edge detection subcircuit is equal to the frequency of the reference clock, and the frequency of the reference clock is less than the preset frequency.

[0008] The matching subcircuit is used to transmit a warning signal to the warning circuit when the target edge counting result of the amplified signal within the preset time length does not match the target edge counting result of the target pulse within the preset time length;

[0009] The early warning circuit is used to execute the first protection strategy when receiving the early warning signal.

[0010] In the case of adopting the above technical solution, the output end of the signal amplifier of the present application is electrically connected to the input end of the early warning circuit through the edge detection subcircuit and the matching subcircuit, so that when the signal amplifier receives the target pulse, it amplifies the target pulse, and then transmits the obtained amplified signal of the target pulse to the edge detection circuit. Since the process of amplifying the target pulse by the signal amplifier can actually be regarded as a process of widening the target pulse to achieve the process of reducing the frequency of the target pulse, therefore, by using a lower frequency reference clock to perform target edge detection on the amplified signal, the target edge counting result of the amplified signal within the preset time length can be accurately obtained. In this case, the matching subcircuit can use the target edge counting result of the amplified signal within the preset time length as the reference counting result, and by matching the target edge counting result of the amplified signal within the preset time length with the target edge counting result of the target pulse within the preset time length, it is determined whether the target pulse has glitches. When the target edge counting result of the amplified signal within the preset time length is equal to the target edge counting result of the target pulse within the preset time length, it indicates that there are glitches in the target pulse, and the processor related to the target pulse is very likely to have a fault attack behavior. Therefore, the matching sub-circuit can transmit a warning signal to the warning circuit, so that the warning circuit executes the first protection strategy when receiving the warning signal, thereby ensuring the information security related to the target pulse.

[0011] For example, when the early warning circuit determines that the intensity of the early warning signal is less than a preset intensity, the early warning circuit can execute a first protection strategy, which includes using a filtering circuit or other glitch processing circuit to process the target pulse to remove the glitch signal of the target pulse, and then transmitting the target pulse signal to the processor core, thereby achieving the purpose of protecting the processor core.

[0012] It can be seen that in the technical solution disclosed in the present application, even if the frequency of the target pulse is relatively high, the glitch detection circuit can be coordinated with the signal amplification circuit to effectively improve the detection capability of the target pulse with a narrow pulse width, and realize the attack identification of the target pulse with a narrow pulse width. Therefore, the attack detection device has the advantages of high glitch detection accuracy and sensitivity, can reduce the frequency dependence on the reference clock, and is suitable for glitch detection of target pulses of various frequencies.

[0013] In addition, in the technical solution disclosed in the present application, the operating frequency of the edge detection subcircuit is equal to the frequency of the reference clock, and the frequency of the reference clock is less than the preset frequency. Since the target pulse is amplified by the signal amplifier, a higher reference clock frequency is not required to perform target edge detection on the amplified signal. Therefore, the operating frequency of the edge detection subcircuit is relatively low, and there is no need to equip edge detection subcircuits such as counters with higher operating frequencies. This can effectively save the area overhead of the edge detection subcircuit and is suitable for scenarios with higher integration requirements.

[0014] In a possible implementation, the signal amplifier includes: a plurality of signal amplifying circuits, the plurality of signal amplifying circuits are connected in series, an output end of a last one of the plurality of signal amplifying circuits is electrically connected to an input end of an edge detection subcircuit, the current signal amplifying circuit is used to receive an input signal of the current signal amplifying circuit, and widen the input signal of the signal amplifying circuit to obtain a widening result;

[0015] If the current signal amplifying circuit is the first of the multiple signal amplifying circuits, the input signal is the target pulse; if the current signal amplifying circuit is the last of the multiple signal amplifying circuits, the stretching result is the amplified signal;

[0016] If the current signal amplifying circuit is one of the second to the last of the plurality of signal amplifying circuits, the input signal is a stretching result of a signal amplifying circuit preceding the current signal amplifying circuit.

[0017] In the technical solution disclosed in the present application, the signal amplifier includes multiple signal amplification circuits connected in series, and the target pulse can be amplified multiple times by the multiple signal amplification circuits, so that when the frequency of the target pulse is relatively high, the signal amplifier can fully amplify the target pulse, thereby improving the sensitivity of glitch detection. Moreover, even if the frequency of the target second pulse is particularly high, the pulse width of the amplified signal obtained by multiple amplification by the signal amplification circuit can also be applied to the edge detection subcircuit with a lower operating frequency, thereby improving the scope of application of glitch detection.

[0018] In a possible implementation, each signal amplification circuit includes a first inverter and a widening subcircuit, the input end of the first inverter is the input end of the signal amplification circuit, the output end of the first inverter is electrically connected to the input end of the widening subcircuit, and the output end of the widening subcircuit is the output end of the signal amplification circuit;

[0019] In the current signal amplification circuit, the first inverter is used to receive an input signal, invert the input signal, and obtain a current inverted signal, and the widening subcircuit is used to invert and extend the pulse width of the current inverted signal to obtain a widening result.

[0020] In the technical solution disclosed in the present application, after the first inverter included in each signal amplification circuit inverts the input signal, the widening subcircuit can not only widen the pulse width of the current inverted signal, but also invert the current inverted signal, ensuring that the pulse width and frequency of the widening result change compared with the target pulse, while the signal is not flipped, so as to ensure that the target edge position detected by the edge detection subcircuit is correct, thereby accurately obtaining the target edge counting result of the amplified signal within a preset time length.

[0021] In a possible implementation, the widening subcircuit includes a Schmitt trigger, the output end of the first inverter is electrically connected to the input end of the Schmitt trigger, and the output end of the Schmitt trigger is the output end of the signal amplification circuit;

[0022] If the voltage of the current inverted signal is within the hysteresis voltage range of the Schmitt trigger, the widening result is the same as the potential of the current inverted signal;

[0023] If the voltage of the current inverted signal is outside the hysteresis voltage range of the Schmitt trigger, the widening result is opposite to the potential of the current inverted signal.

[0024] In a possible implementation, the widening subcircuit includes a second inverter, the output end of the first inverter is electrically connected to the input end of the second inverter, and the output end of the second inverter is the output end of the signal amplification circuit;

[0025] The second inverter is used to invert and widen the current inverted signal to obtain a widening result. The channel length-to-width ratio of the NMOS transistor included in the second inverter is different from the channel width-to-length ratio of the PMOS transistor.

[0026] In the technical solution disclosed in the present application, when the channel length-to-width ratio of the NMOS transistor included in the second inverter is different from the channel width-to-length ratio of the PMOS transistor, the threshold voltage of the NMOS transistor and the threshold voltage of the PMOS transistor can be adjusted, so that the second inverter can not only invert the amplified signal, but also widen the target level.

[0027] In a possible implementation, when the target pulse is triggered by a rising edge, the channel width-to-length ratio of the NMOS transistor included in the second inverter is greater than the channel width-to-length ratio of the PMOS transistor.

[0028] In the technical solution disclosed in the present application, when the channel width-to-length ratio of the NMOS transistor included in the second inverter is greater than the channel width-to-length ratio of the PMOS transistor, the PMOS transistor is more sensitive to the rising edge of the input signal and can widen the high level of the target pulse.

[0029] When the target pulse is triggered by a falling edge, the channel width-to-length ratio of the NMOS transistor included in the second inverter is smaller than the channel width-to-length ratio of the PMOS transistor.

[0030] In the technical solution disclosed in the present application, when the channel width-to-length ratio of the NMOS transistor included in the second inverter is smaller than the channel width-to-length ratio of the PMOS transistor, the PMOS transistor is more sensitive to the falling edge and can widen the low level of the target pulse.

[0031] In one possible implementation, the edge detection subcircuit includes a counter, and the output end of the signal amplifier is electrically connected to the input end of the matching subcircuit through the counter; the counter is used to perform target edge counting on the amplified signal using the reference clock within the preset time length to obtain the target edge counting result of the amplified signal within the preset time length.

[0032] In a possible implementation, the edge detection subcircuit includes a digital delay line and an encoding unit, and the output end of the signal amplifier is electrically connected to the input end of the matching subcircuit through the digital delay line and the encoding unit;

[0033] The digital delay line is used to sample the target edge position of the amplified signal using a reference clock to obtain a sampling result of the target edge position of the amplified signal;

[0034] The encoding unit is used to determine a target edge counting result of the amplified signal within a preset time length based on a target edge position sampling result of the amplified signal.

[0035] In a possible implementation, the attack detection device further includes a shaping circuit, wherein an input end of the shaping circuit is electrically connected to an access terminal of the target pulse, and an output end of the shaping circuit is electrically connected to an input end of the signal amplifier.

[0036] The shaping circuit included in the attack detection device disclosed in the present application can pre-process the target pulse in advance. On the one hand, it can shape the target pulse, and on the other hand, it can filter out smaller glitches in the target pulse in advance, thereby reducing unnecessary attack protection.

[0037] In a second aspect, the present application further provides an attack detection method, which is applied to an attack detection device, wherein the attack detection device includes a signal amplifier, a glitch detection circuit, and an early warning circuit, wherein the glitch detection circuit includes an edge detection subcircuit and a matching subcircuit, and the output end of the signal amplifier is electrically connected to the input end of the early warning circuit through the edge detection subcircuit and the matching subcircuit; the method of the present application includes:

[0038] The signal amplifier receives the target pulse, amplifies the target pulse, and transmits the obtained amplified signal of the target pulse to the edge detection subcircuit;

[0039] The edge detection subcircuit receives the amplified signal, performs target edge detection on the amplified signal using the reference clock within a preset time length, and obtains a target edge counting result of the amplified signal within the preset time length. The operating frequency of the edge detection subcircuit is equal to the frequency of the reference clock, and the frequency of the reference clock is less than the preset frequency.

[0040] The matching subcircuit transmits a warning signal to the warning circuit when the target edge counting result of the amplified signal within the preset time length does not match the target edge counting result of the target pulse within the preset time length;

[0041] When the early warning circuit receives the early warning signal, it executes the first protection strategy.

[0042] In a possible implementation, the attack detection device further includes a shaping circuit, the input end of the shaping circuit is used to be electrically connected to the access terminal of the target pulse, and the output end of the shaping circuit is electrically connected to the input end of the signal amplifier. The method of the present application also includes:

[0043] The shaping circuit receives the target pulse sent by the access terminal, shapes the target pulse, and transmits the shaped target pulse to the signal amplifier.

[0044] The beneficial effects of the technical solution disclosed in the second aspect of this application or any possible implementation solution in the second aspect are the same as the beneficial effects of the first aspect or any possible implementation method of the first aspect, and are not repeated here.

[0045] In a third aspect, the present application further provides a processor, including a processor core and an attack detection device, wherein the attack detection device includes a signal amplifier, a burr detection circuit, and an early warning circuit, and the early warning circuit is electrically connected to a signal interface of the processor core;

[0046] The signal amplifier is electrically connected to the clock terminal of the processor core, and the clock terminal is used to transmit the target pulse to the signal amplifier, and the target pulse is the clock pulse of the processor core; when the processor core receives the trigger signal from the early warning circuit, the second protection strategy for the trigger signal is executed. For example, when the early warning circuit determines that the intensity of the early warning signal is relatively high (the intensity of the early warning signal is greater than or equal to the preset intensity), it can send a trigger signal to the processor core, so that the processor core executes the second protection strategy when receiving the trigger signal from the early warning circuit. The second protection strategy includes safety protection measures such as restarting the processor core or destroying information.

[0047] The beneficial effects of the technical solution disclosed in the third aspect of the present application are the same as the beneficial effects of the technical solution disclosed in the first aspect or any possible implementation method of the first aspect, and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0048] Further details, features and advantages of the present application are claimed in the following description of exemplary embodiments in conjunction with the accompanying drawings, in which:

[0049] Figure 1 A schematic diagram of the structural framework of the attack detection device disclosed in the embodiment of the present application is shown;

[0050] Figure 2 A schematic diagram of the structure of a signal amplifier in the technical solution disclosed in an embodiment of the present application is shown;

[0051] Figure 3 A basic structural diagram of a signal amplifying circuit in the technical solution disclosed in an embodiment of the present application is shown;

[0052] Figure 4A An exemplary structural diagram of a signal amplifying circuit in the technical solution disclosed in an embodiment of the present application is shown;

[0053] Figure 4B A schematic diagram of the analysis of the signal amplification circuit in the technical solution disclosed in the embodiment of the present application is shown;

[0054] Figure 5 A schematic diagram of the structure of an edge detection circuit in the technical solution disclosed in an embodiment of the present application is shown;

[0055] Figure 6 A schematic diagram of the process of the attack detection method disclosed in the embodiment of the present application is shown;

[0056] Figure 7 A schematic diagram of the processor architecture disclosed in an embodiment of the present application is shown. DETAILED DESCRIPTION

[0057] The technical solutions disclosed in the embodiments of the present application will be described in more detail below with reference to the accompanying drawings. Although the technical solutions disclosed in certain embodiments of the present application are shown in the accompanying drawings, it should be understood that the technical solutions disclosed in the present application can be implemented in various forms and should not be interpreted as being limited to the embodiments described herein. Instead, these embodiments are provided to provide a more thorough and complete understanding of the technical solutions disclosed in the embodiments of the present application. It should be understood that the drawings and embodiments of the technical solutions disclosed in the present application are only used for exemplary purposes and are not intended to limit the scope of protection of the technical solutions disclosed in the present application.

[0058] The term "including" and its variations used in this document are open inclusions, that is, "including but not limited to". The term "based on" means "based at least in part on". The term "one embodiment" means "at least one embodiment"; the term "another embodiment" means "at least one other embodiment"; the term "some embodiments" means "at least some embodiments". Relevant definitions of other terms will be given in the description below. It should be noted that the concepts of "first", "second", etc. mentioned in the technical solutions disclosed in the embodiments of the present application are only used to distinguish different devices, units or units, and are not used to limit the order or interdependence of the functions performed by these devices, units or units.

[0059] It should be noted that the modifications of "one" and "plurality" mentioned in the present application are illustrative rather than restrictive, and those skilled in the art should understand that unless otherwise clearly indicated in the context, it should be understood as "one or more".

[0060] In related technologies, fault attacks, especially side channel attacks and physical intrusion attacks, have become an important way to threaten the security of integrated circuits. Attackers may use key signals in the chip's working process to induce predictable errors in the chip through laser injection, power failure or electromagnetic interference, and then obtain sensitive information or tamper with the expected behavior of the chip.

[0061] Currently, security measures such as redundant circuits, error detection and correction codes, and anti-tampering layers can be used to protect chips, but with the continuous emergence of attack methods, these security measures are no longer sufficient to protect chips.

[0062] In order to improve the chip's security protection capabilities, the pulse width of the chip system clock can be measured by the glitch fault detection circuit to determine whether the chip is under attack. However, the measurement sensitivity of this glitch detection technology is not high, which limits the applicability of the glitch detection technology.

[0063] In view of the above problems, an embodiment of the present application provides an attack detection device with relatively high glitch detection sensitivity, which is not limited by the operating frequency of the edge detection subcircuit and can be applied to target pulse glitch detection of various frequencies.

[0064] In practical applications, the attack detection device disclosed in the embodiment of the present application can be used to protect the cryptographic module in the processor core, and can also be used to protect other modules. By analyzing whether the target pulse of the processor core has glitches, it is determined whether the processor core has external fault injection during operation, such as clock glitch injection, so as to timely discover and deal with the attack behavior and ensure the correctness of cryptographic operations or other operations.

[0065] Figure 1 FIG. 2 shows a schematic diagram of the structural framework of the attack detection device disclosed in the embodiment of the present application. Figure 1 As shown, the attack detection device 100 disclosed in the embodiment of the present application may include: a signal amplifier 101, a glitch detection circuit 102 and an early warning circuit, the glitch detection circuit 102 includes an edge detection sub-circuit 1021 and a matching sub-circuit 1022, and the output end of the signal amplifier 101 is electrically connected to the input end of the early warning circuit 103 through the edge detection sub-circuit 1021 and the matching sub-circuit 1022.

[0066] like Figure 1 As shown, the signal amplifier 101 can be used to receive a target pulse, amplify the target pulse, and transmit the obtained amplified signal of the target pulse to the edge detection subcircuit 1021. The target pulse can be a clock pulse of a processor core or a clock pulse of other circuits.

[0067] For example, Figure 1As shown, when the frequency of the target pulse is relatively high, the pulse width of the target pulse is relatively narrow, and the target pulse can be amplified by the signal amplifier 101, thereby reducing the frequency of the target pulse, so that the frequency of the obtained amplified signal is relatively low.

[0068] like Figure 1 As shown, the edge detection subcircuit 1021 is used to receive the amplified signal, and use the reference clock to perform target edge detection on the amplified signal within a preset time length, and obtain the target edge counting result of the amplified signal within the preset time length. Since the target pulse with a higher frequency has been amplified by the signal amplifier 101, the frequency of the amplified signal transmitted to the edge detection subcircuit 1021 is relatively low, and the pulse width is relatively wide. Therefore, the edge detection subcircuit 1021 can use the reference clock with a lower frequency to perform target edge detection on the amplified signal, and can accurately obtain the target edge counting result of the amplified signal within the preset time length. It can be seen that in the technical solution disclosed in the embodiment of the present application, by amplifying the target pulse by the signal amplifier 101, the detection capability of the edge detection subcircuit 1021 for the target pulse with a narrow pulse width can be improved.

[0069] like Figure 1 As shown, the matching subcircuit 1022 is used to transmit an early warning signal to the early warning circuit 103 when the target edge counting result of the amplified signal within the preset time length does not match the target edge counting result of the target pulse within the preset time length.

[0070] like Figure 1 As shown, considering that the edge detection subcircuit 1021 has a relatively high detection capability for target pulses with narrow pulse widths, the target edge counting result of the amplified signal within the preset time length is relatively accurate. Therefore, the target edge counting result of the amplified signal within the preset time length can be used as a reference counting result, and by matching the target edge counting result of the amplified signal within the preset time length with the target edge counting result of the target pulse within the preset time length, it is determined whether the target pulse has glitches.

[0071] like Figure 1 As shown, when the target edge counting result of the amplified signal within the preset time length is equal to the target edge counting result of the target pulse within the preset time length, it indicates that there is a burr in the target pulse, and the processor related to the target pulse is very likely to have a fault attack behavior, so the matching subcircuit 1022 can transmit the early warning signal to the early warning circuit 103. At this time, the early warning circuit 103 is used to execute the first protection strategy when receiving the early warning signal, so as to ensure the information security related to the target pulse.

[0072] For example, Figure 1As shown, in the technical solution disclosed in the embodiment of the present application, the early warning circuit 103 can compare the strength of the early warning signal with the preset strength to determine the protection strategy. For example, when the strength of the early warning signal is less than the preset strength, the protection strategy can be determined as the early warning circuit 103 executing the first protection strategy.

[0073] For example, when the intensity of the warning signal is relatively low (the intensity of the warning signal is less than the preset intensity), it means that the burr of the target pulse is not obvious. Therefore, in the technical solution disclosed in the embodiment of the present application, the warning circuit executes a first protection strategy. The first protection strategy includes using a filtering circuit or other burr processing circuit to process the target pulse to remove the burr signal of the target pulse, and then transmitting the target pulse signal to the processor core, thereby achieving the purpose of protecting the processor core.

[0074] It can be seen that Figure 1 As shown, in the technical solution disclosed in the embodiment of the present application, even if the frequency of the target pulse is relatively high, the glitch detection circuit 102 can cooperate with the signal amplification circuit to effectively improve the detection capability of the target pulse with a narrow pulse width, and realize the attack identification of the target pulse with a narrow pulse width. Therefore, the attack detection device disclosed in the embodiment of the present application has the advantages of relatively high glitch detection accuracy and sensitivity, can reduce the frequency dependence on the reference clock, and is suitable for glitch detection of target pulses of various frequencies.

[0075] Moreover, if Figure 1 As shown, in the technical solution disclosed in the embodiment of the present application, the operating frequency of the edge detection subcircuit 1021 is equal to the frequency of the reference clock, and the frequency of the reference clock is less than the preset frequency. Since the target pulse is amplified by the signal amplifier 101, a higher reference clock frequency is not required to perform target edge detection on the amplified signal. Therefore, the operating frequency of the edge detection subcircuit 1021 is relatively low, and there is no need to equip the edge detection subcircuit 1021 with a counter or the like with a higher operating frequency. This can effectively save the area overhead of the edge detection subcircuit 1021 and is suitable for scenarios with relatively high integration requirements.

[0076] In addition, in the technical solution disclosed in the embodiment of the present application, the process of glitch detection on the target pulse does not rely on special working conditions, such as a higher frequency reference clock or an edge detection circuit with a higher operating frequency. Therefore, it has good stability and versatility.

[0077] It should be noted that the attack detection device 100 disclosed in the embodiment of the present application may also include a shaping circuit 104, the input end of the shaping circuit 104 is used to be electrically connected to the access terminal of the target pulse, and the output end of the shaping circuit 104 is electrically connected to the input end of the signal amplifier 101. In this case, the access terminal of the target pulse can input the target pulse to the shaping circuit 104, so that the shaping circuit 104 receives the target pulse sent by the access terminal, so as to use the shaping circuit 104 to perform waveform shaping on the target pulse, and ensure that the waveform of the target pulse is relatively regular (that is, the waveform of the target pulse changes from unstable to stable), and has a certain driving ability, so that the target pulse input to the signal amplifier 101 meets the signal amplification requirements of the signal amplifier 101, which is convenient for subsequent circuit processing. Moreover, when the burr amplitude of the target pulse is less than the preset amplitude, the burr contained therein can be filtered out during the shaping process of the target pulse by the shaping circuit 104.

[0078] It can be seen that Figure 1 As shown, the shaping circuit 104 included in the attack detection device 100 disclosed in the embodiment of the present application can pre-process the target pulse in advance. On the one hand, it can shape the target pulse, and on the other hand, it can filter out smaller glitches in the target pulse in advance, thereby reducing unnecessary attack protection.

[0079] In one possible implementation, Figure 2 FIG. 1 shows a schematic diagram of the structure of a signal amplifier in the technical solution disclosed in the embodiment of the present application. Figure 2 As shown, in the technical solution disclosed in the embodiment of the present application, the signal amplifier 101 includes: multiple signal amplification circuits A, and the multiple signal amplification circuits A are connected in series. The output end of the last one of the multiple signal amplification circuits A is electrically connected to the input end of the edge detection subcircuit 1021. When the attack detection device 100 includes a shaping circuit 104, the output end of the shaping circuit 104 is connected to the input end of the first one of the multiple signal amplification circuits. In this case, the target pulse is amplified multiple times by the multiple signal amplification circuits A, and when the frequency of the target pulse is relatively high, the signal amplifier 101 can fully amplify the target pulse, thereby improving the sensitivity of glitch detection. Moreover, even if the frequency of the target second pulse is particularly high, the pulse width of the amplified signal obtained by multiple amplification by the signal amplification circuit A can also be applied to the edge detection subcircuit 1021 with a lower operating frequency, thereby improving the scope of application of glitch detection.

[0080] The current signal amplifying circuit A is used to receive the input signal of the current signal amplifying circuit, widen the input signal of the signal amplifying circuit, and obtain a widening result; wherein, if the current signal amplifying circuit is the first of multiple signal amplifying circuits, the input signal is a target pulse, and if the current signal amplifying circuit is the last of multiple signal amplifying circuits, the widening result is an amplified signal; if the current signal amplifying circuit is one of the second to last of multiple signal amplifying circuits, the input signal is the widening result of the signal amplifying circuit previous to the current signal amplifying circuit.

[0081] In practical applications, Figure 3 The basic structure diagram of the signal amplification circuit in the technical solution disclosed in the embodiment of the present application is shown. Figure 3 As shown, in the technical solution disclosed in the embodiment of the present application, the signal amplification circuit may include a first inverter 101A and a widening sub-circuit 101B, the input end of the first inverter 101A is the input end of the signal amplification circuit, the output end of the first inverter 101A is electrically connected to the input end of the widening sub-circuit 101B, and the output end of the widening sub-circuit 101B is the output end of the signal amplification circuit.

[0082] In the current signal amplification circuit, the first inverter 101A is used to receive an input signal, invert the input signal, and obtain a current inverted signal. In this case, the stretching subcircuit 101B is used to invert and extend the pulse width of the current inverted signal to obtain a stretching result, so that compared with the target pulse, the pulse width and frequency of the stretching result change, and the signal does not flip, so that the target edge position detected by the edge detection subcircuit 1021 can be guaranteed to be correct, so as to accurately obtain the target edge counting result of the amplified signal within the preset time length, and ensure the accuracy of the burr detection result.

[0083] In some embodiments, in the technical solution disclosed in the embodiments of the present application, the widening subcircuit includes a Schmitt trigger, the output end of the first inverter is electrically connected to the input end of the Schmitt trigger, and the output end of the Schmitt trigger is the output end of the signal amplification circuit;

[0084] If the voltage of the current inverted signal is within the hysteresis voltage range of the Schmitt trigger, the widening result is the same as the potential of the current inverted signal at the target time. If the voltage of the current inverted signal is outside the hysteresis voltage range of the Schmitt trigger, the widening result is opposite to the potential of the current inverted signal. In this case, the Schmitt trigger can output a widened result with a wider pulse width. At the same time, since the Schmitt trigger has an inverted voltage transmission characteristic, the Schmitt trigger can invert the input result.

[0085] In some embodiments, in the technical solution disclosed in the embodiments of the present application, the widening subcircuit includes a second inverter, the output end of the first inverter is electrically connected to the input end of the second inverter, and the output end of the second inverter is the output end of the signal amplification circuit.

[0086] In the technical solution disclosed in the embodiment of the present application, the second inverter is used to invert and widen the current inverted signal to obtain a widening result. Since the channel length-to-width ratio of the NMOS transistor included in the second inverter is different from the channel width-to-length ratio of the PMOS transistor, in this case, the threshold voltage of the NMOS transistor and the threshold voltage of the PMOS transistor change, so that the second inverter can not only invert the amplified signal, but also widen the target level.

[0087] In practical applications, in the technical solution disclosed in the embodiment of the present application, the difference between the first inverter and the second inverter is whether the saturation currents of the PMOS transistor and the NMOS transistor are the same. For example, the channel width-to-length ratio of the PMOS transistor and the NMOS transistor included in the first inverter can be controlled so that the saturation currents of the PMOS transistor and the NMOS transistor are the same, so that the first transistor has the same conversion time for the rising edge and the falling edge of the input signal, while the channel width-to-length ratios of the PMOS transistor and the NMOS transistor included in the second inverter are not equal, so that the first transistor has different conversion time for the rising edge and the falling edge of the input signal.

[0088] Exemplarily, when the target pulse is triggered by a rising edge, the second inverter is a low threshold level inverter, and the channel width-to-length ratio of the NMOS transistor included in the second inverter is greater than the channel width-to-length ratio of the PMOS transistor.

[0089] For example, the channel width-to-length ratio of the NMOS transistor included in the second inverter can be set to be equal to the reference width-to-length ratio, and the channel width-to-length ratio of the PMOS transistor can be set to be less than the reference width-to-length ratio, so that the channel width-to-length ratio of the NMOS transistor included in the second inverter is greater than the channel width-to-length ratio of the PMOS transistor. In this case, the PMOS transistor is more sensitive to the rising edge of the input signal, so that the second inverter can output a widened result with a high level, thereby achieving the purpose of widening the high level of the target pulse.

[0090] Exemplarily, when the target pulse is triggered by a falling edge, the second inverter is a Gaussian threshold level inverter, and the channel width-to-length ratio of the NMOS transistor included in the second inverter is smaller than the channel width-to-length ratio of the PMOS transistor.

[0091] For example, the channel width-to-length ratio of the NMOS transistor included in the second inverter can be set to be equal to the reference width-to-length ratio, and the channel width-to-length ratio of the PMOS transistor can be set to be greater than the reference width-to-length ratio, so that the channel width-to-length ratio of the NMOS transistor included in the second inverter is smaller than the channel width-to-length ratio of the PMOS transistor. In this case, the PMOS transistor is more sensitive to the falling edge, so that the second inverter can output a widened result of the low level, thereby achieving the purpose of widening the low level of the target pulse.

[0092] In the technical solution disclosed in the embodiment of the present application, assuming that the processor core adopts rising edge triggering, Figure 4A FIG. 1 shows a schematic diagram of the structure of the signal amplification circuit in the technical solution disclosed in the embodiment of the present application. Figure 4A As shown, in the technical solution disclosed in the embodiment of the present application, the signal amplification circuit may include a first inverter 401 and a second inverter 402, and the first inverter 401 and the second inverter 402 are connected in series. The second inverter 402 is a low threshold level inverter.

[0093] In the technical solution disclosed in the embodiment of the present application, the signal amplification circuit has three nodes, namely a first node A, a second node B and a third node C. The first node A is located at the input end of the first inverter 401, the second node B is located between the output end of the first inverter 401 and the input end of the second inverter 402, and the third node C is located at the output end of the second inverter 402.

[0094] Figure 4B FIG. 2 shows an analysis schematic diagram of a signal amplification circuit in the technical solution disclosed in the embodiment of the present application. Figure 4A and Figure 4B As shown, in the technical solution disclosed in the embodiment of the present application, the input signal of the first node A is as follows Figure 4B As shown in the first node A in FIG, the input signal is transmitted to the first inverter 401, so that the first inverter 401 inverts the input signal to obtain the current inverted signal of the second node B.

[0095] like Figure 4A and Figure 4B As shown, since the channel width-to-length ratio of the PMOS transistor and the NMOS transistor included in the first inverter 401 is selected to be the same saturation current (that is, the rising edge and the falling edge conversion time are the same), the first inverter 401 inverts the input signal with a pulse width equal to T0, and the current inverted signal obtained is as follows: Figure 4B The second node B is shown in Figure 2. Figure 4B In the signal of the first node A and the second node B, the duty ratio of the current inverted signal and the input signal changes, but the pulse width or frequency does not change, and the pulse width is still equal to T0.

[0096] like Figure 4A and Figure 4B As shown, since the channel width-to-length ratio of the PMOS transistor included in the second inverter 402 is smaller than the channel width-to-length ratio of the NMOS transistor, the rising edge of the PMOS transistor is sensitive. In this case, when the current inverted signal of the second node B is input to the second inverter 402, the second inverter 402 can not only invert the current inverted signal, but also output Figure 4B The third node C in the figure shows the result of a longer pulse width. Figure 4B The second node B and the third node C in the pulse width are changed, the widening result and the duty cycle of the current inverted signal change, and the pulse width or frequency changes, and the pulse width increases from T0 to T1.

[0097] It can be seen that in the technical solution disclosed in the embodiment of the present application, the signal amplification circuit realizes signal amplification through the first inverter and the second inverter, thereby improving the detection capability of the burr detection circuit for the target pulse.

[0098] In one possible implementation, in the technical solution disclosed in the embodiment of the present application, the edge detection subcircuit may include a counter, and the output end of the signal amplifier is electrically connected to the input end of the matching subcircuit through the counter. The first counter is used to perform target edge counting on the amplified signal using a reference clock within a preset time length to obtain the target edge counting result of the amplified signal within the preset time length.

[0099] In practical applications, in the technical solution disclosed in the embodiment of the present application, the input end of the counter can also be connected to the clock terminal of the processor core, so that the counter can also use the reference clock to count the target edge of the target pulse in a preset time length, and obtain the target edge counting result of the target pulse within the preset time length. When the processor core adopts rising edge triggering, the counter also adopts rising edge triggering. For example, when the counter adopts rising edge triggering, the counter can detect the amplified signal within the preset time length, and when the counter detects the rising edge, the counter adds 1. In this way, the target edge counting result of the target pulse within the preset time length can be obtained.

[0100] In another possible implementation, Figure 5 FIG. 1 shows a schematic diagram of a structure of an edge detection circuit in the technical solution disclosed in the embodiment of the present application. Figure 5 As shown, in the technical solution disclosed in the embodiment of the present application, the edge detection circuit includes a digital delay line 501 and a coding unit 502, and the output end of the signal amplifier is electrically connected to the input end of the matching sub-circuit 1022 through the digital delay line 501 and the coding unit 502.

[0101] The digital delay line 501 is used to sample the target edge position of the amplified signal using a reference clock to obtain a target edge position sampling result of the amplified signal. The encoding unit 502 is used to determine the target edge counting result of the amplified signal within a preset time length based on the target edge position sampling result of the amplified signal.

[0102] In the technical solution disclosed in the embodiment of the present application, the digital delay line 501 includes a plurality of delay units 5011 and a plurality of triggers 5012, wherein the plurality of delay units 5011 are connected in series, and the first input end of the plurality of delay units 5011 is electrically connected to the input end of the signal amplifier. The delay unit 5011 corresponds to the trigger 5012, the first input end of each trigger 5012 is electrically connected to the output end of the corresponding delay unit 5011, and the second input end of each trigger 5012 is connected to the access terminal of the reference clock. The output end of each trigger 5012 is electrically connected to the input end of the encoding unit 502, respectively. When the processor core adopts rising edge triggering, the trigger also adopts rising edge triggering.

[0103] like Figure 5 As shown, taking the trigger 5012 using the rising edge trigger as an example, the amplified signal can be delayed in sequence through multiple delay units 5011, and the output signal of each delay unit 5011 can be input to the corresponding trigger 5012 while being input to the next delay unit 5011. For each trigger 5012, when the rising edge of the reference clock arrives, if the rising edge of the output signal of the delay unit 5011 has not arrived, the trigger 5012 outputs a low-level signal, and if the rising edge of the output signal of the delay unit 5011 arrives, the trigger 5012 outputs a high-level signal. Therefore, when the rising edge of the reference clock arrives, the output signals of each trigger 5012 can form a thermometer code, and the conversion position between the high level and the low level in the thermometer code is the rising edge position of the amplified signal.

[0104] It can be seen that the above method can be used to detect the position of the rising edge of the amplified signal within the preset time length and input it into the encoding unit in the form of a thermometer code. The encoding unit can obtain the thermometer code within the preset time length, and then determine the target edge counting result of the amplified signal within the preset time length by identifying the number of high and low level transitions in the thermometer code.

[0105] The embodiment of the present application also provides an attack detection method, which is applied to an attack detection device. The attack detection method can improve the sensitivity of glitch detection, so that the application range of glitch detection is relatively large. The attack detection device includes a signal amplifier, a glitch detection circuit and an early warning circuit. The glitch detection circuit includes an edge detection subcircuit and a matching subcircuit. The output end of the signal amplifier is electrically connected to the input end of the early warning circuit through the edge detection subcircuit and the matching subcircuit. The attack detection device here can also be the attack detection device described in the embodiment of the present application.

[0106] Figure 6 FIG. 2 is a flow chart of the attack detection method disclosed in the embodiment of the present application. Figure 6 As shown, the attack detection method disclosed in the embodiment of the present application may include:

[0107] Step 601: The signal amplifier receives a target pulse, amplifies the target pulse, and transmits the obtained amplified signal of the target pulse to the edge detection sub-circuit.

[0108] The above-mentioned target pulse can be the clock pulse of the processor core. For the clock pulse with higher frequency, it is amplified by a signal amplifier. The pulse width of the obtained amplified signal is long and the frequency is low. It can effectively enhance the edge detection capability of the edge detection subcircuit without increasing the operating frequency of the edge detection subcircuit.

[0109] Step 602: The edge detection subcircuit receives the amplified signal, performs target edge detection on the amplified signal using a reference clock within a preset time length, and obtains a target edge counting result of the amplified signal within the preset time length. The operating frequency of the edge detection subcircuit is equal to the frequency of the reference clock, and the frequency of the reference clock is less than the preset frequency.

[0110] In the technical solution disclosed in the embodiment of the present application, the target pulse is amplified by a signal amplifier, and the pulse width of the obtained amplified signal is relatively long. A lower frequency reference clock can be used to perform target edge detection on the amplified signal, thereby reducing the dependence of the target pulse glitch detection on the reference clock frequency.

[0111] Step 603: When the target edge counting result of the amplified signal within the preset time length does not match the target edge counting result of the target pulse within the preset time length, the matching subcircuit transmits a warning signal to the warning circuit.

[0112] Step 604: When the early warning circuit receives the early warning signal, it executes the first protection strategy. The first protection strategy can refer to the related description above.

[0113] In an optional manner, the attack detection device disclosed in the embodiment of the present application may further include a shaping circuit, the input end of the shaping circuit is used to be electrically connected to the access terminal of the target pulse, and the output end of the shaping circuit is electrically connected to the input end of the signal amplifier. In this case, the method disclosed in the embodiment of the present application also includes: the shaping circuit receives the target pulse sent by the access terminal, shapes the target pulse, and transmits the shaped target pulse to the signal amplifier.

[0114] The beneficial effects of the attack detection method disclosed in the embodiment of the present application can refer to the beneficial effects of the attack detection device described above, which will not be repeated here.

[0115] Figure 7 FIG. 1 shows a schematic diagram of a processor architecture disclosed in an embodiment of the present application. Figure 7 As shown, the processor 700 disclosed in the embodiment of the present application includes a processor core 701 and an attack detection device 702. The attack detection device 702 may include a signal amplifier 7021, a burr detection circuit 7022, and an early warning circuit 7023. For example, the attack detection device 702 may be as follows Figure 1 The attack detection device shown.

[0116] like Figure 7 As shown, the signal amplifier 7021 is electrically connected to the clock terminal of the processor core 701, so that the clock terminal can be used to transmit the target pulse to the signal amplifier 7021. In this case, the signal amplifier 7021 can amplify the target pulse, and then transmit the obtained amplified signal to the burr detection circuit 7022. The burr detection circuit 7022 can perform burr detection on the amplified signal. When the amplified signal contains burrs, the warning signal can be transmitted to the warning circuit 7023.

[0117] like Figure 7 As shown, the attack detection device 702 disclosed in the embodiment of the present application may further include a shaping circuit 7024, whose output end may be electrically connected to the input end of the signal amplifier 7021, so that the target pulse may be input to the signal amplifier 7021 through the shaping circuit 7024. In this case, the input end of the shaping circuit 7024 is electrically connected to the clock terminal of the processor core 701.

[0118] like Figure 7 As shown, the target pulse is the clock pulse of the processor core 701. Therefore, after the early warning circuit receives the early warning signal sent by the burr detection circuit 7022, it can send a trigger signal to the processor core 701. When the processor core 701 receives the trigger signal from the early warning circuit 7024, the second protection strategy for the trigger signal is executed.

[0119] Exemplarily, when the intensity of the warning signal is relatively high (the intensity of the warning signal is greater than the preset intensity), it means that the burrs of the target pulse are obvious, and the burrs of the target pulse can no longer be removed by conventional filtering circuits or burr processing circuits. Therefore, it can be determined that the warning strategy is for the processor to execute the second protection strategy.

[0120] For example, if Figure 7 As shown, in the technical solution disclosed in the embodiment of the present application, when the early warning circuit 7023 determines that the strength of the early warning signal is relatively high (the strength of the early warning signal is greater than or equal to the preset strength), it can send a trigger signal to the processor core 701, so that the processor core 701 executes the second protection strategy for the trigger signal when receiving the trigger signal from the early warning circuit 7023. For example, the second protection strategy may include security protection measures such as restarting the processor core or destroying information.

[0121] The beneficial effects of the processor disclosed in the embodiment of the present application can refer to the beneficial effects of the attack detection device described above, which will not be repeated here.

[0122] Although the technical solutions disclosed in the present application have been described in conjunction with specific features and embodiments thereof, it is obvious that various modifications and combinations may be made thereto without departing from the spirit and scope of the technical solutions disclosed in the present application. Accordingly, this specification and the accompanying drawings are merely exemplary illustrations of the technical solutions disclosed in the present application as defined by the attached claims, and are deemed to have covered any and all modifications, variations, combinations or equivalents within the scope of the technical solutions disclosed in the present application. Obviously, those skilled in the art may make various changes and modifications to the technical solutions disclosed in the present application without departing from the spirit and scope of the technical solutions disclosed in the present application. Thus, if these modifications and variations of the technical solutions disclosed in the present application fall within the scope of the claims of the present application and their equivalent technologies, the technical solutions disclosed in the present application are also intended to include these changes and variations.

Claims

1. An attack detection device, characterized in that: include: A signal amplifier, a burr detection circuit and an early warning circuit, wherein the burr detection circuit includes an edge detection subcircuit and a matching subcircuit, and the output end of the signal amplifier is electrically connected to the input end of the early warning circuit through the edge detection subcircuit and the matching subcircuit; The signal amplifier is used to receive a target pulse, amplify the target pulse, and transmit the obtained amplified signal of the target pulse to the edge detection subcircuit; The edge detection subcircuit is used to receive the amplified signal, perform target edge detection on the amplified signal using a reference clock within a preset time length, and obtain a target edge counting result of the amplified signal within the preset time length, wherein the operating frequency of the edge detection subcircuit is equal to the frequency of the reference clock, and the frequency of the reference clock is less than the preset frequency; The matching subcircuit is used to transmit a warning signal to the warning circuit when the target edge counting result of the amplified signal within the preset time length does not match the target edge counting result of the target pulse within the preset time length; The early warning circuit is used to execute a first protection strategy when receiving the early warning signal.

2. The attack detection device according to claim 1, characterized in that: The signal amplifier comprises: a plurality of signal amplifying circuits, the plurality of signal amplifying circuits are connected in series, the output end of the last one of the plurality of signal amplifying circuits is electrically connected to the input end of the edge detection subcircuit, the current signal amplifying circuit is used to receive the input signal of the current signal amplifying circuit, and widen the input signal of the signal amplifying circuit to obtain a widening result; If the current signal amplifying circuit is the first of the multiple signal amplifying circuits, the input signal is the target pulse; if the current signal amplifying circuit is the last of the multiple signal amplifying circuits, the stretching result is the amplified signal; If the current signal amplifying circuit is one of the second to the last of the plurality of signal amplifying circuits, the input signal is the stretching result of the signal amplifying circuit before the current signal amplifying circuit.

3. The attack detection device according to claim 2, characterized in that: Each of the signal amplifying circuits comprises a first inverter and a widening subcircuit, the input end of the first inverter is the input end of the signal amplifying circuit, the output end of the first inverter is electrically connected to the input end of the widening subcircuit, and the output end of the widening subcircuit is the output end of the signal amplifying circuit; In the current signal amplification circuit, the first inverter is used to receive the input signal, invert the input signal to obtain a current inverted signal, and the widening subcircuit is used to invert and expand the pulse width of the current inverted signal to obtain the widening result.

4. The attack detection device according to claim 3, characterized in that: The widening subcircuit includes a Schmitt trigger, the output end of the first inverter is electrically connected to the input end of the Schmitt trigger, and the output end of the Schmitt trigger is the output end of the signal amplification circuit; If the voltage of the current inverted signal is within the hysteresis voltage range of the Schmitt trigger, the stretching result is the same as the potential of the current inverted signal at the target time; If the voltage of the current inverted signal is outside the hysteresis voltage range of the Schmitt trigger, the stretching result is opposite to the potential of the current inverted signal at the target time.

5. The attack detection device according to claim 3, characterized in that: The widening subcircuit comprises a second inverter, the output end of the first inverter is electrically connected to the input end of the second inverter, and the output end of the second inverter is the output end of the signal amplifying circuit; The second inverter is used to invert and widen the current inverted signal to obtain the widening result, and the channel length-to-width ratio of the NMOS transistor included in the second inverter is different from the channel width-to-length ratio of the PMOS transistor.

6. The attack detection device according to claim 5, characterized in that: When the target pulse is triggered by a rising edge, the channel width-to-length ratio of the NMOS transistor included in the second inverter is greater than the channel width-to-length ratio of the PMOS transistor; When the target pulse is triggered by a falling edge, the channel width-to-length ratio of the NMOS transistor included in the second inverter is smaller than the channel width-to-length ratio of the PMOS transistor.

7. The attack detection device according to any one of claims 1 to 6, characterized in that: The attack detection device further comprises a shaping circuit, wherein an input end of the shaping circuit is electrically connected to an access terminal of a target pulse, and an output end of the shaping circuit is electrically connected to an input end of the signal amplifier.

8. An attack detection method, characterized in that: Applied to an attack detection device, the attack detection device comprises a signal amplifier, a glitch detection circuit and an early warning circuit, the glitch detection circuit comprises an edge detection subcircuit and a matching subcircuit, the output end of the signal amplifier is electrically connected to the input end of the early warning circuit through the edge detection subcircuit and the matching subcircuit; The method comprises: The signal amplifier receives a target pulse, amplifies the target pulse, and transmits the obtained amplified signal of the target pulse to the edge detection subcircuit; The edge detection subcircuit receives the amplified signal, performs target edge detection on the amplified signal using a reference clock within a preset time length, and obtains a target edge counting result of the amplified signal within the preset time length, wherein the operating frequency of the edge detection subcircuit is equal to the frequency of the reference clock, and the frequency of the reference clock is less than the preset frequency; The matching subcircuit transmits a warning signal to the warning circuit when the target edge counting result of the amplified signal within the preset time length does not match the target edge counting result of the target pulse within the preset time length; The early warning circuit executes a first protection strategy when receiving the early warning signal.

9. The method according to claim 8, characterized in that The attack detection device further includes a shaping circuit, wherein an input end of the shaping circuit is electrically connected to an access terminal of a target pulse, and an output end of the shaping circuit is electrically connected to an input end of the signal amplifier. The method further includes: The shaping circuit receives the target pulse sent by the access terminal, shapes the target pulse, and transmits the shaped target pulse to the signal amplifier.

10. A processor, characterized in that: It includes a processor core and an attack detection device, wherein the attack detection device includes a signal amplifier, a burr detection circuit and an early warning circuit, and the early warning circuit is electrically connected to the signal interface of the processor core; The signal amplifier is electrically connected to the clock terminal of the processor core, and the clock terminal is used to transmit a target pulse to the signal amplifier, and the target pulse is the clock pulse of the processor core; when the processor core receives a trigger signal from the early warning circuit, a second protection strategy for the trigger signal is executed.

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