Silicon carbide power device for improving threshold voltage degradation, preparation method thereof and chip

Abstract

The invention belongs to the technical field of power devices, and provides a silicon carbide power device capable of improving threshold voltage degradation, a preparation method thereof and a chip, a reinforcing layer and a P-type polycrystalline silicon layer are formed in a gate dielectric layer, the reinforcing layer is located above a junction field effect region, the width of the reinforcing layer is equal to or larger than that of the junction field effect region, the reinforcing layer is introduced, and the threshold voltage degradation is improved. The thickness of the insulating layer is improved, the tunneling probability of carriers in the device is reduced, the electron tunneling potential barrier of the device and the tunneling probability of the carriers in the junction field effect region are improved through the P-type polycrystalline silicon layer, the hole concentration of a channel is reduced through the adjusting layer, and the threshold voltage of the device is adjusted.

Description

Silicon carbide power devices with improved threshold voltage degradation and their fabrication methods and chips Technical Field

[0001] This application belongs to the field of power device technology, and in particular relates to a silicon carbide power device with improved threshold voltage degradation, its fabrication method, and chip. Background Technology

[0002] Compared to traditional silicon-based metal-oxide-semiconductor (MOS) devices, SiC MOSFETs offer superior electrical performance, including lower on-resistance, higher breakdown voltage, and better thermal stability. With their advantages such as high temperature resistance, low conduction loss, and excellent high-frequency characteristics, SiC MOSFETs are widely used in new energy power generation, power electronic converters, and electric vehicle drive systems, making them a core component for achieving high efficiency and miniaturization in power electronic devices.

[0003] However, under actual high-frequency switching conditions, the carriers in the channel and JFET region of SiC MOSFET are easily trapped by the gate oxide layer, causing the threshold voltage (Vth) to drift. This problem seriously restricts its long-term reliability and application stability. Summary of the Invention

[0004] To address the aforementioned technical problems, this application provides a silicon carbide power device with improved threshold voltage degradation, its fabrication method, and a chip, aiming to optimize the device's threshold voltage and improve its reliability.

[0005] A first aspect of this application provides a silicon carbide power device, comprising: a silicon carbide substrate and an N-type drift region formed on the front side of the silicon carbide substrate; a junction field-effect region and a P-type well region formed on the N-type drift region; the P-type well region having an L-shaped structure, with its vertical portion adjacent to and in contact with the junction field-effect region; an adjustment layer formed on the vertical portion of the P-type well region, wherein the adjustment layer is N-type doped; and a heavily doped P-type region and a heavily doped N-type region formed on the horizontal portion of the P-type well region. The N-type heavily doped region is in contact with the adjustment layer; a gate dielectric layer is formed on the adjustment layer, and the gate dielectric layer is in contact with the N-type heavily doped region; a P-type polysilicon layer and a reinforcement layer are formed within the gate dielectric layer; a source metal layer is formed on the gate dielectric layer, and the source metal layer is in contact with the gate dielectric layer, the N-type heavily doped region, and the P-type heavily doped region; wherein the reinforcement layer is located above the junction field-effect region, and the width of the reinforcement layer is equal to or greater than that of the junction field-effect region; and a drain metal layer is formed on the back side of the silicon carbide substrate.

[0006] In some embodiments, the conditioning layer is further formed on the junction field-effect region.

[0007] In some embodiments, the width of the adjustment layer is greater than the width of the junction field-effect region, and the width of the adjustment layer is greater than the width of the reinforcement layer.

[0008] In some embodiments, the reinforcement layer includes a plurality of reinforcement dielectric regions stacked together, the width of the plurality of reinforcement dielectric regions gradually decreasing from the adjustment layer toward the source metal layer; in some embodiments, the widths of the plurality of reinforcement dielectric regions are in an arithmetic sequence.

[0009] In some embodiments, the dielectric constant of the plurality of reinforced dielectric regions gradually decreases from the adjustment layer toward the source metal layer.

[0010] In some embodiments, the maximum width of the plurality of reinforced medium regions is the same as the width of the junction field-effect region.

[0011] In some embodiments, the doping concentration of the adjustment layer is greater than the doping concentration of the junction field-effect region.

[0012] A second aspect of this application also provides a method for fabricating a silicon carbide power device as described in any of the above embodiments. The method includes: forming an N-type drift region on the front side of a silicon carbide substrate; forming a junction field-effect region, a P-type well region, an N-type heavily doped region, and a P-type heavily doped region on the N-type drift region by an ion implantation process; wherein the P-type well region has an L-shaped structure, the vertical portion of the P-type well region is adjacent to the junction field-effect region, and the N-type heavily doped region and the P-type heavily doped region are formed on the horizontal portion of the P-type well region; forming an adjustment layer on the vertical portion of the P-type well region; forming a gate dielectric layer on the adjustment layer, and forming a reinforcement layer and the P-type polysilicon layer within the gate dielectric layer; wherein the reinforcement layer is located above the junction field-effect region, and the width of the reinforcement layer is equal to or greater than that of the junction field-effect region; forming a source metal layer covering the gate dielectric layer, the N-type heavily doped region, and the P-type heavily doped region, and forming a drain metal layer on the back side of the silicon carbide substrate.

[0013] A third aspect of this application also provides a chip including a silicon carbide power device as described in any of the above embodiments.

[0014] The beneficial effects of the embodiments of this application are as follows: by forming a reinforcement layer and a P-type polysilicon layer in the gate dielectric layer, the reinforcement layer is located above the junction field-effect region and the width of the reinforcement layer is equal to or greater than that of the junction field-effect region. The reinforcement layer is introduced to increase the thickness of the insulating layer, reduce the tunneling probability of carriers in the device, and the P-type polysilicon layer raises the electron tunneling barrier of the device, reducing the probability of carriers in the junction field-effect region tunneling. The threshold voltage of the device is adjusted by reducing the hole concentration in the channel through the adjustment layer. Attached Figure Description

[0015] Figure 1 is a schematic diagram of a silicon carbide power device provided in an embodiment of this application; Figure 2 is a simulation schematic diagram of a silicon carbide power device provided in an embodiment of this application; Figure 3 is a schematic diagram of the electron current density distribution of a silicon carbide power device provided in an embodiment of this application; Figure 4 is another schematic diagram of a silicon carbide power device provided in an embodiment of this application; Figure 5 is another schematic diagram of a silicon carbide power device provided in an embodiment of this application; Figure 6 is another schematic diagram of a silicon carbide power device provided in an embodiment of this application; Figure 7 is a flowchart of the fabrication method of a silicon carbide power device provided in an embodiment of this application; Figure 8 is a partial cross-sectional schematic diagram of a silicon carbide power device provided in an embodiment of this application; Figure 9 is a partial cross-sectional schematic diagram of a silicon carbide power device provided in an embodiment of this application; Figure 10 is a partial cross-sectional schematic diagram of a silicon carbide power device provided in an embodiment of this application; Figure 11 is a partial cross-sectional schematic diagram of a silicon carbide power device provided in an embodiment of this application; Figure 12 is a partial cross-sectional schematic diagram of a silicon carbide power device provided in an embodiment of this application; Figure 13 is a partial cross-sectional schematic diagram of a silicon carbide power device provided in an embodiment of this application. Detailed Implementation

[0016] To make the technical problems, technical solutions, and beneficial effects to be solved by this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and are not intended to limit the scope of this application.

[0017] Due to inherent defects at the interface between silicon carbide (SiC) and the gate oxide layer, rapid gate voltage jumps during long-term high-frequency switching can cause charge carriers to gain sufficient energy and be trapped by gate oxide traps through tunneling, thermal emission, and other methods. This trapping process has a cumulative effect. Drift in the threshold voltage (Vth) leads to increased device conduction losses, deterioration of switching characteristics, and even false triggering or turn-off failure, reducing overall system efficiency and safety.

[0018] Current technologies struggle to effectively suppress this type of drift phenomenon, often exhibiting issues such as complex structures, high costs, and poor adaptability, failing to meet the long-term stable operation requirements of devices in high-frequency scenarios. Therefore, developing an efficient and reliable suppression scheme to address the Vth drift caused by gate oxide traps in SiC MOSFETs during high-frequency switching has become a pressing technical challenge in this field, possessing significant practical application value and industrial implications.

[0019] To address the aforementioned technical problems, this application provides a silicon carbide power device with improved threshold voltage degradation. As shown in Figure 1, the silicon carbide power device in this application includes: a silicon carbide substrate 110, an N-type drift region 120, a junction field-effect region 150, a P-type well region 130, a conditioning layer 210, a heavily doped P-type region 141, a heavily doped N-type region 142, a gate dielectric layer 220, a P-type polysilicon layer 230, a hardening layer 240, a source metal layer 310, and a drain metal layer 320.

[0020] An N-type drift region 120 is formed on the front side of the silicon carbide substrate 110. A junction field-effect region 150 and a P-type well region 130 are formed on the N-type drift region 120, and the P-type well region 130 has an L-shaped structure. The vertical portion of the P-type well region 130 is adjacent to and in contact with the junction field-effect region 150. A conditioning layer 210 is formed on the vertical portion of the P-type well region 130, and the conditioning layer 210 is N-type doped. A heavily doped P-type region 141 and a heavily doped N-type region 142 are formed on the horizontal portion of the P-type well region 130, and the heavily doped N-type region 142 is in contact with the conditioning layer 210.

[0021] A gate dielectric layer 220 is formed on the conditioning layer 210. The gate dielectric layer 220 is in contact with the N-type heavily doped region 142. A P-type polysilicon layer 230 and a reinforcement layer 240 are formed within the gate dielectric layer 220.

[0022] The source metal layer 310 is formed on the gate dielectric layer and is in contact with the gate dielectric layer, the N-type heavily doped region 142 and the P-type heavily doped region 141. The reinforcement layer 240 is located above the junction field-effect region 150 and the width of the reinforcement layer 240 is equal to or greater than that of the junction field-effect region 150.

[0023] A drain metal layer 320 is formed on the back side of a silicon carbide substrate 110.

[0024] In this embodiment, by forming a reinforcement layer 240 and a P-type polysilicon layer 230 within the gate dielectric layer 220, the reinforcement layer 240 is located above the junction field-effect region 150, and the width of the reinforcement layer 240 is equal to or greater than that of the junction field-effect region 150. Introducing the reinforcement layer 240 increases the thickness of the insulating layer, which can prevent electron tunneling in the junction field-effect region 150, reduce the tunneling probability of carriers in the device, and raise the electron tunneling barrier of the device by the P-type polysilicon layer 230, thus reducing the probability of carriers tunneling in the junction field-effect region 150. Furthermore, by reducing the hole concentration in the channel through the adjustment layer 210, the threshold voltage of the device can be adjusted.

[0025] In some embodiments, the adjustment layer 210 is also formed on the junction field-effect region 150.

[0026] In this embodiment, the adjustment layer 210 covers at least the vertical portion of the P-type well region 130 and may also cover the junction field-effect region 150. The vertical portion of the P-type well region 130 is flush with the upper surface of the junction field-effect region 150. The adjustment layer 210 has a high concentration of N-type doped ions, and the concentration of its N-type doped ions can be greater than that of the junction field-effect region 150. In this application, the N-type polysilicon material in the gate dielectric layer 220 is replaced with a P-type polysilicon layer 230 material to form a P-type polysilicon layer 230. This P-type polysilicon layer 230 can raise the electron tunneling barrier and reduce the tunneling probability. However, the P-type polysilicon layer 230 will raise the threshold voltage of the device. By adjusting the high concentration of N-type doping in the adjustment layer 210, the hole concentration in the channel can be reduced, thereby adjusting the threshold voltage of the device and also helping to reduce the tunneling probability of holes.

[0027] In some embodiments, the width of the adjustment layer 210 is greater than the width of the junction field effect region 150, and the width of the adjustment layer 210 is greater than the width of the reinforcement layer 240.

[0028] In this embodiment, the gate dielectric layer 220 can be a gate oxide layer, and its material can be silicon dioxide. The reinforcement layer 240 covers at least a portion of the gate dielectric layer 220 above the junction field-effect region 150, which can increase the thickness of the gate dielectric material above the junction field-effect region 150. Without reducing the basic characteristics of the device, by setting the reinforcement layer 240, the high concentration of doping in the junction field-effect region 150 is prevented from being captured by gate oxide defects. At the same time, the P-type polysilicon layer 230 reduces the probability of electron tunneling. In high-frequency application scenarios, the threshold voltage (Vth) drift is improved.

[0029] In some embodiments, the dielectric constant of the reinforcing layer 240 is greater than that of silicon oxide.

[0030] In some embodiments, the reinforcing layer 240 may be made of a high-K insulating dielectric material, which may be any insulating material including but not limited to oxides, nitrides, composite materials, etc.

[0031] In some embodiments, under high-frequency applications, the gate oxide / semiconductor interface of SiC MOSFETs in related technologies has a large number of defects. Due to the high electric field of the gate, carriers in the junction field-effect region 150 (JFET region) and the channel are continuously adsorbed to the gate oxide layer, and the carriers tunnel. During the tunneling process, defects trap the carriers and leave fixed charges, causing the threshold voltage (Vth) to drift. Among them, the JFET region has a very large impact on the threshold voltage (Vth). The device structure shown in Figure 1 of this application introduces a hardening layer 240, which uses a stepped insulating layer to adjust the electric field strength of the gate oxide (high-K materials can significantly reduce the tunneling probability, and increasing the thickness of the insulating layer can also significantly reduce the tunneling probability) to avoid the tunneling of carriers in the JFET region. Meanwhile, the P-type polysilicon layer 230 raises the electron tunneling barrier and reduces the tunneling probability. However, the P-type polysilicon layer 230 will increase the device's Vth. By adjusting the high concentration of N-type doping in the layer 210, the hole concentration in the channel is reduced, thus adjusting Vth. This will also reduce the hole tunneling probability.

[0032] Through the above structural design, the gate tunneling current of charge carriers can be significantly reduced, avoiding Vth drift caused by defects trapping a large number of charge carriers. Simulation verification shows that Figures 2 and 3 simulate the electron tunneling of the device at a gate voltage of 22V. Figure 2 shows the direction of the electron tunneling current in the device structure shown in Figure 1. It can be observed that, compared to the conventional structure where the electron tunneling current covers the entire gate oxide interface, the electron tunneling current in the structure of this application exists only in the channel. Figure 3 compares the electron tunneling current density at the gate oxide interface of the conventional structure S1 and the structure S2 of this application. It is significantly observed that the current density in the channel region of the structure of this application is much lower than that of the conventional structure. Typically, the driving voltage of SiC MOSFETs is between -10V and 22V. Low negative bias voltages are usually insufficient to meet the electric field strength requirements for hole tunneling, resulting in a very low tunneling probability.

[0033] In some embodiments, as shown in FIG1, the reinforcement layer 240 includes a plurality of reinforcement medium regions stacked together, the width of the plurality of reinforcement medium regions gradually decreasing from the adjustment layer 210 toward the source metal layer 310.

[0034] In this embodiment, the reinforcement layer 240 includes multiple reinforcement dielectric regions stacked together. The width of the multiple reinforcement dielectric regions gradually decreases from the adjustment layer 210 toward the source metal layer 310. This design can better adjust the gate oxide electric field distribution and avoid electron tunneling caused by high electric field peaks at corners.

[0035] In some embodiments, the widths of the plurality of reinforced medium regions are arranged in an arithmetic sequence.

[0036] In this embodiment, by setting the widths of multiple hardening dielectric regions to be in an arithmetic sequence, the electric field distribution on the surface of the gate dielectric layer 220 can be balanced and adjusted, reducing the electric field spikes at its corners, thereby reducing the probability of electron tunneling.

[0037] In some embodiments, the dielectric constant of the plurality of hardened dielectric regions gradually decreases from the adjustment layer 210 toward the source metal layer 310.

[0038] In this embodiment, the P-type polysilicon layer 230 is heavily P-type doped. The closer it is to the junction field-effect region 150, the greater the dielectric constant of the hardened dielectric region. Furthermore, the thickness of the hardened layer 240 gradually increases from the P-type well region 130 to the junction field-effect region 150, which can increase the difficulty of carriers tunneling into the P-type polysilicon layer 230 within the junction field-effect region 150. This avoids the high concentration of doping in the JFET region being captured by gate oxide defects, thereby reducing the tunneling probability of carriers within the device.

[0039] In some embodiments, the reinforcing layer 240 is a stepped structure (which may be multiple steps, not limited to those shown in Figure 1).

[0040] In some embodiments, the hardening layer 240 includes multiple hardening dielectric regions forming a stepped structure. The thickness of the hardening dielectric regions near the junction field-effect region 150 is larger, and the thickness of the multiple hardening dielectric regions gradually decreases from the drain metal layer 320 to the source metal layer 310. This increases the difficulty of carriers tunneling into the P-type polysilicon layer 230 within the junction field-effect region 150, avoids the high concentration of doping in the JFET region being captured by gate oxide defects, and thus reduces the tunneling probability of carriers within the device.

[0041] In some embodiments, the reinforcing layer 240 includes a plurality of reinforcing medium regions, and the thickness of a single layer of the reinforcing medium region is 10-200 nm.

[0042] In some embodiments, the adjustment layer 210 may be formed by implantation of N-type doped ions, and the N-type doped ions in the adjustment layer 210 may be phosphorus ions or nitrogen ions.

[0043] In some embodiments, the doping concentration of the adjustment layer 210 ranges from 1e16 to 1e17 cm⁻¹. -3 .

[0044] In some embodiments, the coverage area of ​​the adjustment layer 210 is within 0.5 μm near the gate oxide interface.

[0045] In some embodiments, the maximum width of the reinforcement medium region is consistent with the width of the junction field effect region 150 among the plurality of reinforcement medium regions.

[0046] In some embodiments, the width of the reinforcing layer 240 is slightly larger than the width of the junction field-effect region 150, and the reinforcing layer 240 at least causes a portion of the adjustment layer 210 to be directly opposite the p-type polysilicon layer 230.

[0047] In some embodiments, as shown in FIG4, the reinforcing layer 240 can be a stepless reinforcing layer 240 structure, which is simple to manufacture. However, a high electric field spike is easily caused at the interface between the reinforcing layer 240 and the P-type polysilicon layer 230, increasing the probability of electron tunneling at this location. Therefore, by setting the width of the reinforcing layer 240 to be greater than the width of the junction field-effect region 150, and by setting the interface between the reinforcing layer 240 and the P-type polysilicon layer 230 to a concave-convex structure, the interface area between the reinforcing layer 240 and the P-type polysilicon layer 230 can be increased, and the probability of a high electric field spike at the interface can be reduced.

[0048] In some embodiments, as shown in FIG5, the adjustment layer 210 at least covers the vertical portion of the P-type well region 130. The upper surface of the adjustment layer 210 is flush with the upper surface of the junction field-effect region 150. The adjustment layer 210 has a high concentration of N-type doped ions, and the concentration of its N-type doped ions can be greater than that of the junction field-effect region 150. Since the P-type polysilicon layer 230 raises the threshold voltage of the device, by setting at least a portion of the adjustment layer 210 between it and the oppositely disposed P-type polysilicon layer 230, and by using the high concentration of N-type doping in the adjustment layer 210, the hole concentration in the channel can be reduced, thereby adjusting the threshold voltage of the device and also helping to reduce the tunneling probability of holes.

[0049] In some embodiments, as shown in FIG6, the hardening layer 240 includes a plurality of hardening dielectric regions, at least a portion of which is located above the vertical portion of the P-type well region 130, and at least a portion of the P-type polysilicon layer 230 and at least a portion of the gate dielectric layer 220 are disposed between the hardening dielectric region and the vertical portion of the P-type well region 130. In this way, the thickness of the P-type polysilicon layer 230 can be adjusted to avoid the thickness of the P-type polysilicon layer 230 above the vertical portion of the P-type well region 130 being too large, which would affect the threshold voltage of the device.

[0050] In this embodiment, the reinforcement layer 240 includes multiple reinforcement dielectric regions stacked together. The thickness of the multiple reinforcement dielectric regions gradually decreases from the adjustment layer 210 toward the source metal layer 310. This design can better adjust the gate oxide electric field distribution and avoid electron tunneling caused by high electric field peaks at corners.

[0051] In some embodiments, the doping concentration of the adjustment layer 210 is greater than the doping concentration of the junction field-effect region 150.

[0052] This application also provides a method for fabricating a silicon carbide power device as described in any of the above embodiments. As shown in Figure 7, the fabrication method in this embodiment includes steps S100 to S500.

[0053] In step S100, an N-type drift region 120 is formed on the front side of the silicon carbide substrate 110.

[0054] In this embodiment, as shown in FIG8, the silicon carbide substrate 110 can be an N-type silicon carbide substrate 110, and an N-type drift region 120 is formed on the front side of the silicon carbide substrate 110 by epitaxial process.

[0055] In step S200, a junction field-effect region 150, a P-type well region 130, an N-type heavily doped region 142, and a P-type heavily doped region 141 are formed on the N-type drift region 120 by an ion implantation process.

[0056] In this embodiment, as shown in FIG9, an N-type dopant ion is injected into a first preset region on the front side of the N-type drift region 120 to form a junction field-effect region 150, and a P-type dopant ion is injected into a second preset region to form a P-type well region 130. An N-type heavily doped region 142 and a P-type heavily doped region 141 are formed by sequentially injecting P-type dopant ions and N-type dopant ions into a portion of the P-type well region 130. After annealing, the P-type well region 130 is formed into an L-shaped structure. The vertical portion of the P-type well region 130 is adjacent to the junction field-effect region 150, and the N-type heavily doped region 142 and the P-type heavily doped region 141 are formed on the horizontal portion of the P-type well region 130.

[0057] In some embodiments, the concentration of N-type dopant ions in the N-type heavily doped region 142 is greater than the concentration of P-type dopant ions in the P-type well region 130, and the concentration of P-type dopant ions in the P-type heavily doped region 141 is greater than the concentration of P-type dopant ions in the P-type well region 130.

[0058] In step S300, an adjustment layer 210 is formed on the vertical portion of the P-type well region 130.

[0059] In this embodiment, as shown in FIG10, N-type doped ions are implanted into the vertical portion of the P-type well region 130 by ion implantation, and an adjustment layer 210 is formed by annealing.

[0060] In some embodiments, the adjustment layer 210 is also formed on the junction field-effect region 150, and the vertical portion of the P-type well region 130 is flush with the upper surface of the junction field-effect region 150. The adjustment layer 210 has a high concentration of N-type doped ions, and the concentration of its N-type doped ions can be greater than that of the junction field-effect region 150. In this application, the N-type polysilicon material in the gate dielectric layer 220 is replaced with a P-type polysilicon layer 230 material to form a P-type polysilicon layer 230. The P-type polysilicon layer 230 can raise the electron tunneling barrier and reduce the tunneling probability. However, the P-type polysilicon layer 230 will raise the threshold voltage of the device. By adjusting the high concentration of N-type doping in the adjustment layer 210, the hole concentration in the channel can be reduced, thereby adjusting the threshold voltage of the device, and it is also beneficial to reduce the tunneling probability of holes.

[0061] In step S400, a gate dielectric layer 220 is formed on the adjustment layer 210, and a reinforcement layer 240 and a P-type polysilicon layer 230 are formed within the gate dielectric layer 220.

[0062] In this embodiment, as shown in FIG11, an oxide layer is formed by an oxidation process to form a gate dielectric layer 220, and a reinforcement layer 240 is prepared by a dielectric deposition process. The reinforcement layer 240 is located above the junction field effect region 150, and the width of the reinforcement layer 240 is equal to or greater than the junction field effect region 150.

[0063] As shown in Figure 11, a P-type polysilicon layer 230 is formed by depositing P-type polysilicon material under the cover of a mask. The junction field-effect region 150 (JFET region) is N-type doped, and the adjustment layer 210 is also N-type doped. The N-type doping concentration of the adjustment layer 210 is lower than the P-type doping concentration of the P-type well region 130. The adjustment layer 210 can be used for reverse adjustment to reduce the device barrier, thereby achieving the effect of reducing the threshold voltage.

[0064] In step S500, a source metal layer 310 is formed covering the gate dielectric layer 220, the N-type heavily doped region 142, and the P-type heavily doped region 141, and a drain metal layer 320 is formed on the back side of the silicon carbide substrate 110.

[0065] In this embodiment, as shown in FIG12, an insulating dielectric material is deposited to form a gate dielectric layer 220 covering the P-type polysilicon layer 230, such that the gate dielectric layer 220 encapsulates the reinforcement layer 240 and the P-type polysilicon layer 230. As shown in FIG13, an electrode material is deposited on the front side of the device to form a source metal layer 310 in contact with the gate dielectric layer 220, the N-type heavily doped region 142, and the P-type heavily doped region 141, and a drain metal layer 320 located on the back side of the silicon carbide substrate 110.

[0066] In some embodiments, the gate dielectric layer 220 is silicon dioxide, the gate dielectric layer 220 covers the interface between the adjustment layer 210 and the N-type heavily doped region 142, and the source metal layer 310 covers the P-type heavily doped region 141 and at least a portion of the N-type heavily doped region 142.

[0067] This application also provides a chip, including a silicon carbide power device as described in any of the above embodiments.

[0068] In this embodiment, a reinforcement layer 240 and a P-type polysilicon layer 230 are formed within the gate dielectric layer 220. The reinforcement layer 240 is located above the junction field-effect region 150, and the width of the reinforcement layer 240 is equal to or greater than that of the junction field-effect region 150. The reinforcement layer 240 is introduced to increase the thickness of the insulating layer, reduce the tunneling probability of carriers in the device, and raise the electron tunneling barrier of the device by the P-type polysilicon layer 230. The probability of carriers tunneling in the junction field-effect region 150 is reduced, and the threshold voltage of the device is adjusted by reducing the hole concentration in the channel through the adjustment layer 210.

[0069] In some embodiments, other related semiconductor devices, as well as MOSFETs, may be integrated on the chip substrate to form an integrated circuit.

[0070] In one specific application embodiment, the chip can be a switch chip or a driver chip.

[0071] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the above-described division of doped regions and devices is used as an example. In practical applications, the above functions can be assigned to different doped regions and devices as needed, that is, the internal structure of the device can be divided into different doped regions to complete all or part of the functions described above. In the embodiments, the doped regions and devices can be integrated into one unit, or each unit can exist physically separately, or two or more units can be integrated into one unit.

[0072] Furthermore, the specific names of each doped region and device are only for the purpose of distinguishing them from each other and are not intended to limit the scope of protection of this application.

[0073] In the above embodiments, the descriptions of each embodiment have different focuses. For parts that are not described in detail or recorded in a certain embodiment, please refer to the relevant descriptions of other embodiments.

[0074] In addition, in the various embodiments of this application, each doped region can be integrated into one unit, or each unit can exist physically separately, or two or more units can be integrated into one unit.

[0075] The above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application, and should all be included within the protection scope of this application.

Claims

1. A silicon carbide power device with improved threshold voltage degradation, characterized in that, The silicon carbide power device includes: a silicon carbide substrate and an N-type drift region formed on the front side of the silicon carbide substrate; a junction field-effect region and a P-type well region formed on the N-type drift region; the P-type well region has an L-shaped structure, and the vertical portion of the P-type well region is adjacent to and in contact with the junction field-effect region; an adjustment layer formed on the vertical portion of the P-type well region, and the adjustment layer is doped with N-type; a heavily doped P-type region and a heavily doped N-type region formed on the horizontal portion of the P-type well region, and the heavily doped N-type region is adjacent to and in contact with the junction field-effect region. The junction layer has the following components: a junction dielectric layer; a gate dielectric layer formed on the adjustment layer, the gate dielectric layer being in contact with the heavily doped N-type region; a P-type polysilicon layer and a reinforcement layer formed within the gate dielectric layer; a source metal layer formed on the gate dielectric layer, the source metal layer being in contact with the gate dielectric layer, the heavily doped N-type region, and the heavily doped P-type region; wherein the reinforcement layer is located above the junction field-effect region, and the width of the reinforcement layer is equal to or greater than that of the junction field-effect region; and a drain metal layer formed on the back side of the silicon carbide substrate.

2. The silicon carbide power device as described in claim 1, characterized in that, The adjustment layer is also formed on the junction field-effect region.

3. The silicon carbide power device as described in claim 2, characterized in that, The width of the adjustment layer is greater than the width of the junction field effect region, and the width of the adjustment layer is greater than the width of the reinforcement layer.

4. The silicon carbide power device as described in claim 1, characterized in that, The reinforcement layer includes multiple reinforcement medium regions stacked together, and the width of the multiple reinforcement medium regions gradually decreases from the adjustment layer toward the source metal layer.

5. The silicon carbide power device as described in claim 4, characterized in that, The widths of the multiple reinforced medium regions form an arithmetic sequence.

6. The silicon carbide power device as described in claim 4, characterized in that, The dielectric constant of the plurality of reinforced dielectric regions gradually decreases from the adjustment layer toward the source metal layer.

7. The silicon carbide power device as described in claim 4, characterized in that, The maximum width of the plurality of reinforced medium regions is consistent with the width of the junction field effect region.

8. The silicon carbide power device as described in claim 1, characterized in that, The doping concentration of the adjustment layer is greater than the doping concentration of the junction field-effect region.

9. A method for fabricating a silicon carbide power device as described in any one of claims 1-8, characterized in that, The fabrication method includes: forming an N-type drift region on the front side of a silicon carbide substrate; forming a junction field-effect region, a P-type well region, an N-type heavily doped region, and a P-type heavily doped region on the N-type drift region by an ion implantation process; wherein the P-type well region has an L-shaped structure, the vertical portion of the P-type well region is adjacent to the junction field-effect region, and the N-type heavily doped region and the P-type heavily doped region are formed on the horizontal portion of the P-type well region; forming an adjustment layer on the vertical portion of the P-type well region; forming a gate dielectric layer on the adjustment layer, and forming a reinforcement layer and the P-type polysilicon layer within the gate dielectric layer; wherein the reinforcement layer is located above the junction field-effect region, and the width of the reinforcement layer is equal to or greater than that of the junction field-effect region; forming a source metal layer covering the gate dielectric layer, the N-type heavily doped region, and the P-type heavily doped region, and forming a drain metal layer on the back side of the silicon carbide substrate.

10. A chip, characterized in that, Including the silicon carbide power device as described in any one of claims 1-8.

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