Display panel and display device

Abstract

The embodiment of the invention provides a display panel and a display device. The display panel comprises a pixel circuit, and the pixel circuit comprises a driving transistor, a first light-emitting control module and a second light-emitting control module. The first output end of the first shift register circuit is electrically connected with the first signal line. The second output end of the second shift register circuit is electrically connected with the second signal line. The first light-emitting control module and the second light-emitting control module are both electrically connected with the driving transistor and control the driving transistor to output light-emitting driving current when both are turned on. According to the invention, the first light-emitting control module and the second light-emitting control module have a time-sharing starting condition, so that the starting time and the ending time of transmitting the light-emitting driving current generated by the pixel circuit to the light-emitting device are adjusted through the on-off cooperation of the first light-emitting control module and the second light-emitting control module; and the light-emitting duration can be adjusted to be a non-integral multiple or integral multiple clock period.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a display panel and a display device. Background Art

[0002] The display panel includes a pixel circuit, which can generate a light-emitting driving current and transmit it to an electrically connected light-emitting device. The light-emitting device emits light after receiving the light-emitting driving current. The magnitude of the light-emitting driving current affects the light-emitting brightness of the light-emitting device. Some devices in the pixel circuit have leakage current, resulting in a certain error in the current transmitted to the light-emitting device, which also causes an error in the light-emitting brightness of the light-emitting device. The light-emitting brightness can be compensated by adjusting the duration of light emission of the light-emitting device. However, when adjusting the light-emitting duration of the light-emitting device, the adjustment of the light-emitting duration is usually adjusted in terms of the refresh time of a row of pixel circuits, and the adjusted light-emitting duration is usually an integer multiple of the unit time. For a working cycle with a relatively short light-emitting duration, adjusting in multiples of the unit time cannot achieve the time accuracy required for adjusting its light emission, which can easily cause the light-emitting device to flicker. Summary of the invention

[0003] In view of this, the present application provides a display panel and a display device to solve the above problems.

[0004] In a first aspect, an embodiment of the present application provides a display panel, including: a pixel circuit, including a driving transistor, a first light-emitting control module, and a second light-emitting control module, wherein a control end of the first light-emitting control module is electrically connected to a first signal line, and a control end of the second light-emitting control module is electrically connected to a second signal line; the first signal line can output a first level signal and a second level signal, and the control end of the first light-emitting control module is turned on when receiving the first level signal, and is turned off when receiving the second level signal; the second signal line can output a third level signal and a fourth level signal, and the control end of the second light-emitting control module is turned on when receiving the third level signal, and is turned off when receiving the fourth level signal;

[0005] A first shift register, comprising M stages of cascaded first shift register circuits, wherein a first output end of the first shift register circuit is electrically connected to a first signal line; the first shift register circuit receives a first start signal, a first clock signal, and a second clock signal;

[0006] The second shift register comprises M stages of cascaded second shift register circuits; the second output end of the second shift register circuit is electrically connected to the second signal line; the first shift register circuit receives the second start signal, the third clock signal, and the fourth clock signal;

[0007] The first light-emitting control module and the second light-emitting control module are both electrically connected to the driving transistor, and when both are turned on, they control the driving transistor to output a light-emitting driving current.

[0008] In a second aspect, an embodiment of the present application provides a display device, comprising a display panel provided in the first aspect.

[0009] In the embodiment of the present application, the signals output by the first shift register circuit and the second shift register circuit are set to respectively control the first light-emitting control module and the second light-emitting control module in the pixel circuit, so that the first light-emitting control module and the second light-emitting control module have the conditions for time-sharing opening, which is beneficial to adjust the start time and end time of the light-emitting drive current generated by the pixel circuit to the light-emitting device through the on-off coordination of the first light-emitting control module and the second light-emitting control module, thereby achieving more flexible adjustment of the light-emitting time of the light-emitting device, and adjusting the light-emitting time to a non-integer multiple or integer multiple of the clock cycle, and more accurately compensating for the light-emitting brightness of the light-emitting device 200. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative labor.

[0011] Figure 1 A schematic plan view of a display panel provided in an embodiment of the present application;

[0012] Figure 2 A schematic diagram of a pixel circuit provided in an embodiment of the present application;

[0013] Figure 3 A schematic diagram of a first shift register circuit provided in an embodiment of the present application;

[0014] Figure 4 A schematic diagram of a second shift register circuit provided in an embodiment of the present application;

[0015] Figure 5 A working timing diagram of a display panel provided in an embodiment of the present application;

[0016] Figure 6 A working timing diagram of another display panel provided in an embodiment of the present application;

[0017] Figure 7 A working timing diagram of another display panel provided in an embodiment of the present application;

[0018] Figure 8A working timing diagram of another display panel provided in an embodiment of the present application;

[0019] Fig. 9 A working timing diagram of another display panel provided in an embodiment of the present application;

[0020] Fig.10 A working timing diagram of another display panel provided in an embodiment of the present application;

[0021] Fig.11 A working timing diagram of another display panel provided in an embodiment of the present application;

[0022] Fig.12 A working timing diagram of another display panel provided in an embodiment of the present application;

[0023] Fig.13 A working timing diagram of another display panel provided in an embodiment of the present application;

[0024] Fig.14 A working timing diagram of another display panel provided in an embodiment of the present application;

[0025] Fig.15 A working timing diagram of another display panel provided in an embodiment of the present application;

[0026] Fig.16 A schematic diagram of a display device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0027] In order to better understand the technical solution of the present application, the embodiments of the present application are described in detail below with reference to the accompanying drawings.

[0028] It should be clear that the described embodiments are only part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in the field without creative work are within the scope of protection of the present application.

[0029] The terms used in the embodiments of the present application are only for the purpose of describing specific embodiments, and are not intended to limit the present application. The singular forms "a", "an", "the" and "the" used in the embodiments of the present application and the appended claims are also intended to include plural forms, unless the context clearly indicates other meanings.

[0030] It should be understood that the term "and / or" used in this article is only a description of the association relationship of associated objects, indicating that there can be three relationships. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. In addition, the character " / " in this article generally indicates that the associated objects before and after are in an "or" relationship.

[0031] In the description of this specification, it is necessary to understand that the words such as "substantially", "approximately", "approximately", "about", "roughly", "substantially" and the like described in the claims and embodiments of the present application refer to what can be generally recognized within a reasonable process operation range or tolerance range, rather than an exact value.

[0032] It should be understood that although the terms first, second, etc. may be used to describe the light control module, level signal, start signal, clock signal, etc. in the embodiments of the present application, these should not be limited to these terms. These terms are only used to distinguish the light control module, level signal, start signal, clock signal, etc. from each other. For example, without departing from the scope of the embodiments of the present application, the first light control module may also be referred to as the second light control module, and similarly, the second light control module may also be referred to as the first light control module. The applicant of this case has provided a solution to the problems existing in the prior art through careful and in-depth research.

[0033] Figure 1 A schematic plan view of a display panel provided in an embodiment of the present application, Figure 2 A schematic diagram of a pixel circuit provided in an embodiment of the present application is shown in FIG. Figure 3 A schematic diagram of a first shift register circuit provided in an embodiment of the present application, Figure 4 A schematic diagram of a second shift register circuit provided in an embodiment of the present application, Figure 5 A working timing diagram of a display panel provided in an embodiment of the present application.

[0034] The present application embodiment provides a display panel A10, such as Figure 1 As shown, the display panel A10 includes a pixel circuit 100. Figure 2 As shown, the pixel circuit 100 includes a driving transistor Md, and the pixel circuit 100 is electrically connected to the light emitting device 200. The driving transistor Md in the pixel circuit 100 generates a light emitting driving current for driving the light emitting device 200 to emit light.

[0035] The driving transistor Md in the pixel circuit 100 is prone to leakage in a working cycle, resulting in inaccurate light-emitting driving current output to the light-emitting device 200. Optionally, a working cycle of the pixel circuit 100 includes a refresh frame and multiple maintenance frames, each of which includes a light-emitting stage, and the light-emitting device 200 emits light in the light-emitting stage. The gate of the driving transistor Md receives the data voltage Vdata input by the data writing module 10 in the refresh frame, and the magnitude of the data voltage Vdata can control the magnitude of the light-emitting driving current generated by the driving transistor Md, thereby controlling the light-emitting brightness of the light-emitting device 200. However, in the maintenance frame, the gate of the driving transistor Md maintains the potential and no longer receives the data voltage Vdata input by the data writing module 10, and the light-emitting driving current generated by the driving transistor Md is also at a similar level to the light-emitting driving current generated in the refresh frame. However, since the source and drain of the driving transistor Md are always in a potential difference, the gate potential of the driving transistor Md is unstable, which usually causes the light-emitting driving current generated by the driving transistor Md to show a gradual downward trend between adjacent frames, resulting in a decrease in the light-emitting brightness of the light-emitting device 200.

[0036] The luminous brightness of the luminous device 200 can be compensated by adjusting the luminous duration of the luminous device 200. In the related art, after the pixel circuit receives the effective luminous signal output by the shift register circuit, the pixel circuit enters the luminous phase, and the driving transistor in the luminous phase generates current, and the luminous device emits light. It can be understood that the effective pulse duration of the luminous signal output by the shift register circuit is equal to the luminous time of the luminous device. Therefore, when the luminous duration of the luminous device needs to be adjusted, it is completed by adjusting the pulse duration of the effective luminous signal output by the shift register circuit. However, since the working mode of the shift register is cascaded, the multiple pixel circuits in the display panel are turned on row by row under the control of the shift register circuit. The shift register circuit in the cascade operation will receive the clock signal and work according to the cycle of the clock signal, ensuring the orderliness of the operation of the multi-row pixel circuit. In the shift register, when each clock cycle arrives, the data in the shift register circuit will move one bit to the next shift register circuit. In this way, each rising edge or falling edge of the clock signal becomes the precise time point of data shifting, and the pulse duration received and generated by the shift register circuit is in units of clock cycles. Therefore, the duration of the effective light-emitting signal output by the shift register circuit can only be adjusted in units of clock cycles, so that the adjustment of the light-emitting duration of the light-emitting device in the maintenance frame can only be adjusted in units of clock cycles. However, since the adjustment of the duration of the effective light-emitting signal in the related art is completed according to the multiples of the clock cycle, the adjustment is prone to stepping, and there is a situation where the light-emitting time of at least 2 times the clock cycle must be adjusted each time the effective light-emitting signal is adjusted. When the light-emitting duration of the pixel circuit itself in the light-emitting stage in the maintenance frame is short, such an integer multiple adjustment range accounts for a large proportion of its own brightness, which is easy to cause poor brightness compensation and even produce a flickering effect on the visual effect. Therefore, how to flexibly adjust the light-emitting duration more accurately according to actual use needs, avoid the adjusted light-emitting time can only be an integer multiple of the clock cycle, and realize that the adjusted light-emitting time can be a non-integer multiple of the clock cycle, is of great significance to improving the light-emitting compensation effect.

[0037] In order to flexibly adjust the light-emitting duration of the light-emitting device 200, continue to refer to Figure 2 As shown, the present application proposes to set a first light control module 20 and a second light control module 30 in the pixel circuit 100. The control terminal 20A of the first light control module 20 is electrically connected to the first signal line SL1, and the control terminal 301 of the second light control module 30 is electrically connected to the second signal line SL2.

[0038] The first signal line SL1 can output a first level signal V1 and a second level signal V2. The control terminal 20A of the first light-emitting control module 20 is turned on when receiving the first level signal V1, and is turned off when receiving the second level signal V2. In the pixel circuit 100, the first end of the first light-emitting control module 20 is electrically connected to the first power supply voltage PVDD, and the second end is electrically connected to the driving transistor Md. When the control terminal 201 of the first light-emitting control module 20 receives the first level signal V1, the first light-emitting control module 20 is turned on, and the first light-emitting control module 20 transmits the first power supply voltage PVDD to the first electrode of the driving transistor Md. The driving transistor Md generates a light-emitting driving current under the drive of the first power supply voltage PVDD, and the generated light-emitting driving current is output by the second electrode of the driving transistor Md.

[0039] The second signal line SL2 can output a third level signal V3 and a fourth level signal V4. The control terminal 301 of the second light emitting control module 30 is turned on when receiving the third level signal V3, and is turned off when receiving the fourth level signal V4. The first end of the second light emitting control module 30 is electrically connected to the second electrode of the driving transistor Md, and the second end is electrically connected to the first electrode of the light emitting device 200. When the control terminal 30A of the second light emitting control module 30 receives the third level signal V3, the second light emitting control module 30 is turned on, and the received light emitting driving current is transmitted to the first electrode of the light emitting device 200, and the light emitting device 200 emits light.

[0040] In summary, the light-emitting device 200 can receive the light-emitting driving current, which needs to be completed by the first light-emitting control module 20 and the second light-emitting control module 30. The time when the first light-emitting control module 20 receives the first level signal V1 and is turned on is the time when the driving transistor Md generates the light-emitting driving current, and the light-emitting driving current generated by the driving transistor Md needs to be output from the second light-emitting control module 30 to the light-emitting device 200. When the second light-emitting control module 30 is turned on and can receive the light-emitting driving current, the light-emitting device 200 emits light. Then, the first light-emitting control module 20 and the second light-emitting control module 30 are both electrically connected to the driving transistor Md, and when both are turned on, the driving transistor Md is controlled to output the light-emitting driving current to the light-emitting device 200, and the time when the first light-emitting control module 20 and the second light-emitting control module 30 are both turned on is the time when the light-emitting device 200 emits light.

[0041] As can be seen from the above content, when both the first light-emitting control module 20 and the second light-emitting control module 30 are turned on, the first signal line SL1 transmits the first level signal V1 and the second signal line SL2 transmits the third level signal V3, and the pulse duration of the first level signal V1 and the pulse duration of the third level signal V3 are both in units of clock cycles, so if the light-emitting duration of the light-emitting device 200 is controlled by the first level signal V1 or the third level signal V3 alone, the light-emitting time of the light-emitting device 200 is also in units of clock cycles H. However, the present application uses the overlapping time of the first level signal V1 and the third level signal V3, and the time delay between the first level signal V1 and the third level signal V3 can be used to achieve the effect that the overlapping time between the first level signal V1 and the second level signal V3 is a non-integer multiple of the clock cycle, so as to adjust the light-emitting duration of the light-emitting device 200 to a non-integer multiple of the clock cycle, and achieve a more accurate compensation effect on the light-emitting brightness of the light-emitting device 200.

[0042] In the pixel circuit in the related art, the control end of the first light-emitting control module and the control end of the second light-emitting control module are usually electrically connected to the same signal line, and the same signal line is correspondingly electrically connected to the output end of a shift register circuit. When the shift register circuit outputs a valid pulse signal, the first light-emitting control module and the second light-emitting control module are turned on at the same time, and then the light-emitting device emits light.

[0043] Combination Figure 3-Figure 5 As shown, in the present technical solution, in order to realize the time-sharing start-up of the first light-emitting control module 20 and the second light-emitting control module 30 , the display panel A10 is configured to further include a first shift register 300 and a second shift register 400 .

[0044] The first shift register 300 includes M-stage cascaded first shift register circuits 301. Optionally, the M-stage cascaded first shift register circuits 301 are electrically connected to M rows of pixel circuits 100, respectively. The first output terminal 301A of the first shift register circuit 301 is electrically connected to the first signal line SL1, so that the first shift register circuit 301 controls the opening or closing of the first light emitting control module 20. The first shift register circuit 301 receives a first start signal STV1, a first clock signal CK1, and a second clock signal CK2. After the first shift register circuit 301 receives the first start signal STV1, the first shift register circuit 301 starts working. The clock signal received by the first shift register circuit 301 includes a first clock signal CK1 and a second clock signal CK2. Under the joint control of the first start signal STV1, the first clock signal CK1, and the second clock signal CK2, the moment and pulse duration at which the first shift register circuit 301 outputs the first level signal V1 and the second level signal V2 are adjusted.

[0045] The second shift register 400 includes M-stage cascaded second shift register circuits 401. Optionally, the M-stage cascaded second shift register circuits 401 are electrically connected to M rows of pixel circuits 100. The second output terminal 401A of the second shift register circuit 401 is electrically connected to the second signal line SL2, so that the second shift register circuit 401 controls the opening or closing of the second light emitting control module 20. Figure 2 As shown, the second shift register circuit 401 receives the second start signal STV2, the third clock signal CK3, and the fourth clock signal CK4. After the second shift register circuit 401 receives the second start signal STV2, the second shift register circuit 401 starts working. Under the joint control of the second start signal STV2, the third clock signal CK3, and the fourth clock signal CK4, the second shift register circuit 401 adjusts the moment and pulse duration of outputting the third level signal V3 and the fourth level signal V4.

[0046] like Figure 5 As shown, the first level signal V1 and the second level signal V3 coincide when both the first light control module 20 and the second light control module 30 are turned on. At this time, the pixel circuit 100 is in the light emitting stage E1, and the light emitting device 200 can receive the light emitting driving current to emit light. It should be noted that Figure 5 The shaded parts in the last row of show the durations of the pixel circuit 100 being in the light emitting phase E1 and the non-light emitting phase E2 in one working cycle.

[0047] In the embodiment of the present application, the signals output by the first shift register circuit 301 and the second shift register circuit 401 are set to respectively control the first light-emitting control module 20 and the second light-emitting control module 30 in the pixel circuit 100, so that the first light-emitting control module 20 and the second light-emitting control module have the conditions for time-sharing opening, which is beneficial to adjust the start time and end time of the light-emitting drive current generated by the pixel circuit 100 to the light-emitting device 200 through the on-off coordination of the first light-emitting control module 20 and the second light-emitting control module 30, thereby achieving more flexible adjustment of the light-emitting time of the light-emitting device 200, and adjusting the light-emitting time to a non-integer multiple or integer multiple of the clock cycle, and more accurately compensating the light-emitting brightness of the light-emitting device 200.

[0048] In one embodiment of the present application, continue to refer to Figure 3-Figure 5As shown, the first start signal STV1 and the second start signal STV2 proposed in the present application are supplied by different signal lines. The first start signal STV1 and the second start signal STV2 are signals for starting the cascade connection of the first shift register 300 and the second shift register 400, respectively. When the first start signal STV1 reaches the first shift register 300, the multiple first shift register circuits 301 in the first shift register 300 receive the first start signal STV1 in sequence and start working, and the first shift register circuit 301 works to generate the first level signal V1 or the second level signal V2 to control the on and off of the first light-emitting control module 20. When the second start signal STV2 reaches the second shift register 400, the multiple second shift register circuits 401 in the second shift register 400 receive the second start signal STV2 in sequence and start working, and the second shift register circuit 401 works to generate the third level signal V3 or the fourth level signal V4 to control the on and off of the second light-emitting control module 30.

[0049] In the embodiment of the present application, the first start signal STV1 and the second start signal STV2 are respectively supplied by different signal lines, which is beneficial to make the starting working states of the first shift register circuit 301 and the second shift register circuit 401 controlled by different signal lines, and is beneficial to avoid confusion in the cascade state of the first shift register 300 and the second shift register 400 when transmitting the first start signal STV1 or the second start signal STV2, and is beneficial to avoid the first shift register circuit 301 and the second shift register circuit 401 starting to output or end outputting the first level signal V1 and the third level signal V3 at the same time, thereby losing the function of controlling the time-sharing start of the first light-emitting control module 20 and the second light-emitting control module 30. Therefore, using two signal lines to respectively control the working states of the first shift register circuit 301 and the second shift register circuit 401 is beneficial to flexibly control the first shift register circuit 301 and the second shift register circuit 401, thereby providing conditions for flexibly adjusting the effective light-emitting time of the light-emitting device 200.

[0050] It should be supplemented that the pixel circuit 100 proposed in the embodiment of the present application also includes a first reset module 40, a threshold compensation module 50, and a second reset module 60. The first reset module 40 is used to transmit the first reset voltage Vref1 to the gate of the driving transistor Md to reset the gate of the driving transistor Md, thereby ensuring that the driving transistor Md generates an accurate light-emitting driving current in the next working cycle. The threshold compensation module 50 is used to compensate the threshold voltage of the driving transistor Md to the gate of the driving transistor Md. The second reset module 60 is used to transmit the second reset voltage Vref2 to the first pole of the light-emitting device 200 to reset the light-emitting device 200, thereby ensuring the accuracy of the light-emitting brightness of the light-emitting device 200 in the next working cycle. The pixel circuit 100 also receives the first scan signal S1 and the second scan signal S2. The signals transmitted by the first scan signal S1 and the second scan signal S2 are both used to control the corresponding modules to turn on or off.

[0051] In one embodiment of the present application, continue to combine Figure 3-Figure 5 As shown, the first clock signal CK1, the second clock signal CK2, the third clock signal CK3, and the fourth clock signal CK4 are supplied by different signal lines. It can be seen from the above embodiment that the working state of the first shift register circuit 301 is jointly controlled by the first start signal STV1, the first clock signal CK1, and the second clock signal CK2, and the working state of the second shift register circuit 401 is jointly controlled by the second start signal STV2, the third clock signal CK3, and the fourth clock signal CK4. The first clock signal CK1, the second clock signal CK2, the third clock signal CK3, and the fourth clock signal CK4 are supplied by different signal lines, which is conducive to controlling the working states of the first shift register circuit 301 and the second shift register circuit 401 respectively, so as to more accurately and conveniently control the time when the first level signal V1 and the third level signal V3 are output, so as to prepare for more accurate adjustment of the light-emitting duration.

[0052] It should be noted that, optionally, the circuit structure of the first shift register circuit 301 is the same as the circuit structure of the second shift register circuit 401. The first shift register circuit 301 and the second shift register circuit 401 proposed in the embodiment of the present application both include a plurality of transistors, and optionally, the transistors are all P-type transistors for example. When the transistor is a P-type transistor, the gate of the transistor is turned on when it receives a low-level signal and is turned off when it receives a high-level signal. In the embodiment of the present application, corresponding to the shift register circuit including the P-type transistor, the moment when the falling edge of the first clock signal CK1 and the second clock signal CK2 arrives is the effective time point for the working state switching of the first shift register circuit 301. The moment when the falling edge of the third clock signal CK3 and the fourth clock signal CK4 arrives is the effective time point for the working state switching of the second shift register circuit 401. Since the first clock signal CK1 and the second clock signal CK2 simultaneously control the working state of the first shift register circuit 301, the clock cycle H proposed in the embodiment of the present application is the time between the falling edge of the first clock signal CK1 and the falling edge of the second clock signal CK2. Furthermore, the third clock signal CK3 and the fourth clock signal CK4 simultaneously control the working state of the second shift register circuit 401, and the clock cycle H proposed in the embodiment of the present application is also the time between the falling edge of the third clock signal CK2 and the falling edge of the fourth clock signal CK4. Optionally, the clock cycle H of the first shift register circuit 301 is equal to the clock cycle H of the second shift register circuit 401, which is conducive to unifying the working control of the first shift register circuit 301 and the second shift register circuit 401 and avoiding signal disorder.

[0053] Optionally, the effective level signal of the first start signal STV1 is a low level signal. Figure 5 As shown in , when the first start signal SVT1 transmits a valid level signal, the falling edge of the first start signal STV1 coincides with the falling edge of the second clock signal CK2, and the corresponding first level signal V1 is not output immediately, but is output when the falling edge of the first start signal STV1 arrives and turns into a valid pulse signal, waiting for the falling edge of the next clock signal to arrive. Here, after the falling edge of the first start signal STV1, the falling edge of the first clock signal CK1 arrives first, and at this time, the first level signal V1 also starts to be output. Obviously, the time between the falling edge of the second clock signal CK2 and the falling edge of the first clock signal CK1 is a clock cycle H, and such an output delay is conducive to ensuring that the first start signal STV1 stably moves bit by bit in the register, rather than reacting instantly. In this way, the stability and reliability of data transmission can be guaranteed, thereby ensuring the stable operation of the shift register circuit and the accuracy of signal transmission.

[0054] Similarly, when the valid pulse signal of the first start signal STV1 ends, that is, when the rising edge of the first start signal STV1 arrives, the first level signal V1 does not stop outputting immediately, but instead turns into a non-valid pulse signal after the rising edge of the first start signal STV1 arrives, and waits for the falling edge of the next clock signal to arrive before being outputted.

[0055] Optionally, the effective level signal of the second start signal STV2 is also a low level signal. Figure 5 As shown, setting the effective level signal of the first start signal STV1 and the effective level signal of the second start signal STV2 to be low level signals is conducive to more conveniently controlling the first shift register circuit 301 and the second shift register circuit 401, reducing the difficulty of circuit preparation and control. Figure 3 As shown in , when the second start signal SVT2 transmits a valid level signal, the falling edge of the second start signal STV2 coincides with the falling edge of the third clock signal CK3, and the corresponding third level signal V3 is not output immediately, but is output after the falling edge of the second start signal STV2 arrives and turns into a valid pulse signal, waiting for the falling edge of the next clock signal to arrive. Here, after the falling edge of the second start signal STV2, the falling edge of the fourth clock signal CK4 arrives first, and at this time, the third level signal V3 also starts to be output. Similarly, when the valid pulse signal of the second start signal STV2 ends, that is, when the rising edge of the second start signal STV2 arrives, the third level signal V3 does not stop outputting immediately, but is output after the rising edge of the second start signal STV2 arrives and turns into a non-valid pulse signal, waiting for the falling edge of the next clock signal to arrive.

[0056] Furthermore, the working process of the shift register circuit proposed in the embodiment of the present application is introduced below. Optionally, the first level signal V1 is a low level signal, the third level signal V3 is a low level signal, the second level signal V2 is a high level signal, and the fourth level signal V4 is a high level signal.

[0057] Continue to refer Figure 3 As shown, the first shift register circuit 301 further includes a first output unit 310, wherein a first terminal of the first output unit 310 receives a first level signal V1, a second terminal is electrically connected to a first output terminal 301A, and is used to output the first level signal V1. Optionally, the first output unit 310 includes a first transistor M1, a first electrode of the first transistor M1 receives the first level signal V1, and a second electrode is electrically connected to the first output terminal 301A.

[0058] The first shift register circuit 301 further includes a second output unit 320, wherein a first terminal of the second output unit 320 receives a second level signal V2, a second terminal is electrically connected to the first output terminal 301A, and is used to output the second level signal V2. Optionally, the second output unit 320 includes a second transistor M2, a first electrode of the second transistor M2 receives the second level signal V2, and a second electrode is electrically connected to the first output terminal 301A.

[0059] The first shift register circuit 310 further includes a first control unit 330, which receives a first start signal STV1, a first clock signal CK1, and a second clock signal CK2, and is used to control the first output unit 310 or the second output unit 320 to start. Optionally, the first control unit 330 includes a third transistor M3 to an eleventh transistor M11, and the electrical connection method of the third transistor M3 to the eleventh transistor M11 is as follows: Figure 3 shown.

[0060] like Figure 5 As shown, in one working cycle of the first shift register circuit 301, there are a first phase T1, a second phase T2, a third phase T3 and a fourth phase T4.

[0061] In the first stage T1: the first start signal STV1 received by the first control unit 330 is a valid pulse signal, the first clock signal CK1 is a high level signal, and the second clock signal CK2 is a low level signal. Then the fourth transistor M4 and the tenth transistor M10 are turned on, the second node N2 is pulled down, and the third node N3 is raised, then the second transistor M2 is turned on and the first transistor M1 is turned off. At this time, the first control unit 330 controls the first output unit 310 to be turned off, controls the second output unit 320 to be turned on, and the second output unit 320 transmits the second level signal V2 to the first output terminal 301A, so that the first light emitting control module 20 in the pixel circuit 100 is turned off.

[0062] In the second stage T2: the first start signal STV1 received by the first control unit 330 is a valid pulse signal, the first clock signal CK1 is a low level signal, and the second clock signal CK2 is a high level signal. Then the first start signal STV1 writes the third node N3 low, the third transistor M3 is turned on, the fourth transistor M4 is turned off, and the second node N2 is written high by the second level signal V2, then the second transistor M2 is turned off, and the first transistor M1 is turned on. At this time, the first control unit 330 controls the first output unit 310 to turn on, controls the second output unit 320 to turn off, and the first output unit 310 transmits the first level signal V1 to the first output terminal 301A, so that the first light-emitting control module 20 in the pixel circuit 100 is turned on. In addition, in the second stage T2, it also includes the situation that when the first start signal STV1 received by the first control unit 330 is a valid signal, the first clock signal CK1 is a high level signal, and the second clock signal CK2 is a low level signal. At this time, due to the effect of the first capacitor C1, the third node N3 remains in a low level state. At this time, the third transistor M3 is continuously turned on, and the second level signal V2 continuously writes the second node N2 high, so that the second transistor M2 is turned off and the first transistor M1 is turned on. At this time, the first control unit 330 continuously controls the first output unit 310 to be turned on and controls the second output unit 320 to be continuously turned off. The first output unit 310 transmits the first level signal V1 to the first output terminal 301A, so that the first light emission control module 20 in the pixel circuit 100 is continuously turned on.

[0063] In the third stage T3: the first start signal STV1 received by the first control unit 330 turns into an ineffective signal, the first clock signal CK1 is a low-level signal, and the second clock signal CK2 is a high-level signal. Then the sixth transistor M6, the eleventh transistor M11, and the twelfth transistor M12 are turned on, the first node N1 is set to a low-level state, and the ineffective signal transmitted by the first start signal STV1 puts the third node N3 in a high-level state, and the first transistor M1 is turned off; the second clock signal CK2 transmits a high-level signal, then the fourth transistor M4 and the tenth transistor M10 are turned off, the second node N2 maintains a high-level state, and the second transistor M2 is also turned off. Then the potential of the control end of the first light-emitting control module 20 is not updated, the level of the first output end 301A also maintains the first-level signal V1 state, and the first light-emitting control module 20 is continuously turned on.

[0064] In the fourth stage T4: the first start signal STV1 received by the first control unit 330 continues to output a non-valid signal, the first clock signal CK1 turns to a high level signal, and the second clock signal CK2 turns to a low level signal. Then the fourth transistor M4 and the tenth transistor M10 are turned on, the second node N2 is pulled down, and the third node N3 is raised, then the first transistor M1 is turned off and the second transistor M2 is turned on. At this time, the first control unit 330 controls the first output unit 310 to turn off and the second output unit 320 to turn on, and the second output unit 320 transmits the second level signal V2 to the first output terminal 301A, so that the first light-emitting control module 20 in the pixel circuit 100 is turned off. In addition, in the fourth stage T4, it also includes the situation that when the first start signal STV1 received by the first control unit 330 is a non-valid signal, the first clock signal CK1 is a low level signal, and the second clock signal CK2 is a high level signal. At this time, the first start signal STV1 writes the third node N3 high, and the turned-on sixth transistor M6 transmits the first level signal V1 to write the first node N1 low; the fourth transistor M4 is turned off, and the second node N2 maintains the low level state of the previous stage, then the second transistor M2 is continuously turned on, and the first transistor M1 is continuously turned off. At this time, the first control unit 330 continuously controls the first light control module 20 to be turned off.

[0065] like Figure 4 As shown, the second shift register circuit 401 further includes a third output unit 410, a first terminal of the third output unit 410 receives the third level signal V3, a second terminal is electrically connected to the second output terminal 401A, and is used to output the third level signal V3. Optionally, the third output unit 410 includes a transistor No. 1 X1, a first electrode of the transistor No. 1 X1 receives the third level signal V3, and a second electrode is electrically connected to the second output terminal 401A.

[0066] The second shift register circuit 401 further includes a fourth output unit 420, wherein a first terminal of the fourth output unit 420 receives a fourth level signal V4, a second terminal is electrically connected to the second output terminal 401A, and is used to output the fourth level signal V4. Optionally, the fourth output unit 420 includes a transistor No. 2 X2, wherein a first electrode of the transistor No. 2 X2 receives the fourth level signal V4, and a second electrode is electrically connected to the second output terminal 401A.

[0067] The second shift register circuit 401 further includes a second control unit 430, which receives a second start signal STV2, a third clock signal CK3, and a fourth clock signal CK4, and is used to control the third output unit 410 or the fourth output unit 420 to be turned on. Optionally, the second control unit 430 includes transistors No. 3 X3 to No. 11 X11, and the electrical connection method of transistors No. 3 X3 to No. 1 X11 is as follows: Figure 5 shown.

[0068] Combination Figure 5 As shown, in one working cycle of the second shift register circuit 401, a fifth stage T5, a sixth stage T6, a seventh stage T7 and an eighth stage T8 are included. Optionally, the circuit structures of the first shift register circuit 301 and the second shift register circuit 401 are the same. Optionally, the transistors included in the first shift register circuit 301 and the second shift register circuit 401 are of the same type.

[0069] In the fifth stage T5: the second start signal STV2 received by the second control unit 430 is a valid pulse signal, the third clock signal CK3 is a high level signal, and the fourth clock signal CK4 is a low level signal. Then the transistor No. 4 X4 and the transistor No. 10 X10 are turned on, the fifth node N5 is pulled low, and the sixth node N6 is raised, then the transistor No. 2 X2 is turned on and the transistor No. 1 X1 is turned off. At this time, the second control unit 430 controls the third output unit 410 to be turned off, controls the fourth output unit 420 to be turned on, and the third output unit 420 transmits the fourth level signal V4 to the second output terminal 401A, so that the second light emitting control module 30 in the pixel circuit 100 is turned off.

[0070] In the sixth stage T6: the second start signal STV2 received by the second control unit 430 is a valid pulse signal, the third clock signal CK3 is a low level signal, and the fourth clock signal CK4 is a high level signal. Then the second start signal STV2 writes the sixth node N6 low, the No. 3 transistor X3 is turned on, the No. 4 transistor X4 is turned off, and the fifth node N5 is written high by the fourth level signal V4, then the No. 2 transistor X2 is turned off, and the No. 1 transistor X1 is turned on. At this time, the second control unit 430 controls the third output unit 410 to turn on, controls the fourth output unit 420 to turn off, and the third output unit 410 transmits the third level signal V3 to the second output terminal 401A, so that the second light-emitting control module 30 in the pixel circuit 100 is turned on. In addition, in the sixth stage T6, it also includes the situation that when the second start signal STV2 received by the second control unit 430 is a valid pulse signal, the third clock signal CK3 is a high level signal, and the fourth clock signal CK4 is a low level signal. At this time, due to the effect of the capacitor C1, the sixth node N6 is kept in a low level state. At this time, transistor No. 3 X3 is continuously turned on, and the fourth level signal V4 continuously writes the fifth node N5 high, so that transistor No. 2 X2 is turned off and transistor No. 1 X1 is turned on. At this time, the second control unit 430 continuously controls the third output unit 410 to be turned on and controls the fourth output unit 420 to be continuously turned off, and the third output unit 410 transmits the third level signal V3 to the second output terminal 401A, so that the second light emitting control module 30 in the pixel circuit 100 is continuously turned on.

[0071] In the seventh stage T7: the second start signal STV2 received by the second control unit 430 turns into an ineffective signal, the third clock signal CK3 is a low-level signal, and the fourth clock signal CK4 is a high-level signal. Then the transistor No. 6 X6, the transistor No. 11 X11, and the transistor No. 12 X12 are turned on, the fourth node N4 is set to a low-level state, and the ineffective signal transmitted by the second start signal STV2 sets the sixth node N6 to a high-level state, then the transistor No. 1 X1 is turned off; the fourth clock signal CK4 transmits a high-level signal, then the transistor No. 4 X4 and the transistor No. 10 X10 are turned off, the fifth node N5 maintains a high-level state, and the transistor No. 2 X2 is also turned off. Then the potential of the control end of the second light-emitting control module 30 is not updated, the level of the second output end 401A also maintains the third-level signal V3 state, and the second light-emitting control module 30 is continuously turned on.

[0072] In the eighth stage T8: the second start signal STV2 received by the second control unit 430 continues to output a non-valid signal, the third clock signal CK3 turns to a high level signal, and the fourth clock signal CK4 turns to a low level signal. Then transistor No. 4 X4 and transistor No. 10 X10 are turned on, the fifth node N5 is pulled low, and the sixth node N6 is raised, then transistor No. 1 X1 is turned off and transistor No. 2 X2 is turned on. At this time, the second control unit 430 controls the third output unit 410 to turn off and the fourth output unit 420 to turn on, and the fourth output unit 420 transmits the fourth level signal V4 to the second output terminal 401A, so that the second light-emitting control module 30 in the pixel circuit 100 is turned off. In addition, in the eighth stage T8, it also includes the situation that when the second start signal STV2 received by the second control unit 430 is a non-valid signal, the third clock signal CK3 is a low level signal, and the fourth clock signal CK4 is a high level signal. At this time, the second start signal STV2 writes the sixth node N6 high, and the turned-on transistor No. 6 X6 transmits the third level signal V3 to write the fourth node N4 low; the transistor No. 4 X4 is turned off, and the fifth node N5 maintains the low level state of the previous stage, then the transistor No. 2 X2 is continuously turned on, and the transistor No. 1 X1 is continuously turned off. At this time, the second control unit 430 continuously controls the second light control module 30 to be turned off.

[0073] In one embodiment of the present application, continue to combine Figure 3-Figure 5As shown, the periods of the first clock signal CK1, the second clock signal CK2, the third clock signal CK3, and the fourth clock signal CK4 are all N1*H, where N1 is an integer greater than or equal to 1. In combination with the above content, it can be seen that if the periods of the first clock signal CK1, the second clock signal CK2, the third clock signal CK3, and the fourth clock signal CK4 are the same, then the clock period H of the first shift register circuit 301 and the second shift register circuit 401 are also the same, and the clock period H can be used to describe the time of the first shift register circuit 301 in a working state or to describe the time of the second shift register circuit 401 in a working state. In the embodiment of the present application, N1=2 is taken as an example for explanation.

[0074] Figure 6 A working timing diagram of another display panel provided in an embodiment of the present application.

[0075] like Figure 6 As shown, the pixel circuit 100 at least includes a first working cycle T ime1. Optionally, one working cycle T ime1 of the pixel circuit 100 includes at least one refresh frame T ime1A and at least one sustain frame T ime1B, and each of the refresh frame T ime1A and the sustain frame T ime1B includes at least one light-emitting stage E1. During the light-emitting stage E1, both the first light-emitting control module 20 and the second light-emitting control module 30 are turned on. In the non-light-emitting stage E2 in the refresh frame T ime1A and the sustain frame T ime1B, at most one of the first light-emitting control module 20 and the second light-emitting control module 30 is turned on. It can be seen that the time when the pixel circuit 100 is in the light-emitting stage E1 is determined by the time when the first light-emitting control module 20 and the second light-emitting control module 30 are turned on at the same time, that is, it is jointly determined by the signals output by the output terminals of the first shift register circuit 301 and the second shift register circuit 401. At this time, the time when the first level signal V1 and the third level signal V3 are output at the same time is the time when the pixel circuit 100 enters the light-emitting stage E1, when the first level signal V1 and the third level signal V3 are not output at the same time, it is the non-light-emitting stage E2 of the pixel circuit 100, and when the second level signal V2 and the fourth level signal V4 are output, the pixel circuit 100 is also in the non-light-emitting stage.

[0076] Figure 6It is shown that the luminous duration of the pixel circuit 100 is the same when it is in the refresh frame T ime1A and the maintenance frame T ime1B. Since the pixel circuit 100 will have leakage in the maintenance frame T ime1B, when the luminous duration of the maintenance frame T ime1B is still equal to the luminous duration of the refresh frame T ime1A, the luminous brightness will decrease. Therefore, the luminous duration of the maintenance frame T ime1B can be adjusted, for example, the luminous duration of the maintenance frame T ime1B can be extended to compensate the luminous brightness. Since there are many situations in which the luminous duration of the maintenance frame T ime1B is adjusted in actual use, the present application takes the adjustment of the luminous duration in the maintenance frame T ime1B as an example for explanation. The following embodiments will be described in detail. Figure 6 Of course, in some other embodiments, the light-emitting phase E1 duration in the refresh frame Time1A can be set or adjusted to a non-integer multiple of the clock cycle H using the light-adjusting method provided in the embodiment of the present application.

[0077] In the first working cycle T ime1 of the pixel circuit 100 of the embodiment of the present application, when in the refresh frame T ime1A of the pixel circuit 100, the rising edge and the falling edge of the first start signal STV1 are set to be N2*H earlier than the rising edge and the falling edge of the second start signal STV2, where N2 is an integer greater than or equal to 1. In combination with the working process of the shift register circuit mentioned above, it can be known that the corresponding rising edge and the falling edge of the first level signal V1 output by the first shift register circuit 301 are also N2*H earlier than the rising edge and the falling edge of the third level signal V3 output by the second shift register circuit 401.

[0078] The effective pulse duration for controlling both the first light control module 20 and the second light control module 30 to be turned on is N3*H, where N3 is an integer greater than or equal to 1. The effective pulse duration for controlling both the first light control module 20 and the second light control module 30 to be turned on is the duration for which the first level signal V1 and the third level signal V3 are output simultaneously.

[0079] The working timing of the first shift register circuit 301 and the second shift register circuit 401 in the refresh frame T ime1A is taken as the initial working timing. When the pixel circuit 100 enters the sustain frame T ime1B, the working timing is adjusted to adjust the duration of the simultaneous output of the first level signal V1 and the third level signal V3.

[0080] In the embodiment of the present application, the initial working timing of the first shift register circuit 301 and the second shift register circuit 401 is set to be N2*H ahead of the rising edge and falling edge of the first start signal STV1 and the rising edge and falling edge of the second start signal STV2, which is conducive to achieving that the rising edge and falling edge of the first level signal V1 are N2*H ahead of the rising edge and falling edge of the second level signal V2, thereby achieving that the first light control module 20 is turned on N2*H earlier than the second light control module 30. Prepare for the extended light duration in the frame T ime1B to be a non-integer multiple of the clock cycle H.

[0081] For example, in the embodiment of the present application, the effective pulse duration of the first start signal STV1 is 4*H, the ineffective pulse duration is 4*H, the effective pulse duration of the second start signal STV2 is also 4*H, the ineffective pulse duration is 4*H, then the pulse duration of the first level signal V1 and the pulse duration of the third level signal V3 are also 4*H, and the pulse duration of the second level signal V2 and the fourth level signal V4 are also 4*H, and N1=1 and N2=1 are used as an example for explanation. In combination with the above content, it can be known that in the first working cycle T ime1, the time difference between the first level signal V1 and the third level signal V3 is 1*H, and the duration of the simultaneous output of the first level signal V1 and the third level signal V3 is 3*H, then the duration of the light emitting stage E1 of the pixel circuit 100 in the refresh frame T ime1A is also 3*H, and N3=3 at this time. Then, the first level signal V1 and the third level signal V3 both have an effective pulse duration of 1*H that does not overlap. If it is necessary to extend the luminous duration to 3.5*H while maintaining the frame T ime1B, the relevant control signal of the first shift register circuit 301 or the relevant control signal of the second shift register circuit 302 can be directly shifted based on the first start signal STV1 and the second start signal STV2 set at this time, so that the time when the first level signal V1 and the third level signal V3 are output simultaneously is extended by a non-integer multiple of the clock cycle H.

[0082] In one embodiment of the present application, continue to refer to Figure 6 As shown, the falling edge and rising edge of the first clock signal CK1 are set N2*H earlier than the rising edge and falling edge of the third clock signal CK3. The falling edge and rising edge of the second clock signal CK2 are set N2*H earlier than the rising edge and falling edge of the fourth clock signal CK4.

[0083] Since the extension or shortening of the pulse duration of the first start signal STV1 and the second start signal STV2 can only be completed with an integer multiple of the clock cycle H, it is difficult to achieve the extended luminous duration to be a non-integer multiple of the clock cycle H by adjusting the first start signal STV1 and the second start signal STV2. In addition, the first start signal STV1 and the second start signal STV2 need to be combined with the clock signal when acting on the register circuit, so if the first start signal STV1 and the second start signal STV2 are adjusted separately, it may not be possible to accurately achieve non-integer luminous duration adjustment.

[0084] In the embodiment of the present application, in the related art, the falling edge and rising edge of the first clock signal are both N2*H ahead of the rising edge and falling edge of the third clock signal. The falling edge and rising edge of the second clock signal are both N2*H ahead of the rising edge and falling edge of the fourth clock signal, which is conducive to unifying the timing signal for controlling the first shift register circuit 301 and the timing signal for controlling the second shift register circuit 401, and combining the effect of the clock signal to jointly achieve the extension of the light-emitting duration of the non-integer multiple of the clock cycle H.

[0085] In one embodiment of the present application, in the first working cycle Time1, the first start signal STV1, the first clock signal CK1, and the second clock signal CK2 are simultaneously moved by X1*H, and the second start signal STV2, the third clock signal CK3, and the fourth clock signal CK4 are fixed. At this time, the first level signal V1 can also be moved for the same length of time as the first start signal STV1, the first clock signal CK1, and the second clock signal CK2, which is conducive to keeping the pulse length of the first level signal V1 unchanged, and only the time of its output is moved. In addition, the time when the third level signal V3 is output remains unchanged, and the time when the first level signal V1 and the third level signal V3 are simultaneously output also changes.

[0086] In addition, since the first start signal STV1, the first clock signal CK1, and the second clock signal CK2 move simultaneously, the restriction of the clock cycle H on the first start signal STV1 itself when it moves as much as possible to an integer multiple of the clock cycle H can be avoided, so that the first start signal STV1, the first clock signal CK1, and the second clock signal CK2 move simultaneously for a duration that is a non-integer multiple of the clock cycle H, thereby making the output time of the first level signal V1 move by a non-integer multiple of the clock cycle H compared to the output start time in the refresh frame Time1A. This is conducive to extending or shortening the duration of the simultaneous output of the first level signal V1 and the third level signal V3 by a non-integer multiple of the clock cycle H.

[0087] Or, similarly, in the first working cycle Time1, the second start signal STV2, the third clock signal CK3, and the fourth clock signal CK4 are simultaneously moved by X1*H, and the first start signal STV1, the first clock signal CK1, and the second clock signal CK2 are fixed. At this time, the third level signal V3 can also be moved for the same duration as the second start signal STV2, the third clock signal CK3, and the fourth clock signal CK4, which is conducive to keeping the pulse duration of the third level signal V3 unchanged, and only the output time thereof is moved, which is conducive to moving the output time of the third level signal V3 by a non-integer multiple of the clock cycle H compared to the time when the output starts in the refresh frame Time1A. The duration of the simultaneous output of the first level signal V1 and the third level signal V3 is extended or shortened by a non-integer multiple of the clock cycle H.

[0088] The above two methods can both realize that the effective pulse duration of both the first light-emitting control module 20 and the second light-emitting control module 30 is (N3±X1)*H; 0<X1≤N2. At this time, the first level signal V1 or the third level signal V3 also moves X1*H, and the duration of the simultaneous output of the first level signal V1 and the second level signal V2 changes from N3*H to (N3±X1)*H. For example, N2=1, then the duration of the movement of the first level signal V1 or the second level signal V2 is within the range of 0<X1≤1, including the duration of the movement of the first level signal V1 or the third level signal V3 being a non-integer multiple of the clock cycle. For example, when X1=0.5, the duration of the movement of the first level signal V1 or the third level signal V3 is 0.5*H, so that the light-emitting duration of the light-emitting device 200 is adjusted to (3±0.5)*H, thereby achieving the purpose of adjusting the light-emitting duration with a non-integer multiple of the clock cycle H, which is conducive to more flexible adjustment of the light-emitting duration, making the brightness compensation of the light-emitting device 200 more accurate, and improving the display effect of the display panel A10.

[0089] Figure 7 A working timing diagram of another display panel provided in an embodiment of the present application.

[0090] In one embodiment of the present application, Figure 6 , Figure 7 As shown, in the first working cycle Time1, the first start signal STV1, the first clock signal CK1, and the second clock signal CK2 set in the sustain frame Time1B are simultaneously right-shifted by X1*H. The second start signal STV2, the third clock signal CK3, and the fourth clock signal CK4 are all fixed. At this time, compared to Figure 6 At the moment when the first level signal V1 is output, Figure 7The first level signal V1 described in the figure is right-shifted by X1*H, and the duration of the simultaneous output of the first level signal V1 and the third level signal V3 is extended by X1*H, so that the effective pulse duration of both the first light-emitting control module 20 and the second light-emitting control module 30 is turned on is (N3+X1)*H, which is conducive to achieving non-integer adjustment of the light-emitting duration, improving the light-emitting brightness of the light-emitting device 200 while maintaining the frame Time1, and effectively improving the problem of decreased light-emitting brightness caused by leakage current of the pixel circuit 100.

[0091] For example, Figure 7 As shown, X1=0.5 is set. Since the first start signal STV1, the first clock signal CK1, and the second clock signal CK2 are simultaneously shifted right by 0.5*H, the first level signal V1 is also shifted right by 0.5*H, and the duration for which the first level signal V1 and the third level signal V3 are simultaneously output is extended to 3.5*H.

[0092] Figure 8 A working timing diagram of another display panel provided in an embodiment of the present application.

[0093] In one embodiment of the present application, Figure 6 , Figure 8 As shown, in the first working cycle Time1, the second start signal STV2, the third clock signal CK3, and the fourth clock signal CK4 are set to shift left by X1*H at the same time. The first start signal STV1, the third clock signal CK3, and the fourth clock signal CK4 are all fixed. At this time, compared with Figure 6 At the moment when the third level signal V3 is output, Figure 8 The third level signal V3 described in the embodiment is shifted to the left by X1*H, and the duration of the simultaneous output of the first level signal V1 and the third level signal V3 can also be extended by X1*H, so that the effective pulse duration of both the first light-emitting control module and the second light-emitting control module being turned on is (N3+X1)*H. This is conducive to realizing non-integer adjustment of the light-emitting duration and more accurately adjusting the light-emitting duration of the light-emitting device 200.

[0094] For example, Figure 8 As shown, X1=0.5 is set. Since the second start signal STV2, the third clock signal CK3, and the fourth clock signal CK4 are simultaneously shifted left by 0.5*H, the third level signal V3 is also shifted left by 0.5*H, and the duration of simultaneous output of the first level signal V1 and the third level signal V3 is extended to 3.5*H.

[0095] Fig. 9 A working timing diagram of another display panel provided in an embodiment of the present application.

[0096] In one embodiment of the present application, in combination with FIG. Fig. 9As shown, in the first working cycle T ime1, the effective pulse durations of the first start signal STV1 and the second start signal STV2 are both extended by X2*H, where X2 is an integer greater than or equal to 1. As can be seen from the above content, the effective pulse duration of the first start signal STV1 is the same as the duration of the first level signal V1 transmitted by the first signal line SL1, and the effective pulse duration of the second start signal STV2 is the same as the duration of the third level signal V3 transmitted by the second signal line SL2. Then, when only the effective pulse duration of the first start signal STV is extended by X2*H, the output duration of the first level signal V1 is also extended by X2*H, and when only the effective pulse duration of the second start signal STV is extended by X2*H, the output duration of the third level signal V3 is also extended by X2*H. Correspondingly, the duration of the simultaneous output of the first level signal V1 and the third level signal V3 is also extended by X2*H. X2 is an integer, so it is helpful to realize the situation where the light-emitting device 100 needs to compensate for a longer light-emitting duration in maintaining the frame T ime1B. For example, X2=1, the duration of simultaneous output of the first level signal V1 and the third level signal V3 is extended to (3+1)*H.

[0097] Further, the first start signal STV1, the first clock signal CK1, and the second clock signal CK2 are simultaneously moved by X1*H, and the second start signal STV2, the third clock signal CK3, and the fourth clock signal CK4 are fixed. Alternatively, the second start signal STV2, the third clock signal CK3, and the fourth clock signal CK4 are simultaneously moved by X1*H, and the first start signal STV1, the first clock signal CK1, and the second clock signal CK2 are fixed. Then, the duration of the simultaneous output of the first level signal V1 and the third level signal V3 can be extended to (N3+X2±X1)*H, so that the effective pulse duration for controlling the first light-emitting control module 20 and the second light-emitting control module 30 to be turned on is (N3+X2±X1)*H.

[0098] For example, refer to Fig. 9 As shown, when X2=1 and X1=0.5 are set, the first start signal STV1, the first clock signal CK1, and the second clock signal CK2 are simultaneously right-shifted by 0.5*H, and the second start signal STV2, the third clock signal CK3, and the fourth clock signal CK4 are fixed. The effective pulse duration of both the first light-emitting control module 20 and the second light-emitting control module 30 can be extended to (3+1+0.5)*H, and the light-emitting duration can be extended by 1.5*H. This solution is suitable for use when greater light-emitting compensation is required, and the light-emitting duration can be accurately adjusted on the basis of greater light-emitting compensation, which is conducive to improving the applicability of this solution and improving the compensation effect on the display effect of the display panel A10.

[0099] Fig.10 A working timing diagram of another display panel provided in an embodiment of the present application.

[0100] In one embodiment of the present application, Figure 6 , Fig.10 As shown, in the first working cycle T ime1, the first start signal STV1, the first clock signal CK1, and the second clock signal CK2 are simultaneously shifted left by X1*H, while the second start signal STV2, the third clock signal CK3, and the fourth clock signal CK4 are all fixed. Figure 6 At the moment when the first level signal V1 is output, Fig.10 The first level signal V1 described in the embodiment is shifted left by X1*H, and the duration of simultaneous output of the first level signal V1 and the third level signal V3 is shortened by X1*H, thereby making the effective pulse duration of both the first light-emitting control module and the second light-emitting control module turned on (N3-X1)*H, which is conducive to realizing non-integer adjustment of the light-emitting duration, and is conducive to making the present scheme applicable to the situation where it is necessary to reduce the light-emitting brightness of the light-emitting device 200 while maintaining the frame T ime1, and flexibly adjusting the light-emitting brightness of the display panel 100. For example, when encountering an abnormal display in the display panel A10, the light-emitting brightness of the display panel A10 can be flexibly reduced or increased, which is conducive to improving the applicability of the present scheme.

[0101] For example, Fig.10 As shown, X1=0.5 is set. Since the first start signal STV1, the first clock signal CK1, and the second clock signal CK2 are simultaneously shifted left by 0.5*H, the first level signal V1 is also shifted left by 0.5*H, and the duration for which the first level signal V1 and the third level signal V3 are simultaneously output is shortened to 2.5*H.

[0102] Fig.11 A working timing diagram of another display panel provided in an embodiment of the present application.

[0103] In one embodiment of the present application, Figure 6 ,like Fig.11 As shown, in the first working cycle T ime1, the second start signal STV2, the third clock signal CK3, and the fourth clock signal CK4 are simultaneously right-shifted by X1*H, while the first start signal STV1, the third clock signal CK3, and the fourth clock signal CK4 are all fixed. Figure 5 At the moment when the third level signal V3 is output, Fig.11 The third level signal V3 is right shifted by X1*H, and the duration of simultaneous output of the first level signal V1 and the third level signal V3 is also shortened by X1*H, and the effective pulse duration of both the first light-emitting control module and the second light-emitting control module being turned on is (N3-X1)*H.

[0104] For example, Fig.11As shown, X1=0.5 is set. Since the second start signal STV2, the third clock signal CK3, and the fourth clock signal CK4 are simultaneously shifted right by 0.5*H, the third level signal V3 is also shifted right by 0.5*H, and the duration for which the first level signal V1 and the third level signal V3 are simultaneously output is shortened to 2.5*H.

[0105] Fig.12 A working timing diagram of another display panel provided in an embodiment of the present application.

[0106] In one embodiment of the present application, Figure 6 , Fig.12 As shown, in the first working cycle T ime1, the effective pulse durations of the first start signal STV1 and the second start signal STV2 are shortened by X2*H, where X2 is an integer greater than or equal to 1. Then, the durations of the first level signal V1 and the third level signal V3 are also shortened by X2*H, thereby shortening the duration of simultaneous output of the first level signal V1 and the third level signal V3 by X2*H. X2 is an integer, which is conducive to achieving a situation where the light-emitting device 100 needs to shorten a large light-emitting duration in the frame T ime1 B. For example, if X2=1, the duration of simultaneous output of the first level signal V1 and the third level signal V3 is shortened to (3-1)*H.

[0107] Further, the first start signal STV1, the first clock signal CK1, and the second clock signal CK2 are simultaneously moved by X1*H, and the second start signal STV2, the third clock signal CK3, and the fourth clock signal CK4 are fixed. Alternatively, the second start signal STV2, the third clock signal CK3, and the fourth clock signal CK4 are simultaneously moved by X1*H, and the first start signal STV1, the first clock signal CK1, and the second clock signal CK2 are fixed. Then, the duration of the simultaneous output of the first level signal V1 and the third level signal V3 can be shortened to (N3-X2±X1)*H, so that the effective pulse duration for controlling the first light-emitting control module and the second light-emitting control module to be turned on is (N3-X2±X1)*H.

[0108] For example, refer to Fig.12 As shown, when X2=1 and X1=0.5 are set, the first start signal STV1, the first clock signal CK1, and the second clock signal CK2 are simultaneously shifted to the left by 0.5*H, and the second start signal STV2, the third clock signal CK3, and the fourth clock signal CK4 are fixed. The effective pulse duration of both the first light-emitting control module 20 and the second light-emitting control module 30 can be extended to (3-1-0.5)*H, and the light-emitting duration can be shortened by 1.5*H.

[0109] Fig.13 A working timing diagram of another display panel provided in an embodiment of the present application.

[0110] In one embodiment of the present application, Figure 6 , Fig.13 As shown, in the first working cycle T ime1, the effective pulse durations of the first start signal STV1 and the second start signal STV2 are extended by X2*H, where X2 is an integer greater than or equal to 1. The effective pulse duration for controlling both the first light control module 20 and the second light control module 30 to be turned on is (N3+X2)*H.

[0111] In the embodiment of the present application, the clock signals are fixed, and the effective pulse durations of the first start signal STV1 and the second start signal STV2 are extended at the same time, so that the pulse durations of the first level signal V1 and the third level signal V3 are also extended at the same time, which is conducive to adjusting the luminous duration to an integer multiple of the clock cycle H. For example, Fig.13 As shown, optionally, setting X2=2, the pulse durations of the first level signal V1 and the third level signal V3 are both extended by 2*H, and the duration of simultaneous output of the first level signal V1 and the third level signal V3 is also extended by 2*H, so that the light emitting duration of the light emitting device 200 in the maintenance frame T ime1B is adjusted to 5*H.

[0112] Fig.14 A working timing diagram of another display panel provided in an embodiment of the present application.

[0113] In one embodiment of the present application, Figure 6 , Fig.14 As shown, in the first working cycle T ime1, the effective pulse durations of the first start signal STV1 and the second start signal STV2 are shortened by X2*H, where X2 is an integer and 1≤X2<N3. Since the effective light-emitting duration of the light-emitting device 200 in the refresh frame T ime1A is N3*H, setting X2 within the range of 1≤X2<N3 is beneficial to avoid the situation where the light-emitting device 200 cannot emit light. At this time, the effective pulse duration for controlling both the first light-emitting control module 20 and the second light-emitting control module 30 to be turned on is (N3-X2)*H.

[0114] For example, Fig.14 As shown, optionally, setting X2=1, the pulse durations of the first level signal V1 and the third level signal V3 are shortened by 1*H, and the duration of simultaneous output of the first level signal V1 and the third level signal V3 is also shortened by 1*H, so that the light emitting duration of the light emitting device 200 in the maintenance frame T ime1B is adjusted to 2*H.

[0115] Fig.15 A working timing diagram of another display panel provided in an embodiment of the present application.

[0116] In one embodiment of the present application, as shown in FIG. Figure 6 , 15 As shown, in the first working cycle T ime1, the time of the first working cycle T ime1 remains unchanged and the effective pulse duration of the first start signal STV1 is shortened by X2*H, where X2 is an integer and 1≤X2<N3. Since the time of the first working cycle T ime1 remains unchanged, the effective pulse duration of the first start signal STV1 is shortened by X2*H, which also means that the ineffective pulse duration of the first start signal STV1 is prolonged by X2*H. Fig.15 As shown, in the first start signal STV1, at the rising edge where the valid pulse signal switches to the non-valid pulse signal, the rising edge here arrives X2*H in advance. At this time, the pulse duration of the first level signal V1 is also shortened by X2*H, and the pulse duration of the second level signal V2 is extended by X2*H, while the pulse duration of the third level signal V3 is fixed, then the duration of the simultaneous output of the first level signal V1 and the third level signal V3 is also shortened by X2*H, and the effective pulse duration for controlling the first light-emitting control module 20 and the second light-emitting control module 30 to be turned on is (N3-X2)*H. For example, Fig.15 As shown, setting X2=1 makes the time of the first working cycle T ime1 unchanged and shortens the effective pulse duration of the first start signal STV1 to 3*H, and controls the effective pulse duration of both the first light control module 20 and the second light control module 30 to be turned on to 2*H.

[0117] In the embodiment of the present application, the second start signal STV2 is set fixed, and only the effective pulse duration of the first start signal STV1 is changed, so as to shorten the effective pulse duration of both the first light-emitting control module 20 and the second light-emitting control module 30 being turned on, which is beneficial to reducing the number of signals that need to be adjusted and improving the efficiency of signal adjustment.

[0118] Fig.16 A schematic diagram of a display device provided in an embodiment of the present application.

[0119] The present application embodiment provides a display device A20, such as Fig.16 As shown, the display device A20 includes the display panel A10 provided in the above embodiment. The display device A20 can be a device including a display function such as a television, a computer, a mobile phone, etc.

[0120] In the display device A20, the signals output by the first shift register circuit 301 and the second shift register circuit 401 are set to respectively control the first light-emitting control module 20 and the second light-emitting control module 30 in the pixel circuit 100, so that the first light-emitting control module 20 and the second light-emitting control module have the conditions for time-sharing opening, which is beneficial to adjust the start time and end time of the light-emitting driving current generated by the pixel circuit 100 to the light-emitting device 200 through the on-off coordination of the first light-emitting control module 20 and the second light-emitting control module 30, so as to achieve more flexible adjustment of the light-emitting time of the light-emitting device 200, and achieve adjustment of the light-emitting time to a non-integer multiple or integer multiple of the clock cycle, so as to more accurately compensate for the light-emitting brightness of the light-emitting device 200.

[0121] The above description is only a preferred embodiment of the present application and is not intended to limit the present application. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present application shall be included in the scope of protection of the present application.

Claims

1. A display panel, characterized in that: include: A pixel circuit, comprising a driving transistor, a first light-emitting control module and a second light-emitting control module, wherein a control end of the first light-emitting control module is electrically connected to a first signal line, and a control end of the second light-emitting control module is electrically connected to a second signal line; the first signal line can output a first level signal and a second level signal, and the control end of the first light-emitting control module is turned on when receiving the first level signal, and is turned off when receiving the second level signal; the second signal line can output a third level signal and a fourth level signal, and the control end of the second light-emitting control module is turned on when receiving the third level signal, and is turned off when receiving the fourth level signal; A first shift register, comprising M stages of cascaded first shift register circuits, wherein a first output end of the first shift register circuit is electrically connected to the first signal line; the first shift register circuit receives a first start signal, a first clock signal, and a second clock signal; A second shift register, comprising M stages of cascaded second shift register circuits; a second output end of the second shift register circuit is electrically connected to the second signal line; and the first shift register circuit receives a second start signal, a third clock signal, and a fourth clock signal; The first light-emitting control module and the second light-emitting control module are both electrically connected to the driving transistor, and when both are turned on, they control the driving transistor to output a light-emitting driving current.

2. The display panel according to claim 1, characterized in that: The first start signal and the second start signal are supplied through different signal lines.

3. The display panel according to claim 2, characterized in that: The first clock signal, the second clock signal, the third clock signal, and the fourth clock signal are supplied by different signal lines; The first shift register circuit further includes: a first output unit, electrically connected to the first output terminal and configured to output the first level signal; a second output unit, electrically connected to the first output terminal and configured to output the second level signal; a first control unit, the first control unit receiving a first start signal, a first clock signal, and a second clock signal, and being used for controlling the first output unit or the second output unit to be turned on; The second shift register circuit further includes: a third output unit, electrically connected to the second output terminal and configured to output the third level signal; a fourth output unit, electrically connected to the second output terminal and configured to output the fourth level signal; A second control unit receives a second start signal, a third clock signal, and a fourth clock signal, and is used to control the third output unit or the fourth output unit to start.

4. The display panel according to claim 1 or 3, characterized in that: The periods of the first clock signal, the second clock signal, the third clock signal and the fourth clock signal are all N1*H, where N1 is an integer greater than or equal to 1; The pixel circuit includes at least a first working cycle, during which: The rising edge and the falling edge of the first start signal are both N2*H ahead of the rising edge and the falling edge of the second start signal; N2 is an integer greater than or equal to 1; The rising edge and the falling edge of the first level signal are both N2*H earlier than the rising edge and the falling edge of the third level signal; The effective pulse duration for controlling both the first light-emitting control module and the second light-emitting control module to be turned on is N3*H, where N3 is an integer greater than or equal to 1.

5. The display panel according to claim 4, characterized in that: The falling edge and the rising edge of the first clock signal are both N2*H earlier than the rising edge and the falling edge of the third clock signal; The falling edge and the rising edge of the second clock signal are both N2*H earlier than the rising edge and the falling edge of the fourth clock signal.

6. The display panel according to claim 5, characterized in that: In the first working cycle, the first start signal, the first clock signal, and the second clock signal are simultaneously moved by X1*H, and the second start signal, the third clock signal, and the fourth clock signal are fixed; or, in the first working cycle, the second start signal, the third clock signal, and the fourth clock signal are simultaneously moved by X1*H, and the first start signal, the first clock signal, and the second clock signal are fixed; The effective pulse duration when both the first light emitting control module and the second light emitting control module are turned on is (N3±X1)*H; 0<X1≤N2.

7. The display panel according to claim 6, characterized in that: In the first working cycle, the first start signal, the first clock signal, and the second clock signal are simultaneously right-shifted by X1*H; the effective pulse duration when both the first light-emitting control module and the second light-emitting control module are turned on is (N3+X1)*H.

8. The display panel according to claim 6, characterized in that: In the first working cycle, the second start signal, the third clock signal, and the fourth clock signal are simultaneously shifted left by X1*H; the effective pulse duration when the first light-emitting control module and the second light-emitting control module are both turned on is (N3+X1)*H.

9. The display panel according to claim 6, characterized in that: In the first working cycle, the effective pulse durations of the first start signal and the second start signal are both extended by X2*H, where X2 is an integer greater than or equal to 1; The effective pulse duration for controlling both the first light emitting control module and the second light emitting control module to be turned on is (N3+X2±X1)*H.

10. The display panel according to claim 6, characterized in that: In the first working cycle, the first start signal, the first clock signal, and the second clock signal are simultaneously shifted left by X1*H; the effective pulse duration of turning on the first light-emitting control module and the second light-emitting control module is (N3-X1)*H.

11. The display panel according to claim 6, characterized in that: In the first working cycle, the second start signal, the third clock signal, and the fourth clock signal are simultaneously right-shifted by X1*H; the effective pulse duration of turning on the first light-emitting control module and the second light-emitting control module is (N3-X1)*H.

12. The display panel according to claim 6, characterized in that: In the first working cycle, the effective pulse durations of the first start signal and the second start signal are shortened by X2*H, where X2 is an integer greater than or equal to 1; The effective pulse duration for controlling both the first light emitting control module and the second light emitting control module to be turned on is (N3-X2±X1)*H.

13. The display panel according to claim 4, characterized in that: In the first working cycle, the effective pulse durations of the first start signal and the second start signal are both extended by X2*H, where X2 is an integer greater than or equal to 1; The effective pulse duration for controlling both the first light emitting control module and the second light emitting control module to be turned on is (N3+X2)*H.

14. The display panel according to claim 4, characterized in that: In the first working cycle, the effective pulse durations of the first start signal and the second start signal are shortened by X2*H, where X2 is an integer and 1≤X2<N3; The effective pulse duration for controlling both the first light emitting control module and the second light emitting control module to be turned on is (N3-X2)*H.

15. The display panel according to claim 4, characterized in that: In the first working cycle, the time of the first working cycle remains unchanged and the effective pulse duration of the first start signal is shortened by X2*H, where X2 is an integer and 1≤X2<N3; The effective pulse duration for controlling both the first light emitting control module and the second light emitting control module to be turned on is (N3-X2)*H.

16. A display device, characterized in that: Comprising a display panel as described in any one of claims 1-15.

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