A clock synchronization circuit and a clock synchronization method

Abstract

The application discloses a clock synchronization circuit and a clock synchronization method, and relates to the technical field of communication. The clock synchronization circuit of the application comprises a clock synchronization circuit of a receiving circuit and a clock synchronization circuit of a sending circuit. A main receiver and a backup receiver are arranged in the receiving circuit. The delay parameter of the main receiver is obtained by detecting the delay of the backup receiver, so that the clock synchronization of the signal process is realized. Meanwhile, a main sender and a backup sender are arranged in the sending circuit. The delay parameter of the main sender is obtained by measuring the delay of the backup sender, so that the delay of the main sender is compensated, and the clock synchronization during signal sending is realized. The application can compensate the delay generated by each chip in real time, so that the precision of clock synchronization is improved.

Description

Technical Field

[0001] This application relates to the field of communication technology, specifically to a clock synchronization circuit and a clock synchronization method. Background Technology

[0002] Currently, the OTII (Open Telecom IT Infrastructure) specification stipulates that clock synchronization circuits must use RS422 signals as the external 1PPS clock synchronization interface. In this protocol, the 1PPS signal is synchronized via an RS422 transceiver. It receives the 1PPS signal from the upstream device for clock synchronization and then converts the 1PPS signal back to RS422 for transmission to the next-level clock synchronization device. However, transmitting a 1pps clock signal via the transceiver introduces a typical delay of 19ns and a maximum of 30ns, while receiving a 1pps clock signal introduces a typical delay of 36ns and a maximum of 45ns, significantly impacting clock synchronization accuracy. To eliminate the impact of this delay, existing technologies employ the following methods:

[0003] (1) Compensation is performed according to typical values. In the PLL chip in the clock synchronization circuit, the input and output delays are compensated. At this time, it is necessary to compensate for the delay of 19ns and 36ns according to the actual delay during transmission and reception. This method can compensate for the delay of a certain chip. However, since the above typical values ​​are only individual values ​​selected, and the delay of each chip is different for different batches of chips, the compensation of typical values ​​alone cannot meet the compensation requirements of all chips.

[0004] (2) Perform batch delay measurement on the same batch of chips to measure the delay of each batch of chips, and then use different compensation parameters for the delay data of different batches of chips. Although the above scheme can accurately compensate for delay, it requires batch testing of chip delay. Moreover, within the same batch, the delay is different under different temperatures or different usage times. At this time, the chip delay will also change. Therefore, the second method of compensation is inefficient and has low accuracy. Summary of the Invention

[0005] To address at least one of the problems mentioned in the background art, this application provides a clock synchronization circuit and a clock synchronization method that can compensate for the real-time delay generated by each chip, thereby improving the accuracy of clock synchronization.

[0006] The specific technical solutions provided in the embodiments of this application are as follows:

[0007] In a first aspect, a clock synchronization circuit for a receiving circuit is provided, the receiving circuit comprising:

[0008] The primary receiver is used to receive differential signals and convert them into multiple single-ended signals.

[0009] A backup receiver is connected to the output of the primary receiver and receives a first single-ended signal from the primary receiver.

[0010] The first phase detector is used to receive the second single-ended signal and combine it with the first single-ended signal output by the backup receiver to calculate the first delay parameter generated by the single-ended signal after being processed by the backup receiver.

[0011] The first phase-locked loop clock chip is used to receive the third single-ended signal and the first delay parameter, and to configure the first delay parameter into the delay compensation of the first phase-locked loop clock chip.

[0012] In one specific embodiment, the receiving circuit further includes:

[0013] An input connector, the output of which is electrically connected to the input of the master receiver, is used to input external differential signals to the master receiver.

[0014] In one specific embodiment, the output of the first phase detector is electrically connected to a first microcontroller, and the output of the first microcontroller is electrically connected to the first phase-locked loop clock chip via an I2C bus.

[0015] The first microcontroller is used to receive the first delay parameter output by the first phase detector and configure it into the delay compensation of the first phase-locked loop clock chip via the I2C bus.

[0016] Secondly, a clock synchronization method for a receiving circuit is provided, applied to a control chip, the method comprising:

[0017] The primary receiver receives external differential signals and outputs multiple single-ended signals, with the first single-ended signal input to the backup receiver.

[0018] The backup receiver transmits a single-ended signal to the first phase detector, while the first phase detector receives a second single-ended signal from the primary receiver.

[0019] The first phase detector combines the single-ended signal output from the backup receiver with the received second single-ended signal to calculate the first delay parameter;

[0020] The first delay parameter is configured into the delay compensation of the first phase-locked loop clock chip to achieve delay compensation for the main receiver.

[0021] In one specific embodiment, the first delay parameter is configured into the delay compensation of the first phase-locked loop clock chip to achieve delay compensation for the main receiver, specifically including:

[0022] The output of the first phase detector is also electrically connected to a first microcontroller, and the output of the first microcontroller is electrically connected to the phase-locked loop clock chip via an I2C bus.

[0023] After receiving the first delay parameter output by the first phase detector, the first microcontroller configures the first delay parameter into the phase-locked loop clock chip via the I2C bus.

[0024] In one specific embodiment, a clock synchronization circuit for a transmitting circuit is provided, the transmitting circuit comprising:

[0025] The second phase-locked loop clock chip is used to output multiple single-ended signals;

[0026] The second phase detector is electrically connected to the second phase-locked loop clock chip and is used to receive the first single-ended signal.

[0027] A master transmitter, the input of which is electrically connected to the second phase-locked loop clock chip, is used to receive a second single-ended signal;

[0028] A backup transmitter, the input of which is electrically connected to the second phase-locked loop clock chip, is used to receive a third single-ended signal and transmit a second single-ended signal to a second phase detector, so that the second phase detector can calculate a second delay parameter and configure it in the delay compensation of the second phase-locked loop clock chip.

[0029] In one specific embodiment, the transmitting circuit further includes:

[0030] The output of the second phase detector is electrically connected to a second microcontroller, and the output of the second microcontroller is electrically connected to the second phase-locked loop clock chip via an I2C bus.

[0031] The second microcontroller is used to receive the second delay parameter output by the second phase detector and configure it into the delay compensation of the second phase-locked loop clock chip via the I2C bus.

[0032] In one specific embodiment, the transmitting circuit further includes:

[0033] An output connector, the input end of which is electrically connected to the output end of the main transmitter, is used to output a differential signal.

[0034] Thirdly, a clock synchronization method for a transmitting circuit is provided, applied to a control chip, the method comprising:

[0035] The second phase-locked loop clock chip outputs multiple single-ended signals, of which the first single-ended signal is sent to the second phase detector, the second single-ended signal is sent to the main transmitter, and the third single-ended signal is sent to the backup transmitter.

[0036] After receiving the single-ended signal, the backup transmitter transmits the single-ended signal to the second phase detector.

[0037] The second phase detector combines the received single-ended signal from the backup transmitter and the single-ended signal from the second phase-locked loop clock chip to calculate the second delay parameter;

[0038] The second delay parameter is configured into the delay compensation of the second phase-locked loop clock chip to achieve delay compensation for the master transmitter.

[0039] In one specific embodiment, the second delay parameter is configured into the delay compensation of the second phase-locked loop clock chip to achieve delay compensation for the master transmitter, specifically including:

[0040] The output of the second phase detector is also electrically connected to a second microcontroller, and the output of the second microcontroller is electrically connected to the second phase-locked loop clock chip via an I2C bus.

[0041] After receiving the delay compensation output from the second phase detector, the second microcontroller is configured to perform delay compensation on the second phase-locked loop clock chip via the I2C bus.

[0042] The embodiments of this application have the following beneficial effects:

[0043] 1. The clock synchronization circuit of the receiving circuit provided in the embodiments of this application, wherein the first phase detector is capable of receiving the second single-ended signal and the single-ended signal from the backup receiver, and calculating the delay of the single-ended signal in the processing of the backup receiver to obtain the first delay parameter, and configuring the first delay parameter into the delay compensation of the first phase-locked loop clock chip to realize the delay compensation of the primary receiver.

[0044] 2. The clock synchronization circuit of the transmitting circuit provided in this application outputs multiple single-ended signals through the second phase-locked loop clock chip. Then, the second phase detector receives the single-ended signals from the second phase-locked loop and the single-ended signals from the backup transmitter, calculates the second delay parameter, and then configures the second delay parameter into the second phase-locked loop clock chip to achieve delay compensation for the main transmitter. The above scheme can perform real-time delay compensation for the transmitting and receiving circuits of each chip, thereby improving the accuracy of clock synchronization.

[0045] 3. In the clock synchronization circuit of the receiving circuit, a microcontroller is connected to the output of the first phase detector. The phase detector measures the delay of the signal after passing through the backup receiver, and then transmits the delayed data to the microcontroller. The microcontroller outputs the delay parameters to the phase-locked loop clock chip through the I2C bus, thereby realizing the compensation of the main receiver that is actually in use. Since the main receiver and the backup receiver are on the same silicon chip, their delays are not affected by temperature and usage time. At any time, the delay compensation of the main receiver can be accurately performed.

[0046] 4. An input connector is connected to the input terminal of the main receiver, which can connect the received external differential signal to the main receiver. Attached Figure Description

[0047] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0048] Figure 1 A schematic diagram of the clock synchronization circuit of the receiving circuit according to Embodiment 1 of this application is shown;

[0049] Figure 2 A schematic diagram showing the specific connection structure of the receiving circuit according to Embodiment 1 of this application is provided.

[0050] Figure 3 A schematic diagram of a clock synchronization method for a receiving circuit according to Embodiment 2 of this application is shown;

[0051] Figure 4 A schematic diagram of the clock synchronization circuit of the transmitting circuit according to Embodiment 3 of this application is shown;

[0052] Figure 5 A schematic diagram of a clock synchronization method for a transmitting circuit according to Embodiment 4 of this application is shown;

[0053] Figure 6 A schematic diagram of the structure of the electronic device according to this application is shown. Detailed Implementation

[0054] To make the objectives, technical solutions, and advantages of this application clearer, the technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0055] Current technologies compensate based on typical delay values. This method can accurately compensate for a chip's delay when it happens to be within the typical value. However, each chip has a different delay, and simply using typical values ​​for compensation cannot meet the compensation needs of all chips. Therefore, a clock synchronization method is needed that can compensate for the delay of each chip accordingly, thereby improving the accuracy of chip delay compensation. Based on these issues, this embodiment proposes a clock synchronization circuit and a clock synchronization method.

[0056] Example 1

[0057] Provide a clock synchronization circuit for a receiving circuit, such as... Figure 1 As shown, the following components are integrated on the same chip: The receiving circuit includes:

[0058] The primary receiver is used to receive differential signals and convert them into multiple single-ended signals.

[0059] The backup receiver is electrically connected to the output of the primary receiver and receives the first single-ended signal from the primary receiver.

[0060] The first phase detector is used to receive the second single-ended signal from the primary receiver and, in conjunction with the first single-ended signal output from the backup receiver, measure the first delay parameter generated by the single-ended signal passing through the backup receiver.

[0061] The first phase-locked loop clock chip is electrically connected to the output of the main receiver and the first phase detector. The first phase-locked loop clock chip can receive the third single-ended signal and the first delay parameter, and configure the first delay parameter in its delay compensation to realize the delay compensation of the main receiver.

[0062] Two receivers, namely the primary receiver and the backup receiver, are integrated on the same chip. Since the primary receiver and the backup receiver are integrated on the same chip, their physical differences can be ignored, and the delay of the chip's receiving circuit can be obtained as the same.

[0063] In one specific embodiment, the transmitting circuit further includes an input receiver, the output of which is electrically connected to the input of the master receiver, for receiving external differential signals into the master receiver. The OTII specification stipulates that the clock synchronization circuit must use an RS422 signal as the external 1PPS clock synchronization interface; therefore, when receiving differential signals, an input receiver is also included, connected to the input of the master receiver, for receiving external 1PPS signals into this receiving circuit.

[0064] In one specific embodiment, a first microcontroller is electrically connected to the output of the first phase detector, and the output of the first microcontroller is electrically connected to the first phase-locked loop clock chip via an I2C bus.

[0065] The first microcontroller is used to receive the first delay parameter output by the first phase detector and configure it into the delay compensation of the first phase-locked loop clock chip via the I2C bus.

[0066] In one specific embodiment, the specific structure and model of the first microcontroller are not limited. Those skilled in the art can choose one or more of the following microcontrollers for use according to actual needs: CPU, 4KB ROM, 128B RAM, two 16-bit timers / counters, four 8-bit parallel ports, full-duplex serial ports, ADC / DAC, SPI, I2C, ISP, and IAP.

[0067] Those skilled in the art have chosen RS422 to single-ended converter chips, such as TI's SN65C1168E, as the primary and backup receivers. In this embodiment, the primary or backup receiver can convert RS422 signals into single-ended signals for use in subsequent circuits. Figure 2 As shown, the primary or backup receiver converts the single-ended signal into an RS422 signal for transmission. The input signal is a differential signal, connected to pins 13 and 14 of the SN65C1168E chip. After passing through pin 3, it outputs a single-ended signal, which is then transmitted to the 8A34002. Pin 1 of the SN65C1168E chip uses a resistor divider because the SN65C1168E has a differential input. Pin 3 is a single-ended input and connected to the first phase detector. The first phase detector receives two 1PPS signals, measures the signal delay, obtains the first delay parameter, and transmits it to the microcontroller. The microcontroller configures the first delay parameter in the PLL chip via the I2C bus to achieve zero delay between RS422 input and 1PPS output. Testing shows that for servers using the OTII standard, the scheme in this embodiment provides excellent clock synchronization accuracy for the RS422 interface.

[0068] In this embodiment, two receivers on the same silicon wafer have the same delay. A backup receiver is used to delay the sampling clock, compensating for the actual primary receiver. This enables real-time compensation for each chip, improving clock synchronization accuracy. Because it is real-time compensation, it is independent of chip batches and temperature, eliminating the need for batch testing of chip delays and compensation based on typical values. This allows for accurate compensation for different chips.

[0069] Example 2

[0070] Corresponding to the above embodiments, this application provides a clock synchronization method for a receiving circuit, applied to a control chip, such as... Figure 3 As shown, the method includes:

[0071] S1: The primary receiver receives external differential signals and outputs multiple single-ended signals, with the first single-ended signal input to the backup receiver.

[0072] S2: The backup receiver transmits a single-ended signal to the first phase detector, while the first phase detector receives a second single-ended signal from the primary receiver.

[0073] S3: The first phase detector combines the single-ended signal output by the backup receiver with the received second single-ended signal to calculate the first delay parameter;

[0074] S4: The first delay parameter is configured into the delay compensation of the first phase-locked loop clock chip to achieve delay compensation for the main receiver.

[0075] In one specific embodiment, an input connector is further included before the master receiver, the output of which is electrically connected to the master receiver, which is used to access external differential signals into the master receiver.

[0076] In a specific embodiment, step S4 specifically includes: the output terminal of the first phase detector is also electrically connected to a first microcontroller; the output terminal of the first microcontroller is electrically connected to the phase-locked loop clock chip via an I2C bus; after receiving the first delay parameter output by the first phase detector, the first microcontroller configures the first delay parameter into the phase-locked loop clock chip via the I2C bus. By setting the corresponding compensation value in the phase-locked loop clock chip, compensation is achieved for the delay generated by the signal passing through the primary receiver.

[0077] Those skilled in the art have chosen a 1PPS signal as the differential signal, and the primary and backup receivers are RS422 to single-ended converter chips, such as TI's SN65C1168E. In this embodiment, the primary or backup receiver can convert the RS422 signal into a single-ended signal for use in subsequent circuits. The primary or backup receiver converts the single-ended signal into an RS422 signal for transmission. The input signal is a differential signal, connected to pins 13 and 14 of the SN65C1168E chip. After passing through pin 3, it is output as a single-ended signal, which is then transmitted to the 8A34002. Pin 1 of the SN65C1168E chip uses a resistor divider because the SN65C1168E has a differential input. Pin 2 is a single-ended input and is connected to the first phase detector. The first phase detector receives two 1PPS signals, measures the signal delay, obtains the first delay parameter, and transmits it to the microcontroller. The microcontroller configures the first delay parameter into the PLL chip via the I2C bus to achieve zero delay between RS422 input and 1PPS output. Testing shows that for servers using the OTII standard, the solution in this embodiment provides excellent clock synchronization accuracy for the RS422 interface.

[0078] Example 3

[0079] Provide a clock synchronization circuit for a transmitting circuit, such as... Figure 4 As shown, the transmitting circuit includes:

[0080] A dual phase-locked loop clock chip is used to output multiple single-ended signals.

[0081] The second phase detector is electrically connected to the second phase-locked loop clock chip and is used to receive the first single-ended signal from the second phase-locked loop clock chip.

[0082] The main transmitter has its input terminal electrically connected to the second phase-locked loop clock chip and is used to receive the second single-ended signal.

[0083] A backup transmitter has its input terminal electrically connected to the second phase-locked loop clock chip to receive a third single-ended signal. Simultaneously, the output terminal of the backup transmitter is electrically connected to the second phase detector. The backup transmitter transmits a second single-ended signal to the second phase detector, which calculates the second delay parameter and configures it in the delay compensation of the second phase-locked loop clock chip.

[0084] In one specific embodiment, the transmitting circuit further includes an output connector, the input end of which is electrically connected to the output end of the main transmitter for outputting a differential signal.

[0085] In one specific embodiment, to ensure that the phase error calculated by the second phase detector is configured in the output delay compensation of the large PLL chip, thereby ensuring that the phase of the signal output by the PLL chip is the same as the external differential 1PPS signal, a second microcontroller is electrically connected to the output of the second phase detector. The output of the second microcontroller is electrically connected to the second phase-locked loop clock chip via an I2C bus. The second microcontroller is used to receive the second delay parameter output by the second phase detector and configure it in the delay compensation of the second phase-locked loop clock chip via the I2C bus, thereby realizing the delay compensation of the master transmitter.

[0086] Specifically, this embodiment does not limit the specific structure and model of the second microcontroller. Those skilled in the art can choose one or more of the following microcontrollers to use according to actual needs: CPU, 4KB ROM, 128B RAM, two 16-bit timers / counters, four 8-bit parallel ports, full-duplex serial ports, ADC / DAC, SPI, I2C, ISP, and IAP.

[0087] In a specific embodiment, those skilled in the art would select a primary transmitter and a backup transmitter as a transceiver. In the OTII specification, a delay occurs when the 1PPS differential signal is transmitted through the transceiver. To eliminate the delay caused by the primary transmitter and achieve synchronization, a backup transmitter is also configured in the primary transmitter circuit. Specifically, both the primary and backup transmitters are RS422 to single-ended converter chips, such as TI's SN65C1168E. The primary transmitter receives the single-ended signal from the PLL chip and converts it to an RS422 signal for transmission. The PLL chip outputs three single-ended signals: the first is transmitted to the primary transmitter, the second and third are transmitted to the backup transmitter and the second phase detector, respectively. Simultaneously, the signal output from the backup transmitter is also transmitted to the second phase detector. The second phase detector outputs signal delay parameters to configure the PLL chip, thereby compensating for the delay of the primary transmitter. Therefore, the 1PPS signal output by the PLL chip can remain synchronized after being converted into a differential signal by the main transmitter and given to the RJ45 / DB9, thus achieving phase synchronization between the input and differential output of the 1PPS signal.

[0088] Example 4

[0089] Corresponding to the above embodiments, this application provides a clock synchronization method for a transmitting circuit, applied to a control chip, such as... Figure 5 As shown, the method includes:

[0090] S101: The second phase-locked loop clock chip outputs multiple single-ended signals, of which the first single-ended signal is sent to the second phase detector, the second single-ended signal is sent to the main transmitter, and the third single-ended signal is sent to the backup transmitter.

[0091] S102: After receiving the single-ended signal, the backup transmitter transmits the single-ended signal to the second phase detector;

[0092] S103: The second phase detector combines the received single-ended signal from the backup transmitter and the single-ended signal from the second phase-locked loop clock chip to calculate the second delay parameter;

[0093] S104: Configure the second delay parameter into the delay compensation of the second phase-locked loop clock chip to achieve delay compensation for the master transmitter.

[0094] In one specific embodiment, when outputting a single-ended signal, an output connector is also connected to the output terminal of the master transmitter. The input terminal of the output connector is electrically connected to the output terminal of the master transmitter for outputting a differential signal.

[0095] In a specific embodiment, step 104 specifically includes the output terminal of the second phase detector being electrically connected to a second microcontroller, the output terminal of the second microcontroller being electrically connected to the second phase-locked loop clock chip via an I2C bus; after receiving the delay compensation output by the second phase detector, the second microcontroller is configured into the delay compensation of the second phase-locked loop clock chip via the I2C bus.

[0096] In this embodiment, utilizing the idea that two identical transmitters on the same silicon wafer have the same delay, a backup transmitter is set up specifically for sampling clock delay to compensate for the actual transceiver chip in use, thereby improving clock synchronization accuracy. Since this embodiment measures the delay generated by the backup transmitter to compensate the primary transmitter in real time, it eliminates the need for batch and temperature monitoring of the chips, and also eliminates the need for compensation based on typical delay values ​​of the chips. This achieves accurate compensation for different chips, thus improving clock synchronization accuracy.

[0097] Example 5

[0098] An electronic device is provided, including a memory, a processor, and a computer program stored in the memory and executable on the processor. When the processor executes the computer program, it implements the following steps of a clock synchronization method for a receiving circuit:

[0099] Step 201: The primary receiver receives the external differential signal and outputs multiple single-ended signals, wherein the first single-ended signal is input to the backup receiver;

[0100] Step 202: The backup receiver transmits a single-ended signal to the first phase detector, while the first phase detector receives a second single-ended signal from the primary receiver;

[0101] Step 203: The first phase detector combines the single-ended signal output from the backup receiver with the received second single-ended signal to calculate the first delay parameter;

[0102] Step 204: The first delay parameter is configured into the delay compensation of the first phase-locked loop clock chip to achieve delay compensation for the main receiver.

[0103] Alternatively, the processor, when executing a computer program, may implement the following steps for clock synchronization of a transmitting circuit:

[0104] Step 301: The second phase-locked loop clock chip outputs multiple single-ended signals, of which the first single-ended signal is sent to the second phase detector, the second single-ended signal is sent to the main transmitter, and the third single-ended signal is sent to the backup transmitter.

[0105] Step 302: After receiving the single-ended signal, the backup transmitter transmits the single-ended signal to the second phase detector;

[0106] Step 303: The second phase detector combines the received single-ended signal from the backup transmitter and the single-ended signal from the second phase-locked loop clock chip to calculate the second delay parameter;

[0107] Step 304: Configure the second delay parameter into the delay compensation of the second phase-locked loop clock chip to achieve delay compensation for the master transmitter.

[0108] In one embodiment, an electronic device is provided, which may be a server, and its internal structure diagram may be as follows: Figure 6 As shown, this electronic device includes a processor, memory, network interface, and database connected via a system bus. The processor provides computing and control capabilities. The memory includes a non-volatile storage medium and internal memory. The non-volatile storage medium stores the operating system, computer programs, and database. The internal memory provides an environment for the operation of the operating system and computer programs in the non-volatile storage medium. The database stores delay data for backup receivers or backup transmitters. The network interface communicates with external terminals via a network connection. When executed by the processor, the computer program implements a clock circuit synchronization method.

[0109] Those skilled in the art will understand that Figure 6The structure shown is merely a block diagram of a portion of the structure related to the present application and does not constitute a limitation on the electronic device to which the present application is applied. The specific electronic device may include more or fewer components than shown in the figure, or combine certain components, or have different component arrangements.

[0110] Example 6

[0111] In one embodiment of this invention, a computer-readable storage medium is provided having a computer program stored thereon, which, when executed by a processor, performs the following steps:

[0112] Step 401: The primary receiver receives the external differential signal and outputs multiple single-ended signals, wherein the first single-ended signal is input to the backup receiver;

[0113] Step 402: The backup receiver transmits a single-ended signal to the first phase detector, while the first phase detector receives a second single-ended signal from the primary receiver;

[0114] Step 403: The first phase detector combines the single-ended signal output from the backup receiver with the received second single-ended signal to calculate the first delay parameter;

[0115] Step 404: The first delay parameter is configured into the delay compensation of the first phase-locked loop clock chip to achieve delay compensation for the main receiver.

[0116] or

[0117] Step 501: The second phase-locked loop clock chip outputs multiple single-ended signals, of which the first single-ended signal is sent to the second phase detector, the second single-ended signal is sent to the main transmitter, and the third single-ended signal is sent to the backup transmitter.

[0118] Step 502: After receiving the single-ended signal, the backup transmitter transmits the single-ended signal to the second phase detector;

[0119] Step 503: The second phase detector combines the received single-ended signal from the backup transmitter and the single-ended signal from the second phase-locked loop clock chip to calculate the second delay parameter;

[0120] Step 504: Configure the second delay parameter into the delay compensation of the second phase-locked loop clock chip to achieve delay compensation for the master transmitter.

[0121] Those skilled in the art will understand that all or part of the processes in the methods of the above embodiments can be implemented by a computer program instructing related hardware. The computer program can be stored in a non-volatile computer-readable storage medium, and when executed, it can include the processes of the embodiments of the above methods. Any references to memory, storage, databases, or other media used in the embodiments provided in this application can include non-volatile and / or volatile memory. Non-volatile memory can include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), or flash memory. Volatile memory can include random access memory (RAM) or external cache memory. By way of illustration and not limitation, RAM is available in various forms, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), dual data rate SDRAM (DDRSDRAM), enhanced SDRAM (ESDRAM), synchronous link DRAM (SLDRAM), Rambus direct RAM (RDRAM), direct memory bus dynamic RAM (DRDRAM), and memory bus dynamic RAM (RDRAM), etc.

[0122] Although preferred embodiments have been described in this application, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments as well as all changes and modifications falling within the scope of the embodiments of this application.

[0123] Obviously, those skilled in the art can make various modifications and variations to this application without departing from the spirit and scope of this application. Therefore, if such modifications and variations fall within the scope of the claims of this application and their equivalents, this application also intends to include such modifications and variations.

Claims

1. A clock synchronization circuit for a receiving circuit, characterized in that, The receiving circuit includes: The primary receiver is used to receive differential signals and convert them into multiple single-ended signals. A backup receiver is connected to the output of the primary receiver and receives a first single-ended signal from the primary receiver. The first phase detector is used to receive the second single-ended signal and combine it with the first single-ended signal output by the backup receiver to calculate the first delay parameter generated by the single-ended signal passing through the backup receiver. The first phase-locked loop clock chip is used to receive the third single-ended signal and the first delay parameter, and to configure the first delay parameter into the delay compensation of the first phase-locked loop clock chip.

2. The clock synchronization circuit according to claim 1, characterized in that, The receiving circuit further includes: An input connector, the output of which is electrically connected to the input of the master receiver, is used to input external differential signals to the master receiver.

3. The clock synchronization circuit according to claim 1 or 2, characterized in that, The output of the first phase detector is electrically connected to the first microcontroller, and the output of the first microcontroller is electrically connected to the first phase-locked loop clock chip via an I2C bus. The first microcontroller is used to receive the first delay parameter output by the first phase detector and configure it into the delay compensation of the first phase-locked loop clock chip via the I2C bus.

4. A clock synchronization method based on the receiving circuit according to any one of claims 1 to 3, applied to a control chip, characterized in that, The method includes: The primary receiver receives external differential signals and outputs multiple single-ended signals, with the first single-ended signal input to the backup receiver. The backup receiver transmits a single-ended signal to the first phase detector, while the first phase detector receives a second single-ended signal from the primary receiver. The first phase detector combines the single-ended signal output from the backup receiver with the received second single-ended signal to calculate the first delay parameter; The first delay parameter is configured into the delay compensation of the first phase-locked loop clock chip to achieve delay compensation for the main receiver.

5. The clock synchronization method according to claim 4, characterized in that, The first delay parameter is configured into the delay compensation of the first phase-locked loop clock chip to achieve delay compensation for the main receiver, specifically including: The output of the first phase detector is also electrically connected to a first microcontroller, and the output of the first microcontroller is electrically connected to the phase-locked loop clock chip via an I2C bus. After receiving the first delay parameter output by the first phase detector, the first microcontroller configures the first delay parameter into the phase-locked loop clock chip via the I2C bus.

6. A clock synchronization circuit for a transmitting circuit, characterized in that, The transmitting circuit includes: The second phase-locked loop clock chip is used to output multiple single-ended signals; The second phase detector is electrically connected to the second phase-locked loop clock chip and is used to receive the first single-ended signal. A master transmitter, the input of which is electrically connected to the second phase-locked loop clock chip, is used to receive a second single-ended signal; A backup transmitter, the input of which is electrically connected to the second phase-locked loop clock chip, is used to receive a third single-ended signal and transmit a second single-ended signal to a second phase detector, so that the second phase detector can calculate a second delay parameter and configure it in the delay compensation of the second phase-locked loop clock chip.

7. The clock synchronization circuit according to claim 6, characterized in that, The transmitting circuit further includes: The output of the second phase detector is electrically connected to a second microcontroller, and the output of the second microcontroller is electrically connected to the second phase-locked loop clock chip via an I2C bus. The second microcontroller is used to receive the second delay parameter output by the second phase detector and configure it into the delay compensation of the second phase-locked loop clock chip via the I2C bus.

8. The clock synchronization circuit according to claim 6 or 7, characterized in that, The transmitting circuit further includes: An output connector, the input end of which is electrically connected to the output end of the main transmitter, is used to output a differential signal.

9. A clock synchronization method based on the transmitting circuit according to any one of claims 6 to 8, applied to a control chip, characterized in that, The method includes: The second phase-locked loop clock chip outputs multiple single-ended signals, of which the first single-ended signal is sent to the second phase detector, the second single-ended signal is sent to the main transmitter, and the third single-ended signal is sent to the backup transmitter. After receiving the single-ended signal, the backup transmitter transmits the single-ended signal to the second phase detector. The second phase detector combines the received single-ended signal from the backup transmitter and the single-ended signal from the second phase-locked loop clock chip to calculate the second delay parameter. The second delay parameter is configured into the delay compensation of the second phase-locked loop clock chip to achieve delay compensation for the master transmitter.

10. The clock synchronization method according to claim 9, characterized in that, The second delay parameter is configured into the delay compensation of the second phase-locked loop clock chip to achieve delay compensation for the master transmitter, specifically including: The output of the second phase detector is also electrically connected to a second microcontroller, and the output of the second microcontroller is electrically connected to the second phase-locked loop clock chip via an I2C bus. After receiving the delay compensation output from the second phase detector, the second microcontroller is configured to perform delay compensation on the second phase-locked loop clock chip via the I2C bus.

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