Precise high-speed analog-to-digital synchronous conversion system

Abstract

The invention belongs to the field of electronic devices, and provides a precise high-speed analog-to-digital synchronous conversion system which comprises an information processing module, a synchronous control module and a plurality of analog-to-digital conversion modules. Each analog-to-digital conversion module comprises a digital-to-analog conversion unit, a register unit and a discrimination unit; the synchronous control module comprises a control unit and an AND operation unit; the information processing module comprises a rear-end reading unit; the register unit is connected with the analog-to-digital conversion unit and the discrimination unit. The discrimination unit is connected with the operation unit; the register units are connected with the arithmetic unit; the control unit is respectively connected with the operation unit, the rear-end reading unit, the judgment unit and the analog-to-digital conversion unit; and the rear-end reading unit is respectively connected with the register unit and the AND operation unit. The multi-channel parallel register is arranged in front of the information processing module, so that the problem that time difference exists in data transmission of different channels is solved; a data synchronous reading function is realized through the discrimination unit, the arithmetic unit and the control unit.

Description

Technical Field

[0001] The invention relates to the field of electronic devices, and in particular to a precise high-speed analog-to-digital synchronous conversion system. Background Art

[0002] At present, the chips containing analog-to-digital converters can be roughly divided into two categories: general-purpose microcontrollers and application-specific integrated circuits. The analog-to-digital converters of general-purpose microcontrollers are mainly used to handle less frequent analog-to-digital conversion needs, such as current and voltage conversion, etc., and can also measure and convert parameters such as pressure, temperature, and humidity with sensors; application-specific integrated circuits containing analog-to-digital converters are generally used under conditions with more frequent processing needs, such as real-time monitoring of temperature, humidity, and pressure acquisition and data conversion. In application fields such as image detection, phased array radar, and electronic countermeasures that require multi-channel synchronous data acquisition, the use of a single-chip multi-channel high-speed and high-precision analog-to-digital converter to build a system is a very mature design idea, but with the gradual increase in the number of channels in the application system and the gradual improvement in the degree of integration, this design idea can no longer meet the needs. The use of multiple high-speed and high-precision analog-to-digital converters to synchronously acquire large arrays and highly integrated systems is currently the most widely used technology, but the application of multiple high-speed and high-precision analog-to-digital converters synchronous acquisition will inevitably pose challenges to the design of channel consistency between chips.

[0003] Patent CN 109617552A proposes a multi-channel analog-to-digital conversion system and a conversion method thereof. This method realizes the synchronization of multi-channel analog-to-digital conversion to a certain extent, but this method also brings problems such as poor expansion performance, complex structure, and significant impact of typesetting. Summary of the invention

[0004] In order to overcome the deficiencies of the prior art, the purpose of the present invention is to provide a precise high-speed analog-to-digital synchronous conversion system, which solves the problem of transmission delay of signals between different channels through a register unit to realize synchronous reading of multi-channel data; solves the problem of register state recognition and control of the output state of the register unit through a discrimination unit, an AND operation unit and a control unit to realize the adaptive synchronous transmission function of the register unit; solves the problem of manual control of the analog-to-digital conversion unit, the register unit and the AND operation unit through the control unit to realize the control of the working state of the analog-to-digital conversion unit, the control of the node length of the register unit and the control of the working state of the input path of the AND operation unit.

[0005] To achieve the above object, the present invention provides the following solutions:

[0006] A precision high-speed analog-to-digital synchronous conversion system, comprising: an information processing module, a synchronous control module and a plurality of analog-to-digital conversion modules; each analog-to-digital conversion module comprises: a digital-to-analog conversion unit, a storage unit and a discrimination unit; the synchronous control module comprises: a control unit and an AND operation unit; the information processing module comprises: a back-end reading unit;

[0007] In the same analog-to-digital conversion module, the output end of the analog-to-digital conversion unit is connected to the input end of the register unit; in the same analog-to-digital conversion module, the output end of the register unit is connected to the input end of the discrimination unit; the output ends of all the discrimination units are connected to the input end of the AND operation unit; the input ends of all the register units are respectively connected to the output end of the AND operation unit; the output end of the control unit is respectively connected to the input end of the AND operation unit, the input end of the back-end reading unit, the input ends of all the discrimination units and the input ends of all the analog-to-digital conversion units; the output ends of all the register units are connected to the input end of the back-end reading unit; the output end of the back-end reading unit is connected to the input end of the AND operation unit;

[0008] The digital-to-analog conversion unit is used to convert the analog signal input by the channel into a digital signal; the register unit is used to temporarily store the digital signal; the discrimination unit is used to judge the storage state of the register unit, and output a high level when the storage state is a state of storing a node data; the control unit is used to control the working state of the digital-to-analog conversion unit, rewrite the single-node data judgment standard of the discrimination unit, control some input ends of the AND operation unit to maintain a high level according to the host computer instruction, and send a channel status instruction to the back-end reading unit; the AND operation unit is used to perform an AND operation on all input level signals of the AND operation unit, and when all input ends of the AND operation unit are high levels, control the register unit to output a signal; the back-end reading unit is used to receive the digital signal sent by the register unit according to the channel status instruction, and return the reception completion information to the AND operation unit after receiving a group of the digital signals.

[0009] Preferably, the control unit is embedded with a sampling frequency pre-control sub-unit; the implementation formula of the sampling frequency pre-control sub-unit includes: as well as Δ(k) is the difference between the k-1th predicted frequency and the k-1th actual frequency; is the predicted frequency of the k-1th time; f0(k-1) is the actual frequency of the k-1th time; μ i is the i-th adaptive weight; N p is the adaptive sampling frequency multiplication parameter; f s(k) is the kth pre-control sampling frequency.

[0010] Preferably, the control unit further comprises: a CAN communication subunit, an FPGA processing subunit, a frequency decoder, a node capacity decoder and a channel status decoder;

[0011] The input end and output end of the CAN communication subunit are respectively connected to the input end of the host computer and the FPGA processing subunit; the FPGA processing subunit is respectively connected to the input end of the sampling frequency pre-control subunit, the input end of the node capacity decoder and the input end of the channel state decoder; the output end of the sampling frequency pre-control subunit is connected to the input end of the frequency decoder;

[0012] The frequency decoder is a 16-bit decoder; the channel status decoder is an N-bit decoder; the node capacity decoder is an x-bit decoder; the CAN communication subunit is used to receive control instructions from the host computer; the FPGA processing subunit is used to extract frequency instructions, node instructions and channel instructions from the control instructions, and transmit the frequency instructions, the node instructions and the channel instructions to the sampling frequency pre-control subunit, the node capacity decoder and the channel status decoder respectively; the sampling frequency pre-control subunit is used to obtain frequency control information according to the frequency instruction or the pre-control sampling frequency, and transmit the frequency control information to ... The information is transmitted to the frequency decoder; the frequency decoder is used to translate the frequency control information into a 16-bit binary electrical signal, and transmit the 16-bit binary electrical signal to the digital-to-analog conversion unit; the node capacity decoder is used to translate the node instruction into an x-bit electrical signal, and transmit the x-bit electrical signal to the register unit; the bit width of the x-bit electrical signal depends on the number of control input terminals of the register unit; the channel state decoder is used to translate the channel instruction into an N-bit electrical signal, and transmit the N-bit electrical signal to the discrimination unit; the bit width of the N-bit electrical signal depends on the number of the analog-to-digital conversion modules.

[0013] Preferably, each of the determination units comprises: an edge trigger and a counter;

[0014] The input end of the edge trigger is connected to the output end of the first register in the register unit; the input end of the counter is respectively connected to the output end of the edge trigger and the output end of the node capacity decoder;

[0015] The edge trigger is used to output a high level once when detecting an edge jump of the output of the first register; the counter is used to record the number of times the edge trigger outputs a high level, and realizes adaptive output of a high level according to the x-bit electrical signal.

[0016] Preferably, the register unit comprises a plurality of data registers connected in series.

[0017] Preferably, an OR operator is provided between each of the discrimination units and the AND operation unit;

[0018] The input end of the OR operator is respectively connected to the output end of the discrimination unit of the channel and the output end of the channel state decoder corresponding to the channel; the output end of the OR operator is connected to the input end of the AND operation unit;

[0019] The OR operator is used to control the working state of the channel according to the output level of the output end of the channel state decoder corresponding to the channel.

[0020] Preferably, the number of the data registers ranges from 9 to 20.

[0021] Preferably, the back-end reading unit is an N-way parallel synchronous reading device.

[0022] The present invention discloses the following technical effects:

[0023] The present invention provides a precise high-speed analog-to-digital synchronous conversion system. The system solves the problem of transmission delay between signals of different channels through a register unit, and realizes synchronous reading of multi-channel data. The system solves the problem of register state recognition and control of register unit output state through a discrimination unit, an AND operation unit, and a control unit, and realizes the adaptive synchronous transmission function of the register unit. The system solves the problem of manual control of the analog-to-digital conversion unit, the register unit, and the AND operation unit through the control unit, and realizes the control of the working state of the analog-to-digital conversion unit, the control of the register unit node length, and the control of the working state of the AND operation unit input path. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative labor.

[0025] Figure 1 A schematic diagram of the structure of a precision high-speed analog-to-digital synchronous conversion system provided by an embodiment of the present invention;

[0026] Figure 2 A schematic diagram of the structure of a control unit provided in an embodiment of the present invention;

[0027] Figure 3 A schematic diagram of the structure of a discrimination unit provided in an embodiment of the present invention;

[0028] Description of reference numerals:

[0029] 1-control unit, 2-digital-to-analog conversion unit, 3-register unit, 4-discrimination unit, 5-AND operation unit, 6-back-end reading unit. DETAILED DESCRIPTION

[0030] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0031] The purpose of the present invention is to provide a precise high-speed analog-to-digital synchronous conversion system, which solves the problem of transmission delay of signals between different channels through a register unit, so as to realize synchronous reading of multi-channel data; solves the problem of register state recognition and control of register unit output state through a discrimination unit, an AND operation unit and a control unit, so as to realize the adaptive synchronous transmission function of the register unit; solves the problem of manual control of the analog-to-digital conversion unit, the register unit and the AND operation unit through the control unit, so as to realize the control of the working state of the analog-to-digital conversion unit, the control of the register unit node length and the control of the working state of the AND operation unit input path.

[0032] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, the present invention is further described in detail below with reference to the accompanying drawings and specific embodiments.

[0033] Figure 1 A schematic diagram of the structure of a high-speed analog-to-digital conversion system according to an embodiment of the present invention is shown in FIG. Figure 1 As shown, the present invention provides a precise high-speed analog-to-digital synchronous conversion system, comprising: an information processing module, a synchronous control module and a plurality of analog-to-digital conversion modules; each analog-to-digital conversion module comprises: a digital-to-analog conversion unit 2, a storage unit 3 and a discrimination unit 4; the synchronous control module comprises: a control unit 1 and an AND operation unit 5; the information processing module comprises: a back-end reading unit 6;

[0034] In the same analog-to-digital conversion module, the output end of the analog-to-digital conversion unit is connected to the input end of the register unit 3; in the same analog-to-digital conversion module, the output end of the register unit 3 is connected to the input end of the discrimination unit 4; the output ends of all the discrimination units 4 are connected to the input end of the AND operation unit 5; the input ends of all the register units 3 are respectively connected to the output end of the AND operation unit 5; the output end of the control unit 1 is respectively connected to the input end of the AND operation unit 5, the input end of the back-end reading unit 6, the input ends of all the discrimination units 4 and the input ends of all the analog-to-digital conversion units; the output ends of all the register units 3 are connected to the input end of the back-end reading unit 6; the output end of the back-end reading unit 6 is connected to the input end of the AND operation unit 5;

[0035] The digital-to-analog conversion unit 2 is used to convert the analog signal input by the channel into a digital signal; the register unit 3 is used to temporarily store the digital signal; the discrimination unit 4 is used to judge the storage state of the register unit 3, and output a high level when the storage state is a state of storing a node data; the control unit 1 is used to control the working state of the digital-to-analog conversion unit 2, rewrite the single-node data judgment standard of the discrimination unit 4, control some input ends of the AND operation unit 5 to maintain a high level according to the host computer instruction, and send a channel status instruction to the back-end reading unit 6; the AND operation unit 5 is used to perform an AND operation on all input level signals of the AND operation unit 5, and when all input ends of the AND operation unit 5 are high levels, control the register unit 3 to output a signal; the back-end reading unit 6 is used to receive the digital signal sent by the register unit 3 according to the channel status instruction, and return the reception completion information to the AND operation unit 5 after receiving a group of the digital signals.

[0036] Specifically, the control unit 1 has a built-in sampling frequency pre-control sub-unit; the implementation formula of the sampling frequency pre-control sub-unit includes: as well as Δ(k) is the difference between the k-1th predicted frequency and the k-1th actual frequency; is the predicted frequency of the k-1th time; f0(k-1) is the actual frequency of the k-1th time; μ i is the i-th adaptive weight; N p is the adaptive sampling frequency multiplication parameter; f s (k) is the kth pre-control sampling frequency.

[0037] Furthermore, N p The best frequency doubling parameters for different frequency bands can be obtained by collecting data on acquisition effects at different frequencies and using cluster analysis, such as the knn algorithm.

[0038] Figure 2 A schematic diagram of the structure of a control unit 1 provided in an embodiment of the present invention is shown in FIG. Figure 2 As shown, the control unit 1 also includes: a CAN communication subunit, an FPGA processing subunit, a frequency decoder, a node capacity decoder, and a channel status decoder;

[0039] The input end and output end of the CAN communication subunit are respectively connected to the input end of the host computer and the FPGA processing subunit; the FPGA processing subunit is respectively connected to the input end of the sampling frequency pre-control subunit, the input end of the node capacity decoder and the input end of the channel state decoder; the output end of the sampling frequency pre-control subunit is connected to the input end of the frequency decoder;

[0040] The frequency decoder is a 16-bit decoder; the channel status decoder is an N-bit decoder; the node capacity decoder is an x-bit decoder; the CAN communication subunit is used to receive control instructions from the host computer; the FPGA processing subunit is used to extract frequency instructions, node instructions and channel instructions from the control instructions, and transmit the frequency instructions, the node instructions and the channel instructions to the sampling frequency pre-control subunit, the node capacity decoder and the channel status decoder respectively; the sampling frequency pre-control subunit is used to obtain frequency control information according to the frequency instruction or the pre-control sampling frequency, and transmit the frequency control information to the host computer. Input to the frequency decoder; the frequency decoder is used to translate the frequency control information into a 16-bit binary electrical signal, and transmit the 16-bit binary electrical signal to the digital-to-analog conversion unit 2; the node capacity decoder is used to translate the node instruction into an x-bit electrical signal, and transmit the x-bit electrical signal to the register unit 3; the bit width of the x-bit electrical signal depends on the number of control input terminals of the register unit 3; the channel state decoder is used to translate the channel instruction into an N-bit electrical signal, and transmit the N-bit electrical signal to the discrimination unit 4; the bit width of the N-bit electrical signal depends on the number of the analog-to-digital conversion modules.

[0041] Specifically, CAN communication is a multi-node communication protocol that uses a frame format to transmit data. CAN frames are divided into two formats: standard frames and extended frames. The standard frame consists of an 11-bit identifier, a data field, a control field, and a CRC (cyclic redundancy check). The identifier is used to identify the priority and content of the message, the data field is used to transmit the actual data, the control field contains the control information of the frame, and the CRC is used by the sending node to calculate the checksum and the receiving node to verify the integrity of the data. The extended frame uses a 29-bit identifier, and the other components are the same as the standard frame. The use of extended frames enables the CAN network to handle more nodes and larger amounts of data. The choice of identifier is crucial for CAN communication. The identifier used by the frame determines its priority on the bus, and a lower identifier means a higher priority. When designing and configuring the CAN network, the identifier needs to be set reasonably to ensure the correct operation of the system. CAN communication has the advantages of strong real-time performance, long transmission distance, strong anti-electromagnetic interference ability, and low cost; it adopts a two-wire serial communication method, has strong error detection capability, and can work in a high noise interference environment; it has a reliable error handling and error detection mechanism. Based on the above reasons, this embodiment chooses to set the CAN communication subunit to communicate data with the host computer to ensure the reliability of system operation.

[0042] Figure 3 A schematic diagram of the structure of the discrimination unit 4 provided in an embodiment of the present invention is shown in FIG. Figure 3 As shown, each of the determination units 4 includes: an edge trigger and a counter;

[0043] The input end of the edge trigger is connected to the output end of the first register in the register unit 3; the input end of the counter is respectively connected to the output end of the edge trigger and the output end of the node capacity decoder;

[0044] The edge trigger is used to output a high level once when detecting an edge jump of the output of the first register; the counter is used to record the number of times the edge trigger outputs a high level, and realizes adaptive output of a high level according to the x-bit electrical signal.

[0045] Specifically, there are three common triggering modes of triggers: level triggering, edge triggering, and pulse triggering. Level triggering relies on the detection of the level size. Such devices are prone to triggering the flip-flop phenomenon, which will reduce the anti-interference ability of the circuit; the master-slave trigger of the pulse trigger is easily interfered with and is not practical. The secondary state of edge triggering depends only on the logical state of the input when the rising edge (also called the positive edge) or the falling edge (also called the negative edge) of the clock signal arrives. Before and after, the change of the input signal has no effect on the output state of the trigger. This feature effectively improves the anti-interference ability of the trigger, and thus also improves the working reliability. Based on the above reasons, this embodiment selects the edge trigger as the detection part of the discrimination unit 4.

[0046] Preferably, the register unit 3 includes a plurality of data registers connected in series.

[0047] Furthermore, an OR operator is provided between each of the determination units 4 and the AND operation unit 5;

[0048] The input end of the OR operator is respectively connected to the output end of the discrimination unit 4 of the channel and the output end of the channel state decoder corresponding to the channel; the output end of the OR operator is connected to the input end of the AND operation unit 5;

[0049] The OR operator is used to control the working state of the channel according to the output level of the output end of the channel state decoder corresponding to the channel.

[0050] Preferably, the number of the data registers ranges from 9 to 20.

[0051] Optionally, the back-end reading unit 6 is an N-way parallel synchronous reading device.

[0052] Specifically, when the analog-to-digital conversion system provided by this embodiment is used to perform multi-channel data conversion, a control signal can be input through the host computer, and the FPGA processing subunit can convert the control signal into the corresponding frequency instruction, the node instruction and the channel instruction according to the built-in program; the node instruction and the channel instruction can output multiple parallel electrical signals through the decoder, and the frequency instruction can also output multiple parallel electrical signals through the sampling frequency pre-control subunit and a decoder. The 16-bit binary electrical signal output by the frequency decoder is the frequency information represented by binary, which is transmitted to the analog-to-digital conversion unit and uses the 16-bit binary electrical signal to cover the previous sampling frequency. For example, the 16-bit binary electrical signal corresponding to the sampling frequency of 1000 times / s is 0000001111101000. The x-bit electrical signal output by the node capacity decoder corresponds to each of the data registers in the register unit 3 in turn. When the electrical signal is at a high level, the corresponding data register is switched to a registerable state. When the electrical signal is at a low level, the corresponding data register is switched to a non-registerable state. When the data register is in a non-registerable state, it is equivalent to a wire. For example, when the x-bit (assuming x is 8) electrical signal is 00111111, the first two data registers in the register unit 3 are switched to a non-registerable state, and the remaining data registers are switched to a registerable state. The N-bit electrical signal output by the channel status decoder cooperates with the OR operator to realize the control of the channel working state. When the electrical signal input to the OR operator is at a high level, its output is fixed at a high level. When the electrical signal input to the OR operator is at a low level, its output is only controlled by the register unit 3 connected thereto. When the channel is in a stop working state, it is only necessary to control the output of the OR operator of the channel to be fixed at a high level. For example, when the N-bit (assuming N is 16) electrical signal is 1111000000000000, channels 1-4 are in a stop working state, and the remaining channels are in a normal working state.

[0053] Preferably, FPGA is a product further developed on the basis of programmable devices such as PAL, GAL, EPLD, CPLD, etc. It appears as a semi-custom circuit in the field of ASIC, which solves the shortcomings of custom circuits and overcomes the shortcomings of limited gate circuits of original programmable devices. Since FPGA needs to be repeatedly burned and written, its basic structure for realizing combinational logic cannot be completed by fixed NAND gates like ASIC, but can only adopt a structure that is easy to repeatedly configure. The lookup table can meet this requirement very well. At present, mainstream FPGAs all adopt a lookup table structure based on SRAM technology, and some military products and aerospace-grade FPGAs also adopt a lookup table structure based on Flash or fuse and anti-fuse technology. The method of changing the content of the lookup table by burning a file realizes the repeated configuration of FPGA. At present, the FPGAs produced by Xilinx and Altera, the two major companies with the largest FPGA market share, are based on SRAM technology, and need to be connected to an off-chip memory to save the program when in use. FPGA also has the advantages of radiation resistance, high and low temperature resistance, low power consumption and fast speed. Therefore, this embodiment uses the FPGA processing subunit as the core chip of the control unit 1 to meet the requirements of stable operation of this embodiment.

[0054] Optionally, the control unit 1 of this embodiment is also embedded with a temperature detection subunit, a power consumption detection subunit (or a current protection subunit) and a self-test subunit. The temperature detection subunit is used to detect the local temperature of the analog-to-digital conversion of the chip where the system is located. When the temperature exceeds the preset temperature (set to 125°C in this embodiment), the analog-to-digital conversion unit is controlled to perform frequency reduction sampling, and the frequency reduction method adopts a relatively gentle linear decline method. The power consumption detection subunit is used to detect the local power consumption of the analog-to-digital conversion of the chip, and when the local power consumption abnormally increases to the risk range, the sampling frequency and the power supply voltage are reduced. The self-test subunit cooperates with the temperature detection subunit and the power consumption detection subunit to start self-test. In addition, it is also used for self-test of the channel status. When a certain channel is abnormal and cannot work normally, the remaining channels in the restricted state are controlled to be replaced, and the abnormal channel information is uploaded to the report log.

[0055] Preferably, the present embodiment further includes a power supply circuit unit. The power supply circuit unit includes a programmable digital PWM control chip, a digital dual-channel synchronous buck power supply chip, a switching power supply chip, a high-power switching power supply chip and a linear power supply chip, and the power supply circuit unit can meet the power supply requirements of various devices with different power consumption and working at different voltages.

[0056] The beneficial effects of the present invention are as follows:

[0057] The present invention solves the problem of transmission delay between signals of different channels through a register unit, and realizes synchronous reading of multi-channel data; solves the problem of register state recognition and control of register unit output state through a discrimination unit, an AND operation unit and a control unit, and realizes the adaptive synchronous transmission function of the register unit; solves the problem of manual control of the analog-to-digital conversion unit, the register unit and the AND operation unit through the control unit, and realizes the control of the working state of the analog-to-digital conversion unit, the control of the register unit node length and the control of the working state of the AND operation unit input path.

[0058] The various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.

[0059] The principles and implementation methods of the present invention are described in this article using specific examples. The description of the above embodiments is only used to help understand the method and core idea of ​​the present invention. At the same time, for those skilled in the art, according to the idea of ​​the present invention, there will be changes in the specific implementation methods and application scope. In summary, the content of this specification should not be understood as limiting the present invention.

Claims

1. A precision high-speed analog-to-digital synchronous conversion system, characterized in that: include: Information processing module, synchronization control module and several analog-to-digital conversion modules; Each analog-to-digital conversion module includes: a digital-to-analog conversion unit, a storage unit and a determination unit; the synchronization control module includes: a control unit and an AND operation unit; the information processing module includes: a back-end reading unit; In the same analog-to-digital conversion module, the output end of the analog-to-digital conversion unit is connected to the input end of the register unit; in the same analog-to-digital conversion module, the output end of the register unit is connected to the input end of the discrimination unit; the output ends of all the discrimination units are connected to the input end of the AND operation unit; the input ends of all the register units are respectively connected to the output end of the AND operation unit; the output end of the control unit is respectively connected to the input end of the AND operation unit, the input end of the back-end reading unit, the input ends of all the discrimination units and the input ends of all the analog-to-digital conversion units; the output ends of all the register units are connected to the input end of the back-end reading unit; the output end of the back-end reading unit is connected to the input end of the AND operation unit; The digital-to-analog conversion unit is used to convert the analog signal input by the channel into a digital signal; the register unit is used to temporarily store the digital signal; the discrimination unit is used to judge the storage state of the register unit, and output a high level when the storage state is a state of storing a node data; the control unit is used to control the working state of the digital-to-analog conversion unit, rewrite the single-node data judgment standard of the discrimination unit, control some input ends of the AND operation unit to maintain a high level according to the host computer instruction, and send a channel status instruction to the back-end reading unit; the AND operation unit is used to perform an AND operation on all input level signals of the AND operation unit, and when all input ends of the AND operation unit are high levels, control the register unit to output a signal; the back-end reading unit is used to receive the digital signal sent by the register unit according to the channel status instruction, and return the reception completion information to the AND operation unit after receiving a group of the digital signals.

2. A precise high-speed analog-to-digital synchronous conversion system according to claim 1, characterized in that: The control unit has a built-in sampling frequency pre-control sub-unit; The implementation formula of the sampling frequency pre-control subunit includes: as well as Δ(k) is the difference between the k-1th predicted frequency and the k-1th actual frequency; is the predicted frequency of the k-1th time; f0(k-1) is the actual frequency of the k-1th time; μ i is the i-th adaptive weight; N p is the adaptive sampling frequency multiplication parameter; f s (k) is the kth pre-control sampling frequency.

3. A precise high-speed analog-to-digital synchronous conversion system according to claim 2, characterized in that: The control unit also includes: a CAN communication subunit, an FPGA processing subunit, a frequency decoder, a node capacity decoder, and a channel status decoder; The input end and output end of the CAN communication subunit are respectively connected to the input end of the host computer and the FPGA processing subunit; the FPGA processing subunit is respectively connected to the input end of the sampling frequency pre-control subunit, the input end of the node capacity decoder and the input end of the channel state decoder; the output end of the sampling frequency pre-control subunit is connected to the input end of the frequency decoder; The frequency decoder is a 16-bit decoder; the channel status decoder is an N-bit decoder; the node capacity decoder is an x-bit decoder; the CAN communication subunit is used to receive control instructions from the host computer; the FPGA processing subunit is used to extract frequency instructions, node instructions and channel instructions from the control instructions, and transmit the frequency instructions, the node instructions and the channel instructions to the sampling frequency pre-control subunit, the node capacity decoder and the channel status decoder respectively; the sampling frequency pre-control subunit is used to obtain frequency control information according to the frequency instruction or the pre-control sampling frequency, and transmit the frequency control information to ... The information is transmitted to the frequency decoder; the frequency decoder is used to translate the frequency control information into a 16-bit binary electrical signal, and transmit the 16-bit binary electrical signal to the digital-to-analog conversion unit; the node capacity decoder is used to translate the node instruction into an x-bit electrical signal, and transmit the x-bit electrical signal to the register unit; the bit width of the x-bit electrical signal depends on the number of control input terminals of the register unit; the channel state decoder is used to translate the channel instruction into an N-bit electrical signal, and transmit the N-bit electrical signal to the discrimination unit; the bit width of the N-bit electrical signal depends on the number of the analog-to-digital conversion modules.

4. A precise high-speed analog-to-digital synchronous conversion system according to claim 3, characterized in that: Each of the determination units comprises: an edge trigger and a counter; The input end of the edge trigger is connected to the output end of the first register in the register unit; the input end of the counter is respectively connected to the output end of the edge trigger and the output end of the node capacity decoder; The edge trigger is used to output a high level once when detecting an edge jump of the output of the first register; the counter is used to record the number of times the edge trigger outputs a high level, and realizes adaptive output of a high level according to the x-bit electrical signal.

5. A precise high-speed analog-to-digital synchronous conversion system according to claim 4, characterized in that: The register unit includes a plurality of data registers connected in series.

6. A precise high-speed analog-to-digital synchronous conversion system according to claim 4, characterized in that: An OR operator is provided between each of the discrimination units and the AND operation unit; The input end of the OR operator is respectively connected to the output end of the discrimination unit of the channel and the output end of the channel state decoder corresponding to the channel; the output end of the OR operator is connected to the input end of the AND operation unit; The OR operator is used to control the working state of the channel according to the output level of the output end of the channel state decoder corresponding to the channel.

7. A precise high-speed analog-to-digital synchronous conversion system according to claim 5, characterized in that: The number of the data registers ranges from 9 to 20.

8. A precise high-speed analog-to-digital synchronous conversion system according to claim 5, characterized in that: The back-end reading unit is an N-way parallel synchronous reading device.

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