Method and equipment for decoding channel code by using storage and calculation integrated device

Abstract

The present invention provides a method and apparatus for decoding a channel code received from a noisy communication channel. The method comprises: demodulating the received channel code to obtain a demodulated data vector; and decoding the demodulated data vector by using a storage and calculation integrated device (CIM) to obtain one or more candidate output code words, wherein the demodulated data vector is decoded by using a guess random additive noise decoding (GRAND) algorithm to obtain candidate output code words. By implementing the GRAND using the CIM technique, the integration of storage and computing operations (e.g., multiply-add (MAC) operations on input vectors and weight matrices) in a memory cell due to the inherent small size of the memory cell relative to a logic gate enables simultaneous evaluation of multiple error patterns, thus significantly reducing worst case latency of the GRAND hardware implementation.

Description

Technical Field

[0001] The present disclosure relates to the field of data decoding. More specifically, the present disclosure relates to a method and apparatus for decoding a channel code received from a noisy communication channel using a compute-in-memory device (CIM) using a guessed random additive noise decoding (GRAND) algorithm. Background Art

[0002] Due to the emergence of applications with strict reliability and ultra-low delay requirements, the concern for short channel codes and corresponding decoding algorithms has recently arisen in the industry and academia.GRAND has been used as a universal decoding technology for linear block codes with short length and high rate. Conventionally, the hardware implementation of GRAND relies on registers, logic gates and other peripheral circuits to check multiple test error patterns for codebook membership. Such hardware implementation requires huge overhead in terms of logic gates, and complicates the interconnection circuit. Therefore, the number of error patterns that can be evaluated in parallel is limited, and this constitutes the main bottleneck of the worst-case decoding delay of the hardware implementation of GRAND. For some mission-critical applications that have a pressing requirement for ultra-low delay, it is crucial to reduce the worst-case decoding delay of the hardware implementation of GRAND. Therefore, the hardware implementation of GRAND still has room for improvement, to further reduce the worst-case decoding delay. Summary of the invention

[0003] It is an object of the present invention to provide a GRAND hardware implementation solution with reduced decoding latency.

[0004] According to a first aspect of the present invention, a device for decoding a channel code received from a noisy communication channel is provided. The device comprises: a demodulator configured to demodulate the received channel code to obtain a demodulated data vector; a syndrome computer configured to calculate a data vector syndrome for the demodulated data vector; a controller configured to receive the data vector syndromes and formulate search keywords using the data vector syndromes respectively; a storage-computation integrated device configured to: store a plurality of pre-calculated test error pattern syndromes; receive the search keywords from the controller; use the search keywords to simultaneously evaluate the plurality of test error pattern syndromes according to a codebook membership criterion; and determine the address of a candidate test error pattern corresponding to a candidate test error pattern syndrome that satisfies the codebook membership criterion; and a word generation module configured to: retrieve the index of a non-zero element of the candidate test error pattern using the determined address; and generate a candidate output codeword based on the retrieved index of the non-zero element of the test error pattern and the input data vector.

[0005] According to a second aspect of the present invention, a method for decoding a channel code received from a noisy communication channel is provided. The method comprises: demodulating the received channel code; decoding the one or more input codewords to obtain one or more candidate output codewords, decoding each input codeword using a guessed random additive noise decoding algorithm to obtain a candidate output codeword by the following operations: calculating a syndrome for an input data vector; formulating a search keyword using the data vector syndrome; evaluating multiple test error pattern syndromes according to a codebook membership criterion using the search keyword; determining an address of a candidate test error pattern corresponding to a candidate test error pattern syndrome that satisfies the codebook membership criterion; using the determined address to retrieve an index of a non-zero element of the candidate test error pattern; and generating the candidate output codeword based on the retrieved index of the non-zero element of the test error pattern and the input data vector; and wherein the multiple test error pattern syndromes are pre-calculated and stored in the storage-computation integrated device; and wherein the multiple test error pattern syndromes are evaluated simultaneously by the storage-computation integrated device based on the data vector syndrome using the codebook membership criterion.

[0006] By implementing GRAND using CIM technology, due to the inherent small size of memory cells relative to logic gates, the integration of storage and computation operations (e.g., multiplication-addition (MAC) operations on input vectors and weight matrices) in memory cells enables multiple error modes to be evaluated simultaneously in parallel, thereby significantly reducing the worst-case latency of GRAND implementation. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Embodiments of the present invention are described in more detail below with reference to the accompanying drawings, in which:

[0008] Figure 1 A flow chart showing a method implemented in a data receiver according to one embodiment of the present invention for decoding a channel code y received from a data transmitter via a noisy communication channel;

[0009] Figure 2 A very large scale integration (VLSI) architecture of an apparatus for decoding a channel code received from a noisy communication channel according to one embodiment of the present invention is shown;

[0010] Figure 3 shows a VLSI microstructure of a classifier module according to one embodiment of the present invention;

[0011] Figure 4 How to apply search keywords to a computing-in-a-box device (CIM) according to one embodiment of the present invention is shown;

[0012] Figure 5shows a VLSI microstructure of a Most Likely Candidate Selection (MLCS) module according to one embodiment of the present invention;

[0013] Figure 6 An exemplary 4×4 resistive random access memory (ReRAM) is shown;

[0014] Figure 7 Shows how to implement the GRAND algorithm on ReRAM;

[0015] Figure 8 shows an example ReRAM storing a 4×4 matrix of TEP syndromes according to one embodiment of the present invention;

[0016] Fig. 9 An exemplary implementation of the GRAND algorithm by performing a codebook membership verification process using two ReRAMs according to an embodiment of the present invention is shown;

[0017] Fig.10 shows a 4×4 content addressable memory (CAM) that can store 4 words, where each word consists of 4 bits stored in a CAM cell; and

[0018] Fig.11 An exemplary implementation of the GRAND algorithm by utilizing a CAM array is shown. DETAILED DESCRIPTION

[0019] In the following description, embodiments are described as preferred examples. It will be apparent to those skilled in the art that modifications, including additions and / or substitutions, may be made without departing from the scope and spirit of the invention. Certain details may be omitted so as not to obscure the invention; however, this disclosure is written to enable those skilled in the art to practice the teachings herein without undue experimentation.

[0020] Figure 1 A flow chart of a method S100 implemented in a data receiver according to an embodiment of the present invention is depicted, the method being used to decode a channel code y received from a data transmitter via a noisy communication channel. As shown, the method comprises:

[0021] Step S101: Demodulate the received channel code y to obtain a demodulated data vector

[0022] Step S102: Demodulate the data vector Decode to obtain one or more candidate output codewords

[0023] In step S102, the demodulated data vector is decoded by using the guessed random additive noise decoding algorithm through the following steps: Decode to obtain one or more candidate output codewords

[0024] S201: Calculate the data vector syndrome sc of the demodulated data vector;

[0025] S202: Evaluate multiple test error pattern (TEP) syndromes se based on the data vector syndrome sc using a codebook membership criterion i ;

[0026] S203: Determine an address Add of a candidate test error pattern corresponding to a candidate test error pattern syndrome satisfying a codebook membership criterion;

[0027] S204: using the determined address Add to retrieve the index of the non-zero element of the candidate test error pattern; and

[0028] S205: Retrieving index and demodulation data vector based on non-zero elements of test error pattern To generate candidate output codewords

[0029] Multiple TEP syndromes i The TEP syndromes can be pre-calculated from multiple test error patterns and stored in a computing-in-memory device (CIM); and the CIM simultaneously evaluates multiple TEP syndromes se according to the codebook membership criteria. i .

[0030] More specifically, the generated TEPe is applied to the demodulation vector And the resulting vector of verification codebook membership is used to execute the GRAND algorithm:

[0031]

[0032] where H represents the parity check matrix corresponding to the underlying linear block code.

[0033] If the codebook membership verification equation (1) is satisfied, then e is the guessed noise, and ⊕e is the estimated codeword.

[0034] To check that the Hamming weight is 1 The TEP, codebook membership verification equation (1) can be expanded as follows:

[0035]

[0036] in (denoted as sc) represents the demodulated data vector The (nk)-bit syndrome, and H·1i T (denoted as se) is a Hamming weight of 1 (1 i ) is used for TEP(e) with (nk)-bit syndrome.

[0037] In a similar way, to verify the error pattern with Hamming weight > 1, the linear property of the underlying code can be fully utilized to aggregate the Hamming weight to 1 (1 i ) and then generate t syndromes corresponding to the error pattern with Hamming weight t For example, the Hamming weight is 2 (e = 1 i,( , where i∈[1..n], j∈[1..n] and i≠j) the codebook membership of a TEP can be checked as

[0038]

[0039] Codebook membership verification (1) can be simplified to:

[0040]

[0041] This means that for any generated TEP(e), the codebook membership (1) is decomposed into the terms and For any TEP(e), if the sum Producing a (nk)-bit zero vector (0) of the TEP(e) satisfies the codebook membership.

[0042] In other words, the complement of the syndrome of the data vector can be calculated To perform codebook membership evaluation; Calculate the complement of each of the multiple TEP syndromes The plurality of TEP syndromes are stored in a first sub-memory in the CIM; the plurality of complements of the TEP syndromes are stored in a second sub-memory in the CIM; and the complement of the TEP syndromes is stored in the first sub-memory. The bitwise AND of

[0043] Next, each TEP syndrome is evaluated by performing the complement of the data vector syndrome by the second sub-memory The second intermediate output is obtained by bitwise AND with the TEP syndrome (sc) And the sum of the first intermediate output and the second intermediate output produces a zero vector In the case of , it is determined that the TEP syndrome satisfies the codebook membership criteria.

[0044] The received channel code y may be demodulated based on a hard decision algorithm during the first decoding stage to obtain a hard decision vector Next, for the hard decision vector Calculate the syndrome sc. If the syndrome sc produces 0, it means that the hard decision vector If it is noise-free and a valid codeword, the decoding is assumed to be successful. Otherwise, the decoding continues and moves to the next stage, where the received channel code y is further demodulated based on the soft decision algorithm to obtain a soft decision vector (y).

[0045] By decoding the soft decision vector (y), multiple candidate output codewords are obtained. Previously, the method also included:

[0046] S103: Arrange multiple soft decision vector elements y of the soft decision vector (y) according to the reliability order j Classification; and

[0047] S104: Return the individual elements y of the multiple soft decision vector elements respectively j Multiple sorting indexes Ind j .

[0048] In one embodiment, the reliability order can be a plurality of soft decision vector elements y j The absolute value of y j in increasing order.

[0049] By decoding the soft decision vector (y), multiple candidate output codewords are obtained. Afterwards, the method further comprises the following steps:

[0050] S105: Calculate one or more candidate output codewords The likelihood value M of each j ;

[0051] S106: Select the highest likelihood value M by comparing one or more likelihood values ​​using a comparator tree final ;as well as

[0052] S107: Identify the most likely candidate codeword with the highest likelihood value and return it as the final estimated output codeword

[0053] Figure 2 A very large scale integration (VLSI) architecture of a device 100 for decoding a channel code received from a noisy communication channel according to an embodiment of the present invention is shown. The device includes a demodulator 101, a parity check matrix memory 102, a syndrome computer 103, a controller 104, a CIM 105, and a word generation module 106.

[0054] The demodulator 101 is configured to demodulate the received channel code y to obtain a demodulated data vector

[0055] The parity check matrix memory 102 is configured to store a (nk)×n bit parity check matrix H. The syndrome computer 103 is configured to retrieve the parity check matrix H from the parity check matrix memory 102 and apply the parity check matrix H to the hard decision vector To calculate the (nk)-bit data vector syndrome sc.

[0056] The controller 104 is configured to receive the data vector syndrome sc and formulate a search key S_key to perform codebook membership evaluation, respectively.

[0057] The CIM 105 may be configured to store a plurality of pre-computed TEP syndromes. i ; receiving a search keyword S_key and using the search keyword S_key to simultaneously evaluate multiple TEP syndromes se according to the codebook membership criteria i ; and determining an address Add of a candidate TEP corresponding to a candidate TEP syndrome satisfying the codebook membership criteria.

[0058] The word generation module 106 is configured to: retrieve the index of the non-zero element of the candidate TEP from the index memory 107 using the determined address Add; and based on the retrieved index of the non-zero element of the candidate TEP and the hard decision vector Generate candidate output codewords

[0059] The demodulator 101 may be configured to demodulate the received channel code y based on a hard decision algorithm to obtain a hard decision (or hard input) vector.

[0060] In an exemplary embodiment of the soft-input GRAND, the demodulator 101 may be further configured to demodulate the received channel code based on a soft decision algorithm to obtain a soft decision (or soft input) vector.

[0061] The apparatus 100 may further include a device configured to convert the element y of the soft decision vector j Classification module 108 (such as Figure 3 ).

[0062] More specifically, the classifier module 108 may be configured to: j The reliability order of multiple soft decision vector elements y j Classification; and return multiple soft decision vector elements y respectively j Multiple sorted indexes

[0063] The controller 104 may also be configured to calculate a plurality of candidate output codewords The likelihood value M of each j .

[0064] The apparatus 100 further comprises a most likely candidate selection (MLCS) module 109 configured to select a plurality of likelihood values ​​M by using a comparator tree. j Compare and select the highest likelihood value M final And select the likelihood value M final Return to the controller. The controller 104 is then further configured to select a plurality of candidate output code words generated by the word generation module 106. The most likely candidate codeword with the highest likelihood value is identified as the final estimated codeword

[0065] In some embodiments, Figure 3 As shown, the classifier module 108 may also be configured to receive the parity check matrix H from the parity check matrix memory and generate a plurality of classified TEP syndromes.

[0066] Therefore, the controller 104 may also be configured to receive the classified TEP syndrome se i * , and using the data vector syndrome s C and sorted TEP syndrome se i * To specify the search keyword S_key.

[0067] CIM 105 may be configured to store i,( , where i∈[1..n], j∈[1..n] and i≠j) is the error pattern associated with all (nk) bit syndromes (se i ⊕se j ). For a linear block code of length n, there exists a code with Hamming weight 2 TEP. This is calculated offline using H TEP syndromes are stored in CIM 105, such as Figure 4 The syndrome stored in CIM 105 i ⊕se j ) depends only on H and is not affected by the classifier module; therefore, the content of CIM 105 does not change with each channel code received from the channel.

[0068] CIM 105 can be configured to generate multiple output parity bits So that:

[0069]

[0070] The parity bit p output by CIM 105 k is transmitted to the MLCS module 109. The MLCS module 109 finds the most likely codeword from the candidate codewords that satisfy the codebook membership constraint, i.e., by solving the following problem:

[0071] The candidate codewords correspond to CIM entries that match the applied search keyword (p . =1).

[0072] Figure 5 The micro-architecture of the MLCS module 109 is shown, which receives the likelihood value from the controller and the parity bit p from CIM k , The likelihood value of the candidate codeword (M Candidates ) is calculated as follows:

[0073]

[0074] Where i∈[1..n], j∈[1..n] and i≠j.

[0075] Use the comparator tree via The candidate object M is selected in the stage Candidates The highest likelihood value M final Then the highest likelihood value M final Forwarded to controller 104 (see Figure 2 ), the controller generates the final estimated codeword

[0076] In one exemplary embodiment, the simplified codebook membership verification (4) may be implemented by using a non-volatile resistive random access memory (ReRAM) based CIM. Figure 6 An exemplary 4×4 ReRAM is shown, which is configured to facilitate input vector with the matrix elements stored in memory The output of ReRAM is the MAC output.

[0077] Figure 7 Shows how to implement the GRAND algorithm on ReRAM. Precomputed TEP syndrome se i,jThe (n–k)×Q matrix (where i∈[1..(n–k)], j∈[1..Q]) of the channel code is stored in the ReRAM, and the syndrome (sc) of the received channel code is applied to the ReRAMs input. The parameter Q represents the maximum number of TEPs.

[0078] In addition, each element of both the TEP syndrome se and the data vector syndrome sc is either 0 or 1 and The high resistance state or the low resistance state of the ReRAM can be used to represent a 0 or a 1 of the ReRAM.

[0079] MAC gets the In addition, at each output MAC result The current sense amplifier is used at the i The generated current I i Below a certain threshold I th , then the output of the sense amplifier p i (p i ∈[0,1]) is 0. Symbol p i represents the output of the sense amplifier and is given by:

[0080]

[0081] Figure 8 Shows storage of TEP syndrome se i,j An example ReRAM with a 4×4 matrix (where i∈[1..4], j∈[1..4]). At the input of the ReRAM, the syndrome sc of the received channel code is applied. If the input vector sc i , If any element of is 0, the corresponding word line in the ReRAM is inactive. It depends on whether the output current Ii of the bit line is below or above a certain threshold I th , sense amplifier deployed at the ReRAM output (MAC result Produces 0 or 1.

[0082] like Figure 5 As can be seen in FIG. 1 , the second output (p2=0) produces 0 because the MAC result of sc (sc=[1 0 1 0]) and se (se=[0 0 01]) is 0 (o ％ =1×0+0×0+1×0+0×1=0), while all other outputs generate 1.

[0083] Fig. 9An exemplary implementation of the GRAND algorithm by using two ReRAMs to perform the simplified codebook membership verification described above is shown. As shown, the first ReRAM (ReRAM1) receives the complement syndrome As input, it stores the (nk)×Q bit matrix of the TEP syndrome (se), while the second ReRAM (ReRAM2) receives sc as input and stores the complement of the TEP syndrome A (nk)×Q-bit matrix.

[0084] The outputs of the first and second ReRAMs (p i ) are NOR merged and fed to the Q to log2(Q) priority encoder (PE). Note that the output of the NOR will be 1 if and only if any TEP syndrome (se) stored in the ReRAM satisfies the codebook membership criteria (4). The priority encoder will output the log2(Q)-bit address of the first TEP syndrome (se) that has satisfied the simplified codebook membership criteria, and the address can be used to retrieve the corresponding TEP syndrome from the memory.

[0085] Return to reference Figure 2 , a log2(Q) bit address can be used to access the index memory 107 (see Figure 2 ) and retrieves the index of the non-zero element of TEP. The word generation module 106 uses the HW×log2(n) bit index vector output by the index memory 107, where HW is the Hamming weight of TEP(e), to flip the hard decision vector from the communication channel and generate the estimated codeword

[0086] In some embodiments, the TEP syndromes may be sorted into one or more subsets according to the Hamming weights of the corresponding TEPs. The one or more subsets of the TEP syndromes are stored in one or more sub-memories, respectively. And the one or more subsets of the TEP syndromes are evaluated by the one or more sub-memories, respectively, based on the data vector syndromes using the codebook membership criteria.

[0087] In one exemplary embodiment, a subset of TEP syndromes may be stored and evaluated by using a volatile content addressable memory (CAM) based CIM.

[0088] Fig.10A 4×4 CAM is shown that can store 4 words, where each word consists of 4 bits stored in a CAM cell. The CAM is equipped with differential search lines (SL), match lines (ML), match line sense amplifiers (ML-SA), and an address encoder (AE). The search process for the CAM begins with loading the search data (search key) into the search register (SR), followed by precharging the match lines to a high state and broadcasting the search word on the differential search lines. If the search key matches any of the CAM words, the corresponding ML remains charged, while all other MLs are discharged. The corresponding address of the matching word is then output by the address encoder.

[0089] Fig.11 An exemplary implementation of the GRAND algorithm using an array of Q×(nk)-bit CAMs is shown, where Q is the CAM depth and (nk) is the CAM width. Each CAM is configured to store a subset of the TEP syndrome (se) The syndrome (sc) of the channel code received from the communication channel is loaded into the search register as the search key. If the search key (sc) matches any TEP syndrome (se) in the CAM, the corresponding match line remains charged, while all other match lines are discharged. The address encoder (AE) returns the address of the corresponding matching TEP syndrome. In each clock cycle, the controller 104 activates a single CAM, and the search key (sc) is then applied to that particular CAM. A total of P clock cycles are required to search the search key across all P CAMs. If the search key (sc) is found in any of the P CAM modules, then A multiplexer may be used to retrieve the address of a matching TEP syndrome (se).

[0090] The functional units and modules according to the embodiments disclosed herein can be implemented using a computing device, a computer processor or an electronic circuit system, including but not limited to an application specific integrated circuit (ASIC), a field programmable gate array (FPGA), a microcontroller and other programmable logic devices configured or programmed according to the teachings of the present disclosure. The computer instructions or software codes running in the computing device, computer processor or programmable logic device can be easily made by practitioners in the field of software or electronic technology based on the teachings of the present disclosure.

[0091] All or part of the method according to the embodiment may be executed in one or more computing devices including a server computer, a personal computer, a notebook computer, a mobile computing device (eg, a smart phone), and a tablet computer.

[0092] Embodiments may include computer storage media, transient and non-transitory memory devices having computer instructions or software codes stored therein that may be used to program or configure a computing device, a computer processor, or an electronic circuit system to perform any of the processes of the present invention. Storage media, transient and non-transitory memory devices may include, but are not limited to, floppy disks, optical disks, Blu-ray disks, DVDs, CD-ROMs and magneto-optical disks, ROMs, RAMs, flash memory devices, or any type of medium or device suitable for storing instructions, codes, and / or data.

[0093] Each of the functional units and modules according to various embodiments may also be implemented in a distributed computing environment and / or a cloud computing environment, where all or part of the machine instructions are executed in a distributed manner by one or more processing devices interconnected by a communication network, such as an intranet, a wide area network (WAN), a local area network (LAN), the Internet, and other forms of data transmission media.

[0094] The foregoing description of the present invention has been provided for the purpose of illustration and description. This description is not intended to be exhaustive or to limit the invention to the precise form disclosed. Many modifications and variations will be apparent to practitioners in the art.

[0095] The embodiment was chosen and described in order to best explain the principles of the invention and its practical application, thereby enabling others skilled in the art to understand the invention for various embodiments and with various modifications as are suited to the particular use contemplated.

Claims

1. A device for decoding a channel code received from a noisy communication channel, the device comprising: a demodulator configured to demodulate the received channel code to obtain a demodulated data vector; a syndrome computer configured to calculate a data vector syndrome for the demodulated data vector; A controller configured to receive the data vector syndromes and formulate search keywords using the data vector syndromes respectively; A storage and computing integrated device, which is configured to: storing a plurality of pre-computed test error pattern syndromes; receiving the search keyword from the controller; simultaneously evaluating the plurality of test error pattern syndromes according to a codebook membership criterion using the search keyword; as well as determining an address of a candidate test error pattern corresponding to a candidate test error pattern syndrome that satisfies the codebook membership criteria; and A word generation module is configured to: retrieving an index of a non-zero element of the candidate test error pattern using the determined address; as well as A candidate output codeword is generated based on the retrieved indices of the non-zero elements of the test error pattern and the input data vector.

2. The device according to claim 1, characterized in that The demodulator is configured to demodulate the received channel code based on a hard decision algorithm to obtain a hard decision vector.

3. The device according to claim 1, characterized in that The demodulator is configured to demodulate the received channel code based on a soft decision algorithm to obtain a soft decision vector; and The apparatus also includes a classifier module configured to: classify the individual elements of the soft decision vector according to a reliability order of the plurality of individual elements of the soft decision vector; and respectively return a plurality of sorted indexes of the plurality of individual elements of the soft decision vector.

4. The device according to claim 3, characterized in that The reliability order is the increasing order of the absolute values ​​of the individual elements of the soft decision vector.

5. The device according to claim 3, characterized in that The controller is further configured to calculate a likelihood value for each of the one or more candidate output codewords based on the corresponding demodulated data vector; The apparatus further comprises a most likely candidate selection module configured to select a highest likelihood value by comparing one or more likelihood values ​​using a comparator tree; and The controller is further configured to identify a most likely candidate codeword having the highest likelihood value among the one or more candidate output codewords.

6. The device according to claim 1, characterized in that The plurality of test error pattern syndromes are sorted into one or more subsets according to Hamming weights corresponding to the test error pattern syndromes; and The storage-computing integrated device includes one or more sub-memory devices, each of which is configured as follows: storing a corresponding test error pattern check subset; as well as The corresponding test error pattern syndrome subset is evaluated using the codebook membership criterion based on the channel codeword syndrome.

7. The device according to claim 6, characterized in that The storage-computing integrated device also includes one or more address encoders, each address encoder is coupled to a corresponding sub-memory and is configured to generate an address of a test error pattern of a test error pattern check sub-set that satisfies the code book membership criteria among the test error pattern check sub-sets stored in the corresponding sub-memory.

8. The device according to claim 7, characterized in that Each of the one or more sub-memories is a content addressable memory.

9. The device according to claim 1, characterized in that The controller is further configured to calculate the complement of the syndrome of the data vector; The storage-computing integrated device comprises: A first sub-memory configured to store the plurality of test error pattern syndromes; and A second sub-memory configured to store a plurality of complements of the test error pattern syndrome; A priority encoder is configured to determine the test error pattern syndrome as the candidate test error pattern syndrome that satisfies the codebook membership criterion.

10. The device according to claim 9, characterized in that The first sub-memory is further configured to, for each test error pattern syndrome, perform a bitwise AND operation on the data vector syndrome and the complement of the test error pattern syndrome to obtain a first intermediate output; The second sub-memory is further configured to, for each test error pattern syndrome, perform a bitwise AND operation on the complement of the data vector syndrome and the test error pattern syndrome to obtain a second intermediate output; and The priority encoder is further configured to, if summing the first intermediate output and the second intermediate output produces a zero vector, determine that the test error pattern syndrome is the candidate test error pattern syndrome.

11. The device according to claim 10, characterized in that Each of the first sub-memory and the second sub-memory is a resistive random access memory.

12. A method for decoding a channel code received from a noisy communication channel, characterized in that The method comprises: Demodulating the received channel code; The one or more input codewords are decoded to obtain one or more candidate output codewords, and each input codeword is decoded to obtain a candidate output codeword using a guessed random additive noise decoding algorithm by the following operations: calculating a syndrome for an input data vector; Formulate a search keyword using the data vector syndrome; evaluating a plurality of test error pattern syndromes according to a codebook membership criterion using the search keyword; determining an address of a candidate test error pattern corresponding to a candidate test error pattern syndrome that satisfies the codebook membership criteria; retrieving an index of a non-zero element of the candidate test error pattern using the determined address; and generating the candidate output codeword based on the retrieved indices of the non-zero elements of the test error pattern and the input data vector; and wherein the plurality of test error pattern syndromes are pre-calculated and stored in the storage-computation integrated device; and The plurality of test error pattern syndromes are simultaneously evaluated by the integrated storage and computing device based on the data vector syndrome using the codebook membership criteria.

13. The method according to claim 12, characterized in that The received channel code is demodulated based on a hard decision algorithm to obtain a hard decision vector as input data.

14. The method according to claim 12, characterized in that Demodulating the received channel code based on a soft decision algorithm to obtain a soft decision vector as input data; as well as sorting the plurality of individual elements of the soft decision vector according to an order of reliability; A plurality of sorted indices of the individual elements of the soft decision vector are returned respectively.

15. The method according to claim 14, characterized in that The reliability order is an increasing order of absolute values ​​of the plurality of the individual elements of the soft decision vector.

16. The method according to claim 14, characterized in that The method further comprises obtaining the plurality of candidate output codewords after decoding the received channel code from the communication channel: calculating a likelihood value for each of the plurality of candidate output codewords; selecting a highest likelihood value by comparing the likelihood values ​​using a comparator tree; as well as A most likely candidate output codeword having the highest likelihood value is identified among the candidate output codewords.

17. The method according to claim 12, characterized in that Also includes: sorting the plurality of test error pattern syndromes into one or more subsets; storing the one or more subsets of the test error pattern syndromes in one or more sub-memories in the storage-computation integrated device respectively; The one or more subsets of test error pattern syndromes are respectively evaluated by the one or more sub-memories based on the data vector syndromes using the codebook membership criterion.

18. The method according to claim 17, characterized in that The plurality of test error pattern syndromes are sorted according to the Hamming weights of the corresponding test error patterns.

19. The method according to claim 17, characterized in that Also includes: Calculating the complement of the channel codeword syndrome; calculating the complement of each of the plurality of test error pattern syndromes; Storing the plurality of test error pattern syndromes in a first sub-memory in the storage-computation-in-one device; The multiple complements of the test error pattern syndrome are stored in the second sub-memory in the storage-computation integrated device.

20. The method according to claim 19, characterized in that Each test error pattern syndrome is evaluated by: Obtaining a first intermediate output by performing, by the first sub-memory, a bitwise AND of the channel codeword syndrome and the complement of the test error pattern syndrome; Obtaining a second intermediate output by performing a bitwise AND of the complement of the channel codeword syndrome and the test error pattern syndrome by the second sub-memory; The test error pattern syndrome is determined to satisfy the codebook membership criterion if summing the first intermediate output and the second intermediate output produces a zero vector.

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