Image sensing apparatus and imaging apparatus including same

Abstract

The invention relates to an image sensing device and an imaging device including the same. An image sensing apparatus includes: a pixel configured to output a reference signal corresponding to a sensing node that is reset and an image signal corresponding to a sensing node in which photoelectric charges are accumulated in each of a high conversion gain (HCG) mode and a low conversion gain (LCG) mode; an analog-to-digital converter (ADC) configured to perform analog-to-digital conversion on the reference signal of the HCG mode, the image signal of the HCG mode, the image signal of the LCG mode, and the reference signal of the LCG mode in sequence; and a ramp generator configured to generate a first ramp signal for analog-to-digital conversion in an HCG mode and generate a second ramp signal for analog-to-digital conversion in an LCG mode, the second ramp signal having a waveform different from a waveform of the first ramp signal.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This patent document claims priority to and the benefit of Korean Patent Application No. 10-2023-0073621, filed on June 8, 2023, the disclosure of which is incorporated herein by reference in its entirety as a part of the disclosure of this patent document. Technical Field

[0003] The technologies and implementations disclosed in this patent document generally relate to an image sensing device capable of generating a high dynamic range (HDR) image and an imaging device including the same. Background Art

[0004] Image sensing devices are devices that capture optical images by converting light into electrical signals using photosensitive semiconductor materials that react to light. With the development of the automotive, medical, computer and communication industries, the demand for high-performance image sensing devices is increasing in corresponding fields such as smartphones, digital cameras, game consoles, IoT (Internet of Things), robots, surveillance cameras and medical micro cameras.

[0005] In recent years, in order to provide high-quality images, interest in HDR images has rapidly increased, and a variety of technologies capable of acquiring HDR images are being developed. Among these technologies, a technology for changing the conversion gain of a pixel that detects incident light and converts the incident light into an electrical signal can acquire an image relatively accurately for each of high illumination and low illumination, but there is a problem of consuming more resources for hardware implementation of high illumination and low illumination images. Summary of the invention

[0006] According to an embodiment of the disclosed technology, an image sensing device may include: a pixel configured to: in each of a high conversion gain (HCG) mode and a low conversion gain (LCG) mode, output not only a reference signal corresponding to a reset sensing node, but also an image signal corresponding to a sensing node having accumulated photocharge, wherein in the HCG mode, the sensing node has a first capacitance, and in the LCG mode, the sensing node has a second capacitance greater than the first capacitance; an analog-to-digital converter (ADC) configured to sequentially perform analog-to-digital conversion on a reference signal of the HCG mode, an image signal of the HCG mode, an image signal of the LCG mode, and a reference signal of the LCG mode; and a ramp generator configured to generate a first ramp signal for analog-to-digital conversion in the HCG mode, and to generate a second ramp signal for analog-to-digital conversion in the LCG mode, and the second ramp signal has a waveform different from that of the first ramp signal.

[0007] According to another embodiment of the disclosed technology, an imaging device may include: an image sensing device configured to generate image data based on each of a reference signal corresponding to a reset sensing node and an image signal corresponding to a sensing node that has accumulated photocharges in each of a high conversion gain (HCG) mode and a low conversion gain (LCG) mode, wherein the sensing node has a first capacitance in the HCG mode and a second capacitance greater than the first capacitance in the LCG mode; and an image signal processor configured to generate a high dynamic range (HDR) image using the image data generated in the HCG mode and the image data generated in the LCG mode. The image sensing device may include: an analog-to-digital converter (ADC) configured to perform analog-to-digital conversion on a reference signal of the HCG mode, an image signal of the HCG mode, an image signal of the LCG mode, and a reference signal of the LCG mode in sequence; and a ramp generator configured to generate a first ramp signal for analog-to-digital conversion in the HCG mode, and a second ramp signal for analog-to-digital conversion in the LCG mode, wherein the second ramp signal has a waveform different from that of the first ramp signal.

[0008] According to another embodiment of the disclosed technology, an imaging device may include: a pixel configured to: output a reference signal corresponding to a reset sensing node and an image signal corresponding to a sensing node that has accumulated photocharge in each of a high conversion gain (HCG) mode and a low conversion gain (LCG) mode, wherein the sensing node has a first capacitance in the HCG mode and a second capacitance greater than the first capacitance in the LCG mode; an analog-to-digital converter (ADC) configured to sequentially perform analog-to-digital conversion on a reference signal of the HCG mode, an image signal of the HCG mode, an image signal of the LCG mode, and a reference signal of the LCG mode; and a ramp generator configured to generate a first ramp signal for analog-to-digital conversion in the HCG mode and a second ramp signal for analog-to-digital conversion in the LCG mode. Each of the first ramp signal and the second ramp signal may have a negative slope. In addition, the voltage level at which the second ramp signal starts to fall for reading out the image signal of the LCG mode is lower than the voltage level at which the second ramp signal starts to fall for reading out the reference signal of the LCG mode by a signal offset. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] The above and other features and advantageous aspects of the disclosed technology will become readily apparent with reference to the following detailed description when considered in conjunction with the accompanying drawings.

[0010] Figure 1 is a block diagram illustrating an example of an imaging device based on some implementations of the disclosed technology.

[0011] Figure 2 Some implementations based on the disclosed technology are shown Figure 1 A circuit diagram of an example of pixels included in a pixel array shown in FIG.

[0012] Figure 3 is a graph showing an example of the response of a high conversion gain (HCG) pixel and a low conversion gain (LCG) pixel in terms of brightness based on some implementations of the disclosed technology.

[0013] Figure 4 is a circuit diagram illustrating an example of an analog-to-digital converter (ADC) based on some implementations of the disclosed technology.

[0014] Figure 5 Some implementations based on the disclosed technology are shown Figure 4 An example of a ramp generator is shown in the diagram.

[0015] Figure 6 Some implementations based on the disclosed technology are shown Figure 4 A schematic diagram of another example of a ramp generator is shown in FIG.

[0016] Figure 7 is a diagram showing some implementations based on the disclosed technology. Figure 4 A timing diagram of an example operation of an analog-to-digital converter (ADC) to convert a pixel signal into image data is shown.

[0017] Figure 8 Some implementations based on the disclosed technology are shown Figure 4 Another example of a ramp generator is shown in FIG.

[0018] Fig. 9 is a diagram showing some implementations based on the disclosed technology. Figure 8 A timing diagram of an example operation of an analog-to-digital converter (ADC) to convert a pixel signal into image data is shown.

[0019] Fig.10 is a schematic diagram illustrating an example of an analog-to-digital converter (ADC) based on some implementations of the disclosed technology.

[0020] Fig.11 is a schematic diagram illustrating another example of an analog-to-digital converter (ADC) based on some implementations of the disclosed technology.

[0021] Fig.12 It is a method to illustrate some implementations based on the disclosed technology. Fig.10 or Fig.11 A timing diagram of an example operation of an analog-to-digital converter (ADC) to convert a pixel signal into image data is shown. DETAILED DESCRIPTION

[0022] This patent document provides implementations and examples of image sensing devices capable of generating high dynamic range (HDR) images and imaging devices including the same, which can be used in a configuration to substantially solve one or more technical or engineering problems and alleviate limitations or shortcomings encountered in certain image sensing devices in the art. Some implementations of the disclosed technology relate to image sensing devices and imaging devices including the same that can generate high dynamic range (HDR) images using relatively simple hardware. The disclosed technology provides multiple implementations of image sensing devices and imaging devices including the same, which can perform analog-to-digital conversion using a pair of a comparator and a counter for each column line (or each pixel) of a pixel array, thereby significantly reducing the size of the analog-to-digital converter (ADC).

[0023] Reference will now be made in detail to embodiments of the disclosed technology, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numerals will be used throughout the accompanying drawings to refer to the same or similar parts. Although the present disclosure is susceptible to various modifications and alternative forms, specific embodiments thereof are illustrated by way of example in the accompanying drawings. However, the present disclosure should not be construed as being limited to the embodiments set forth herein.

[0024] Hereinafter, various embodiments will be described with reference to the accompanying drawings. However, it should be understood that the disclosed technology is not limited to specific embodiments, but includes various modifications, equivalents and / or alternatives of the embodiments. Embodiments of the disclosed technology can provide various effects that can be directly or indirectly recognized by the disclosed technology.

[0025] Various embodiments of the disclosed technology relate to image sensing devices and imaging devices including the same that can generate high dynamic range (HDR) images using relatively simple hardware. It should be understood that the above general description of the disclosed technology and the following detailed description are illustrative and explanatory and are intended to provide further explanation of the disclosure claimed.

[0026] Figure 1 is a block diagram illustrating an example of an imaging device 10 based on some implementations of the disclosed technology.

[0027] Reference Figure 1 The imaging device 10 may refer to a device such as a digital still camera for capturing still images or a digital video camera for capturing moving images. For example, the imaging device 10 may be implemented as a digital single-lens reflex (DSLR) camera, a mirrorless camera, or a smartphone, etc. The imaging device 10 may include a device having both a lens and an image pickup element so that the device can capture (or capture) a target object and thus can create an image of the target object.

[0028] The imaging device 10 may include an image sensing device 100 and an image signal processor (ISP) 200 .

[0029] The image sensing device 100 may be a complementary metal oxide semiconductor image sensor (CIS) for converting incident light into an electrical signal. The image sensing device 100 may include a pixel array 110, a row driver 120, a ramp generator 130, an analog-to-digital converter (ADC) 140, an output buffer 150, a column driver 160, and a timing controller 170. Figure 1 The components of image sensing device 100 shown are discussed only by way of example, and this patent document also includes many other changes, substitutions, variations, changes, and modifications.

[0030] The pixel array 110 may include a plurality of imaging pixels arranged in rows and columns. In one example, the plurality of imaging pixels may be arranged into a two-dimensional (2D) pixel array including rows and columns. In another example, the plurality of imaging pixels may be arranged into a three-dimensional (3D) pixel array. The plurality of imaging pixels may convert optical signals into electrical signals on a unit pixel basis or on a pixel group basis, wherein the pixels in the pixel group share at least some internal circuit. The pixel array 110 may receive a drive signal from a row driver 120, including a row selection signal, a pixel reset signal, and a transfer signal. Upon receiving the drive signal, the corresponding imaging pixel in the pixel array 110 may be activated to perform operations corresponding to the row selection signal, the pixel reset signal, and the transfer signal.

[0031] Each pixel of the pixel array 110 may have at least two or more different sensitivities. Here, sensitivity may refer to an increment (or an increment of response) of the image data IDATA relative to an increment of the incident light intensity. That is, as the sensitivity increases, the amount of increase in the image data IDATA in response to an increase in the incident light intensity also increases. As the sensitivity decreases, the amount of increase in the image data IDATA in response to an increase in the incident light intensity decreases. In some implementations, the term "sensitivity" may be determined by a conversion gain.

[0032] Based on the command and control signals provided by the controller circuit such as the timing controller 170, the row driver 120 can activate the pixel array 110 to perform certain operations on the imaging pixels in the corresponding row. In some implementations, the row driver 120 can select one or more imaging pixels arranged in one or more rows of the pixel array 110. The row driver 120 can generate a row selection signal to select one or more rows among the plurality of rows. The row driver 120 can sequentially enable a pixel reset signal for resetting the imaging pixels corresponding to at least one selected row, and a transfer signal for the pixels corresponding to at least one selected row. Therefore, the reference signal and the image signal, which are analog signals generated by each of the imaging pixels in the selected row, can be sequentially transferred to the ADC 140. The reference signal can be an electrical signal provided to the ADC 140 when the sensing node (e.g., floating diffusion node) of the imaging pixel is reset, and the image signal can be an electrical signal provided to the ADC 140 when the photocharge generated by the imaging pixel is accumulated in the sensing node. As required, the reference signal indicating the unique reset noise of each pixel and the image signal indicating the intensity of the incident light can be collectively referred to as a pixel signal.

[0033] CMOS image sensors may use correlated double sampling (CDS) to remove undesired offset values ​​of pixels known as fixed pattern noise by sampling the pixel signal twice and removing the difference between the two samples. In one example, correlated double sampling (CDS) may remove undesired offset values ​​of pixels by comparing the pixel output voltages obtained before and after the accumulation of photocharges generated by incident light at the sensing node, thereby measuring only the pixel output voltage based on the incident light. In some embodiments of the disclosed technology, ADC 140 may sequentially sample and hold the voltage levels of the reference signal and the image signal provided from pixel array 110 to each of the plurality of column lines.

[0034] The ramp generator 130 may generate a ramp signal required for an analog-to-digital conversion (ADC) operation of the ADC 140 under the control of the timing controller 170 , and may provide the generated ramp signal to the ADC 140 .

[0035] ADC 140 may sample and hold the pixel signal of each column based on the pixel signal received from each column line of pixel array 110, may convert the resulting signal into a digital signal, and may output the digital signal. In some implementations, ADC 140 may be implemented as a ramp comparison ADC. The ramp comparison ADC may include: a comparator circuit for comparing an analog pixel signal with a ramp signal that ramps up or down according to time; and a timer (or counter) for performing counting until the voltage of the ramp signal matches the analog pixel signal.

[0036] The output buffer 150 may temporarily save the column-based image data (i.e., data (IDATA) obtained by analog-to-digital conversion of the pixel signal) provided from the ADC 140 to output the image data. In one example, the image data provided from the ADC 140 to the output buffer 150 may be temporarily stored in the output buffer 150 based on a control signal of the timing controller 170. The output buffer 150 may provide an interface to compensate for a data rate difference or a transmission rate difference between the image sensing device 100 and other devices.

[0037] The column driver 160 may select a column of the output buffer based on receiving a control signal from the timing controller 170, and may sequentially output the image data (IDATA) temporarily stored in the selected column of the output buffer 150. In some implementations, based on receiving an address signal from the timing controller 170, the column driver 160 may generate a column selection signal based on the address signal, and may select a column of the output buffer 150, thereby outputting the image data (IDATA) from the selected column of the output buffer 150 as an output signal.

[0038] The timing controller 170 may control operations of the row driver 120 , the ramp generator 130 , the ADC 140 , the output buffer 150 , and the column driver 160 .

[0039] The timing controller 170 may provide clock signals required for the operation of the corresponding components of the image sensing device 100, control signals for timing control, and address signals for selecting rows or columns to the row driver 120, the ramp generator 130, the ADC 140, the output buffer 150, and the column driver 160. In an embodiment of the disclosed technology, the timing controller 170 may include a logic control circuit, a phase-locked loop (PLL) circuit, a timing control circuit, and a communication interface circuit, etc.

[0040] The ISP 200 may perform image processing on the image data received from the image sensing device 100. The ISP 200 may reduce the noise of the image data, and may perform a variety of image signal processing (e.g., interpolation, synthesis, gamma correction, color filter array interpolation, color / tone correction using a color correction matrix (CCM), color correction, color enhancement, lens distortion correction, etc.) for improving the image quality of the image data. In addition, the ISP 200 may compress the image data that has been created by performing image signal processing for improving the image quality, so that the ISP 200 may create an image file using the compressed image data. Alternatively, the ISP 200 may restore the image data from the image file. In this case, the scheme for compressing such image data may be a reversible format or an irreversible format. As a representative example of such a compression format, in the case of using a static image, a Joint Photographic Experts Group (JPEG) format, a JPEG 2000 format, etc. may be used. In addition, in the case of using a moving image, a plurality of frames may be compressed according to the Moving Picture Experts Group (MPEG) standard, so that a moving image file may be created. For example, an image file may be created according to the Exchangeable Image File Format (Exif) standard.

[0041] The image signal processor (ISP) 200 may generate an HDR image by synthesizing at least two images with different sensitivities. For example, the image sensing device 100 may output a low sensitivity image generated by low sensitivity pixels (i.e., low conversion gain pixels) having relatively low sensitivity and a high sensitivity image generated by high sensitivity pixels (i.e., high conversion gain pixels) having relatively high sensitivity. The image signal processor (ISP) 200 may merge the low sensitivity image and the high sensitivity image to form an HDR image. Here, low sensitivity and high sensitivity may correspond to relative concepts, the image sensing device 100 may generate image data (IDATA) having at least N different sensitivities (where N is an integer of 2 or greater), and the image sensing processor 200 may use the resulting image data (IDATA) to generate an HDR image.

[0042] The ISP 200 may transmit the ISP image data to a host device (not shown). The host device (not shown) may be a processor (e.g., an application processor) for processing the ISP image data received from the ISP 200, a memory (e.g., a nonvolatile memory) for storing the ISP image data, or a display device (e.g., a liquid crystal display (LCD)) for visually displaying the ISP image data.

[0043] In addition, the ISP 200 may transmit a control signal for controlling the operation (eg, whether to operate, operation timing, operation mode, etc.) of the image sensing device 100 to the image sensing device 100 .

[0044] Figure 2 Some implementations based on the disclosed technology are shown Figure 1 1 is a circuit diagram of an example of a pixel included in the pixel array 110 shown in FIG.

[0045] refer to Figure 2 , the pixel (PX) may be any one of a plurality of pixels included in the pixel array 110. Although for ease of description Figure 2 Only one pixel (PX) is shown, but other implementations are possible, and it should be noted that other pixels may also have substantially the same structure and operation as the pixel (PX) without departing from the scope or spirit of the disclosed technology.

[0046] The pixel (PX) may include a photoelectric conversion element (PD), a transfer transistor (TX), a reset transistor (RX), a floating diffusion region (FD), a dual conversion gain (DCG) transistor (DCX), a first capacitor and a second capacitor (C1-C2), a source follower transistor (SF), and a selection transistor (SX). Figure 4 It is shown that the pixel (PX) includes only one photoelectric conversion element (PD), but other implementations are possible, and it should be noted that the pixel (PX) can also be a shared pixel including multiple photoelectric conversion elements. In this case, multiple transfer transistors can be provided to correspond to the photoelectric conversion elements respectively.

[0047] Each photoelectric conversion element (PD) can generate and accumulate photocharges corresponding to the incident light intensity. For example, each photoelectric conversion element (PD) can be implemented as a photodiode, a phototransistor, a photogate, a pinned photodiode, or a combination thereof.

[0048] If the photoelectric conversion element (PD) is implemented as a photodiode, the photoelectric conversion element (PD) may be a region in which a second conductive impurity (eg, N-type impurity) is doped in a substrate including a first conductive impurity (eg, P-type impurity).

[0049] The transfer transistor (TX) may be coupled between the photoelectric conversion element (PD) and the floating diffusion region (FD). The transfer transistor (TX) may be turned on or off in response to a transfer control signal (TG). If the transfer transistor (TX) is turned on, photocharges accumulated in the corresponding photoelectric conversion element (PD) may be transferred to the floating diffusion region (FD).

[0050] The reset transistor (RX) may be disposed between the floating diffusion region (FD) and the power supply voltage (VDD), and a voltage of the floating diffusion region (FD) may be reset to the power supply voltage (VDD) in response to a reset control signal (RG).

[0051] The floating diffusion region (FD) may accumulate photocharges received from the transfer transistor (TX). The floating diffusion region (FD) may be coupled to a first capacitor (C1) connected to a ground terminal. For example, the floating diffusion region (FD) may be a region doped with a second conductive impurity (e.g., an N-type impurity) in a substrate (e.g., a P-type substrate) including a first conductive impurity. In this case, the substrate and the impurity-doped region may be modeled as a first capacitor (C1) as a junction capacitor. The floating diffusion region (FD) may be referred to as a sensing node.

[0052] The DCG transistor (DCX) may be coupled between the floating diffusion region (FD) and the second capacitor (C2), and may selectively connect the second capacitor (C2) to the floating diffusion region (FD) in response to a DCG control signal (CG). The second capacitor (C2) may include at least one of a metal-insulator-metal (MIM) capacitor, a metal-insulator-polysilicon (MIP) capacitor, a metal-oxide-semiconductor (MOS) capacitor, and a junction capacitor. When the DCG transistor (DCX) is turned off, the floating diffusion region (FD) may have an electrostatic capacitance (or a first electrostatic capacitance) corresponding to the capacitance of the first capacitor (C1). When the DCG transistor (DCX) is turned on, the floating diffusion region (FD) may have a capacitance corresponding to the sum of the capacitance of the first capacitor (C1) and the capacitance of the second capacitor (C2). That is, the DCG transistor (DCX) may control the capacitance of the floating diffusion region (FD).

[0053] When the DCG control signal (DCG) has a logic high level, the pixel (PX) in a state where the DCG transistor (DCX) is turned on can operate in a low conversion gain (LCG) mode, in which the photocharge is converted into an electrical signal with a relatively low conversion gain. When the DCG control signal (DCG) has a logic low level, the pixel (PX) in a state where the DCG transistor (DCX) is turned off can operate in a high conversion gain (HCG) mode, in which the photocharge is converted into an electrical signal with a relatively high conversion gain.

[0054] In some implementations, a logic high level may represent a voltage level for activating (e.g., turning on) a corresponding element (e.g., a transistor), while a logic low level may represent a voltage level for deactivating (e.g., turning off) a corresponding element (e.g., a transistor).

[0055] Although for ease of description Figure 2 An example case of using only one DCG transistor (DCX) is shown, but other implementations are possible, and multiple DCG transistors may also be used. In this case, the capacitance of the floating diffusion region (FD) may have more values ​​(eg, three or more values).

[0056] The source follower transistor (SF) can be coupled between the selection transistor (SX) and the power supply voltage (VDD), can amplify the potential change of the floating diffusion region (FD) that has received the photocharge accumulated in the photoelectric conversion element (PD), and can transmit the amplified result to the selection transistor (SX).

[0057] The selection transistor (SX) may be coupled between the source follower transistor (SF) and the output signal line and may be turned on by a selection control signal (SEL) so that the selection transistor (SX) can output the electrical signal received from the source follower transistor (SF) as a pixel signal (PS).

[0058] Figure 3 is a graph showing an example of the response of a high conversion gain (HCG) pixel and a low conversion gain (LCG) pixel in terms of brightness according to some implementations of the disclosed technology.

[0059] refer to Figure 3 , a high conversion gain (HCG) pixel may refer to a pixel operating in an HCG mode, and a low conversion gain (LCG) pixel may refer to a pixel operating in an LCG mode. Figure 3 It can be seen that, in association with a high conversion gain (HCG) pixel whose response increment is relatively large as the incident light intensity increases and a low conversion gain (LCG) pixel whose response increment is relatively small as the incident light intensity increases, the response of the HCG pixel and the response of the LCG pixel change depending on the intensity of the incident light applied to the corresponding pixel. Here, the response may refer to the image data (IDATA) of the corresponding pixel.

[0060] In this case, the response may have a signal-to-noise ratio (SNR) limit (ie, an SNR threshold level) and a saturation level.

[0061] The signal-to-noise ratio (SNR) threshold level refers to a threshold that can meet a predetermined reference SNR. A response less than the SNR threshold level can be regarded as an invalid response that does not meet the reference SNR, while a response greater than the SNR threshold level can be regarded as a valid response that meets the reference SNR. The reference SNR can be determined experimentally in consideration of the characteristics of the image sensing device 100.

[0062] The saturation level refers to the maximum level indicating the intensity of incident light. The saturation level may be determined by the ability of the pixel to convert the intensity of incident light into photocharges (e.g., the capacitance of the photoelectric conversion element), the ability of the photocharge to be converted into an analog signal (e.g., the capacitance of the floating diffusion (FD) region), and the ability of the analog signal to be converted into a digital signal (e.g., the input range of the ADC). As the intensity of incident light increases, the response may increase in proportion to the intensity of incident light until the response reaches a saturation level. After the response reaches the saturation level, the response may not increase although the intensity of incident light increases. For example, after the response reaches the saturation level, the response may have the same value as the saturation value without increasing above the saturation level.

[0063] The effective response of each pixel may refer to a response that can satisfy the reference SNR and indicates a strong response of the incident light. The range of incident light intensity corresponding to the effective response of the pixel may be referred to as the dynamic range of the pixel. That is, the dynamic range of the pixel may refer to the range of incident light intensity in which each pixel has an effective response.

[0064] The HCG pixel provides a response having a relatively large increase in response to an increase in the incident light intensity. Therefore, the response of the HCG pixel can have a relatively large slope in response to an increase in the incident light intensity until the response reaches a saturation level; and after the response reaches the saturation level, the response of the HCG pixel has a fixed level corresponding to the saturation level regardless of whether the incident light intensity increases or not.

[0065] The LCG pixel provides a response with a relatively small increase in response to an increase in the incident light intensity. Therefore, the response of the LCG pixel can increase with a relatively small slope in response to an increase in the incident light intensity until the response reaches a saturation level; and after the response reaches the saturation level, the response of the LCG pixel has a fixed level corresponding to the saturation level regardless of the increase in the incident light intensity.

[0066] like Figure 3 As shown, the minimum value of the HCG pixel dynamic range (DR_H) (or the first dynamic range) can be smaller than the minimum value of the LCG pixel dynamic range (DR_L) (or the second dynamic range), and the maximum value of the HCG pixel dynamic range (DR_H) can be smaller than the maximum value of the LCG pixel dynamic range (DR_L). Therefore, in a low illumination range where the incident light intensity is relatively small, the HCG pixel can be more suitable for sensing the intensity of the incident light. In a high illumination range where the incident light intensity is relatively large, the LCG pixel can be more suitable for sensing the intensity of the incident light.

[0067] A high dynamic range (HDR) can be achieved using both the response of the HCG pixel suitable for the low illumination range and the response of the LCG pixel suitable for the high illumination range. In other words, the above-mentioned case of using both the HCG pixel and the LCG pixel can allow the entire pixel array to have a high dynamic range (HDR) corresponding to a specific range from the minimum value of the HCG pixel dynamic range to the maximum value of the LCG pixel dynamic range, compared to other cases where only one of the HCG pixel and the LCG pixel is used. To this end, at least a portion of the HCG pixel dynamic range and at least a portion of the LCG pixel dynamic range can overlap each other.

[0068] The method for synthesizing a high dynamic range (HDR) image corresponding to a high dynamic range (HDR) using HCG pixels and LCG pixels may be implemented as a method for synthesizing an HDR image by calculating (e.g., summing) HCG pixel responses and LCG pixel responses, and / or a method for forming an image based on HCG pixel responses at low illumination levels and forming an image based on LCG pixel responses at high illumination levels, but is not limited thereto.

[0069] Figure 4 is a circuit diagram illustrating an example of an analog-to-digital converter (ADC) 140 based on some implementations of the disclosed technology.

[0070] Reference Figure 4 ADC 140 may receive a ramp signal (V ramp ), a pixel signal (PS) may be received from a pixel (PX), and a ramp signal (V ramp ) and pixel signal (PS) generate and output ADC data (ADC_OUT).

[0071] The ADC 140 may include third and fourth capacitors ( C3 , C4 ), a comparator 142 , and a counter 144 .

[0072] The third capacitor C3 can receive the ramp signal (V ramp ), and the ramp signal (V ramp) The fourth capacitor C4 may receive the pixel signal (PS) and may transmit the pixel signal (PS) to the comparator 142.

[0073] The comparator 142 can compare the ramp signal (V ramp ) and the pixel signal (PS), a comparison data (CMP_OUT) may be generated according to the result of the comparison, and the comparison data (CMP_OUT) may be transmitted to the counter 144. In some embodiments, when the ramp signal (V ramp) is greater than the pixel signal (PS), the comparator 142 may generate the comparison data (CMP_OUT) having a logic high level. In addition, when the ramp signal (V ramp ) is less than the pixel signal (PS), the comparator 142 may generate the comparison data (CMP_OUT) having a logic low level. That is, the comparison data (CMP_OUT) may indicate that the ramp signal (V ramp ) and the pixel signal (PS).

[0074] The comparator 142 may perform an auto-zeroing operation according to an auto-zeroing signal (AZ). Here, the auto-zeroing operation may be for a ramp signal (V ramp ) and the pixel signal (PS) to adjust the ramp signal (V ramp ) and the voltage level of the pixel signal (PS). The comparator 142 may perform the auto-zero operation in a period in which the auto-zero signal (AZ) is at a logic high level. The auto-zero signal (AZ) may be generated and provided by the timing controller 170. The comparator 142 may perform the auto-zero operation at each of the start time of the HCG mode and the start time of the LCG mode.

[0075] The counter 144 may be activated in response to the counter enable signal (CNT_EN), the activated counter 144 may perform counting in response to the logic high level comparison data (CMP_OUT), and may output the counting result as ADC data (ADC_OUT). Here, the ADC data (ADC_OUT) may correspond to Figure 1 Image data (IDATA) described in .

[0076] Figure 5 Some implementations based on the disclosed technology are shown Figure 4 A diagram of an example of a ramp generator 130 - 1 is shown.

[0077] Reference Figure 5 , the ramp generator 130-1 may correspond to Figure 4 An embodiment of the ramp generator 130 , and the ramp generator 130 - 1 may be a bidirectional ramp generator 132 .

[0078] The bidirectional ramp generator 132 can generate a ramp signal (V ramp ) and a ramp signal with a negative (-) slope (V ramp The bidirectional ramp generator 132 may generate a ramp signal (V) having a negative (-) slope in response to a DCG control signal (DCG) having a logic low level. rampThe bidirectional ramp generator 132 may generate a ramp signal (V ramp ).

[0079] For this operation, the bidirectional ramp generator 132 may include a plurality of current sources connected in parallel, a plurality of switches respectively connected to the current sources and turned on or off in sequence, and a load resistor configured to generate a specific voltage based on current received from the current sources, but is not limited thereto.

[0080] Figure 6 Some implementations based on the disclosed technology are shown Figure 4 A schematic diagram of another example of a ramp generator is shown.

[0081] Reference Figure 6 , the ramp generator 130-2 may correspond to Figure 4 The ramp generator 130 - 2 may include a negative ramp generator 134 , a positive ramp generator 136 , and a ramp signal selector 138 .

[0082] The negative ramp generator 134 can generate a ramp signal (V ramp ).

[0083] The positive ramp generator 136 can generate a ramp signal (V ramp ).

[0084] The ramp signal selector 138 can select and output a ramp signal (V ramp ) or a ramp signal with a positive slope (V ramp ).

[0085] The ramp signal selector 138 may include a first ramp switch (SW_R1) and a second ramp switch (SW_R2). The first ramp switch (SW_R1) may be turned on in response to a DCG control signal (DCG) having a logic low level, and may be turned off in response to a DCG control signal (DCG) having a logic high level. The second ramp switch (SW_R2) may be turned on in response to a DCG control signal (DCG) having a logic high level, and may be turned off in response to a DCG control signal (DCG) having a logic low level.

[0086] That is, the ramp signal selector 138 may output a ramp signal (V R ) having a negative slope in response to the DCG control signal (DCG) having a logic low level. ramp ), and a ramp signal (Vramp ).

[0087] For this operation, the negative ramp generator 134 may include a plurality of current sources connected in parallel, a plurality of switches connected to the current sources and turned off in sequence, and a load resistor configured to generate a specific voltage based on receiving current from the current sources. The positive ramp generator 134 may include a plurality of current sources connected in parallel, a plurality of switches connected to the current sources and turned on in sequence, and a load resistor configured to generate a specific voltage based on receiving current from the current sources, but is not limited thereto.

[0088] Figure 7 is a diagram showing some implementations based on the disclosed technology for Figure 4 A timing diagram of an example operation of an analog-to-digital converter (ADC) to convert a pixel signal into image data is shown.

[0089] Reference Figure 7 , the operation of converting the pixel signal into image data may be performed and divided into a first reset period (RST1), a first signal period (SIG1), a second signal period (SIG2), and a second reset period (RST2). The first reset period (RST1) may refer to a period in which a reference signal of a pixel (PX) operating in an HCG mode is AD (analog-to-digital) converted, and the first signal period (SIG1) may refer to a period in which an image signal of a pixel (PX) operating in an HCG mode is AD converted. The second signal period (SIG2) may refer to a period in which an image signal of a pixel (PX) operating in an LCG mode is AD converted, and the second reset period (RST2) may refer to a period in which a reference signal of a pixel (PX) operating in an LCG mode is AD converted.

[0090] In the first reset period (RST1), the DCG control signal (DCG) may have a logic low level so that the floating diffusion region (FD) may have a relatively small capacitance. Thereafter, when the pixel reset signal (RG) temporarily has a logic high level, a pixel signal (PS) corresponding to a voltage for resetting the floating diffusion region (FD) may be output from the pixel (PX) operating in the HCG mode.

[0091] When the auto-zero signal (AZ) has a logic high level, the comparator 142 can ramp ) and the pixel signal (PS). After a predetermined time has passed, in response to the DCG control signal (DCG) having a logic low level, the ramp generator 130 may output a ramp signal (V R ) that decreases with a negative slope from a voltage (i.e., a ramp upper limit value RU) that is increased by a ramp offset from the first auto-zero level (AZL1). rampHere, the ramp offset may be a value indicating a degree of level change of a ramp (rising or falling) starting from a voltage level at which auto-zeroing is performed according to the characteristics of the ramp generator 130.

[0092] The comparison data (CMP_OUT) can be ramp ) is greater than the pixel signal (PS) and has a logic high level during the period in which the ramp signal (V ramp ) has a logic low level during the period when the pixel signal (PS) is less than the pixel signal (PS).

[0093] The counter enable signal (CNT_EN) can be ramp ) has a logic high level in a period in which the comparison data (CMP_OUT) has a positive slope or a negative slope. The counter 144 may be activated in response to the counter enable signal (CNT_EN) having a logic high level, and the activated counter 144 may perform counting in a period in which the comparison data (CMP_OUT) is at a logic high level, and may output a first reference value (RV1) indicating a counting result as ADC data (ADC_OUT).

[0094] The first reference value RV1 may be a digital value representing a pixel signal PS (ie, a reference signal of the HCG mode) corresponding to a voltage of a reset floating diffusion region (FD) of a pixel (PX) operating in the HCG mode.

[0095] In the first signal period (SIG1), when the DCG control signal (DCG) has a logic low level and the transfer signal (TG) temporarily has a logic high level, a pixel signal (PS) corresponding to a voltage of a floating diffusion region (FD) in which photocharges generated by a pixel are accumulated may be output from a pixel (PX) operating in the HCG mode. The voltage level of the pixel signal PS may decrease in response to the amount of photocharges accumulated in the floating diffusion region FD.

[0096] When the first signal period SIG1 begins, the ramp signal (V ramp ) can return to the ramp upper limit value (RU). Then, after a predetermined time has passed, the ramp generator 130 can output a ramp signal (V ramp ).

[0097] According to the ramp signal (V ramp ) and the pixel signal (PS), the comparison data (CMP_OUT) can have a logic high level or a logic low level.

[0098] The counter 144 activated in response to the counter enable signal (CNT_EN) having a logic high level may perform counting in a period in which the comparison data (CMP_OUT) is at a logic high level, and may output a first signal value (SV1) indicating a counting result as ADC data (ADC_OUT).

[0099] The first signal value (SV1) may be a digital value indicating a pixel signal PS (ie, an image signal of the HCG mode) corresponding to a voltage of a floating diffusion region (FD) accumulating photocharges generated by a pixel (PX) operating in the HCG mode.

[0100] In the HCG mode, a value corresponding to a voltage difference between an image signal and a reference signal (ie, a signal component from which reset noise is removed) may be obtained by subtracting a first reference value (RV1) from a first signal value (SV1).

[0101] In the second signal period (SIG2), the DCG control signal (DCG) may have a logic high level, and the floating diffusion region (FD) may have a relatively large capacitance. A pixel signal (PS) corresponding to a voltage of the floating diffusion region (FD) accumulating photocharges generated by the pixel PX may be output from the pixel (PX) operating in the LCG mode.

[0102] When the auto-zero signal (AZ) has a logic high level, the comparator 142 can ramp ) and the pixel signal (PS). After a predetermined time has passed, in response to the DCG control signal (DCG) having a logic low level, the ramp generator 130 may output a ramp signal (V R ) that increases with a positive slope from a voltage (i.e., a ramp lower limit value RD) that is reduced by a ramp offset from the second auto-zero level (AZL2). ramp ).

[0103] An auto-zero operation should be performed to read out an image signal of a pixel (PX) operating in the LCG mode, but the auto-zero operation has a disadvantage in that such auto-zero is performed based on a pixel signal (PS) corresponding to a voltage of a floating diffusion region (FD) in which photocharges are accumulated. Therefore, when a ramp signal (V ramp ), the ramp signal (V ramp ) and the pixel signal (PS), so that the comparison data (ADC_OUT) cannot represent the image signal of the pixel (PX) operating in the LCG mode.

[0104] In some implementations, in order to normally compare the ramp signal (V ramp) and the pixel signal (PS), a ramp signal with a positive slope (V ramp ) to increase the ramp signal (V ramp ) and the pixel signal (PS) are compared with each other. Here, the ramp signal (V ramp ) and the slope of the ramp signal in LCG mode (V ramp ) can have different signs and the same absolute value.

[0105] The counter 144 may be activated in response to the counter enable signal (CNT_EN) having a logic high level, and the activated counter 144 may perform counting in a period in which the comparison data (CMP_OUT) is at a logic high level. Then, the counter 144 may output a second signal value (SV2) indicating the counting result as ADC data (ADC_OUT).

[0106] The second signal value (SV2) may be a digital value representing a portion of the pixel signal PS (i.e., the image signal of the LCG mode) corresponding to the voltage of the floating diffusion region (FD) accumulating the photocharges of the pixel (PX) operating in the LCG mode, and the sum of the second signal value (SV2) and the margin value (MV) may represent the image signal of the LCG mode. The margin value (MV) may be a value corresponding to the ramp signal (V ramp ) and the slope upper limit value (RU), and can be based on the slope lower limit value (RD), the slope starting point and the ramp signal (V ramp ) is predetermined by the slope of the

[0107] In the second reset period (RST2), when the pixel reset signal (RG) temporarily has a logic high level, a pixel signal (PS) corresponding to a voltage resetting the floating diffusion area (FD) may be output from the pixel (PX) operating in the LCG mode.

[0108] When the second reset period (RST2) begins, the ramp signal (V ramp ) can return to the ramp lower limit value (RD), and after a predetermined time has passed, the ramp generator 130 can output a ramp signal (V ramp ).

[0109] According to the ramp signal (V ramp ) and the pixel signal (PS), the comparison data (CMP_OUT) can have a logic high level or a logic low level.

[0110] The counter 144 activated in response to the counter enable signal (CNT_EN) having a logic high level may perform counting in a period in which the comparison data (CMP_OUT) is at a logic high level, and may output a second reset value (RV2) indicating the counting result as ADC data (ADC_OUT).

[0111] The second reset value (RV2) may be a digital value representing a pixel signal PS (ie, a reference signal of the LCG mode) corresponding to a voltage of a reset floating diffusion region (FD) of a pixel (PX) operating in the LCG mode.

[0112] In the LCG mode, a value corresponding to a voltage difference between an image signal and a reference signal (ie, a signal component from which reset noise is removed) may be obtained by subtracting a second reference value (RV2) from a sum of a second signal value (SV2) and a margin value (MV).

[0113] Here, the second signal value (SV2) may be maintained at a constant value through an auto-zero operation in the LCG mode, and the second reference value (RV2) may be varied according to the amount of photo charges.

[0114] Figure 8 Some implementations based on the disclosed technology are shown Figure 4 A diagram of another example of a ramp generator is shown.

[0115] Reference Figure 8 , the ramp generator 130-3 may correspond to Figure 4 The example of the ramp generator 130 is shown in FIG. 1 , and the ramp generator 130 - 3 may include an offset adjustable ramp generator 138 .

[0116] The offset adjustable ramp generator 138 can generate a ramp signal (V ramp Here, after the DCG control signal (DCG) changes from a logic low level to a logic high level, the offset adjustable ramp generator 138 may generate an offset adjusted ramp signal (V ramp ). In this case, the specific period of time may be Fig. 9 The term "offset adjustment" may refer to a ramp signal (V ramp ) is an overall adjustment of the voltage level of the ramp signal (V ramp ) is lowered by a certain voltage (i.e., Fig. 9The signal offset (SOF) may be provided in real time from an external device (e.g., an ISP 200 configured to calculate a difference between a first reference value RV2 obtained from a first reset period RST1 and a first signal value SV1 obtained from a first signal period SIG1), or may be a predetermined voltage, but the scope of the disclosed technology is not limited thereto.

[0117] For this operation, the offset adjustable ramp generator 138 may include a plurality of current sources connected in parallel, a plurality of switches respectively connected to the current sources and turned on or off in sequence, and a load resistor configured to generate a specific voltage based on the current received from the current source. The load resistor may be a variable resistor capable of temporarily changing the resistance value to perform offset adjustment, but is not limited thereto.

[0118] Fig. 9 is a diagram showing some implementations based on the disclosed technology for Figure 8 A timing diagram showing an example operation of an ADC to convert a pixel signal into image data.

[0119] Reference Fig. 9 , an operation of converting a pixel signal into image data may be performed and divided into a first reset period ( RST1 ), a first signal period ( SIG1 ), a second signal period ( SIG2 ), and a second reset period ( RST2 ).

[0120] In addition to Figure 7 In addition to some differences in the operation of the time periods (RST1, SIG1, SIG2, RST2), Fig. 9 The rest of the operations during the period (RST1, SIG1, SIG2, RST2) are the same as Figure 7 The operation is basically the same, so Fig. 9 The timing diagram below will focus on Figure 7 The difference in the timing diagram is described.

[0121] In the second signal period (SIG2), the DCG control signal (DCG) may have a logic high level, and the floating diffusion region (FD) may have a relatively large capacitance. A pixel signal (PS) corresponding to a voltage of the floating diffusion region (FD) in which photocharges generated by the pixel (PX) are accumulated may be output from the pixel (PX) operating in the LCG mode.

[0122] When the auto-zero signal (AZ) has a logic high level, the comparator 142 can ramp) and the pixel signal (PS). After a predetermined time has passed, the ramp generator 130 may output a ramp signal (V) that decreases (or falls) with a negative slope in response to the logic high level DCG control signal (DCG). ramp ).

[0123] Ramp signal (V ramp ) can be lowered in the second signal period SIG2 than the voltage level of the ramp signal (V ramp )The voltage level at which the signal starts to drop in the second reset period (RST2) is lower than the signal offset (SOF). The signal offset (SOF) may be a digital value corresponding to the voltage difference between the first auto-zero level (AZL1) and the second auto-zero level (AZL2). Alternatively, the signal offset (SOF) may be determined based on the voltage difference between the reference signal and the image signal in the HCG mode. In some embodiments, the signal offset (SOF_offset) may be set to a level at which a second signal value (SV2) and a second reset value (RV2) that may generally indicate the incident light intensity may be generated based on the voltage level of the reference signal in the HCG mode (i.e., the first auto-zero level AZL1) even in dark conditions where the incident light intensity is low in the LCG mode.

[0124] The counter 144 may be activated in response to the counter enable signal (CNT_EN) having a logic high level, and the activated counter 144 may perform counting in a period in which the comparison data (CMP_OUT) is at a logic high level. Then, the counter 144 may output the second signal value (SV2) as ADC data (ADC_OUT).

[0125] The second signal value (SV2) can be a digital value representing a portion of the pixel signal PS (i.e., the image signal of the LCG mode) corresponding to the voltage of the floating diffusion region (FD) in which the photo charges of the pixel (PX) operating in the LCG mode are accumulated, and the sum of the second signal value (SV2) and the signal offset (SOF) can represent the image signal of the LCG mode.

[0126] In the second reset period (RST2), when the pixel reset signal (RG) temporarily has a logic high level, a pixel signal (PS) corresponding to a voltage resetting the floating diffusion area (FD) may be output from the pixel (PX) operating in the LCG mode.

[0127] When the second reset period (RST2) begins, the ramp signal (V ramp ) has a voltage level higher than the ramp signal (V ramp) starts to drop in the second signal period SIG2 by a voltage level higher than the signal offset (SOF). After a predetermined time has passed, the offset adjustable ramp generator 130-3 may output a ramp signal (V ramp ).

[0128] That is to say, Fig. 9 It can be seen that a ramp signal with a negative slope (V ramp ) instead of using a ramp signal with a positive slope (V ramp ), and can use an offset-adjusted ramp signal (V ramp As a result, the ramp signal (V ramp ) and the size of the pixel signal (PS) can be normally compared with each other.

[0129] According to the ramp signal (V ramp ) and the pixel signal (PS), the comparison data (CMP_OUT) can have a logic high level or a logic low level.

[0130] The counter 144 activated in response to the counter enable signal (CNT_EN) having a logic high level may perform counting in a period in which the comparison data (CMP_OUT) is at a logic high level, and may output a second reset value (RV2) indicating the counting result as ADC data (ADC_OUT).

[0131] The second reset value (RV2) may be a digital value representing a pixel signal PS (ie, a reference signal of the LCG mode) corresponding to a voltage of a reset floating diffusion region (FD) of a pixel (PX) operating in the LCG mode.

[0132] In the LCG mode, a value corresponding to the voltage difference between the image signal and the reference signal (i.e., a signal component from which reset noise is removed) can be obtained by subtracting the second reference value (RV2) from the sum of the second signal value (SV2) and the signal offset (SOF). Here, the second signal value (SV2) can be maintained at a constant value by an auto-zeroing operation in the LCG mode, and the second reference value (RV2) can be varied according to the amount of photocharge.

[0133] Fig.10 is a schematic diagram illustrating an example of an analog-to-digital converter (ADC) based on some other implementations of the disclosed technology.

[0134] Reference Fig.10 ADC 140 may be indirectly coupled to the pixel (PX) and Figure 5The ramp generator 130 - 1 , the first path control circuit 180 - 1 may be connected between the ramp generator 130 - 1 and the ADC 140 , and the second path control circuit 180 - 2 may be connected between the pixel (PX) and the ADC 140 .

[0135] The first path control circuit 180-1 may, in response to a DCG control signal (DCG) having a logic low level, convert the ramp signal (V ramp ) is transmitted to the non-inverting terminal of the comparator 142. The first path control circuit 180-1 may respond to the DCG control signal (DCG) having a logic high level, and transmit the ramp signal (V ramp ) is transmitted to the inverting terminal of the comparator 142.

[0136] To this end, the first path control circuit 180-1 may include: a first switch SW1, which is opened by a logic low level DCG control signal (DCG) and short-circuited by a logic high level DCG control signal (DCG); and a second switch SW2, which is short-circuited by a logic low level DCG control signal (DCG) and opened by a logic high level DCG control signal (DCG).

[0137] The second path control circuit 180-2 may transmit the pixel signal (PS) of the pixel (PX) to the inverting terminal of the comparator 142 through the fourth capacitor C4 in response to the logic low level DCG control signal (DCG). The second path control circuit 180-2 may transmit the pixel signal (PS) of the pixel (PX) to the non-inverting terminal of the comparator 142 through the third capacitor C3 in response to the logic high level DCG control signal (DCG).

[0138] To this end, the second path control circuit 180-2 may include: a third switch SW3, which is short-circuited by a logic low level DCG control signal (DCG) and opened by a logic high level DCG control signal (DCG); and a fourth switch SW4, which is opened by a logic low level DCG control signal (DCG) and short-circuited by a logic high level DCG control signal (DCG).

[0139] In each of the HCG mode in which the DCG control signal (DCG) is at a logic low level and the LCG mode in which the DCG control signal (DCG) is at a logic high level, the first path control circuit 180-1 and the second path control circuit 180-2 can transmit the signal on the pixel side and the signal on the ramp generator side as input signals of the comparator 142 to terminals opposite to each other.

[0140] Fig.11 is a schematic diagram illustrating another example of an analog-to-digital converter (ADC) based on some implementations of the disclosed technology.

[0141] Reference Fig.11 ADC 140 may be indirectly coupled to the pixel (PX) and Figure 6 The ramp generator (134, 136), the third path control circuit 180-3 can be coupled between the ADC 140 and the ramp generator (134, 136), and the fourth path control circuit 180-4 can be coupled between the pixel (PX) and the ADC 140.

[0142] The third path control circuit 180-3 may respond to the DCG control signal (DCG) having a logic low level by converting the ramp signal (V ramp ) is transmitted to the non-inverting terminal of the comparator 142. The third path control circuit 180-3 may respond to the DCG control signal (DCG) having a logic high level, and transmit the ramp signal (V ramp ) is transmitted to the inverting terminal of the comparator 142.

[0143] To this end, the third path control circuit 180-3 may include: a fifth switch SW5, which is opened by a logic low level DCG control signal (DCG) and short-circuited by a logic high level DCG control signal (DCG); and a sixth switch SW6, which is short-circuited by a logic low level DCG control signal (DCG) and opened by a logic high level DCG control signal (DCG).

[0144] The fourth path control circuit 180-4 may transmit the pixel signal (PS) of the pixel (PX) to the inverting terminal of the comparator 142 through the fourth capacitor C4 in response to the DCG control signal (DCG) having a logic low level. The fourth path control circuit 180-4 may transmit the pixel signal (PS) of the pixel (PX) to the non-inverting terminal of the comparator 142 through the third capacitor C3 in response to the DCG control signal (DCG) having a logic high level.

[0145] To this end, the fourth path control circuit 180-2 may include: a seventh switch SW7, which is short-circuited by a logic low-level DCG control signal (DCG) and opened by a logic high-level DCG control signal (DCG); and an eighth switch SW8, which is opened by a logic low-level DCG control signal (DCG) and short-circuited by a logic high-level DCG control signal (DCG).

[0146] In each of the HCG mode in which the DCG control signal (DCG) is at a logic low level and the LCG mode in which the DCG control signal (DCG) is at a logic high level, the third path control circuit 180-3 and the fourth path control circuit 180-4 can transmit the signal on the pixel side and the signal on the ramp generator side as input signals of the comparator 142 to terminals opposite to each other.

[0147] Fig.12 is a diagram showing some implementations based on the disclosed technology for Fig.10 or Fig.11 is a timing diagram of an example operation of an analog-to-digital converter (ADC) shown in to convert a pixel signal into image data.

[0148] Reference Fig.12 , the operation of converting the pixel signal into image data may be performed and divided into a first reset period (RST1), a first signal period (SIG1), a second signal period (SIG2) and a second reset period (RST2). Figure 7 In addition to some differences in the operations of the time periods (RST1, SIG1, SIG2, RST2), Fig.12 The rest of the operations during the period (RST1, SIG1, SIG2, RST2) are the same as Figure 7 The operation is basically the same, so Fig.12 The timing diagram will be described below with Figure 7 The description will focus on the differences in the timing diagrams.

[0149] In the second signal period (SIG2), the DCG control signal (DCG) may have a logic high level, and the floating diffusion region (FD) may have a relatively large capacitance. A pixel signal (PS) corresponding to a voltage of the floating diffusion region (FD) in which photocharges generated by the pixel (PX) are accumulated may be output from the pixel (PX) operating in the LCG mode.

[0150] When the auto-zero signal (AZ) has a logic high level, the comparator 142 can ramp ) and the pixel signal (PS). After a predetermined time has passed, the ramp generator 130 may output a ramp signal (V) rising (or increasing) with a positive slope from the ramp lower limit value (RD) in response to the logic high DCG control signal (DCG). ramp ).

[0151] The counter 144 may be activated in response to the counter enable signal (CNT_EN) having a logic high level, and the activated counter 144 may perform counting in a period in which the comparison data (CMP_OUT) is at a logic high level. Then, the counter 144 may output the second signal value SV2 as ADC data (ADC_OUT).

[0152] The comparison data (CMP_OUT) corresponds to the ramp signal (V ramp ) and the pixel signal (PS). In HCG mode, the ramp signal (V ramp ) may be input to the non-inverting terminal of the comparator 142, and the pixel signal (PS) may be input to the inverting terminal of the comparator 142, so that the comparison data (CMP_OUT) of the HCG mode may have the same Figure 7 The comparison data (CMP_OUT) has the same waveform as the comparison data (CMP_OUT).

[0153] However, in LCG mode, because the ramp signal (V ramp ) is input to the inverting terminal of the comparator 142 and the pixel signal (PS) is input to the non-inverting terminal of the comparator 142, so the remaining portion of the comparison data (CMP_OUT) in the LCG mode except for the period in which the auto-zero operation is performed may have the same Figure 7 The waveform corresponds to the inverse format of the waveform of the comparison data (CMP_OUT).

[0154] Therefore, the second signal value (SV2) may be a digital value indirectly indicating a pixel signal PS (i.e., an image signal of the LCG mode) corresponding to a voltage of a floating diffusion region (FD) in which photocharges of a pixel (PX) operating in the LCG mode are accumulated, and a value obtained by subtracting the second signal value (SV2) from a total signal value corresponding to the entire signal range (AZL1-AZL2) may represent an image signal of the LCG. The entire signal range (AZL1-AZL2) may refer to a value in which the ramp signal (V ramp ) rises or falls at a specific slope to pass the ramp signal (V ramp ) and the pixel signal (PS) produces a voltage range indicating image data of the pixel signal (PS).

[0155] In the second reset period (RST2), when the pixel reset signal (RG) temporarily has a logic high level, a pixel signal (PS) corresponding to a voltage resetting the floating diffusion area (FD) may be output from the pixel (PX) operating in the LCG mode.

[0156] When the second reset period RST2 begins, the ramp signal (V ramp) can return to the ramp lower limit value (RD), and after a predetermined time, the ramp generator 130 can output a ramp signal (V ramp ).

[0157] According to the ramp signal (V ramp ) and the pixel signal (PS), the comparison data (CMP_OUT) can have a logic high level or a logic low level.

[0158] The counter 144 activated in response to the counter enable signal (CNT_EN) having a logic high level may perform counting in a period in which the comparison data (CMP_OUT) is at a logic high level, and may output a second reset value (RV2) indicating the counting result as ADC data (ADC_OUT).

[0159] As mentioned above, in LCG mode, because the ramp signal (V ramp ) is input to the inverting terminal of the comparator 142 and the pixel signal (PS) is input to the non-inverting terminal of the comparator 142, so the remaining portion of the comparison data (CMP_OUT) in the LCG mode except for the period in which the auto-zero operation is performed may have the same Figure 7 The waveform corresponds to the inverse format of the waveform of the comparison data (CMP_OUT).

[0160] Therefore, the second reset value (RV2) can be a digital value indirectly indicating the pixel signal PS (i.e., the reference signal of the LCG mode) corresponding to the voltage of the reset floating diffusion area (FD) of the pixel (PX) operating in the LCG mode, and the value obtained by subtracting the second reset value (RV2) from the total signal value corresponding to the entire signal range (AZL1~AZL2) can represent the reference signal in the LCG mode.

[0161] In the LCG mode, a value corresponding to the voltage difference between the image signal and the reference signal (i.e., a signal component with reset noise removed) can be obtained by subtracting a first value from a second value, the first value being obtained by subtracting a second reset value (RV2) from a total signal value, the second value being obtained by subtracting a second signal value (SV2) from the total signal value. In other words, the signal component with reset noise removed can be obtained by subtracting the second signal value (SV2) from the second reset value (RV2). Here, the second signal value (SV2) can be maintained at a constant value by an auto-zeroing operation in the LCG mode, and the second reference value (RV2) can vary according to the amount of photocharge.

[0162] ISP 200 can perform such as Figure 7 , Fig. 9 and Fig.12Operations such as summation or subtraction between data slices described in , but the scope of the disclosed technology is not limited thereto, and it should be noted that Figure 7 , Fig. 9 and Fig.12 Such summation or subtraction between data slices (eg, subtraction using a hybrid method of up-counting and down-counting operations used in counter 144 ) may also be performed in image sensing device 100 .

[0163] Image sensing devices based on some implementations of the disclosed technology can perform analog-to-digital conversion using a pair of one comparator and one counter for each column line (for each pixel), thereby significantly reducing the size of the analog-to-digital converter (ADC) 140 .

[0164] In addition, since the image sensing devices based on some implementations of the present technology perform automatic zeroing again after reading out the image signal in the HCG mode and before reading out the image signal in the LCG mode, the image sensing device can set the automatic zeroing level regardless of the switching noise generated when switching from the HCG mode to the LCG mode, so that the image sensing device can perform accurate analog-to-digital conversion in the LCG mode without ensuring an additional ramp range.

[0165] It is obvious from the above description that an image sensing device based on some implementations of the disclosed technology and an imaging device including the image sensing device can use a pair of a comparator and a counter to perform analog-to-digital conversion for each column line (or each pixel) of a pixel array, thereby significantly reducing the size of the analog-to-digital converter (ADC).

[0166] Embodiments of the disclosed technology can provide various effects that can be directly or indirectly recognized through the above-mentioned patent documents.

[0167] Although a number of illustrative embodiments have been described, it should be appreciated that modifications and improvements of the disclosed embodiments and other embodiments may be devised based on what is described and / or illustrated in this patent document.

Claims

1. An image sensing device, comprising: A pixel, which: in each of an HCG mode and an LCG mode, outputs a reference signal corresponding to a reset sensing node and an image signal corresponding to the sensing node in which photo charges are accumulated, wherein in the HCG mode, the sensing node has a first capacitance, and in the LCG mode, the sensing node has a second capacitance greater than the first capacitance, HCG refers to a high conversion gain, and LCG refers to a low conversion gain; an ADC that sequentially performs analog-to-digital conversion on the reference signal of the HCG mode, the image signal of the HCG mode, the image signal of the LCG mode, and the reference signal of the LCG mode, wherein the ADC refers to an analog-to-digital converter; and A ramp generator generates a first ramp signal for analog-to-digital conversion in the HCG mode and generates a second ramp signal for analog-to-digital conversion in the LCG mode, wherein the second ramp signal has a waveform different from that of the first ramp signal.

2. The image sensing device according to claim 1, wherein: The ramp generator performs an automatic zeroing operation at each of the time points at which the HCG mode starts and the time points at which the LCG mode starts, wherein the automatic zeroing operation is used to adjust a pixel signal having both the reference signal and the image signal and a ramp signal having both the first ramp signal and the second ramp signal.

3. The image sensing device according to claim 1, wherein: The first ramp signal has a negative slope; and The second ramp signal has a positive slope.

4. The image sensing device according to claim 3, wherein: The slope of the first ramp signal and the slope of the second ramp signal have the same absolute value.

5. The image sensing device according to claim 3, wherein: The ramp generator comprises: A bidirectional ramp generator generates the first ramp signal or the second ramp signal in response to a DCG control signal for selecting the HCG mode or the LCG mode, wherein DCG refers to dual conversion gain.

6. The image sensing device according to claim 3, wherein: The ramp generator comprises: a negative ramp generator, which generates the first ramp signal; and A positive ramp generator generates the second ramp signal.

7. The image sensing device according to claim 3, wherein: The ADC comprises: a comparator that generates comparison data indicating a result of comparison between a pixel signal having both the reference signal and the image signal and a ramp signal having both the first ramp signal and the second ramp signal; and A counter generates ADC data indicating a result of counting in a period in which the comparison data is at a logic high level.

8. The image sensing device according to claim 7, wherein: The comparator comprises: a non-inverting terminal that receives the ramp signal in each of the HCG mode and the LCG mode; and An inversion terminal receives the pixel signal in each of the HCG mode and the LCG mode.

9. The image sensing device according to claim 7, wherein: The comparator comprises: a non-inverting terminal receiving the first ramp signal in the HCG mode and receiving the pixel signal in the LCG mode; and An inverting terminal receives the pixel signal in the HCG mode and receives the second ramp signal in the LCG mode.

10. The image sensing device according to claim 1, wherein: Each of the first ramp signal and the second ramp signal has a negative slope.

11. The image sensing device according to claim 10, wherein: A voltage level at which the second ramp signal starts to fall for reading out the image signal of the LCG pattern is lower than a voltage level at which the second ramp signal starts to fall for reading out the reference signal of the LCG pattern by a signal offset.

12. The image sensing device according to claim 11, wherein: The signal offset varies according to a voltage difference between the reference signal and the image signal in the HCG mode.

13. The image sensing device according to claim 1, wherein: The pixel also includes: A DCG transistor is connected between the sensing node and a DCG capacitor, wherein the DCG transistor is turned off in the HCG mode and turned on in the LCG mode, DCG refers to dual conversion gain.

14. An imaging device, comprising: An image sensing device that generates image data based on each of a reference signal corresponding to a reset sensing node and an image signal corresponding to the sensing node in which photo charges are accumulated in each of an HCG mode and an LCG mode, wherein the sensing node has a first capacitance and the sensing node has a second capacitance greater than the first capacitance in each of an HCG mode and an LCG mode, wherein HCG refers to a high conversion gain and LCG refers to a low conversion gain; and an image signal processor that generates an HDR image using the image data generated in the HCG mode and the image data generated in the LCG mode, HDR referring to high dynamic range, Wherein, the image sensing device comprises: an ADC that sequentially performs analog-to-digital conversion on the reference signal of the HCG mode, the image signal of the HCG mode, the image signal of the LCG mode, and the reference signal of the LCG mode, wherein the ADC refers to an analog-to-digital converter; and a ramp generator for generating a first ramp signal for analog-to-digital conversion in the HCG mode, And generating a second ramp signal for analog-to-digital conversion in the LCG mode, wherein the second ramp signal has a waveform different from that of the first ramp signal.

15. The imaging device according to claim 14, wherein: The first ramp signal has a negative slope, and the second ramp signal has a positive slope; The ADC includes a comparator having a non-inverting terminal and an inverting terminal, the non-inverting terminal being used to receive the ramp signal in each of the HCG mode and the LCG mode, and the inverting terminal being used to receive the pixel signal in each of the HCG mode and the LCG mode; as well as The image signal processor subtracts a reference value from the sum of a signal value and a margin value, and obtains image data corresponding to a voltage difference between the image signal and the reference signal in the LCG mode, wherein the signal value is obtained by conversion of the image signal in the LCG mode, and the reference value is obtained by conversion of the reference signal in the LCG mode.

16. The imaging device according to claim 14, wherein: The first ramp signal has a negative slope, and the second ramp signal has a positive slope; The ADC includes a comparator having a non-inverting terminal for receiving the ramp signal in the HCG mode and receiving the pixel signal in the LCG mode, and a non-inverting terminal for receiving the pixel signal in the HCG mode and receiving the second ramp signal in the LCG mode; as well as The image signal processor obtains image data corresponding to a voltage difference between the image signal and the reference signal in the LCG mode by subtracting a signal value from a reference value, wherein the reference value is obtained by conversion of the reference signal in the LCG mode, and the signal value is obtained by conversion of the image signal in the LCG mode.

17. The imaging device according to claim 14, wherein: Each of the first ramp signal and the second ramp signal has a negative slope; The voltage level at which the second ramp signal starts to fall for reading the image signal of the LCG mode is lower than the voltage level at which the second ramp signal starts to fall for reading the reference signal of the LCG mode by a signal offset; as well as The image signal processor subtracts a reference value from the sum of a signal value and the signal offset, and obtains image data corresponding to a voltage difference between the image signal and the reference signal in the LCG mode, wherein the signal value is obtained by conversion of the image signal in the LCG mode, and the reference value is obtained by conversion of the reference signal in the LCG mode.

18. An image sensing device, comprising: A pixel, which: in each of an HCG mode and an LCG mode, outputs a reference signal corresponding to a reset sensing node and an image signal corresponding to the sensing node in which photo charges are accumulated, wherein in the HCG mode, the sensing node has a first capacitance, and in the LCG mode, the sensing node has a second capacitance greater than the first capacitance, HCG refers to a high conversion gain, and LCG refers to a low conversion gain; an ADC that sequentially performs analog-to-digital conversion on the reference signal of the HCG mode, the image signal of the HCG mode, the image signal of the LCG mode, and the reference signal of the LCG mode, wherein the ADC refers to an analog-to-digital converter; and a ramp generator that generates a first ramp signal for analog-to-digital conversion in the HCG mode and a second ramp signal for analog-to-digital conversion in the LCG mode, wherein each of the first ramp signal and the second ramp signal has a negative slope; and The voltage level at which the second ramp signal starts to decrease for reading the image signal of the LCG mode is lower than the voltage level at which the second ramp signal starts to decrease for reading the reference signal of the LCG mode by a signal offset.

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