Memory, manufacturing method thereof and electronic equipment

Abstract

The invention discloses a memory, a manufacturing method thereof and electronic equipment. The memory comprises a semiconductor substrate which comprises active regions and trench isolation structures for limiting the active regions, and the active regions are arranged in a zigzag shape; a word line structure extending in a first horizontal direction in the substrate; the bit line structure extends in a second horizontal direction perpendicular to the first horizontal direction on the substrate; the insulating patterns are arranged between the adjacent bit line structures; and a storage node landing pad including a lower portion disposed between two bit line structures adjacent to each other and two insulation patterns adjacent to each other, and an upper portion extending from the lower portion and disposed on one of the two insulation patterns. The horizontal extending direction of the active area intersects with the first horizontal direction and the second horizontal direction respectively, the distance between every two adjacent bit line structures is smaller than the distance between every two adjacent insulation patterns, and the plane geometric center of the orthographic projection of the upper portion on the substrate deviates to but is located outside the orthographic projection of one of the two insulation patterns on the substrate.

Description

Technical Field

[0001] The embodiments of the present disclosure relate to the field of semiconductor technology, and more particularly to a memory device and a method for manufacturing the memory device, and an electronic device. Background Art

[0002] Common memories include dynamic random access memory (DRAM), ferroelectric random access memory (FeRAM), phase change memory (PCM), magnetic random access memory (MRAM), etc. These memories usually include multiple storage cells, each storage cell includes a transistor and a storage node coupled to the transistor. For example, the storage nodes in DRAM, FeRAM, PCM, and MRAM can be capacitors, ferroelectric capacitors, phase change units, and magnetic tunnel junctions (MTJs), respectively. One of the source and drain of the transistor is connected to the bit line, the other of the source and drain of the transistor is connected to the storage node, and the gate of the transistor is connected to the word line. Under the control of the word line, the transistor writes data information to the storage node or reads data information from the storage node through the bit line.

[0003] Typically, a storage node is coupled to a transistor via a storage node landing pad. However, the current configuration of the storage node landing pad still needs to be improved. Summary of the invention

[0004] According to a first aspect of an embodiment of the present disclosure, a memory is provided, comprising: a semiconductor substrate, comprising an active area and a trench isolation structure defining the active area, the active area being arranged in a zigzag shape; a word line structure extending along a first horizontal direction in the semiconductor substrate; a bit line structure extending along a second horizontal direction perpendicular to the first horizontal direction on the semiconductor substrate; an insulating pattern arranged between adjacent bit line structures; a storage node landing pad, comprising a first portion arranged between two bit line structures adjacent to each other and two insulating patterns adjacent to each other, and a second portion extending from the first portion and arranged on one of the two insulating patterns adjacent to each other, wherein the horizontal extension direction of the active area intersects with the first horizontal direction and the second horizontal direction respectively, the spacing between the two insulating patterns adjacent to each other is greater than the spacing between the two bit line structures adjacent to each other, and the plane geometric center of the orthographic projection of the second portion on the semiconductor substrate is biased toward the orthographic projection of one of the two insulating patterns adjacent to each other on the semiconductor substrate, and the plane geometric center is located outside the orthographic projection of one of the two insulating patterns adjacent to each other on the semiconductor substrate.

[0005] In some embodiments, an overlapping area of ​​an orthographic projection of the second portion and one of the two adjacent insulating patterns on the semiconductor substrate is greater than an overlapping area of ​​an orthographic projection of the second portion and any of the two adjacent bit line structures on the semiconductor substrate.

[0006] In some embodiments, an orthographic projection of the second portion on the semiconductor substrate has a symmetry axis extending along the second horizontal direction.

[0007] In some embodiments, a maximum dimension of the second portion in the second horizontal direction is greater than or equal to a dimension of the insulation pattern in the second horizontal direction.

[0008] In some embodiments, a maximum dimension of the second portion in the second horizontal direction is greater than or equal to a spacing between the two insulating patterns adjacent to each other.

[0009] In some embodiments, the bit line structure includes: a bit line stack structure; and a spacer structure disposed on a sidewall of the bit line stack structure.

[0010] In some embodiments, the memory further includes: a storage node pattern disposed on the storage node landing pad, wherein an orthographic projection of the storage node pattern on the semiconductor substrate is in a hexagonal close-packed form.

[0011] In some embodiments, the memory further includes: a contact pattern disposed between the storage node landing pad and the active area and electrically connecting the storage node landing pad and the active area.

[0012] According to a second aspect of an embodiment of the present disclosure, a method for manufacturing a memory is provided, comprising: providing a semiconductor substrate, wherein the semiconductor substrate comprises an active area and a trench isolation structure defining the active area, and the active area is arranged in a zigzag shape; forming a word line structure extending along a first horizontal direction in the semiconductor substrate; forming a bit line structure extending along a second horizontal direction on the semiconductor substrate; forming an insulating pattern between adjacent bit line structures, wherein two bit line structures adjacent to each other and two insulating patterns adjacent to each other define a contact hole; forming a storage node landing pad, wherein the storage node landing pad comprises a first portion located in the contact hole and a second portion extending from the first portion and located on one of the two insulating patterns adjacent to each other, wherein the horizontal extension direction of the active area intersects the first horizontal direction and the second horizontal direction respectively, and the plane geometric center of the orthographic projection of the second portion on the semiconductor substrate is biased toward the orthographic projection of one of the two insulating patterns on the semiconductor substrate, and the plane geometric center is located outside the orthographic projection of one of the two insulating patterns on the semiconductor substrate.

[0013] According to a third aspect of an embodiment of the present disclosure, an electronic device is provided, comprising a processor and a memory provided by any embodiment of the present disclosure. The memory is coupled to the processor.

[0014] In the memory provided by the embodiments of the present disclosure, the storage node landing pad includes a first part (lower part) located between two bit line structures adjacent to each other and two insulating patterns adjacent to each other, and a second part (upper part) extending from the first part and arranged on one of the two insulating patterns, wherein the second part mainly overlaps with one of the two insulating patterns adjacent to each other, thereby alleviating or avoiding the problem of narrowing (necking) of the extension portion of the first part connected to the second part. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1A It is a partial structural plan diagram of a memory;

[0016] Figure 1B For along Figure 1A A schematic diagram of the cross-sectional structure taken along the A1-A2 line in FIG.

[0017] Figure 1C For along Figure 1A A schematic diagram of the cross-sectional structure taken along the line B1-B2 in FIG.

[0018] Figure 1D For along Figure 1A Schematic diagram of the cross-sectional structure taken along the C1-C2 line;

[0019] Figure 1E For along Figure 1A Schematic diagram of the cross-sectional structure taken along the D1-D2 line;

[0020] Figure 2A A partial structural plan view of a memory provided in some embodiments of the present disclosure;

[0021] Figure 2B For a Figure 2A A schematic diagram of the cross-sectional structure taken along the A1-A2 line in FIG.

[0022] Figure 2C For a Figure 2A A schematic diagram of the cross-sectional structure taken along the line B1-B2 in FIG.

[0023] Figure 2D For a Figure 2A Schematic diagram of the cross-sectional structure taken along the C1-C2 line;

[0024] Figure 2E For a Figure 2A Schematic diagram of the cross-sectional structure taken along the D1-D2 line;

[0025] Figures 3A-3E A schematic diagram of various stages of a method for manufacturing a memory provided in some embodiments of the present disclosure;

[0026] Figure 4 A schematic block diagram of the structure of an electronic device provided for some embodiments of the present disclosure. DETAILED DESCRIPTION

[0027] The technical solution of the present disclosure will be further described in detail below in conjunction with the accompanying drawings and embodiments. Although the exemplary implementation methods of the present disclosure are shown in the accompanying drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the implementation methods described here. On the contrary, these implementation methods are provided in order to enable a more thorough understanding of the present disclosure and to fully convey the scope of the present disclosure to those skilled in the art.

[0028] The present disclosure is described in more detail in the following paragraphs by way of example with reference to the accompanying drawings. The advantages and features of the present disclosure will become more apparent from the following description and claims. It should be noted that the drawings are in very simplified form and in non-precise proportions, and are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present disclosure.

[0029] It will be understood that the meaning of “on,” “over,” and “over” of the present disclosure should be interpreted in the broadest manner, so that “on” not only means that it is “on” something with no intervening features or layers (i.e., directly on something), but also includes the meaning that it is “on” something with intervening features or layers.

[0030] In the embodiments of the present disclosure, the terms "first", "second", "third", etc. are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence.

[0031] In the disclosed embodiments, the term "layer" refers to a material portion including an area having a thickness. A layer may extend over the entirety of a lower or upper structure, or may have an extent less than the extent of a lower or upper structure. In addition, a layer may be an area of ​​a homogeneous or inhomogeneous continuous structure having a thickness less than the thickness of a continuous structure. For example, a layer may be located between the top and bottom surfaces of a continuous structure, or a layer may be between any horizontal faces at the top and bottom surfaces of a continuous structure. A layer may extend horizontally, vertically, and / or along an inclined surface. A layer may include multiple sublayers.

[0032] In the embodiments of the present disclosure, the term "coupling" refers to two (or more) conductive structures being operably connected to each other. Depending on actual needs, it may include but is not limited to the following situations: 1) the two conductive structures are directly electrically connected; 2) the two conductive structures are indirectly electrically connected (through other conductive structures); 3) although the two conductive structures are not electrically connected (for example, an insulating layer is provided between the two), one of the two conductive structures can control the electrical properties of the other of the two conductive structures in response to an electrical signal, for example, the gate (or word line) is coupled with the active area (or channel area).

[0033] It should be noted that the technical solutions and technical features recorded in the embodiments of the present disclosure can be arbitrarily combined without conflict.

[0034] Figure 1A It is a partial structural plan diagram of a memory. Figure 1B For along Figure 1A The schematic diagram of the cross-sectional structure taken along the A1-A2 line in FIG. Figure 1C For along Figure 1A The schematic diagram of the cross-sectional structure taken along the line B1-B2 in FIG. Figure 1D For along Figure 1A Schematic diagram of the cross-sectional structure taken along the C1-C2 line in FIG. Figure 1E For along Figure 1A Schematic diagram of the cross-sectional structure taken along the D1-D2 line.

[0035] like Figures 1A-1E As shown, in the memory, a trench isolation structure 105 is arranged in a semiconductor substrate 100 to define an active area ACT; a word line structure WLS is arranged in the semiconductor substrate 100, the word line structure WLS extends along a first horizontal direction X and passes through the active area ACT and the trench isolation structure 105; a bit line structure BLS is arranged on the semiconductor substrate 100, the bit line structure BLS extends along a second horizontal direction Y and crosses the word line structure WLS; an insulating pattern ISP is arranged between adjacent bit line structures BLS; a storage node landing pad LP includes a lower portion P1 arranged in a contact hole defined by two adjacent bit line structures BLS and two adjacent insulating patterns ISP, and an upper portion P2 extending from the lower portion P1 and arranged on one of the two adjacent bit line structures BLS. Exemplarily, in Figure 1C and Figure 1E , it is shown that one storage node landing pad LP is divided into a lower portion P1 and an upper portion P2 by a black solid line parallel to the top surfaces of the bit line structure BLS and the insulation pattern ISP.

[0036] like Figures 1A-1EAs shown, in the memory, the word line structure WLS includes a word line 110, a gate insulating layer 109 disposed between the word line and the semiconductor substrate 100, and a word line capping layer pattern 111 disposed on the word line 110; an isolation layer 115 is disposed on the semiconductor substrate 100, and a bit line structure BLS and an insulating pattern ISP are disposed on the isolation layer 115; the bit line structure BLS includes a bit line stack structure BLSS and a spacer structure SPS disposed on the sidewall of the bit line stack structure BLSS, and the bit line stack structure BLSS includes a bit line 120 and a bit line capping pattern 121 arranged on the bit line 120, the bit line 120 is coupled to the corresponding active area ACT through a bit line contact plug 118 penetrating the isolation layer 115; the contact pattern 128 is arranged in a contact hole defined by two adjacent bit line structures BLS and two adjacent insulation patterns ISP, the storage node landing pad LP is coupled to the corresponding active area ACT through the contact pattern 128 penetrating the isolation layer 115; the pad insulation pattern 135 is arranged between adjacent storage node landing pads.

[0037] During the study, the inventors of the present application noticed that: Figures 1A-1E In the memory shown, the upper portion P2 of the storage node landing pad LP mainly overlaps with one of the two bit line structures BLS adjacent to each other, and the extension portion of the lower portion P1 connected to the upper portion P2 is located on the side wall of the bit line structure BLS; as the semiconductor device is miniaturized, the above extension portion becomes narrower (necking), which easily leads to the problem of the extension portion being disconnected or having too large resistance; in order to alleviate or avoid the above problem, a technical solution in the prior art is to add a step of etching the spacer structure SPS on the side wall of the bit line capping layer pattern 121 to increase the lateral size of the upper portion of the contact hole, thereby increasing the lateral size of the extension portion of the lower portion P1 of the storage node landing pad LP formed subsequently. However, the above solution requires the addition of additional process steps, which is not conducive to reducing manufacturing costs.

[0038] At least some embodiments of the present disclosure provide a memory. The memory includes: a semiconductor substrate, including an active area and a trench isolation structure defining the active area, the active area is arranged in a zigzag shape; a word line structure, extending along a first horizontal direction in the semiconductor substrate; a bit line structure, extending along a second horizontal direction perpendicular to the first horizontal direction on the semiconductor substrate; an insulating pattern, arranged between adjacent bit line structures; a storage node landing pad, including a first portion arranged between two adjacent bit line structures and two adjacent insulating patterns, and a second portion extending from the first portion and arranged on one of the two adjacent insulating patterns, wherein the horizontal extension direction of the active area intersects the first horizontal direction and the second horizontal direction respectively, the spacing between the two adjacent insulating patterns is greater than the spacing between the two adjacent bit line structures, and the plane geometric center of the orthographic projection of the second portion on the semiconductor substrate is biased toward the orthographic projection of one of the two adjacent insulating patterns on the semiconductor substrate, and the plane geometric center is located outside the orthographic projection of one of the two adjacent insulating patterns on the semiconductor substrate.

[0039] In the memory provided by the embodiment of the present disclosure, the second part (upper part) of the storage node landing pad mainly overlaps with one of the two insulating patterns adjacent to each other. Since the size of the insulating pattern in the second horizontal direction can be adjusted as needed (for example, the size of the insulating pattern in the second horizontal direction can be reduced as long as it can meet sufficient insulation performance to reduce or avoid leakage), the problem of the extension portion of the first part (lower part) of the storage node landing pad connected to the second part is narrowed (necking). It can be understood that the adjustable range of the size of the insulating pattern in the second horizontal direction is greater than the adjustable range of the size of the bit line structure in the first horizontal direction (refer to the above-mentioned related description); compared with the technical solution in the prior art (etching to increase the lateral size of the upper part of the contact hole), the technical solution provided by the embodiment of the present disclosure does not require the addition of additional process steps.

[0040] Figure 2A A partial structural plan view of a memory provided in some embodiments of the present disclosure is provided. Figure 2B For a Figure 2A The schematic diagram of the cross-sectional structure taken along the A1-A2 line in FIG. Figure 2C For a Figure 2A The schematic diagram of the cross-sectional structure taken along the line B1-B2 in FIG. Figure 2D For a Figure 2A Schematic diagram of the cross-sectional structure taken along the C1-C2 line in FIG. Figure 2E For a Figure 2A Schematic diagram of the cross-sectional structure taken along the D1-D2 line.

[0041] like Figure 2A-2EAs shown, the memory includes a semiconductor substrate 100, a word line structure WLS, a bit line structure BLS, an insulation pattern ISP, and a storage node landing pad LP.

[0042] For example, Figure 2A-2E As shown, the semiconductor substrate 100 may include an active region ACT and a trench isolation structure 105 defining the active region ACT. For example, the active region ACT is in a strip shape, and the active region ACT is arranged in a zigzag shape (also called a zigzag shape). Figure 3A As shown, the horizontal extension direction of the active area ACT intersects the first horizontal direction X and the second horizontal direction Y respectively, and the multiple active areas ACT arranged along the second horizontal direction Y are regarded as an active area row, and two adjacent active area rows are staggered.

[0043] For example, the material of the semiconductor substrate 100 (i.e., the material of the active area ACT) may include any suitable semiconductor material, such as silicon, germanium, silicon germanium, etc. For example, the material of the trench isolation structure 105 may include any suitable dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, or any combination thereof.

[0044] For example, Figure 2A-2E As shown, the word line structure WLS is disposed in the semiconductor substrate 100, and the word line structure WLS extends along the first horizontal direction X and passes through the active area ACT and the trench isolation structure 105. Figure 3B As shown in FIG. 1 , an active area ACT is passed through by two word line structures. Figure 2A-2E As shown, the word line structure WLS may include a word line 110 , a gate insulating layer 109 disposed between the word line and the semiconductor substrate 100 , and a word line capping layer pattern 111 disposed on the word line 110 .

[0045] For example, the material of the word line 110 may include any suitable conductive material, such as titanium nitride (TiN), tantalum nitride (TaN), tungsten, metal silicide or any combination thereof. For example, the material of the gate dielectric layer 10 may include any suitable dielectric material, such as silicon oxide, high-K dielectric material or any combination thereof; for example, the high-K dielectric material may include but is not limited to hafnium oxide (HfO 2 ), zirconium oxide (ZrO 2 ) etc. For example, the material of the word line capping layer pattern 111 may include any suitable dielectric material, such as silicon nitride, silicon oxynitride, etc.

[0046] For example, Figure 2A-2E As shown, the bit line structure BLS is disposed on the semiconductor substrate 100, and the bit line structure BLS extends along the second horizontal direction Y and crosses the word line structure WLS. Figure 2A-2EAs shown, the bit line structure BLS may include a bit line stack structure BLSS and a spacer structure SPS disposed on the sidewall of the bit line stack structure BLSS, and the bit line stack structure BLSS may include a bit line 120 and a bit line capping layer pattern 121 disposed on the bit line 120. For example, an air gap may be disposed in the spacer structure SPS to reduce parasitic capacitance.

[0047] For example, the material of the bit line 120 may include any suitable conductive material, such as titanium nitride (TiN), tantalum nitride (TaN), tungsten, metal silicide, doped polysilicon, or any combination thereof. For example, the material of the bit line capping layer pattern 121 may include any suitable dielectric material, such as silicon nitride, silicon oxynitride, etc. For example, the spacer structure SPS may include any suitable dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, or any combination thereof.

[0048] For example, Figure 2A-2E As shown in FIG. 1 , the insulating pattern ISP is disposed between adjacent bit line structures BLS. Figure 2A-2E As shown, the insulation pattern ISP extends along the first horizontal direction X and is disposed on the word line structure WLS.

[0049] For example, the material of the insulating pattern ISP may include any suitable dielectric material, such as silicon nitride, silicon oxynitride, or any combination thereof.

[0050] For example, Figure 2A-2E As shown, the memory may further include an isolation layer 115 disposed on the semiconductor substrate 100, and the bit line structure BLS and the insulation pattern ISP are disposed on the isolation layer 115. Figure 2A-2E As shown, the memory may further include a bit line contact plug 118 penetrating the isolation layer 115, and the bit line 120 is coupled to the corresponding active area ACT through the bit line contact plug 118. Figure 2A-2E As shown, the bit line contact plug 118 is at least partially located in a recess of the semiconductor substrate 100 , and the recess at least partially exposes the corresponding active area ACT.

[0051] For example, the material of the isolation layer 115 may be an insulating material, and has a certain etching selectivity ratio with the material of the insulating pattern ISP. For example, in some examples, the material of the isolation layer 115 includes silicon oxide, and the material of the insulating pattern ISP includes silicon nitride. For example, the material of the bit line contact plug 118 may include any suitable conductive material, such as doped polysilicon, metal silicide, or any combination thereof.

[0052] For example, Figure 2A-2EAs shown, the storage node landing pad LP includes a first portion (lower portion) P1 disposed between two bit line structures BLS adjacent to each other and two insulating patterns ISP adjacent to each other, and a second portion (upper portion) P2 extending from the first portion P1 and disposed on one of the two insulating patterns ISP adjacent to each other. Figure 2A-2E As shown in FIG. 1 , the first portion P1 is disposed in a contact hole defined by two adjacent bit line structures BLS and two adjacent insulation patterns ISP. Figure 2A As shown, the orthographic projection of the second portion P2 on the semiconductor substrate 100 is in a hexagonal close-packed form.

[0053] For example, the storage node landing pad LP may include any suitable conductive material, such as titanium nitride (TiN), tantalum nitride (TaN), tungsten, or any combination thereof, etc. For example, in some examples, the storage node landing pad LP may include a diffusion barrier pattern formed of titanium nitride and a conductive pattern formed of tungsten.

[0054] For example, Figure 2A-2E As shown, the memory may further include a contact pattern 128, which is disposed between the storage node landing pad LP and the active area ACT and electrically connects the storage node landing pad LP and the active area ACT. Figure 2A-2E As shown, the contact pattern 128 is disposed in a contact hole defined by two adjacent bit line structures BLS and two adjacent insulation patterns ISP, the contact pattern 128 penetrates the isolation layer 115 , and the storage node landing pad LP is coupled to the corresponding active area ACT through the contact pattern 128 .

[0055] For example, the material of the contact pattern 128 may include any suitable conductive material, such as doped polysilicon, metal silicide, or any combination thereof.

[0056] For example, Figure 2A-2E As shown, the memory may further include a pad insulating pattern 135 disposed between adjacent storage node landing pads LP.

[0057] For example, the material of the pad insulating pattern 135 may include any suitable dielectric material, such as silicon oxide, silicon nitride, silicon oxynitride, or any combination thereof.

[0058] For example, the memory may further include a storage node pattern, the storage node pattern is disposed on the storage node landing pad LP, and the orthographic projection of the storage node pattern on the semiconductor substrate 100 is in a hexagonal close-packed form. For example, the storage node pattern may be a capacitor, a ferroelectric capacitor, a phase change unit, a magnetic tunnel junction (MTJ), etc. The embodiments of the present disclosure are described by taking the storage node pattern as a capacitor as an example, but this should not be regarded as a limitation of the present disclosure.

[0059] For example, in some embodiments, reference Figure 3E As shown, the capacitor (i.e., storage node pattern) CAP includes a first electrode 140, a second electrode 150, and a capacitor dielectric layer 145 disposed between the first electrode 140 and the second electrode 150. For example, the first electrode 140 can be coupled to the corresponding active area ACT through the storage node landing pad LP and the contact pattern 128. For example, the orthographic projection of the first electrode 140 on the semiconductor substrate 100 is in a hexagonal close-packed form. For example, the second electrode 150 can be formed as a common electrode.

[0060] For example, the materials of the first electrode 140 and the second electrode 150 include any suitable conductive material, such as titanium nitride (TiN), tantalum nitride (TaN), tungsten, metal silicide, doped polysilicon or any combination thereof. For example, the material of the capacitor dielectric layer 145 includes any suitable dielectric material, such as silicon oxide, silicon nitride, high-K dielectric material or any combination thereof; for example, the material of the capacitor dielectric layer 145 may also include a dielectric material having ferroelectricity or antiferroelectricity, such as hafnium oxide in a ferroelectric phase, hafnium zirconium oxide in a ferroelectric phase, etc.; that is, the capacitor CAP may be formed as a ferroelectric capacitor.

[0061] It should be noted that the structure of the capacitor CAP in the drawings of the present disclosure is schematic, and the embodiments of the present disclosure do not limit the structure of the capacitor CAP, as long as the first electrode 140, the second electrode 150 and the capacitor dielectric layer 145 are arranged to form a capacitor. For example, the first electrode 140 can be columnar (as shown in the figure), or plate-shaped or U-shaped, or any other suitable shape; the second electrode 150 conformally covers the sidewall and / or top surface of the first electrode 150, and the capacitor dielectric layer 145 is located between the first electrode 140 and the second electrode 150. For example, in some embodiments, in the first semiconductor structure, one or more support layers for supporting the first electrode can be provided, and the support layer is in a grid shape, and the capacitor dielectric layer 145 and the second electrode 150 can partially cover the support layer.

[0062] For example, Figure 2AAs shown, the spacing between two adjacent insulating patterns ISP is greater than the spacing between two adjacent bit line structures BLS, and the plane geometric center of the orthographic projection of the second portion P2 on the semiconductor substrate 100 is biased toward the orthographic projection of one of the two adjacent insulating patterns ISP on the semiconductor substrate 100, and the plane geometric center is located outside the orthographic projection of one of the two adjacent insulating patterns ISP on the semiconductor substrate 100. Such a configuration is conducive to increasing the size of the extension portion of the first portion P1 of the storage node landing pad LP connected to the second portion in the second horizontal direction Y, thereby avoiding or reducing the problem of necking of the extension portion.

[0063] For example, Figure 2A As shown, the overlapping area of ​​the second portion P2 and the orthographic projection of one of the two adjacent insulating patterns ISP on the semiconductor substrate 100 is greater than the overlapping area of ​​the second portion P2 and the orthographic projection of any of the two adjacent bit line structures BLS on the semiconductor substrate 100. Here, the overlapping area of ​​the second portion P2 and the orthographic projection of one of the two adjacent insulating patterns ISP on the semiconductor substrate 100 refers to: the area of ​​the overlapping portion of the orthographic projection of the second portion P2 on the semiconductor substrate 100 and the orthographic projection of one of the two adjacent insulating patterns ISP on the semiconductor substrate 100; similarly, the overlapping area of ​​the second portion P2 and the orthographic projection of any of the two adjacent bit line structures BLS on the semiconductor substrate 100 refers to: the area of ​​the overlapping portion of the orthographic projection of the second portion P2 on the semiconductor substrate 100 and the orthographic projection of any of the two adjacent bit line structures BLS on the semiconductor substrate 100. For example, in some examples, the overlapping area between the second portion P2 and any of the orthographic projections of two adjacent bit line structures BLS on the semiconductor substrate 100 can be 0, that is, the orthographic projection of the second portion P2 on the semiconductor substrate 100 does not overlap with the orthographic projection of any of the two adjacent bit line structures BLS on the semiconductor substrate 100.

[0064] For example, the plane shape of the orthographic projection of the second portion P2 on the semiconductor substrate 100 may be a circle (eg Figure 2A As shown), ellipse, rounded rhombus, rounded rectangle, etc. For example, Figure 2A As shown, the orthographic projection of the second portion P2 on the semiconductor substrate 100 may have a symmetry axis extending along the second horizontal direction Y; for example, the symmetry axis is substantially equal to the spacing between the orthographic projections of two adjacent bit line structures BLS on the semiconductor substrate 100. Figure 2AAs shown, the orthographic projection of the second part P2 on the semiconductor substrate 100 may also have a symmetry axis extending along the first horizontal direction X, and the distance between the symmetry axis and the orthographic projection of one of the two adjacent insulating patterns ISP on the semiconductor substrate 100 is smaller than the distance between the symmetry axis and the orthographic projection of the other of the two adjacent insulating patterns ISP on the semiconductor substrate 100.

[0065] For example, Figure 2A As shown, the maximum size of the second portion P2 in the second horizontal direction Y may be greater than or equal to the size of the insulating pattern ISP in the second horizontal direction Y. Such a configuration is conducive to further increasing the size of the extension portion of the first portion P1 of the storage node landing pad LP connected to the second portion in the second horizontal direction Y, thereby avoiding or alleviating the problem of necking of the extension portion.

[0066] For example, Figure 2A As shown, the maximum size of the second portion P2 in the second horizontal direction Y may be greater than or equal to the spacing between two adjacent insulating patterns ISP. This arrangement is conducive to further increasing the size of the extension portion of the first portion P1 of the storage node landing pad LP connected to the second portion in the second horizontal direction Y, thereby avoiding or alleviating the problem of necking of the extension portion.

[0067] It should be noted that, in the embodiment of the present disclosure, “two bit line structures adjacent to each other” refer to two bit line structures adjacent to each other in the second horizontal direction, which together with the two bit line structures adjacent to each other define a contact hole.

[0068] Since the adjustable range of the size of the insulation pattern ISP in the second horizontal direction Y is greater than the adjustable range of the size of the bit line structure BLS in the first horizontal direction X, in the memory provided in the embodiment of the present disclosure, the second part (upper part) of the storage node landing pad mainly overlaps with one of the two insulation patterns adjacent to each other, so as to facilitate the adjustment of the size of the insulation pattern ISP in the second horizontal direction Y as needed (correspondingly, the spacing between the two insulation patterns ISP adjacent to each other can also be adjusted) to reduce or avoid the problem of narrowing (necking) of the extension portion of the first part (lower part) of the storage node landing pad connected to the second part.

[0069] At least some embodiments of the present disclosure further provide a method for manufacturing a memory, which can be used to manufacture the memory provided by the aforementioned embodiments (refer to Figure 2A-2E shown). Figures 3A-3E The present invention provides a schematic diagram of various stages of a method for manufacturing a memory according to some embodiments of the present invention. Figures 3A-3E and Figure 2A-2EThe manufacturing method of the memory provided by the embodiment of the present disclosure is described. For example, the manufacturing method may include the following steps S100 to S600.

[0070] S100: providing a semiconductor substrate.

[0071] For example, refer to Figure 3A and Figure 2A-2E As shown, the initial semiconductor substrate may be etched to form a plurality of active areas ACT arranged in an array and shallow trenches defining the plurality of active areas ACT, and then a trench isolation structure 105 may be formed in the shallow trenches. For example, the semiconductor substrate 100 may include an active area ACT and a trench isolation structure 105 defining the active area ACT ( Figure 3A For example, the active area ACT is in the shape of a strip, and the active area ACT is arranged in a zigzag shape (also called a Z-shaped, zigzag). Figure 3A As shown, the horizontal extension direction of the active area ACT intersects the first horizontal direction X and the second horizontal direction Y respectively, and the multiple active areas ACT arranged along the second horizontal direction Y are regarded as an active area row, and two adjacent active area rows are staggered.

[0072] S200: forming a word line structure extending along a first horizontal direction in a semiconductor substrate.

[0073] For example, refer to Figure 3B and Figure 2A-2E As shown, a word line trench extending along the first horizontal direction X can be formed in the semiconductor substrate 100 by etching, and the word line trench passes through the active area ACT and the trench isolation structure 105; then, a gate insulation layer 109, a word line 110 and a word line capping layer pattern 111 are sequentially formed in the word line trench.

[0074] S300: forming a bit line structure extending along a second horizontal direction on a semiconductor substrate.

[0075] For example, refer to Figure 3C and Figure 2A-2EAs shown, an isolation layer 115 may be first formed on a semiconductor substrate 100, and an initial bit line contact plug may be formed penetrating the isolation layer 115; then, a bit line material layer and a bit line capping layer may be sequentially formed on the isolation layer 115 and the initial bit line contact plug, and the bit line capping layer, the bit line material layer, and the initial bit line contact plug may be patterned to obtain a bit line capping layer pattern 121, a bit line 120, and a bit line contact plug 118 correspondingly, wherein the bit line 120 and the bit line capping layer pattern 121 together constitute a bit line stacking structure BLSS; then, a spacer structure SPS may be formed on the sidewall of the bit line stacking structure BLSS, wherein the bit line spacer structure SPS also covers the sidewall of the bit line contact plug 118. For example, an air gap may be provided in the spacer structure SPS to reduce parasitic capacitance.

[0076] S400: forming an insulation pattern between adjacent bit line structures.

[0077] For example, refer to Figure 3D and Figure 2A-2E As shown, an insulating layer may be first formed between adjacent bit line structures; then, the insulating layer may be patterned to form a contact hole and an insulating pattern ISP defining the contact hole. It is understood that in the process of forming the contact hole, a portion of the isolation layer 115 may be etched to expose the corresponding active area ACT. For example, the insulating pattern ISP extends along the first horizontal direction X and is disposed on the word line structure WLS. For example, two bit line structures BLS adjacent to each other and two insulating patterns ISP adjacent to each other define a contact hole.

[0078] S500: forming a storage node landing pad.

[0079] For example, refer to Figure 2A-2E As shown, a contact pattern 128 can be first formed in the contact hole; then, a diffusion barrier layer and a metal layer are formed in sequence, wherein the diffusion barrier layer conformally covers the top surface of the bit line structure BLS, the top surface of the insulating pattern ISP, the top surface of the contact pattern 128 and the side wall of the contact hole, and the metal layer covers the diffusion barrier layer and fills the contact hole; thereafter, the metal layer and the diffusion barrier layer are patterned to obtain a conductive pattern and a diffusion barrier pattern correspondingly, wherein the conductive pattern and the diffusion barrier pattern together constitute a storage node landing pad LP.

[0080] For example, Figure 2A-2E As shown, the storage node landing pad LP includes a first portion (lower portion) P1 located in the contact hole and a second portion (upper portion) P2 extending from the first portion P1 and located on one of the two insulating patterns ISP adjacent to each other. Figure 2A As shown, the orthographic projection of the second portion P2 on the semiconductor substrate 100 is in a hexagonal close-packed form.

[0081] For example, Figure 2AAs shown, the spacing between two adjacent insulating patterns ISP is greater than the spacing between two adjacent bit line structures BLS, and the plane geometric center of the orthographic projection of the second portion P2 on the semiconductor substrate 100 is biased toward the orthographic projection of one of the two adjacent insulating patterns ISP on the semiconductor substrate 100, and the plane geometric center is located outside the orthographic projection of one of the two adjacent insulating patterns ISP on the semiconductor substrate 100. Such a configuration is conducive to increasing the size of the extension portion of the first portion P1 of the storage node landing pad LP connected to the second portion in the second horizontal direction Y, thereby avoiding or reducing the problem of necking of the extension portion.

[0082] For example, Figure 2A As shown, the overlapping area of ​​the orthographic projection of the second portion P2 and one of the two adjacent insulating patterns ISP on the semiconductor substrate 100 is greater than the overlapping area of ​​the orthographic projection of the second portion P2 and any of the two adjacent bit line structures BLS on the semiconductor substrate 100 .

[0083] For example, the plane shape of the orthographic projection of the second portion P2 on the semiconductor substrate 100 may be a circle (eg Figure 2A As shown), ellipse, rounded rhombus, rounded rectangle, etc. For example, Figure 2A As shown, the orthographic projection of the second portion P2 on the semiconductor substrate 100 may have a symmetry axis extending along the second horizontal direction Y; for example, the symmetry axis is substantially equal to the spacing between the orthographic projections of two adjacent bit line structures BLS on the semiconductor substrate 100. Figure 2A As shown, the orthographic projection of the second part P2 on the semiconductor substrate 100 may also have a symmetry axis extending along the first horizontal direction X, and the distance between the symmetry axis and the orthographic projection of one of the two adjacent insulating patterns ISP on the semiconductor substrate 100 is smaller than the distance between the symmetry axis and the orthographic projection of the other of the two adjacent insulating patterns ISP on the semiconductor substrate 100.

[0084] For example, Figure 2A As shown, the maximum size of the second portion P2 in the second horizontal direction Y may be greater than or equal to the size of the insulating pattern ISP in the second horizontal direction Y. Such a configuration is conducive to further increasing the size of the extension portion of the first portion P1 of the storage node landing pad LP connected to the second portion in the second horizontal direction Y, thereby avoiding or alleviating the problem of necking of the extension portion.

[0085] For example, Figure 2AAs shown, the maximum size of the second portion P2 in the second horizontal direction Y may be greater than or equal to the spacing between two adjacent insulating patterns ISP. This arrangement is conducive to further increasing the size of the extension portion of the first portion P1 of the storage node landing pad LP connected to the second portion in the second horizontal direction Y, thereby avoiding or alleviating the problem of necking of the extension portion.

[0086] S600: forming a storage node pattern on a storage node landing pad.

[0087] For example, a storage node pattern may be formed on the storage node landing pad LP, wherein the storage node pattern has a hexagonal close-packed orthographic projection on the semiconductor substrate 100. For example, the storage node pattern may be a capacitor, a ferroelectric capacitor, a phase change unit, a magnetic tunnel junction (MTJ), etc.

[0088] Taking the storage node pattern as a capacitor as an example, refer to Figure 2A-2E and Figure 3E As shown, a first electrode 140 may be first formed on the storage node landing pad LP; then, a capacitor dielectric layer 145 is formed to conformally cover the top surface and sidewalls of the first electrode 140; then, a second electrode 150 is formed to cover the capacitor dielectric layer 145, wherein the first electrode 140, the capacitor dielectric layer 145 and the second electrode 150 together constitute a capacitor CAP. For example, the second electrode 150 may be formed as a common electrode.

[0089] It should be noted that details not described in the embodiment of the manufacturing method disclosed herein can be referred to the relevant description of the aforementioned memory embodiment and will not be repeated here.

[0090] In the manufacturing method provided by the embodiment of the present disclosure, the second part (upper part) of the storage node landing pad mainly overlaps with one of the two insulating patterns adjacent to each other. Since the size of the insulating pattern in the second horizontal direction can be adjusted as needed (for example, the size of the insulating pattern in the second horizontal direction can be reduced as long as it can meet sufficient insulation performance to reduce or avoid leakage), the problem of the extension portion of the first part (lower part) of the storage node landing pad connected to the second part being narrowed (necking) can be alleviated or avoided. Compared with the technical solution in the prior art (etching to increase the lateral size of the upper part of the contact hole), the technical solution provided by the embodiment of the present disclosure does not require the addition of additional process steps.

[0091] At least some embodiments of the present disclosure also provide an electronic device. Figure 4 The following is a schematic block diagram of the structure of an electronic device provided in some embodiments of the present disclosure. Figure 4As shown, the electronic device 1 includes a processor 20 and a memory 10 coupled to each other, wherein the memory 10 is the memory provided by any of the aforementioned embodiments.

[0092] For example, the processor 20 may include, but is not limited to, a central processing unit (CPU), a graphics processing unit (GPU), etc. The memory 10 may be configured to store data to be processed by the processor 20 and / or data processed by the processor.

[0093] For example, the electronic device 1 includes but is not limited to mobile phones, tablet computers, smart bracelets, wearable electronic devices, virtual reality devices, augmented reality devices, vehicle-mounted devices, servers, workstations, etc.

[0094] The above is only a specific implementation of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any person skilled in the art who is familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present disclosure, which should be included in the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be based on the protection scope of the claims.

Claims

1. A memory, characterized in that: include: A semiconductor substrate, comprising an active region and a trench isolation structure defining the active region, wherein the active region is arranged in a zigzag shape; a word line structure extending in a first horizontal direction in the semiconductor substrate; A bit line structure extending on the semiconductor substrate along a second horizontal direction perpendicular to the first horizontal direction; An insulating pattern disposed between adjacent bit line structures; a storage node landing pad, comprising a first portion disposed between two bit line structures adjacent to each other and two insulating patterns adjacent to each other, and a second portion extending from the first portion and disposed on one of the two insulating patterns adjacent to each other, In which, the horizontal extension direction of the active area intersects with the first horizontal direction and the second horizontal direction respectively, the spacing between the two adjacent insulating patterns is greater than the spacing between the two adjacent bit line structures, and the plane geometric center of the orthographic projection of the second part on the semiconductor substrate is biased towards the orthographic projection of one of the two adjacent insulating patterns on the semiconductor substrate, and the plane geometric center is located outside the orthographic projection of one of the two adjacent insulating patterns on the semiconductor substrate.

2. The memory according to claim 1, characterized in that: An overlapping area between the second portion and an orthographic projection of one of the two adjacent insulating patterns on the semiconductor substrate is greater than an overlapping area between the second portion and an orthographic projection of any of the two adjacent bit line structures on the semiconductor substrate.

3. The memory according to claim 1, characterized in that: An orthographic projection of the second portion on the semiconductor substrate has a symmetry axis extending along the second horizontal direction.

4. The memory according to claim 3, characterized in that: A maximum dimension of the second portion in the second horizontal direction is greater than or equal to a dimension of the insulation pattern in the second horizontal direction.

5. The memory according to any one of claims 1 to 4, characterized in that: A maximum dimension of the second portion in the second horizontal direction is greater than or equal to a distance between the two insulating patterns adjacent to each other.

6. The memory according to any one of claims 1 to 4, characterized in that: The bit line structure comprises: Bit line stacking structure; The spacer structure is disposed on the sidewall of the bit line stack structure.

7. The memory according to any one of claims 1 to 4, characterized in that: Also includes: A storage node pattern is disposed on the storage node landing pad, wherein an orthographic projection of the storage node pattern on the semiconductor substrate is in a hexagonal close-packed form.

8. The memory according to claim 7, characterized in that: Also includes: A contact pattern is disposed between the storage node landing pad and the active area and electrically connects the storage node landing pad and the active area.

9. A method for manufacturing a memory, characterized in that: include: Providing a semiconductor substrate, wherein the semiconductor substrate comprises an active region and a trench isolation structure defining the active region, and the active region is arranged in a zigzag shape; forming a word line structure extending along a first horizontal direction in the semiconductor substrate; forming a bit line structure extending along a second horizontal direction on the semiconductor substrate; forming an insulating pattern between adjacent bit line structures, wherein two bit line structures adjacent to each other and two insulating patterns adjacent to each other define a contact hole; forming a storage node landing pad, wherein the storage node landing pad includes a first portion located in the contact hole and a second portion extending from the first portion and located on one of the two insulating patterns adjacent to each other, In which, the horizontal extension direction of the active area intersects with the first horizontal direction and the second horizontal direction respectively, and the plane geometric center of the orthographic projection of the second part on the semiconductor substrate is biased towards the orthographic projection of one of the two insulating patterns on the semiconductor substrate, and the plane geometric center is located outside the orthographic projection of one of the two insulating patterns on the semiconductor substrate.

10. An electronic device, characterized in that: include: processor; as well as The memory according to any one of claims 1 to 8, wherein the memory is coupled to the processor.

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