Display panel, method for manufacturing display panel, and display device

Abstract

The present application provides a display panel, a manufacturing method thereof, and a display device. The display panel includes: an array substrate including a first metal layer, the first metal layer including a first auxiliary electrode and a first anode; a pixel definition layer covering the first metal layer; the pixel definition layer including a first auxiliary opening and a first pixel opening; a light-emitting layer including a first light-emitting unit and located on a side of the pixel definition layer away from the array substrate, the first light-emitting unit being connected to the first anode and the first auxiliary electrode, respectively; and a second metal layer including a cathode, located on a side of the light-emitting layer away from the pixel definition layer. The display panel also includes a shielding layer located between the pixel definition layer and the light-emitting layer, the shielding layer being connected to the first light-emitting unit and not to the cathode; the first auxiliary electrode having a first undercut structure, the first light-emitting unit being disconnected at the first undercut structure. The display panel, the manufacturing method thereof, and the display device provided by the present application can overcome the problem of large-scale evaporation.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a display panel, a method for manufacturing a display panel, and a display device. Background Art

[0002] Organic Light-Emitting Diode (OLED) displays are widely used in various fields due to their lightweight, wide viewing angle, fast response, low-temperature resistance, high luminous efficiency, and ability to be made into curved flexible displays. To achieve color display, OLED displays use multiple fine metal masking processes to form red, blue, and green sub-pixels, respectively. However, due to the size and precision limitations of the mask, a certain amount of process error margin must be reserved when forming the sub-pixels. This results in a low pixel density for OLED displays formed using masking, making them difficult to use in large-scale displays. Summary of the Invention

[0003] In view of this, the present application provides a display panel and a display device having high pixel density and capable of being applied to large-size display devices.

[0004] To solve the above problems, the technical solutions provided by this application are as follows:

[0005] The present application provides a display panel, which includes: an array substrate, including a first metal layer, the first metal layer including a first auxiliary electrode and a first anode located on one side of the first auxiliary electrode; a pixel definition layer, located on one side of the array substrate and covering the first metal layer; the pixel definition layer including a first auxiliary opening and a first pixel opening, a portion of the first auxiliary electrode is exposed from the first auxiliary opening, and a portion of the first anode is exposed from the first pixel opening; a light-emitting layer, including a first light-emitting unit and located on a side of the pixel definition layer away from the array substrate, the first light-emitting unit being connected to the first anode and the first auxiliary electrode, respectively; and a second metal layer, including a cathode, the cathode being located on a side of the light-emitting layer away from the pixel definition layer; wherein the display panel also includes a shielding layer, the shielding layer being located between the pixel definition layer and the light-emitting layer, the shielding layer being connected to the first light-emitting unit and not connected to the cathode; the first auxiliary electrode having a first undercut structure, the first undercut structure corresponding to the position of the first auxiliary opening, and the first light-emitting unit being disconnected at the first undercut structure.

[0006] The present application also provides a display device, which includes the display panel as described above.

[0007] The present application also provides a method for manufacturing a display panel, the method comprising: forming an array substrate, the array substrate comprising a first metal layer, the first metal layer comprising a first auxiliary electrode, a first anode located on one side of the first auxiliary electrode, a second auxiliary electrode, and a second anode located on one side of the second auxiliary electrode;

[0008] A pixel definition layer is formed on one side of the array substrate, the pixel definition layer covering the first metal layer and including a first auxiliary opening, a first pixel opening, a second auxiliary opening, and a second pixel opening, a portion of the first auxiliary electrode and a portion of the second auxiliary electrode being exposed through the first auxiliary opening and the second auxiliary opening, respectively, and the remaining pixel definition layer within the first pixel opening and the second pixel opening covering the first anode and the second anode, respectively;

[0009] A patterned shielding layer is formed on a side of the pixel definition layer away from the array substrate, wherein a portion of the first auxiliary electrode and a portion of the second auxiliary electrode are respectively exposed from the shielding layer;

[0010] etching the first auxiliary electrode and the second auxiliary electrode respectively to obtain a first undercut structure and a second undercut structure;

[0011] completely removing the remaining pixel definition layer in the first pixel opening to expose the first anode through a dry etching process, and removing a portion of the pixel definition layer in the second pixel opening, with the remaining pixel definition layer in the second pixel opening covering the second anode;

[0012] forming a first initial light-emitting layer by evaporation on the entire surface and forming a first initial cathode layer on the first initial light-emitting layer, and removing the remaining portions of the first initial light-emitting layer and the first initial cathode layer by a dry etching process to obtain a first light-emitting unit and a first cathode portion, respectively, wherein the first light-emitting unit is connected to the first anode and the first auxiliary electrode, respectively, and is disconnected at the first undercut structure, and the first cathode portion is connected to the first auxiliary electrode;

[0013] completely removing the remaining pixel definition layer within the second pixel opening by a dry etching process to expose the second anode; and

[0014] A second initial light-emitting layer is formed by full-surface vapor deposition and a second initial cathode layer is formed on the second initial light-emitting layer, and the remaining parts of the second initial light-emitting layer and the second initial cathode layer are removed by a dry etching process to obtain a second light-emitting unit and a second cathode portion, respectively. The second light-emitting unit is respectively connected to the second anode and the second auxiliary electrode and is disconnected at the second undercut structure, and the second cathode portion is connected to the second auxiliary electrode.

[0015] The present application provides a display panel, a method for preparing a display panel, and a display device, wherein the display panel includes: an array substrate, including a first metal layer, the first metal layer including a first auxiliary electrode and a first anode located on one side of the first auxiliary electrode; a pixel definition layer, located on one side of the array substrate and covering the first metal layer; the pixel definition layer including a first auxiliary opening and a first pixel opening, a portion of the first auxiliary electrode being exposed from the first auxiliary opening, and a portion of the first anode being exposed from the first pixel opening; a light-emitting layer, including a first light-emitting unit and located on a side of the pixel definition layer away from the array substrate, the first light-emitting unit being connected to the first anode and the first auxiliary electrode, respectively; and a second metal layer including a cathode, the cathode being located on a side of the light-emitting layer away from the pixel definition layer; wherein the display panel also includes a shielding layer, the shielding layer being located between the pixel definition layer and the light-emitting layer, the shielding layer being connected to the first light-emitting unit and not connected to the cathode; the first auxiliary electrode having a first undercut structure, the first undercut structure corresponding to the position of the first auxiliary opening, and the first light-emitting unit being disconnected at the first undercut structure. The present application sets a patterned shielding layer between the pixel definition layer and the light-emitting layer. When forming the light-emitting unit corresponding to the sub-pixel (for example, the first light-emitting unit), the pixel definition layer can be protected and the first initial light-emitting layer can be first formed by whole-surface vapor deposition, and then the excess first initial light-emitting layer can be removed by a photolithography process to obtain the light-emitting unit corresponding to the sub-pixel (for example, the first light-emitting unit). In the process of obtaining the light-emitting unit corresponding to the sub-pixel (for example, the first light-emitting unit), the present application does not need to use multiple fine metal mask processes to evaporate and form red sub-pixels, blue sub-pixels and green sub-pixels respectively, and is not limited by the size and precision limitations of the mask plate. Therefore, the problem of large-size vapor deposition of OLED can be solved, and a display panel with high pixel density can be produced. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For those skilled in the art, other drawings can be obtained based on these drawings without creative work.

[0017] Figure 1 A schematic cross-sectional view of a display panel provided in some embodiments of the present application.

[0018] Figure 2 A schematic flow chart of a method for preparing a display panel provided in some embodiments of the present application.

[0019] Figure 3 A cross-sectional view of an intermediate structure provided in some embodiments of the present application.

[0020] Figure 4 for Figure 3 The cross-sectional view of the first intermediate structure shown is a cross-sectional view after the first dry etching.

[0021] Figure 5 For Figure 4 A cross-sectional view of the first intermediate structure after the first light-emitting unit and the first cathode portion are formed is shown.

[0022] Figure 6 For Figure 5 The cross-sectional view is shown after a second light emitting unit and a second cathode portion are formed on the intermediate structure of the first display panel.

[0023] Figure 7 For Figure 6 The cross-sectional view after a third light emitting unit and a third cathode portion are formed on the first intermediate structure to obtain a second intermediate structure is shown. DETAILED DESCRIPTION

[0024] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the embodiments described are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without making creative efforts are within the scope of protection of this application.

[0025] In the description of the present application, it should be understood that the orientation or positional relationship indicated by the terms "upper" and "lower" is based on the orientation or positional relationship shown in the accompanying drawings, and is only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present application. In addition, the terms "first" and "second" are used for descriptive purposes only and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, the features defined as "first" and "second" may explicitly or implicitly include one or more features. In the description of the present application, the meaning of "multiple" is two or more, unless otherwise clearly and specifically defined.

[0026] The present application may repeat reference numerals and / or reference letters in different embodiments. This repetition is for the purpose of simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or settings discussed.

[0027] See also Figure 1The present application provides a display panel 100, which can be an OLED display panel of the type such as low-temperature polysilicon (LTPS), indium gallium zinc oxide (IGZO), or active-matrix organic light-emitting diode (AMOLED).

[0028] The display panel 100 includes an array substrate 110, a pixel definition layer 120, a shielding layer 130, a light emitting layer 140, and a second metal layer 150. The array substrate 110, the pixel definition layer 120, the shielding layer 130, the light emitting layer 140, and the second metal layer 150 are stacked in sequence.

[0029] In some embodiments of the present application, the array substrate 110 includes a first metal layer 10, the first metal layer 10 includes a first auxiliary electrode 11, a first anode 12 located on one side of the first auxiliary electrode 11, a second auxiliary electrode 13, a second anode 14 located on one side of the second auxiliary electrode 13, a third auxiliary electrode 15 and a third anode 16 located on one side of the third auxiliary electrode 15.

[0030] In some embodiments of the present application, the first anode 12 is located between the first auxiliary electrode 11 and the second auxiliary electrode 13, the second auxiliary electrode 13 is located between the first anode 12 and the second anode 14, the second anode 14 is located between the second auxiliary electrode 13 and the third auxiliary electrode 15, and the third anode 16 is located on a side of the third auxiliary electrode 15 away from the second anode 14. In other embodiments, the arrangement order of the first auxiliary electrode 11, the first anode 12, the second auxiliary electrode 13, the second anode 14, the third auxiliary electrode 15, and the third anode 16 is not limited and can be set according to actual conditions.

[0031] In some embodiments of the present application, the first metal layer 10 may further include more auxiliary electrodes and anodes.

[0032] In some embodiments of the present application, the first auxiliary electrode 11, the first anode 12, the second auxiliary electrode 13, the second anode 14, the third auxiliary electrode 15, and the third anode are disposed in the same layer and made of the same material. The following describes the film structure of the first auxiliary electrode 11, the first anode 12, the second auxiliary electrode 13, the second anode 14, the third auxiliary electrode 15, and the third anode 16, using the first auxiliary electrode 11 as an example. The first anode 12, the second anode 14, and the third anode 16 can each form an electric field with the cathode to enable display on the display panel. The first auxiliary electrode 11, the second auxiliary electrode 13, and the third auxiliary electrode 15 can each contact the cathode to reduce the impedance of the cathode, improve the electrical properties of the display panel, and reduce the power consumption of the display panel.

[0033] Among them, the first auxiliary electrode 11 includes a first electrode layer 101, a second electrode layer 102 and a third electrode layer 103 located between the first electrode layer 101 and the second electrode 102, stacked in the stacking direction of the array substrate 110 and the pixel definition layer 120, and the first electrode layer 101 is located on the array substrate 110.

[0034] The material of the first electrode layer 101 is the same as or different from the material of the second electrode layer 102, and the material of the first electrode layer 101 and the second electrode layer 102 is different from the material of the third electrode layer 103. In some embodiments of the present application, the material of the first electrode layer 101 and the second electrode layer 102 is indium tin oxide (ITO) or indium zinc oxide (IZO), and the material of the third electrode layer 103 is silver (Ag). The first auxiliary electrode 11 has a sandwich structure and is made of different materials, which facilitates obtaining a first undercut structure 111 with the upper and lower layers recessed and the middle layer protruding.

[0035] One end of the third electrode layer 103 of the first auxiliary electrode 11 protrudes from the first electrode layer 101 and the second electrode layer 102 to form a first undercut structure 111 (see FIG. Figure 4 ). Accordingly, one end of the third electrode layer 103 of the second auxiliary electrode 13 protrudes from the first electrode layer 101 and the second electrode layer 102 of the second auxiliary electrode 13 to form a second undercut structure 121 (see Figure 4 ). Accordingly, one end of the third electrode layer 103 of the third auxiliary electrode 15 protrudes from the first electrode layer 101 and the second electrode layer 102 of the third auxiliary electrode 15 to form a third undercut structure 131 (see Figure 4 ).

[0036] The first auxiliary electrode 11 has a first undercut structure 111 , the second auxiliary electrode 13 has a second undercut structure 121 , and the third auxiliary electrode 15 has a third undercut structure 131 .

[0037] Among them, the first undercut structure 111 includes a first undercut groove 112, the first undercut groove 112 includes a first sub-groove 1121 and a second sub-groove 1122 that are connected, the first sub-groove 1121 is located between the third electrode layer 103 of the first auxiliary electrode 11, the first electrode layer 101 and the array substrate 110, and the second sub-groove 1122 is located between the third electrode layer 103 and the second electrode layer 102 of the first auxiliary electrode 11.

[0038] Among them, the second undercut structure 121 includes a second undercut groove 122, the second undercut groove 122 includes a third sub-groove 1221 and a fourth sub-groove 1222 that are connected, the third sub-groove 1221 is located between the third electrode layer 103 of the second auxiliary electrode 13, the first electrode layer 101 and the array substrate 110, and the fourth sub-groove 1222 is located between the third electrode layer 103 and the second electrode layer 102 of the second auxiliary electrode 13.

[0039] Among them, the third undercut structure 131 includes a third undercut groove 132, the third undercut groove 132 includes a connected fifth sub-groove 1321 and a sixth sub-groove 1322, the fifth sub-groove 1321 is located between the third electrode layer 103, the first electrode layer 101 and the array substrate 110 of the second auxiliary electrode 13 of the third auxiliary electrode 15, and the sixth sub-groove 1322 is located between the third electrode layer 103 and the second electrode layer 102 of the third auxiliary electrode 15.

[0040] In some embodiments of the present application, the array substrate 110 further includes a light shielding layer 104 facing away from the pixel definition layer 120, and a transistor 105 located between the light shielding layer 104 and the first metal layer 10. The light shielding layer 104 includes a plurality of first light shielding portions 1041 and a plurality of second light shielding portions 1042. The transistor 105 is located between the light shielding layer 104 and the first metal layer 10. The first auxiliary electrode 11, the second auxiliary electrode 13, and the third auxiliary electrode 15 are each connected to a first light shielding portion 1041. The first anode 12, the second anode 14, and the third anode 16 are each connected to a transistor 105. The transistor 105, each connected to the first anode 12, the second anode 14, and the third anode 16, is each connected to a second light shielding portion 1042.

[0041] In some embodiments of the present application, the array substrate 110 may further include film layers such as a substrate, and the transistor 105 may include an active layer, a gate layer, a source and drain layer, etc., which are not described in detail here.

[0042] The pixel definition layer 120 is located on one side of the array substrate 110 and covers the first metal layer 10 .

[0043] In some embodiments of the present application, the pixel definition layer 120 includes a first auxiliary opening 21, a first pixel opening 22, a second auxiliary opening 23, a second pixel opening 24, a third auxiliary opening 25, and a third pixel opening 26. A portion of the first auxiliary electrode 11 is exposed through the first auxiliary opening 21, and a portion of the first anode 12 is exposed through the first pixel opening 22. A portion of the second auxiliary electrode 13 is exposed through the second auxiliary opening 23, and a portion of the second anode 14 is exposed through the second pixel opening 24. A portion of the third auxiliary electrode 15 is exposed through the third auxiliary opening 25, and a portion of the third anode 16 is exposed through the third pixel opening 26. The first auxiliary opening 21 is connected to the second sub-groove 1122 of the first undercut groove 112, the second auxiliary opening 23 is connected to the fourth sub-groove 1222 of the second undercut groove 122, and the third auxiliary opening 25 is connected to the sixth sub-groove 1322 of the third undercut groove 132.

[0044] The shielding layer 130 is located on a side of the pixel definition layer 120 away from the array substrate 110 . The shielding layer 130 includes a first shielding unit 31 , a second shielding unit 32 and a third shielding unit 33 that are spaced apart.

[0045] The first shielding unit 31 is positioned opposite the first light-emitting unit 41 (see below) of the light-emitting layer 140. The first shielding unit 31 is disconnected at the first auxiliary opening 21 and the first pixel opening 22, respectively, and is connected to the second electrode layer 102 of the first auxiliary electrode 11. The first shielding unit 31 is located on the surface of the pixel definition layer 120 away from the array substrate 110 and on the sidewalls of the first auxiliary opening 21.

[0046] The second shielding unit 32 is positioned opposite the second light-emitting unit 42 (see below) of the light-emitting layer 140. The second shielding unit 32 is disconnected at the second auxiliary opening 23 and the second pixel opening 24, respectively, and is connected to the second electrode layer 102 of the second auxiliary electrode 13. The second shielding unit 32 is located on the surface of the pixel definition layer 120 away from the array substrate 110 and on the sidewalls of the second auxiliary opening 23.

[0047] The third shielding unit 33 is positioned opposite the third light-emitting unit 43 (see below) of the light-emitting layer 140. The third shielding unit 33 is disconnected at the third auxiliary opening 25 and the third pixel opening 26, respectively, and is connected to the second electrode layer 102 of the third auxiliary electrode 15. The third shielding unit 33 is located on the surface of the pixel definition layer 120 away from the array substrate 110 and on the sidewalls of the third auxiliary opening 25.

[0048] The shielding layer 130 is a single layer.

[0049] In some embodiments of the present application, the shielding layer 130 is made of at least one of metals such as molybdenum-titanium (MoTi) alloy, titanium (Ti), and molybdenum (Mo).

[0050] In some embodiments of the present application, a first opening 34 is defined between the first blocking unit 31 and the second blocking unit 32, and a second opening 35 is defined between the second blocking unit 32 and the third blocking unit 33. The pixel definition layer 120 has a third opening 27 and a fourth opening 28. The third opening 27 is located opposite the first opening 34, and the fourth opening 28 is located opposite the second opening 35.

[0051] Among them, the light-emitting layer 140 is located on the side of the blocking layer 130 away from the pixel definition layer 120, and the light-emitting layer 140 includes a first light-emitting unit 41, a second light-emitting unit 42 and a third light-emitting unit 43 arranged at intervals. The first light-emitting unit 41 is respectively connected to the first anode 12 and the first auxiliary electrode 11, the second light-emitting unit 42 is respectively connected to the second anode 14 and the second auxiliary electrode 13, and the third light-emitting unit 43 is respectively connected to the third anode 16 and the third auxiliary electrode 15.

[0052] In some embodiments of the present application, the first light-emitting unit 41 is disconnected at the first undercut structure 111 to form a first light-emitting portion 411 and a second light-emitting portion 412. The first light-emitting portion 411 falls within the first sub-groove 1121 of the first undercut groove 112 and is connected to the end surface of the first electrode layer 101 of the first auxiliary electrode 11 facing the first sub-groove 1121 of the first undercut groove 112, the surface of the third electrode layer 103 of the first auxiliary electrode 11 protruding from the first electrode layer 101 and parallel to the array substrate 110, and the surface of the array substrate 110 exposed from the first undercut groove 112. The second light-emitting portion 412 is located on the surface of the first shielding unit 31 facing away from the pixel definition layer 120 and is connected to the surfaces of the second electrode layer 102 and the third electrode layer 103 of the first auxiliary electrode 11 parallel to the array substrate 110.

[0053] In some embodiments of the present application, the second light-emitting unit 42 is disconnected at the second undercut structure 121 to form a third light-emitting portion 421 and a fourth light-emitting portion 422. The third light-emitting portion 421 falls within the third sub-groove 1221 of the second undercut groove 122 and is connected to the end surface of the first electrode layer 101 of the second auxiliary electrode 13 facing the third sub-groove 1221 of the second undercut groove 122, the surface of the third electrode layer 103 of the second auxiliary electrode 13 protruding from the first electrode layer 101 and parallel to the array substrate 110, and the surface of the array substrate 110 exposed from the second undercut groove 122. The third light-emitting portion 421 is located on the surface of the second shielding unit 32 facing away from the pixel definition layer 120 and is connected to the surfaces of the second electrode layer 102 and the third electrode layer 103 of the second auxiliary electrode 13 parallel to the array substrate 110.

[0054] In some embodiments of the present application, the third light-emitting unit 43 is disconnected at the third undercut structure 131 to form a fifth light-emitting portion 431 and a sixth light-emitting portion 432. The fifth light-emitting portion 431 falls within the fifth sub-groove 1321 of the third undercut groove 132 and is connected to the end surface of the first electrode layer 101 of the third auxiliary electrode 15 facing the fifth sub-groove 1321 of the third undercut groove 132, the surface of the third electrode layer 103 of the second auxiliary electrode 13 protruding from the first electrode layer 101 and parallel to the array substrate 110, and the surface of the array substrate 110 exposed from the third undercut groove 132. The sixth light-emitting portion 432 is located on the surface of the third shielding unit 33 facing away from the pixel definition layer 120 and is connected to the surfaces of the second electrode layer 102 and the third electrode layer 103 of the third auxiliary electrode 15 parallel to the array substrate 110.

[0055] A first gap 401 is defined between the first light-emitting unit 41 and the second light-emitting unit 42, and a second gap 402 is defined between the second light-emitting unit 42 and the third light-emitting unit 43. The cathode (see below) is disconnected at the first gap 401 and the second gap 402. The third opening 27 of the pixel definition layer 120, the first opening 34 of the shielding layer 130, and the first gap 401 of the light-emitting layer 140 are positioned opposite each other. The fourth opening 28 of the pixel definition layer 120, the second opening 35 of the shielding layer 130, and the second gap 402 of the light-emitting layer 140 are positioned opposite each other.

[0056] The second metal layer 150 is located on the side of the light-emitting layer 140 facing away from the shielding layer 130. The second metal layer 150 includes a cathode 50, which includes a first cathode portion 51, a second cathode portion 52, and a third cathode portion 53. The first cathode portion 51 covers the first light-emitting unit 41, the second cathode portion 52 covers the second light-emitting unit 42, and the third cathode portion 53 covers the third light-emitting unit 43. The first cathode portion 51 is continuous at the first undercut structure 111, the second cathode portion 52 is continuous at the second undercut structure 121, and the third cathode portion 53 is continuous at the third undercut structure 131.

[0057] In some embodiments of the present application, the first cathode portion 51 is connected to the end surface of the third electrode layer 103 of the first undercut structure 111 facing the first undercut groove 112, the second cathode portion 52 is connected to the end surface of the third electrode layer 103 of the second undercut structure 121 facing the second undercut groove 122, and the third cathode portion 53 is connected to the end surface of the third electrode layer 103 of the third undercut structure 131 facing the third undercut groove 132.

[0058] The first cathode portion 51 is connected to the first light emitting unit 41 but not to the first blocking unit 31 , the second cathode portion 52 is connected to the second light emitting unit 42 but not to the second blocking unit 32 , and the third cathode portion 53 is connected to the third light emitting unit 43 but not to the third blocking unit 33 .

[0059] The display panel 100 further includes an encapsulation layer 160 . The encapsulation layer 160 covers the second metal layer 150 and fills the first gap 401 , the first opening 34 , the third opening 27 , the second gap 402 , the second opening 35 and the fourth opening 28 .

[0060] See also Figures 1 to 7 , the present application also provides a method for preparing a display panel, comprising:

[0061] Step S1, see Figure 2 and Figure 3 , forming an array substrate 110.

[0062] Among them, the array substrate 110 includes a first metal layer 10, the first metal layer 10 includes a first auxiliary electrode 11, a first anode 12 located on one side of the first auxiliary electrode 11, a second auxiliary electrode 13, a second anode 14 located on one side of the second auxiliary electrode 13, a third auxiliary electrode 15, and a third anode 16 located on one side of the third auxiliary electrode 15.

[0063] Among them, the first metal layer 10 includes a first electrode layer 101, a second electrode layer 102 and a third electrode layer 103 located between the first electrode layer 101 and the second electrode 102, stacked in the stacking direction of the array substrate 110 and the pixel definition layer 120, and the first electrode layer 101 is located on the array substrate 110.

[0064] The material of the first electrode layer 101 is the same as or different from the material of the second electrode layer 102 . The material of the first electrode layer 101 and the material of the second electrode layer 102 are different from the material of the third electrode layer 103 .

[0065] Step S2, see Figure 2 and Figure 3 , a pixel definition layer 120 is formed on one side of the array substrate 110 .

[0066] Among them, the pixel definition layer 120 covers the first metal layer 10 and includes a first auxiliary opening 21, a first pixel opening 22, a second auxiliary opening 23, a second pixel opening 24, a third auxiliary opening 25 and a third pixel opening 26. A portion of the first auxiliary electrode 11, a portion of the second auxiliary electrode 13 and the third auxiliary electrode 15 are exposed from the first auxiliary opening 21, the second auxiliary opening 23 and the third auxiliary opening 25 respectively, and the remaining pixel definition layer located in the first pixel opening 22, the second pixel opening 24 and the third pixel opening 26 respectively covers the first anode 12, the second anode 14 and the third anode 16.

[0067] The thickness of the remaining pixel definition layer located within the first pixel opening 22 , the second pixel opening 24 and the third pixel opening 26 gradually increases in the stacking direction of the pixel definition layer 120 and the array substrate 110 .

[0068] Step S3, see Figure 2 and Figure 3 A patterned shielding layer 130 is formed on a side of the pixel definition layer 120 away from the array substrate 110 .

[0069] Part of the first auxiliary electrode 11 , part of the second auxiliary electrode 13 , and part of the third auxiliary electrode 15 are respectively exposed from the shielding layer.

[0070] Among them, the blocking layer 130 can play an isolation role when the remaining pixel definition layer 120 in the first pixel opening 22, the second pixel opening 24 and the third pixel opening 26 is subsequently removed through a dry etching process, so as to protect the pixel definition layer 120 and the first metal layer 10 at other positions, so as to prevent the pixel definition layer 120 and the first metal layer 10 at other positions from being synchronously etched or damaged.

[0071] The shielding layer 130 includes a first shielding unit 31, a second shielding unit 32, and a third shielding unit 33, which are spaced apart. The first shielding unit 31 corresponds to the first auxiliary electrode 11 and the first anode 12, the second shielding unit 32 corresponds to the second auxiliary electrode 13 and the second anode 14, and the third shielding unit 33 corresponds to the third auxiliary electrode 15 and the third anode 16. The first shielding unit 31 is located on the surface of the pixel definition layer 120 away from the array substrate 110 and on the sidewalls of the first auxiliary opening 21. The second shielding unit 32 is located on the surface of the pixel definition layer 120 away from the array substrate 110 and on the sidewalls of the second auxiliary opening 23. The third shielding unit 33 is located on the surface of the pixel definition layer 120 away from the array substrate 110 and on the sidewalls of the third auxiliary opening 25.

[0072] A first opening 34 is defined between the first shielding unit 31 and the second shielding unit 32, and a second opening 35 is defined between the second shielding unit 32 and the third shielding unit 33. The third opening 27 is opposite to the first opening 34, and the fourth opening 28 is opposite to the second opening 35.

[0073] Step S4, see Figure 2 and Figure 3 The first auxiliary electrode 11 , the second auxiliary electrode 13 and the third auxiliary electrode 15 are etched respectively to obtain a first undercut structure 111 , a second undercut structure 121 and a third undercut structure 131 , thereby forming a first intermediate structure 1001 .

[0074] In some embodiments of the present application, the auxiliary electrode can be first etched with an acid capable of etching silver, and then the auxiliary electrode can be etched with an acid capable of etching indium tin oxide (ITO), thereby forming an undercut structure in which the third electrode layer 103 extends beyond the first electrode layer 101 and the second electrode layer, without adding process steps.

[0075] Among them, the first auxiliary electrode 11 includes a first bottom cut groove 112, the first bottom cut groove 112 includes a first sub-groove 1121 and a second sub-groove 1122 that are connected, the first sub-groove 1121 is located between the third electrode layer 103, the first electrode layer 101 and the array substrate 110 of the first auxiliary electrode 11, and the second sub-groove 1122 is located between the third electrode layer 103 and the second electrode layer 102 of the first auxiliary electrode 11.

[0076] Among them, the second auxiliary electrode 13 includes a second bottom cut groove 122, the second bottom cut groove 122 includes a third sub-groove 1221 and a fourth sub-groove 1222 that are connected, the third sub-groove 1221 is located between the third electrode layer 103, the first electrode layer 101 and the array substrate 110 of the second auxiliary electrode 13, and the fourth sub-groove 1222 is located between the third electrode layer 103 and the second electrode layer 102 of the second auxiliary electrode 13.

[0077] Among them, the third auxiliary electrode 15 includes a third bottom cut groove 132, the third bottom cut groove 132 includes a connected fifth sub-groove 1321 and a sixth sub-groove 1322, the fifth sub-groove 1321 is located between the third electrode layer 103, the first electrode layer 101 and the array substrate 110 of the second auxiliary electrode 13 of the third auxiliary electrode 15, and the sixth sub-groove 1322 is located between the third electrode layer 103 and the second electrode layer 102 of the third auxiliary electrode 15.

[0078] Step S5, see Figure 2 and Figure 4 The remaining pixel definition layer in the first pixel opening 22 is completely removed by a dry etching process to expose the first anode 12 , and a portion of the pixel definition layer 120 in the second pixel opening 24 and the third pixel opening 26 is removed respectively.

[0079] The remaining pixel definition layer 120 located in the second pixel opening 24 covers the second anode 14 , and the remaining pixel definition layer 120 located in the third pixel opening 26 covers the third anode 16 .

[0080] After step S5, the thickness of the remaining pixel definition layer 120 located in the second pixel opening 24 in the stacking direction of the pixel definition layer 120 and the array substrate 110 is less than the thickness of the remaining pixel definition layer 120 located in the third pixel opening 26 in the stacking direction of the pixel definition layer 120 and the array substrate 110.

[0081] Step S6, see Figure 2 and Figure 5 , a first initial light-emitting layer 170 is formed by full-surface vapor deposition and a first initial cathode layer 171 is formed on the first initial light-emitting layer 170, and the remaining parts of the first initial light-emitting layer 170 and the first initial cathode layer 171 are removed by a photolithography process to obtain a first light-emitting unit 41 and a first cathode portion 51, respectively.

[0082] The first light emitting unit 41 is connected to the first anode 12 and the first auxiliary electrode 11 respectively and is disconnected at the first undercut structure 111 , and the first cathode portion 51 is connected to the first auxiliary electrode 11 .

[0083] The first cathode portion 51 is not connected to the first shielding unit 31 .

[0084] Step S7, see Figure 2 and Figure 5 The remaining pixel definition layer 120 in the second pixel opening 24 is completely removed by a dry etching process to expose the second anode 14 , and a portion of the pixel definition layer 120 in the third pixel opening 26 is removed.

[0085] The thickness of a portion of the pixel definition layer 120 located within the third pixel opening 26 in the stacking direction of the pixel definition layer 120 and the array substrate 110 is greater than 0.

[0086] Step S8, see Figure 2 and Figure 6 , a second initial light-emitting layer 180 is formed by vapor deposition on the entire surface and a second initial cathode layer 181 is formed on the second initial light-emitting layer 180, and the remaining parts of the second initial light-emitting layer 180 and the second initial cathode layer 181 are removed by a photolithography process to obtain a second light-emitting unit 42 and a second cathode portion 52 respectively.

[0087] The second light emitting unit 42 is connected to the second anode 14 and the second auxiliary electrode 13 respectively and is disconnected at the second undercut structure 121 . The second cathode portion 52 is connected to the second auxiliary electrode 13 .

[0088] The second cathode portion 52 is not connected to the second shielding unit 32 .

[0089] There is a first gap 401 between the first light emitting unit 41 and the second light emitting unit 42 , and the cathode 50 (see below) is disconnected at the first gap 401 .

[0090] Step S9, please refer to Figure 2 and Figure 6 The remaining pixel definition layer 120 located in the third pixel opening 26 is completely removed by a dry etching process to expose the third anode 16 .

[0091] Step S10, see Figure 2 and Figure 7 , a third initial light-emitting layer 190 is formed by full-surface vapor deposition and a third initial cathode layer 191 is formed on the third initial light-emitting layer 190, and the remaining parts of the third initial light-emitting layer 190 and the third initial cathode layer 191 are removed by a photolithography process to obtain a third light-emitting unit 43 and a third cathode portion 53, respectively.

[0092] The third light emitting unit 43 is connected to the third anode 16 and the third auxiliary electrode 15 respectively and is disconnected at the third undercut structure 131 . The third cathode portion 53 is connected to the third auxiliary electrode 15 to form a second intermediate structure 1002 .

[0093] The first cathode portion 51, the second cathode portion 52 and the third cathode portion 53 are the cathode 50 and the second metal layer 150 or parts of the cathode 50 and the second metal layer 150. The first light emitting unit 41, the second light emitting unit 42 and the third light emitting unit 43 are the light emitting layer or parts of the light emitting layer.

[0094] There is a second gap 402 between the second light emitting unit 42 and the third light emitting unit 43 , and the cathode is disconnected at the second gap 402 .

[0095] Among them, the first cathode portion 51 and the first light-emitting unit 41 correspond to the first sub-pixel, the second cathode portion 52 and the second light-emitting unit 42 correspond to the second sub-pixel, and the third cathode portion 53 and the third light-emitting unit 43 correspond to the third sub-pixel. The first sub-pixel, the second sub-pixel, and the third sub-pixel are sub-pixels of different colors, that is, the first light-emitting unit 41, the second light-emitting unit 42, and the third light-emitting unit 43 emit light of different colors. In this embodiment, the first sub-pixel, the second sub-pixel, and the third sub-pixel are respectively one of a red sub-pixel, a green sub-pixel, and a blue sub-pixel. In other embodiments, sub-pixels of other colors may be included, and accordingly, the display panel also includes more light-emitting units and cathode portions.

[0096] The third cathode portion 53 is not connected to the third shielding unit 33 .

[0097] The pixel definition layer 120 has a third opening 27 and a fourth opening 28. The third opening 27 is located opposite the first opening 34 and the first gap 401, and the fourth opening 28 is located opposite the second opening 35 and the second gap 402. The third opening 27 and the fourth opening 28 are formed simultaneously during the dry etching process when the remaining pixel definition layer 120 located within the first pixel opening 22, the second pixel opening 24, and the third pixel opening 26 is dry-etched.

[0098] After step S10, please refer to Figure 1, further comprising the step of forming an encapsulation layer 160 , the encapsulation layer 160 covers the second metal layer 150 and fills the first gap 401 , the first opening 34 , the third opening 27 , the second gap 402 , the second opening 35 and the fourth opening 28 .

[0099] The encapsulation layer 160 is used to protect the cathode 50 and the light-emitting layer 140 and isolate moisture. The encapsulation layer 160 fills the first gap 401, the first opening 34, the third opening 27, the second gap 402, the second opening 35, and the fourth opening 28, disconnecting each light-emitting unit to prevent the intrusion of water and oxygen. It also prevents the area between adjacent sub-pixels from emitting light, which could cause mixed light and display abnormalities.

[0100] The present application also provides a display device (not shown), which includes the above display panel 100. The display device can be an electronic product such as a smart bracelet, a smart watch, a smart phone, a tablet computer, a laptop computer, a desktop computer, a television, etc.

[0101] The present application provides a display panel, a method for preparing a display panel, and a display device, wherein the display panel includes: an array substrate, including a first metal layer, the first metal layer including a first auxiliary electrode and a first anode located on one side of the first auxiliary electrode; a pixel definition layer, located on one side of the array substrate and covering the first metal layer; the pixel definition layer including a first auxiliary opening and a first pixel opening, a portion of the first auxiliary electrode being exposed from the first auxiliary opening, and a portion of the first anode being exposed from the first pixel opening; a light-emitting layer, including a first light-emitting unit and located on a side of the pixel definition layer away from the array substrate, the first light-emitting unit being connected to the first anode and the first auxiliary electrode, respectively; and a second metal layer including a cathode, the cathode being located on a side of the light-emitting layer away from the pixel definition layer; wherein the display panel also includes a shielding layer, the shielding layer being located between the pixel definition layer and the light-emitting layer, the shielding layer being connected to the first light-emitting unit and not connected to the cathode; the first auxiliary electrode having a first undercut structure, the first undercut structure corresponding to the position of the first auxiliary opening, and the first light-emitting unit being disconnected at the first undercut structure. The present application sets a patterned shielding layer between the pixel definition layer and the light-emitting layer. When forming the light-emitting unit corresponding to the sub-pixel (for example, the first light-emitting unit), the pixel definition layer can be protected and the first initial light-emitting layer can be first formed by whole-surface vapor deposition, and then the excess first initial light-emitting layer can be removed by a photolithography process to obtain the light-emitting unit corresponding to the sub-pixel (for example, the first light-emitting unit). In the process of obtaining the light-emitting unit corresponding to the sub-pixel (for example, the first light-emitting unit), the present application does not need to use multiple fine metal mask processes to evaporate and form red sub-pixels, blue sub-pixels and green sub-pixels respectively, and is not limited by the size and precision limitations of the mask plate. Therefore, the problem of large-size vapor deposition of OLED can be solved, and a display panel with high pixel density can be produced.

[0102] In addition, since the formation of the light-emitting units of the present application is carried out separately, when forming the first light-emitting unit, the anodes corresponding to other pixels are protected by the remaining pixel definition layer in the pixel opening. When the corresponding light-emitting unit needs to be formed, the remaining pixel definition layer in the pixel opening is removed by a dry etching process. The operation is simple and convenient, and the cost is low.

[0103] In addition, a patterned shielding layer is used and the shielding layer is disconnected at the bottom cut structure. The shielding layer does not need to form an bottom cut structure at the bottom cut structure. Different light-emitting units and cathode parts as well as cathode overlaps can be formed respectively in conjunction with the remaining pixel definition layer in the pixel opening. The operation is simple and convenient, and the cost is low.

[0104] In addition, since the auxiliary electrode (for example, the first auxiliary electrode) has an undercut structure and a shielding layer, and the shielding layer is disconnected at the undercut structure, the light-emitting layer is disconnected at the undercut structure, and the cathode is continuous at the undercut structure and connected to the side (end face) of the auxiliary electrode (edge ​​contact), after power is turned on, a certain amount of Ag migration can be achieved (Ag ions on the auxiliary electrode can migrate to the cathode), which can reduce the impedance of the cathode and make the cathode and the auxiliary electrode better connected.

[0105] In summary, although the present application has been disclosed as above with preferred embodiments, the above preferred embodiments are not intended to limit the present application. Ordinary technicians in this field can make various changes and modifications without departing from the spirit and scope of the present application. Therefore, the scope of protection of the present application shall be based on the scope defined by the claims.

Claims

1. A display panel, characterized in that: include: An array substrate includes a first metal layer, wherein the first metal layer includes a first auxiliary electrode and a first anode located on one side of the first auxiliary electrode; a pixel definition layer, located on one side of the array substrate and covering the first metal layer; The pixel definition layer includes a first auxiliary opening and a first pixel opening, a portion of the first auxiliary electrode is exposed from the first auxiliary opening, and a portion of the first anode is exposed from the first pixel opening; a light-emitting layer, comprising a first light-emitting unit and located on a side of the pixel definition layer away from the array substrate, wherein the first light-emitting unit is respectively connected to the first anode and the first auxiliary electrode; and a second metal layer comprising a cathode, wherein the cathode is located on a side of the light-emitting layer away from the pixel definition layer; In which, the display panel also includes a blocking layer, which is located between the pixel definition layer and the light-emitting layer, and the blocking layer is connected to the first light-emitting unit and is not connected to the cathode; the first auxiliary electrode has a first undercut structure, and the first undercut structure corresponds to the position of the first auxiliary opening, and the first light-emitting unit is disconnected at the first undercut structure.

2. The display panel according to claim 1, wherein The first metal layer further includes a second auxiliary electrode and a second anode located on one side of the second auxiliary electrode; The pixel definition layer further includes a second auxiliary opening and a second pixel opening, a portion of the second auxiliary electrode is exposed from the second auxiliary opening, and a portion of the second anode is exposed from the second pixel opening; The light-emitting layer further includes a second light-emitting unit, which is spaced apart from the first light-emitting unit and connected to the second anode and the second auxiliary electrode respectively; The second auxiliary electrode has a second undercut structure, the second undercut structure corresponds to a position of the second auxiliary opening, and the second light emitting unit is disconnected at the second undercut structure.

3. The display panel according to claim 2, wherein: The first metal layer further includes a third auxiliary electrode and a third anode located on one side of the third auxiliary electrode; The pixel definition layer further includes a third auxiliary opening and a third pixel opening, a portion of the third auxiliary electrode is exposed from the third auxiliary opening, and a portion of the third anode is exposed from the third pixel opening; The light-emitting layer further includes a third light-emitting unit, the third light-emitting unit is spaced apart from the second light-emitting unit and is respectively connected to the third anode and the third auxiliary electrode; The third auxiliary electrode has a third undercut structure, the third undercut structure corresponds to the position of the third auxiliary opening, and the third light emitting unit is disconnected at the third undercut structure.

4. The display panel according to claim 3, wherein: The blocking layer includes a first blocking unit, which is located between the pixel definition layer and the first light-emitting unit. The first blocking unit is disconnected at the first auxiliary opening and the first pixel opening respectively and connected to the first auxiliary electrode. The first blocking unit is connected to the first light-emitting unit but not to the cathode.

5. The display panel according to claim 4, wherein: The shielding layer includes a second shielding unit, the second shielding unit is located between the pixel definition layer and the second light-emitting unit and is spaced apart from the first shielding unit, the second shielding unit is disconnected at the second auxiliary opening and the second pixel opening respectively and connected to the second auxiliary electrode, the second shielding unit is connected to the second light-emitting unit but is not connected to the cathode; and / or The blocking layer includes a third blocking unit, which is located between the pixel definition layer and the third light-emitting unit and is spaced apart from the second blocking unit. The third blocking unit is disconnected at the third auxiliary opening and the third pixel opening respectively and is connected to the third auxiliary electrode. The third blocking unit is connected to the third light-emitting unit but not to the cathode.

6. The display panel according to claim 5, wherein: There is a first gap between the first light emitting unit and the second light emitting unit, there is a second gap between the second light emitting unit and the third light emitting unit, and the cathode is disconnected at the first gap and the second gap; A first opening is provided between the first shielding unit and the second shielding unit, and a second opening is provided between the second shielding unit and the third shielding unit; The pixel definition layer has a third opening and a fourth opening. The third opening, the first opening, and the first gap are opposite to each other. The fourth opening, the second opening, and the second gap are opposite to each other.

7. The display panel according to claim 6, wherein: The display panel further includes an encapsulation layer, which covers the second metal layer and fills the first gap, the first opening, the third opening, the second gap, the second opening, and the fourth opening.

8. The display panel according to claim 1, wherein: The first auxiliary electrode includes a first electrode layer, a second electrode layer, and a third electrode layer located between the first electrode layer and the second electrode layer, the first electrode layer, the second electrode layer, and the third electrode layer are stacked in the stacking direction of the array substrate and the pixel definition layer, and the first electrode layer is located on the array substrate; Wherein, at the first auxiliary opening, one end of the third electrode layer protrudes from the first electrode layer and the second electrode layer.

9. The display panel according to claim 8, wherein: The first auxiliary electrode has a first undercut groove, the first undercut groove includes a first sub-groove and a second sub-groove that are connected to each other, the first sub-groove is located between the third electrode layer, the first electrode layer and the array substrate, and the second sub-groove is located between the third electrode layer and the second electrode layer; The first light-emitting unit includes a first light-emitting portion and a second light-emitting portion, the first light-emitting portion is located in the first sub-groove and is respectively connected to the array substrate, the first electrode layer and the third electrode layer, a portion of the second light-emitting portion is located on the side of the blocking layer away from the pixel definition layer, and another portion of the second light-emitting portion is located in the first sub-groove and is respectively connected to the blocking layer, the second electrode layer and the third electrode layer.

10. The display panel according to claim 6, wherein: The cathode includes a first cathode portion, a second cathode portion, and a third cathode portion, wherein the first cathode portion, the second cathode portion, and the third cathode portion cover the first light-emitting unit, the second light-emitting unit, and the third light-emitting unit, respectively; The first cathode portion is continuous at the first undercut structure, the second cathode portion is continuous at the second undercut structure, and the third cathode portion is continuous at the third undercut structure.

11. The display panel according to claim 3, wherein: The array substrate further includes: a light-shielding layer comprising a plurality of light-shielding portions; and a transistor, located between the light shielding layer and the first metal layer; Wherein, the first anode, the second anode and the third anode are respectively connected to one of the transistors; Each transistor in which the first auxiliary electrode, the second auxiliary electrode, and the third auxiliary electrode are connected to the first anode, the second anode, and the third anode, respectively, is connected to one of the light shielding portions.

12. A display device, characterized in that: The display panel comprises the display panel according to any one of claims 1 to 11.

13. A method for preparing a display panel, characterized in that: include: forming an array substrate, the array substrate comprising a first metal layer, the first metal layer comprising a first auxiliary electrode, a first anode located on one side of the first auxiliary electrode, a second auxiliary electrode, and a second anode located on one side of the second auxiliary electrode; A pixel definition layer is formed on one side of the array substrate, the pixel definition layer covering the first metal layer and including a first auxiliary opening, a first pixel opening, a second auxiliary opening, and a second pixel opening, a portion of the first auxiliary electrode and a portion of the second auxiliary electrode being exposed from the first auxiliary opening and the second auxiliary opening, respectively, and the remaining pixel definition layer located within the first pixel opening and the second pixel opening covering the first anode and the second anode, respectively; forming a patterned shielding layer on a side of the pixel definition layer away from the array substrate, wherein a portion of the first auxiliary electrode and a portion of the second auxiliary electrode are respectively exposed from the shielding layer; etching the first auxiliary electrode and the second auxiliary electrode respectively to obtain a first undercut structure and a second undercut structure; completely removing the remaining pixel definition layer in the first pixel opening to expose the first anode through a dry etching process, and removing a portion of the pixel definition layer in the second pixel opening, with the remaining pixel definition layer in the second pixel opening covering the second anode; forming a first initial light-emitting layer by evaporation over the entire surface and forming a first initial cathode layer on the first initial light-emitting layer, and removing the remaining portions of the first initial light-emitting layer and the first initial cathode layer by a dry etching process to obtain a first light-emitting unit and a first cathode portion, respectively, wherein the first light-emitting unit is connected to the first anode and the first auxiliary electrode, respectively, and is disconnected at the first undercut structure, and the first cathode portion is connected to the first auxiliary electrode; completely removing the remaining pixel definition layer located in the second pixel opening by a dry etching process to expose the second anode; and A second initial light-emitting layer is formed by full-surface vapor deposition and a second initial cathode layer is formed on the second initial light-emitting layer, and the remaining parts of the second initial light-emitting layer and the second initial cathode layer are removed by a dry etching process to obtain a second light-emitting unit and a second cathode portion, respectively. The second light-emitting unit is respectively connected to the second anode and the second auxiliary electrode and is disconnected at the second undercut structure, and the second cathode portion is connected to the second auxiliary electrode.

Images