Display device and method for manufacturing display device

Abstract

The invention relates to a display device and a manufacturing method of the display device. The display device can comprise a display area and a non-display area, pixels are arranged in the display area, and the non-display area is an area outside the display area; the pixel circuit layer comprises a pixel circuit; and a partition wall disposed on the pixel circuit layer of the display area and the non-display area, and including a pixel defining layer and a spacer disposed on the pixel defining layer, in which in the non-display area, one end portion of the pixel defining layer and one end portion of the spacer may not overlap when viewed from a plane.

Description

Technical Field

[0001] The present disclosure relates to a display device and a method for manufacturing the display device. Background Art

[0002] With the development of information technology, the importance of display devices as a connection medium between users and information has attracted attention.

[0003] The display device may include a display area in which pixels are arranged and capable of displaying an image and a non-display area which is an area outside the display area. In addition, the display device may include an electrode (e.g., a cathode electrode) for supplying power to the pixel, and the electrode of the display device may be deposited in a portion of the display area and the non-display area of ​​the display device.

[0004] The edge of the region where the electrode is deposited in the display device may be defined in the non-display region. For example, the region where the electrode is deposited may be arranged across the display region and the non-display region.

[0005] In addition, the electrodes of the display device may be patterned on other layers to contact other layers directly adjacent to the display device. In the case where the electrodes of the display device are not sufficiently bonded to other layers directly adjacent to the display device, there is a risk of electrode lifting in the non-display area. This may reduce the performance of the display device, and therefore, research is ongoing to reasonably arrange the electrodes on other layers in the non-display area of ​​the display device to maintain a sufficient bonding state. Summary of the invention

[0006] An object of the present disclosure is to provide a display device and a method for manufacturing the display device, which can reduce the risk of warping of electrodes of the display device in a non-display area.

[0007] According to an embodiment of the present disclosure, a display device may include: a display area and a non-display area, wherein pixels are arranged in the display area, and the non-display area is an area outside the display area; a pixel circuit layer, including a pixel circuit; and a partition wall, which is arranged on the pixel circuit layer of the display area and the non-display area and includes a pixel defining layer and a partition arranged on the pixel defining layer, wherein, in the non-display area, one end of the pixel defining layer and one end of the partition may not overlap when observed from a plane.

[0008] According to an embodiment, the pixel defining layer may include: a first pixel defining layer, arranged on the pixel circuit layer and having a first defining layer width; and a second pixel defining layer, arranged on the first pixel defining layer and having a second defining layer width, wherein the spacer may include: a first spacer, arranged on the pixel defining layer and having a first spacer width; and a second spacer, arranged on the first spacer and having a second spacer width.

[0009] According to an embodiment, the first defining layer width may be greater than the second defining layer width, and the pixel defining layer may include an uneven side surface.

[0010] According to an embodiment, the first spacer width may be smaller than the second defining layer width, and the second spacer width may be smaller than the first spacer width.

[0011] According to an embodiment, the spacer may include a curved surface, and the second spacer is more recessed toward the inside than the first spacer in a direction in which a plane on which the pixel circuit layer is arranged extends.

[0012] According to an embodiment, the pixel defining layer may further include: a third pixel defining layer arranged on the second pixel defining layer and having a third defining layer width, wherein the spacer may further include: a third spacer arranged on the second spacer and having a third spacer width.

[0013] According to an embodiment, an end portion of the first pixel defining layer, an end portion of the second pixel defining layer, and an end portion of the third pixel defining layer may not overlap when viewed from a plane.

[0014] According to an embodiment, an end portion of the first pixel defining layer, an end portion of the second pixel defining layer, and an end portion of the third pixel defining layer may overlap when viewed from a plane.

[0015] According to an embodiment, an end portion of the first spacer and an end portion of the third pixel defining layer may not overlap each other when viewed from a plane, and a width of the second spacer may be smaller than a width of the first spacer and a width of the third spacer.

[0016] According to an embodiment, an end portion of the first spacer and an end portion of the third pixel defining layer may not overlap each other when viewed from a plane, and the first spacer width, the second spacer width, and the third spacer width may be the same as each other.

[0017] According to an embodiment, an end portion of the first spacer and an end portion of the third pixel defining layer may not overlap each other when viewed from a plane, and a width of the second spacer may be smaller than a width of the first spacer and a width of the third spacer.

[0018] According to an embodiment, the display device may further include: a first electrode and a second electrode, arranged on the pixel circuit layer, wherein the second electrode may include a 2-1 electrode arranged in the display area and a 2-2 electrode arranged in the non-display area, and the 2-2 electrode may be arranged on the partition wall.

[0019] According to an embodiment, the 2-2nd electrode may cover the pixel defining layer and side surfaces of the partition.

[0020] According to a method for manufacturing a display device of an embodiment of the present disclosure, the display device includes a display area where pixels are arranged and a non-display area which is an area outside the display area, and the manufacturing method includes the following steps: depositing a basic pixel defining layer on a pixel circuit layer in the display area and the non-display area, and depositing a basic spacer on the basic pixel defining layer; and etching the basic spacer, wherein the step of etching the basic spacer may include the following step: etching the basic spacer in such a way that the basic spacer arranged in the non-display area exposes at least a portion of the basic pixel defining layer.

[0021] According to an embodiment, the step of depositing the basic pixel defining layer may include the following steps: depositing a first basic pixel defining layer on the pixel circuit layer, and depositing a second basic pixel defining layer on the first basic pixel defining layer, and the step of depositing the basic spacer may include the following steps: depositing a first basic spacer on the basic pixel defining layer, and depositing a second basic spacer on the first basic spacer.

[0022] According to an embodiment, the step of etching the base spacer may include the step of etching in such a manner that the first base spacer and the second base spacer have the same width as each other.

[0023] According to an embodiment, the step of etching the base spacer may further include the step of etching the second base spacer deeper than the first base spacer, wherein, in the step of etching the base spacer, the first base spacer may be formed to a first spacer width, and the second base spacer may be formed to a second spacer width, and the second spacer width may have a width smaller than the first spacer width.

[0024] According to an embodiment, the manufacturing method of the display device may further include the following steps: etching the basic pixel defining layer, wherein, in the step of etching the basic pixel defining layer, a first pixel defining layer is formed by etching the first basic pixel defining layer in a manner having a first defining layer width, and a second pixel defining layer is formed by etching the second basic pixel defining layer in a manner having a second defining layer width smaller than the first defining layer width.

[0025] According to a method for manufacturing a display device of an embodiment of the present disclosure, as a method for manufacturing a display device including a display area where pixels are arranged and a non-display area as an area other than the display area, the method may include the following steps: depositing a basic pixel defining layer on a pixel circuit layer of the display area and the non-display area, and depositing a basic spacer on the basic pixel defining layer; etching the basic spacer; and etching the basic pixel defining layer, wherein the step of depositing the basic pixel defining layer may include the following steps: depositing a first basic pixel defining layer on the pixel circuit layer, and depositing a second basic pixel defining layer on the first basic pixel defining layer, wherein the step of depositing the basic spacer may include the following steps: depositing a first basic spacer on the basic pixel defining layer, and depositing a second basic spacer on the first basic spacer, wherein in the step of etching the basic pixel defining layer, the first basic pixel defining layer may be etched to form a first pixel defining layer having a first defining layer width, the second basic pixel defining layer may be etched to form a second pixel defining layer having a second defining layer width smaller than the first defining layer width, and an end portion of the first pixel defining layer and an end portion of the second pixel defining layer may not overlap each other when viewed from a plane.

[0026] According to an embodiment, in the step of etching the basic spacer, the first basic spacer may be etched to form a first spacer having a first spacer width, the second basic spacer may be etched to form a second spacer having a second spacer width, the second spacer width is smaller than the first spacer width, and each of the basic spacer and the basic pixel defining layer may include an inorganic material, and the inorganic material may include one or more of the group consisting of silicon nitride and silicon oxide.

[0027] According to an embodiment of the present disclosure, a display device and a method for manufacturing the display device capable of reducing the risk of warping of electrodes of the display device in a non-display area can be provided. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1 is a schematic plan view showing a display device according to the embodiment.

[0029] Figure 2 is a schematic cross-sectional view showing a display device according to an embodiment.

[0030] Figure 3 is a schematic cross-sectional view showing a light emitting element according to an embodiment.

[0031] Figure 4 is a schematic block diagram showing an electrical connection structure for a light emitting element according to an embodiment.

[0032] Figure 5 It is shown Figure 1 Schematic enlargement of the EA1 region.

[0033] Figure 6 is a diagram schematically showing a partition wall structure according to a first embodiment.

[0034] Figure 7 is a diagram schematically showing a partition wall structure according to a second embodiment.

[0035] Figure 8 is a diagram schematically showing a partition wall structure according to a third embodiment.

[0036] Fig. 9 is a flowchart illustrating a method of manufacturing a display device according to an embodiment.

[0037] Figures 10 to 13 Schematic cross-sectional views showing the steps of a method for manufacturing a display device according to an embodiment.

[0038] Fig.14 is a flowchart illustrating a method of manufacturing a display device according to an embodiment.

[0039] Fig.15 Schematic cross-sectional views showing steps of a method for manufacturing a display device according to an embodiment. Specific embodiments

[0040] The present disclosure may be subjected to various changes and may have various forms, and specific embodiments are illustrated in the drawings and described in detail herein. However, this does not limit the present disclosure to a specific disclosed form, and should be understood to include all changes, equivalents and substitutes included in the concept and technical scope of the present disclosure.

[0041] The terms "first", "second" and the like can be used to describe various constituent elements, but the constituent elements should not be limited to the terms. The terms are only used to distinguish one constituent element from another constituent element. For example, without departing from the scope of the present disclosure, the first constituent element can be named as the second constituent element, and similarly, the second constituent element can also be named as the first constituent element. Unless the context clearly indicates otherwise, the expression in the singular also includes the expression in the plural.

[0042] In the present disclosure, the terms "including" or "having" should be understood as being used to specify the existence of features, numbers, steps, operations, constituent elements, parts or combinations thereof recorded in the specification, rather than excluding in advance the existence or additional possibility of one or more other features or numbers, steps, operations, constituent elements, parts or combinations thereof. Furthermore, when a layer, film, region, plate or other part is located "on" another part, this includes not only the case where it is located "immediately above" another part, but also the case where there is another part in the middle. Furthermore, in the present specification, when it is mentioned that a layer, film, region, plate or other part is formed on another part, the direction formed is not only limited to the upper direction, but also includes formation along the side or lower direction. On the contrary, when a layer, film, region, plate or other part is located "below" another part, this includes not only the case where it is located "immediately below" another part, but also the case where there is another part in the middle.

[0043] The present disclosure relates to a display device and a method for manufacturing the display device. Hereinafter, a display device and a method for manufacturing the display device according to an embodiment will be described with reference to the accompanying drawings.

[0044] Figure 1 is a schematic plan view showing a display device according to an embodiment.

[0045] Reference Figure 1 , the display device DD is configured to emit light. The display device DD includes a light emitting element LD. According to an embodiment, the display device DD may be provided in a variety of forms. For example, the display device DD may be formed as a plane in a rectangular form having a short side in a first direction DR1 and a long side in a second direction DR2 intersecting the first direction DR1. In the present disclosure, the first direction DR1 may be a row direction of pixels PXL. The second direction DR2 may be a column direction of pixels PXL. The third direction DR3 may be a display direction of the display device DD. According to an embodiment, the display device DD may be applied to a smart phone, a notebook computer, a tablet personal computer (PC: personal computer), a wearable device (e.g., a head mounted device, a smart watch, smart glasses, etc.), a television or a vehicle infotainment system, etc., and may also be applied to various implementation forms.

[0046] The display device DD may include a base layer BSL and pixels PXL arranged on the base layer BSL. The display device DD may further include a driving circuit part (eg, a scan driving part and a data driving part) for driving the pixels PXL, wirings, and pads.

[0047] The display device DD may include a display area DA and a non-display area NDA. The non-display area NDA may refer to an area outside the display area DA. The non-display area NDA may surround at least a portion of the display area DA.

[0048] The base layer BSL may form a basic component of the display device DD. The base layer BSL may be a rigid or flexible substrate or film. For example, the base layer BSL may be a hard substrate made of glass or tempered glass, a soft substrate (or a thin film) made of plastic or metal, or at least one insulating layer. The material and / or physical properties of the base layer BSL are not particularly limited. According to an embodiment, the base layer BSL may be substantially transparent. Here, "substantially transparent" may mean capable of transmitting light with a transmittance of more than one degree. In another embodiment, the base layer BSL may be translucent or opaque. In addition, according to an embodiment, the base layer BSL may also include a reflective substance.

[0049] The display area DA may indicate an area where the pixels PXL are arranged. The non-display area NDA may indicate an area where the pixels PXL are not arranged. A driving circuit part, wirings, and pads connected to the pixels PXL of the display area DA may be arranged in the non-display area NDA.

[0050] According to an embodiment, the pixels PXL (or, sub-pixels SPX) may be arranged in various structures. For example, the pixels PXL (or, sub-pixels SPX) may be arranged in stripes (eg, S-stripe) or According to the embodiment, the sizes of the sub-pixels SPX may be locally different, and the sub-pixels SPX may have various shapes. For example, when viewed from a plane, the sub-pixels SPX may have a quadrilateral shape or a hexagonal shape. However, the present disclosure is not necessarily limited thereto.

[0051] According to an embodiment, the pixel PXL includes a light emitting element LD. The pixel PXL (or, sub-pixel SPX) may include a first sub-pixel SPX1, a second sub-pixel SPX2, and a third sub-pixel SPX3. At least one first sub-pixel SPX1, a second sub-pixel SPX2, and a third sub-pixel SPX3 may form a pixel unit PXU capable of emitting light of multiple colors.

[0052] For example, each of the first subpixel SPX1, the second subpixel SPX2, and the third subpixel SPX3 may emit light of one color. For example, the first subpixel SPX1 may be a red pixel that emits red (e.g., first color) light, the second subpixel SPX2 may be a green pixel that emits green (e.g., second color) light, and the third subpixel SPX3 may be a blue pixel that emits blue (e.g., third color) light. The colors, types, and / or quantities of the first subpixel SPX1, the second subpixel SPX2, and the third subpixel SPX3 constituting each pixel unit PXU are not limited to specific examples.

[0053] Figure 2 is a schematic cross-sectional view showing a display device according to an embodiment. Figure 2 It can be along Figure 1 A cross-sectional view of the display device DD taken along line A to A'. Figure 3 is a schematic cross-sectional view showing a light emitting element according to an embodiment.

[0054] Reference Figure 2 and Figure 3 , the display device DD may include a pixel circuit layer PCL and a light emitting element layer LEL.

[0055] The pixel circuit layer PCL may include a pixel circuit PXC (see Figure 4 The pixel circuit layer PCL may include a base layer BSL, a conductive layer for forming the pixel circuit PXC, and an insulating layer disposed between the conductive layers.

[0056] According to an embodiment, the pixel circuit PXC may include a thin film transistor (Thin Film Transistor), and may be electrically connected to the light emitting element LD to provide an electrical signal for causing the light emitting element LD to emit light.

[0057] The light emitting element layer LEL may be disposed on the pixel circuit layer PCL. According to an embodiment, the light emitting element layer LEL may include a light emitting element LD, a partition wall PW, a connection electrode CL, and an encapsulation film TFE.

[0058] The partition wall PW may define a region where the light emitting portion EL is arranged. For example, the light emitting portion EL may be arranged between the partition walls PW.

[0059] The partition wall PW may include a pixel defining layer PDL and a spacer SEP disposed on the pixel defining layer PDL. The partition wall PW may be disposed in the display area DA and may also be disposed in the non-display area NDA. The partition walls PW may be spaced apart from each other.

[0060] The partition wall PW may be disposed on the pixel circuit layer PCL. The partition wall PW may have a protruding structure protruding in a direction (eg, a thickness direction of the base layer BSL, ie, the third direction DR3) on the pixel circuit layer PCL.

[0061] The pixel defining layer PDL may define a region where the first electrode ELT1 (eg, an anode electrode) is disposed. According to an embodiment, the pixel defining layer PDL may define a region where the light emitting part EL is disposed.

[0062] According to an embodiment, the pixel defining layer PDL may have a multi-layer structure. For example, the pixel defining layer PDL may include a first pixel defining layer PDL1, a second pixel defining layer PDL2 disposed on the first pixel defining layer PDL1, and a third pixel defining layer PDL3 disposed on the second pixel defining layer PDL2. However, the present disclosure is not limited thereto.

[0063] The spacer SEP may physically separate the light emitting portion EL of each of the adjacent sub-pixels SPX in the display area DA. For example, at least a portion of the light emitting portion EL may be separated from other adjacent light emitting portions EL at the edge of the upper surface of the spacer SEP. For example, the spacer SEP may physically separate the first sub-pixel SPX1 and the second sub-pixel SPX2 in the display area DA.

[0064] According to an embodiment, the separator SEP may have a multi-layer structure. For example, the separator SEP may include a first separator SEP1, a second separator SEP2 disposed on the first separator SEP1, and a third separator SEP3 disposed on the second separator SEP2. However, the present disclosure is not limited thereto.

[0065] The spacer SEP and the pixel defining layer PDL may include a side surface having a step difference. The side surfaces of the spacer SEP and the pixel defining layer PDL may not be flat. The spacer SEP and the pixel defining layer PDL may include portions protruding in respective width directions. For example, the spacer SEP and the pixel defining layer PDL may have ends that are inconsistent with each other. When viewed from a plane, the spacer SEP and the pixel defining layer PDL may have ends that do not overlap with each other. A width of the spacer SEP and a width of the pixel defining layer PDL may be different from each other. The width of each of the spacer SEP and the pixel defining layer PDL may be defined based on the direction (e.g., the first direction DR1 or the second direction DR2) in which the plane in which the base layer BSL is arranged extends.

[0066] The light emitting element LD may be disposed on the pixel circuit layer PCL. According to an embodiment, the light emitting element LD may include a first electrode ELT1, a light emitting portion EL, and a second electrode ELT2.

[0067] The first electrode ELT1 may be arranged on the pixel circuit layer PCL. The light emitting portion EL may be arranged on the first electrode ELT1. The light emitting portion EL may cover the first electrode ELT1. According to an embodiment, the light emitting portion EL may be arranged in an area defined by the partition wall PW. For example, the light emitting portion EL may be arranged in an area surrounded by the partition wall PW. The second electrode ELT2 may be arranged on the light emitting portion EL. According to an embodiment, the second electrode ELT2 may completely cover the light emitting portion EL.

[0068] According to an embodiment, one surface of the light emitting portion EL may be electrically connected to the first electrode ELT1, and the other surface of the light emitting portion EL may be electrically connected to the second electrode ELT2. The first electrode ELT1 may be an anode electrode ANO for the light emitting portion EL, and the second electrode ELT2 may be a cathode electrode CAT for the light emitting portion EL.

[0069] According to an embodiment, the first electrode ELT1 and the second electrode ELT2 may include a conductive material. For example, the conductive material may include one or more of the group consisting of gold (Au), silver (Ag), aluminum (Al), molybdenum (Mo), chromium (Cr), titanium (Ti), nickel (Ni), neodymium (Nd), copper (Cu), and platinum (Pt). Alternatively, according to an embodiment, the conductive material may include silver nanowires (AgNW), indium tin oxide (ITO: Indium Tin Oxide), indium zinc oxide (IZO: Indium Zinc Oxide), indium gallium zinc oxide (IGZO: Indium Gallium Zinc Oxide), antimony zinc oxide (AZO: Antimony Zinc Oxide), indium tin zinc oxide (ITZO: Indium Tin Zinc Oxide), zinc oxide (ZnO: Zinc Oxide), tin dioxide (SnO 2 :Tin Oxide), carbon nanotube (Carbon Nano Tube) and graphene (graphene) group one or more. However, the present disclosure is not necessarily limited thereto.

[0070] The light emitting portion EL may have a multilayer thin film structure including a light generation layer (e.g., a light emitting layer EML). The light emitting portion EL includes: a hole injection layer HIL (hole injection layer) for injecting holes; a hole transport layer HTL (hole transport layer) for excellent hole transportability and for suppressing the movement of electrons not combined in the light emitting layer EML and increasing the chance of recombination of holes and electrons; a light emitting layer EML for emitting light by recombination of injected electrons and holes; an electron transport layer ETL (electron transport layer) for smoothly transferring electrons to the light emitting layer EML; and an electron injection layer EIL (electron injection layer) for injecting electrons. The light emitting portion EL may emit light based on an electrical signal provided from an anode electrode ANO (e.g., a first electrode ELT1) and a cathode electrode CAT (e.g., a second electrode ELT2).

[0071] In addition, according to an embodiment, the second electrode ELT2 may be manufactured in a manner of being deposited on the entire surface within the display area DA. Accordingly, the power supplied to the second electrode ELT2 may be supplied to each sub-pixel SPX. In addition, the second electrode ELT2 may be manufactured in a manner of being further deposited on at least a portion of the non-display area NDA outside the display area DA across the display area DA.

[0072] According to an embodiment, the second electrode ELT2 may include a 2-1st electrode ELT2-1 arranged (e.g., formed) in the display area DA and a 2-2nd electrode ELT2-2 arranged (e.g., formed) in the non-display area NDA. The 2-1st electrode ELT2-1 and the 2-2nd electrode ELT2-2 may be formed in the same process. For example, the 2-1st electrode ELT2-1 and the 2-2nd electrode ELT2-2 may be deposited in the same process and thus may include the same material. The 2-1st electrode ELT2-1 and the 2-2nd electrode ELT2-2 may be formed integrally.

[0073] In the display device DD according to the embodiment, since the spacer SEP and the pixel defining layer PDL have ends that are not consistent with each other, when the 2-2nd electrode ELT2-2 is deposited in the non-display area NDA, the contact area with the lower layer of the deposited conductive material can be increased, and accordingly, the adhesion with the surface on which the 2-2nd electrode ELT2-2 is deposited can be increased. In this regard, referring to Figure 6 The following drawings will be described later.

[0074] The 2-2 electrode ELT2-2 may be electrically connected to the connection electrode CL disposed on the pixel circuit layer PCL. The connection electrode CL may be formed in the same process as the first electrode ELT1. For example, the connection electrode CL and the first electrode ELT1 may be deposited in the same process, and accordingly, may include the same material as each other. The connection electrode CL and the first electrode ELT1 may be formed integrally.

[0075] The encapsulation film TFE may be arranged on the light emitting element LD (e.g., the second electrode ELT2). The encapsulation film TFE may offset the step difference generated by the light emitting element LD and the pixel defining layer PDL. The encapsulation film TFE may include a plurality of insulating films covering the light emitting element LD. According to an embodiment, the encapsulation film TFE may also have a structure in which inorganic films and organic films are alternately stacked. According to an embodiment, the encapsulation film TFE may be a thin film encapsulation film.

[0076] Figure 4 is a schematic block diagram showing an electrical connection structure of a light emitting element according to an embodiment. Figure 4 An electrical connection structure including a pixel circuit PXC corresponding to each sub-pixel SPX may be shown. Figure 5 It is shown Figure 1 Schematic enlargement of the EA1 region. Figure 5 1 is a schematic plan view showing a connection relationship between the second power line PL2 and the second electrode ELT2 according to the embodiment. Figure 5 A structure in which the 2-1st electrode ELT2-1 of the display area DA is electrically connected to the second power line PL2 formed in the non-display area NDA may be shown.

[0077] Reference Figure 4 , the sub-pixel SPX may include a pixel circuit PXC configured to drive the light emitting element LD.

[0078] The pixel circuit PXC may include more than one circuit element. For example, the pixel circuit PXC may include a transistor and a storage capacitor. For example, the pixel circuit PXC may include a driving transistor, a switching transistor, and a storage capacitor. However, the present disclosure is not necessarily limited thereto.

[0079] The pixel circuit PXC may be electrically connected to the scan line SL and the data line DL. The scan line SL may supply a scan signal to the pixel circuit PXC, and according to an embodiment, the scan line SL may be electrically connected to a gate electrode of a switching transistor of the pixel circuit PXC. The light emitting element LD may be configured to emit light corresponding to a data signal provided from the data line DL.

[0080] The pixel circuit PXC may be electrically connected to the first power line PL1 and the second power line PL2. For example, the first electrode ELT1 of the light emitting element LD may be electrically connected to the pixel circuit PXC and the first power line PL1, and the second electrode ELT2 of the light emitting element LD may be electrically connected to the second power line PL2. The first power line PL1 and the second power line PL2 may be arranged on the base layer BSL.

[0081] The power supply of the first power line PL1 and the power supply of the second power line PL2 may have different potentials from each other. For example, the power supply of the first power line PL1 may be a high potential pixel power supply receiving power from the first voltage potential VDD, and the power supply of the second power line PL2 may be a low potential pixel power supply receiving power from the second voltage potential VSS. The potential difference between the power supply of the first power line PL1 and the power supply of the second power line PL2 may be set to be above the threshold voltage of the light emitting element LD.

[0082] The first power line PL1 may be electrically connected to the pixel circuit PXC (eg, a driving transistor). The second power line PL2 may be electrically connected to a cathode electrode (eg, a second electrode ELT2) of the light emitting element LD.

[0083] According to an embodiment, the second power line PL2 may be electrically connected to the second electrode ELT2. Figure 5 , the second electrode ELT2 may also receive power through the second power line PL2 arranged in the non-display area NDA. According to an embodiment, the 2-1st electrode ELT2-1 arranged in the display area DA may be adjacent to the 2-2nd electrode ELT2-2 arranged in the non-display area NDA. The 2-1st electrode ELT2-1 arranged in the display area DA may be electrically connected to the 2-2nd electrode ELT2-2 arranged in the non-display area NDA. According to an embodiment, the 2-2nd electrode ELT2-2 in the non-display area NDA may be adjacent to the connection electrode CL. The 2-2nd electrode ELT2-2 in the non-display area NDA may be electrically connected to the connection electrode CL. According to an embodiment, the connection electrode CL may be adjacent to the second power line PL2. The connection electrode CL may be electrically connected to the second power line PL2. Therefore, the second electrode ELT2 formed across the display area DA and the non-display area NDA may be electrically connected to the second power line PL2 in the non-display area NDA. As described above, since the 2-1st electrode ELT2-1 and the second power line PL2 within the display area DA are electrically connected to each other, power supplied from the second power line PL2 may be applied to the entire display area DA.

[0084] Each light emitting element LD may be connected between the first power line PL1 and the second power line PL2 in the forward direction to form its own effective light source, and these effective light sources may be gathered to form the light emitting element LD of the sub-pixel SPX.

[0085] The light emitting element LD may emit light with a brightness corresponding to the driving current supplied by the pixel circuit PXC. During each frame period, the pixel circuit PXC may supply a driving current corresponding to the data signal to the light emitting element LD. The light emitting element LD may emit light with a brightness corresponding to the current flowing through the light emitting element LD.

[0086] Below, refer to Figure 2 and Figure 6 , structural features of the partition wall PW included in the display device DD are described. Figure 6 is a diagram schematically showing the structure of a partition wall PW according to the first embodiment.

[0087] Reference Figure 2 and Figure 6 , the partition wall PW may have a multilayer structure in which a pixel defining layer PDL is arranged and a spacer SEP is arranged on the pixel defining layer PDL. The pixel defining layer PDL may include a first pixel defining layer PDL1, a second pixel defining layer PDL2, and a third pixel defining layer PDL3. The spacer SEP may include a first spacer SEP1, a second spacer SEP2, and a third spacer SEP3.

[0088] The first pixel defining layer PDL1 may be adjacent to the pixel circuit layer PCL. According to an embodiment, the first pixel defining layer PDL1 may be directly arranged on the pixel circuit layer PCL. The first pixel defining layer PDL1 may physically divide the first electrode ELT1. The first pixel defining layer PDL1 may physically divide the connection electrode CL. The first pixel defining layer PDL1 may cover one end of the first electrode ELT1 and the connection electrode CL. There may be a step difference between the first pixel defining layer PDL1 and the first electrode ELT1 and the connection electrode CL. Since there is a step difference between the first pixel defining layer PDL1 and the first electrode ELT1 and the connection electrode CL, the deposition surface area of ​​the 2-2 electrode ELT2-2 may be increased compared to a case where there is no step difference between the first pixel defining layer PDL1 and the first electrode ELT1 and the connection electrode CL (for example, a case where the height of the first pixel defining layer PDL1 is the same as the height of the connection electrode CL).

[0089] The first pixel defining layer PDL1 may have a first defining layer width PDL_W1. The first defining layer width PDL_W1 may be a maximum width defined in the first pixel defining layer PDL1. The first defining layer width PDL_W1 may be the thickest width among the widths of the partition wall PW. Hereinafter, the width of the pixel defining layer PDL defined in the present disclosure may be defined based on a direction (e.g., a first direction DR1 or a second direction DR2) in which a plane in which the base layer BSL or the pixel circuit layer PCL is arranged extends.

[0090] The second pixel defining layer PDL2 may be disposed on the first pixel defining layer PDL1. The second pixel defining layer PDL2 may be adjacent to the first pixel defining layer PDL1. According to an embodiment, the second pixel defining layer PDL2 may be directly disposed on the first pixel defining layer PDL1.

[0091] The second pixel defining layer PDL2 may have a second defining layer width PDL_W2. The second defining layer width PDL_W2 may be a maximum width defined in the second pixel defining layer PDL2. The second defining layer width PDL_W2 may be smaller than the first defining layer width PDL_W1. Therefore, when viewed from a plane, the second pixel defining layer PDL2 and the first pixel defining layer PDL1 may have ends that are inconsistent with each other. When viewed from a plane, the ends of the second pixel defining layer PDL2 and the ends of the first pixel defining layer PDL1 may not overlap. The second pixel defining layer PDL2 may have a structure that is more recessed in the width direction than the first pixel defining layer PDL1. The first pixel defining layer PDL1 may have a structure that is more protruding in the width direction than the second pixel defining layer PDL2.

[0092] The third pixel defining layer PDL3 may be disposed on the second pixel defining layer PDL2. The third pixel defining layer PDL3 may be adjacent to the second pixel defining layer PDL2. According to an embodiment, the third pixel defining layer PDL3 may be directly disposed on the second pixel defining layer PDL2.

[0093] The third pixel defining layer PDL3 may have a third defining layer width PDL_W3. The third defining layer width PDL_W3 may be a maximum width defined in the third pixel defining layer PDL3. The third defining layer width PDL_W3 may be smaller than the second defining layer width PDL_W2. Therefore, when viewed from a plane, the third pixel defining layer PDL3 and the second pixel defining layer PDL2 may have ends that are inconsistent with each other. When viewed from a plane, the ends of the third pixel defining layer PDL3 and the ends of the second pixel defining layer PDL2 may not overlap. The third pixel defining layer PDL3 may have a structure that is more recessed in the width direction than the second pixel defining layer PDL2. The second pixel defining layer PDL2 may have a structure that is more protruding in the width direction than the third pixel defining layer PDL3.

[0094] Each of the first pixel defining layer PDL1, the second pixel defining layer PDL2, and the third pixel defining layer PDL3 may have ends that are inconsistent with each other. When viewed from a plane, each of the first pixel defining layer PDL1, the second pixel defining layer PDL2, and the third pixel defining layer PDL3 may not overlap.

[0095] However, the present disclosure is not limited thereto. For example, when viewed from a plane, the first pixel defining layer PDL1 and the second pixel defining layer PDL2 may have ends that coincide with each other, and may have ends that do not coincide with the third pixel defining layer PDL3.

[0096] When viewed from a plane, each of the first pixel defining layer PDL1, the second pixel defining layer PDL2, and the third pixel defining layer PDL3 may have ends that are inconsistent with each other, and the pixel defining layer PDL may have a curved surface. For example, the side surface of the pixel defining layer PDL may not be flat, and when viewed from a plane, Figure 2 When the cross-sectional direction defined in is taken as a reference, the cross-section of the pixel defining layer PDL may have a stepped shape.

[0097] According to the existing display structure, each of the first pixel defining layer PDL1, the second pixel defining layer PDL2, and the third pixel defining layer PDL3 has ends that coincide with each other (eg, their ends overlap each other on a plane). Figure 2When the cross-sectional direction defined in is taken as a reference, the cross-sectional shape of the pixel defining layer PDL has a substantially rectangular shape. Therefore, when the 2-2nd electrode ELT2-2 is deposited on the non-display area NDA, a sufficient surface area required for adhesion to the pixel defining layer PDL cannot be ensured. For example, in the non-display area NDA, it may be difficult for the 2-2nd electrode ELT2-2 to cover at least a portion of the pixel defining layer PDL, and it may often happen that the 2-2nd electrode ELT2-2 is deposited only on the structure corresponding to the third spacer SEP3. Therefore, a warping phenomenon may occur for the 2-2nd electrode ELT2-2 in the non-display area NDA.

[0098] According to the partition wall PW structure of the embodiment, a tortuous surface can be formed in the pixel defining layer PDL (for example, on the side surface of the pixel defining layer PDL), and the surface area of ​​the pixel defining layer PDL capable of depositing the 2-2 electrode ELT2-2 can be increased. For example, since a tortuous surface is formed in the partition wall PW in the non-display area NDA, the 2-2 electrode ELT2-2 can be deposited in a manner having a larger area than in a case where a tortuous surface is not formed in the partition wall PW. For example, in the non-display area NDA, the 2-2 electrode ELT2-2 can cover the side surface of the pixel defining layer PDL forming the tortuous surface. The area capable of depositing the 2-2 electrode ELT2-2 increases, so that the adhesion between the 2-2 electrode ELT2-2 and the pixel defining layer PDL can be increased, and the warping phenomenon for the 2-2 electrode ELT2-2 can not occur in the non-display area NDA.

[0099] The pixel defining layer PDL may include an inorganic material. For example, the pixel defining layer PDL may include silicon oxide (SiO x ) and silicon nitride (SiN x )

[0100] According to an embodiment, the first pixel defining layer PDL1 and the third pixel defining layer PDL3 may include the same material as each other, and may include a material different from that of the second pixel defining layer PDL2. For example, the first pixel defining layer PDL1 and the third pixel defining layer PDL3 may include silicon oxide (SiO x ), and the second pixel defining layer PDL2 may include silicon nitride (SiN x ). However, the present disclosure is not limited thereto.

[0101] In another embodiment, the pixel defining layer PDL may also include an organic material. For example, the pixel defining layer PDL may include one or more of the group consisting of acrylic resin, epoxy resin, phenol resin, polyamide resin, and polyimide resin.

[0102] The first spacer SEP1 may be disposed on the third pixel defining layer PDL3. The first spacer SEP1 may be adjacent to the third pixel defining layer PDL3. According to an embodiment, the first spacer SEP1 may be directly disposed on the third pixel defining layer PDL3.

[0103] According to an embodiment, the first spacer SEP1 may have two or more different widths. For example, the first spacer SEP1 may have a first spacer width SEP_W1 at one end and may have a width smaller than the first spacer width SEP_W1 at the other end.

[0104] The first spacer width SEP_W1 may be the maximum width defined in the first spacer SEP1. The first spacer width SEP_W1 may be less than the third definition layer width PDL_W3. Therefore, the first spacer SEP1 and the third pixel definition layer PDL3 may have ends that are inconsistent with each other. When viewed from a plane, the end of the first spacer SEP1 and the end of the third pixel definition layer PDL3 may not overlap with each other. However, the present disclosure is not limited to this. The first spacer width SEP_W1 and the third definition layer width PDL_W3 may be the same as each other. The first spacer SEP1 and the third pixel definition layer PDL3 may have ends that are consistent with each other. When viewed from a plane, the end of the first spacer SEP1 and the end of the third pixel definition layer PDL3 may overlap with each other.

[0105] The second spacer SEP2 may be disposed on the first spacer SEP1. The second spacer SEP2 may be adjacent to the first spacer SEP1. According to an embodiment, the second spacer SEP2 may be directly disposed on the first spacer SEP1.

[0106] The second separator SEP2 may have two or more different widths. For example, the second separator SEP2 may have the same width at one end and the other end, and may have a narrower width in the central region than at one end and the other end. The second separator SEP2 may have a second separator width SEP_W2 at one end and the other end, and may have a width in the central region that is smaller than the second separator width SEP_W2.

[0107] The second spacer width SEP_W2 may be the maximum width defined in the second spacer SEP2. The second spacer width SEP_W2 may be smaller than the first spacer width SEP_W1. Since the second spacer width SEP_W2 is smaller than the first spacer width SEP_W1, the second spacer SEP2 may have a structure that is recessed inwardly compared to the first spacer SEP1.

[0108] The third spacer SEP3 may be disposed on the second spacer SEP2. The third spacer SEP3 may be adjacent to the second spacer SEP2. According to an embodiment, the third spacer SEP3 may be directly disposed on the second spacer SEP2.

[0109] The third spacer SEP3 may have two or more different widths. For example, the third spacer SEP3 may have a third spacer width SEP_W3 at one end and a width narrower than the third spacer width SEP_W3 at the other end.

[0110] The third separator width SEP_W3 may be the maximum width defined in the third separator SEP3. The third separator width SEP_W3 may be greater than the second separator width SEP_W2. According to an embodiment, the third separator width SEP_W3 may be the same as the first separator width SEP_W1. However, the present disclosure is not limited thereto. The third separator width SEP_W3 and the first separator width SEP_W1 may be greater than the second separator width SEP_W2, so that the separator SEP has an undercut structure in which the first separator SEP1 and the third separator SEP3 protrude more toward the outside than the second separator SEP2.

[0111] Since the first spacer SEP1 and the third spacer SEP3 of the spacer SEP have an undercut structure that protrudes more toward the outside than the second spacer SEP2, the spacer SEP may have a width that gradually narrows from one end to the center and gradually widens from the center to the other end. The spacer SEP may include a curved surface. Therefore, compared with a case where the spacer SEP does not include a curved surface, when the 2-2 electrode ELT2-2 is deposited on the non-display area NDA, the surface area for depositing the 2-2 electrode ELT2-2 on the spacer SEP may be increased. For example, when the 2-2 electrode ELT2-2 is deposited on the non-display area NDA, the 2-2 electrode ELT2-2 may cover the side surface of the spacer SEP. Therefore, a warping phenomenon with respect to the 2-2 electrode ELT2-2 may be prevented in the non-display area NDA.

[0112] The spacer SEP may include an inorganic material. For example, the spacer SEP may include silicon oxide (SiO x ) and silicon nitride (SiNx )

[0113] According to an embodiment, the first spacer SEP1 and the third spacer SEP3 may include the same material, and may include a material different from that of the second spacer SEP2. For example, the first spacer SEP1 and the third spacer SEP3 may include silicon nitride (SiN x ), the second spacer SEP2 may include silicon oxide (SiO x ). However, the present disclosure is not limited thereto. In another embodiment, the spacer SEP may also include an organic material. For example, the spacer SEP may also include one or more of the group consisting of acrylic resin, epoxy resin, phenol resin, polyamide resin, and polyimide resin.

[0114] A partition wall PW including a partition member SEP and a pixel defining layer PDL according to an embodiment may be formed in at least a portion of the non-display area NDA. The partition walls PW may be arranged to be spaced apart from each other, and the partition walls PW may be arranged on the pixel circuit layer PCL, and two or more protruding structures may be formed (or included) on the pixel circuit layer PCL. Since the protruding structure is formed in the non-display area NDA, when the 2-2 electrode ELT2-2 is deposited on the non-display area NDA, the surface area on which the 2-2 electrode ELT2-2 can be deposited may be increased, and a warping phenomenon for the 2-2 electrode ELT2-2 may be prevented in the non-display area NDA.

[0115] The partition wall PW including the spacer SEP and the pixel defining layer PDL according to the embodiment may have two or more widths different from each other. For example, the width of the pixel defining layer PDL may be different from the width of the spacer SEP. For example, the first pixel defining layer PDL1, the second pixel defining layer PDL2, the third pixel defining layer PDL3, and the second spacer SEP2 may have different widths, respectively. Since the spacer SEP and the pixel defining layer PDL have different widths, one end of the spacer SEP and one end of the pixel defining layer PDL may not be consistent. When viewed from a plane, one end of the spacer SEP and one end of the pixel defining layer PDL may not overlap. Therefore, the partition wall PW may have a tortuous surface, and the surface area on which the 2-2 electrode ELT2-2 can be deposited may be increased.

[0116] Below, we will refer to Figure 7 and Figure 8The structure of the partition wall PW according to the second embodiment and the third embodiment is described. The contents overlapping with the above contents will not be described repeatedly. Figure 7 is a diagram schematically showing the structure of a partition wall according to a second embodiment. Figure 8 is a diagram schematically showing the structure of a partition wall according to a third embodiment.

[0117] The second embodiment is different from the first embodiment in that, when viewed from a plane, the first pixel defining layer PDL1, the second pixel defining layer PDL2, and the third pixel defining layer PDL3 have ends that are consistent with each other. The third embodiment is different from the first embodiment in that the first spacer SEP1, the second spacer SEP2, and the third spacer SEP3 have ends that are consistent with each other.

[0118] Reference Figure 7 , the first pixel defining layer PDL1, the second pixel defining layer PDL2, and the third pixel defining layer PDL3 may have the same ends as each other. When viewed from a plane, the ends of each of the first pixel defining layer PDL1, the second pixel defining layer PDL2, and the third pixel defining layer PDL3 may overlap with each other. The first defining layer width PDL_W1, the second defining layer width PDL_W2, and the third defining layer width PDL_W3 may be the same as each other.

[0119] The spacer SEP according to the second embodiment may include the same undercut structure as the first embodiment. The partition wall PW according to the second embodiment may include the spacer SEP having the undercut structure, so that when the 2-2nd electrode ELT2-2 is deposited on the non-display area NDA, the surface area bonded to the spacer SEP may be increased, and a warping phenomenon with respect to the 2-2nd electrode ELT2-2 may be prevented in the non-display area NDA.

[0120] Reference Figure 8 , the first separator SEP1, the second separator SEP2, and the third separator SEP3 may have the same ends as each other. When viewed from a plane, the ends of each of the first separator SEP1, the second separator SEP2, and the third separator SEP3 may overlap with each other. The first separator width SEP_W1, the second separator width SEP_W2, and the third separator width SEP_W3 may be the same as each other.

[0121] The pixel defining layer PDL may have the same structure as that of the first embodiment. Since a tortuous surface is formed in the pixel defining layer PDL, the surface area of ​​the pixel defining layer PDL on which the 2-2 electrode ELT2-2 can be deposited may be increased. Accordingly, the adhesion between the 2-2 electrode ELT2-2 and the pixel defining layer PDL may be increased, and a warping phenomenon with respect to the 2-2 electrode ELT2-2 may be prevented in the non-display area NDA.

[0122] Below, we will refer to Figures 9 to 13 A method of manufacturing a display device including the partition wall PW according to the first embodiment is described. Fig. 9 is a flowchart illustrating a method of manufacturing a display device according to an embodiment.

[0123] Figures 10 to 13 Schematic cross-sectional views of the steps of a method for manufacturing a display device according to an embodiment. Figures 10 to 13 In order to more clearly illustrate only the structure of the partition wall PW arranged in the non-display area NDA, the connection electrode CL is not shown, and the configuration of the display device DD arranged in the non-display area NDA is shown.

[0124] Reference Fig. 9 , the manufacturing method of the display device DD according to the first embodiment includes the following steps: depositing a basic pixel defining layer and a basic spacer on a pixel circuit layer ( S100 ); etching the basic spacer ( S200 ); and etching the basic pixel defining layer ( S300 ).

[0125] Reference Fig.10 In the step (S100) of depositing a basic pixel defining layer and a basic spacer on the pixel circuit layer, the basic pixel defining layer PDL' may be deposited on the pixel circuit layer PCL, and the basic spacer SEP' may be deposited on the basic pixel defining layer PDL'. The basic pixel defining layer PDL' may completely cover the pixel circuit layer PCL. The basic spacer SEP' may completely cover the basic pixel defining layer PDL'. The basic spacer SEP' may have an end portion that is consistent with the basic pixel defining layer PDL'. When viewed from a plane, an end portion of the basic spacer SEP' and an end portion of the basic pixel defining layer PDL' may overlap each other.

[0126] In the present disclosure, as a process for depositing the structure of the display device DD, one or more of a chemical vapor deposition (CVD) process and an atomic layer deposition (ALD) process may be used. However, the present disclosure is not limited to a specific example.

[0127] The basic pixel defining layer PDL′ may include a first basic pixel defining layer PDL1 ′, a second basic pixel defining layer PDL2 ′, and a third basic pixel defining layer PDL3 ′.

[0128] The first base pixel defining layer PDL1' may be deposited on the pixel circuit layer PCL. The second base pixel defining layer PDL2' may be deposited on the first base pixel defining layer PDL1'. The third base pixel defining layer PDL3' may be deposited on the second base pixel defining layer PDL2'.

[0129] The basic pixel defining layer PDL' may include an inorganic material. In one embodiment, the first basic pixel defining layer PDL1' and the third basic pixel defining layer PDL3' may include the same material as each other, and may include a material different from that of the second basic pixel defining layer PDL2'. For example, the first basic pixel defining layer PDL1' and the third basic pixel defining layer PDL3' may include silicon oxide (SiO x ), the second basic pixel defining layer PDL2' may include silicon nitride (SiN x ). However, the present disclosure is not limited thereto.

[0130] In another embodiment, the basic pixel defining layer PDL' may also include an organic material. For example, the basic pixel defining layer PDL' may also include one or more of the group consisting of acrylic resin, epoxy resin, phenol resin, polyamide resin and polyimide resin.

[0131] The base spacer SEP' may include a first base spacer SEP1', a second base spacer SEP2', and a third base spacer SEP3'.

[0132] The first base spacer SEP1 ′ may be deposited on the third basic pixel defining layer PDL3 ′. The second base spacer SEP2 ′ may be deposited on the first base spacer SEP1 ′. The third base spacer SEP3 ′ may be deposited on the second base spacer SEP2 ′.

[0133] The base spacer SEP' may include an inorganic material. According to an embodiment, the first base spacer SEP1' and the third base spacer SEP3' may include the same material as each other, and may include a material different from that of the second base spacer SEP2'. For example, the first base spacer SEP1' and the third base spacer SEP3' may include silicon nitride (SiN x ), the second base spacer SEP2′ may include silicon oxide (SiOx ).

[0134] In another embodiment, the base spacer SEP' may also include an organic material, for example, the base spacer SEP' may also include one or more of the group consisting of acrylic resin, epoxy resin, phenol resin, polyamide resin, and polyimide resin.

[0135] Reference Fig.11 In the step (S200) of etching the base separator, the base separator SEP' may be etched to have the same end. For example, when viewed from a plane, the base separator SEP' may be etched to have ends overlapping each other. In the present disclosure, the etching process may adopt one or more of wet etching and dry etching. However, the present disclosure is not limited to a specific example.

[0136] The base spacer SEP' may be etched to form an opening portion exposing the base pixel defining layer PDL'. The base spacer SEP' may be etched to form the spacer SEP. The spacer SEP may form a protrusion on the base pixel defining layer PDL'.

[0137] The first base spacer SEP1' may be etched to form a first spacer SEP1 having a first spacer width SEP_W1. The second base spacer SEP2' may be etched to form a second spacer SEP2 having an intermediate width M2. The third base spacer SEP3' may be etched to form a third spacer SEP3 having a third spacer width SEP_W3. The first spacer width SEP_W1, the intermediate width M2, and the third spacer width SEP_W3 may have the same width as each other. According to an embodiment, the first spacer SEP1, the second spacer SEP2, and the third spacer SEP3 may have the same width as each other.

[0138] Reference Fig.12, in the step (S200) of etching the base separator, after the base separator SEP' is etched to have the same end, the second separator SEP2 may be further selectively etched. Since the second separator SEP2 is further etched, the second separator SEP2 may have a second separator width SEP_W2. The second separator SEP2 may be etched deeper relative to the first separator SEP1 and the third separator SEP3. The second separator SEP2 may be etched so that the first separator SEP1 and the third separator SEP3 form a tip. The second separator width SEP_W2 may be smaller than the first separator width SEP_W1 and the third separator width SEP_W3.

[0139] By etching the second spacer SEP2, an undercut structure of the spacer SEP may be formed. The second spacer SEP2 may be etched to form a curved surface. The second spacer SEP2 may have a different width from the first spacer SEP1 and the third spacer SEP3.

[0140] Reference Fig.13 In the step of etching the basic pixel defining layer (S300), the pixel defining layer PDL may be formed by etching the basic pixel defining layer PDL'. The pixel defining layer PDL may be etched to have a step-shaped cross section. Figure 2 , the pixel defining layer PDL may be etched to expose at least a portion of the connection electrode CL.

[0141] The first basic pixel defining layer PDL1' may be etched to form a first pixel defining layer PDL1 having a first defining layer width PDL_W1. The first basic pixel defining layer PDL1' may be etched to have the thickest first defining layer width PDL_W1 in the partition wall PW. The second basic pixel defining layer PDL2' may be etched to form a second pixel defining layer PDL2 having a second defining layer width PDL_W2. The second basic pixel defining layer PDL2' may be etched to have a second defining layer width PDL_W2 less than the first defining layer width PDL_W1. The third basic pixel defining layer PDL3' may be etched to form a third pixel defining layer PDL3 having a third defining layer width PDL_W3. The third basic pixel defining layer PDL3' may be etched to have a third defining layer width PDL_W3 less than the second defining layer width PDL_W2. The third defining layer width PDL_W3 may be greater than the first spacer width SEP_W1. However, the present disclosure is not limited thereto. The third defining layer width PDL_W3 and the first spacer width SEP_W1 may be the same as each other.

[0142] Below, we will refer to Figures 10 to 12 and Fig.14A method of manufacturing a display device including the partition wall PW according to the second embodiment is described. Fig.14 is a flowchart illustrating a method of manufacturing a display device according to an embodiment. Fig.14 2. The flowchart showing the method for manufacturing the partition wall PW according to the second embodiment may be described below. The contents overlapping with the aforementioned contents will not be described again.

[0143] refer to Fig.14 , the manufacturing method of the display device DD according to the second embodiment may include the following steps: depositing a basic pixel defining layer and a basic spacer on a pixel circuit layer ( S100 ); and etching the basic spacer ( S200 ).

[0144] Reference Figures 10 to 12 In the step of depositing a basic pixel defining layer and a basic spacer on a pixel circuit layer ( S100 ), a basic pixel defining layer PDL′ may be deposited on the pixel circuit layer PCL. A basic spacer SEP′ may be deposited on the basic pixel defining layer PDL′.

[0145] In the step of etching the base spacer ( S200 ), the base spacer SEP′ may be etched such that the spacer SEP forms an undercut structure.

[0146] The manufacturing method of the partition wall PW according to the second embodiment may not include the step of etching the basic pixel defining layer (S300). Since the basic pixel defining layer is not etched, the pixel defining layer PDL may have ends that are consistent with each other. For example, the first basic pixel defining layer PDL1', the second basic pixel defining layer PDL2' and the third basic pixel defining layer PDL3' may have ends that are consistent with each other. The first basic pixel defining layer PDL1', the second basic pixel defining layer PDL2' and the third basic pixel defining layer PDL3' may have ends that overlap with each other on a plane. The pixel defining layer PDL may not be etched to expose at least a portion of the connecting electrode CL.

[0147] Below, we will refer to Figures 9 to 11 and Fig.15 A method of manufacturing a display device including the partition wall PW according to the third embodiment is described. Fig.15 Schematic cross-sectional views of the manufacturing method of the display device according to the third embodiment according to the steps. Fig.15 In order to more clearly show the structure of the partition wall PW, the connection electrode CL is not shown.

[0148] Reference Fig. 9 , the manufacturing method of the display device DD according to the third embodiment includes the following steps: depositing a basic pixel defining layer and a basic spacer on a pixel circuit layer ( S100 ); etching the basic spacer ( S200 ); and etching the basic pixel defining layer ( S300 ).

[0149] Reference Fig.10 In the step (S100) of depositing a basic pixel defining layer and a basic spacer on a pixel circuit layer, a pixel circuit layer PCL may be formed, a basic pixel defining layer PDL' may be deposited on the pixel circuit layer PCL, and a basic spacer SEP' may be deposited on the basic pixel defining layer PDL'.

[0150] Reference Fig.11 , in the step (S200) of etching the base spacer, the base spacer SEP' may be etched to have the same end. The base spacer SEP' may be etched to have overlapping ends on a plane. For the partition wall PW according to the third embodiment, the step (S200) of etching the base spacer may not include a step of further selectively etching the second spacer SEP2. Therefore, the spacer SEP may have the same end.

[0151] Reference Fig.15 In the step of etching the basic pixel defining layer ( S300 ), the basic pixel defining layer PDL′ may be etched to form a pixel defining layer PDL. The pixel defining layer PDL may be etched to have a step-shaped cross section.

[0152] By the manufacturing method of the display device DD according to the embodiment, the partition wall PW forming the protruding structure can be arranged in the non-display area NDA, and since the partition wall PW forms the protruding structure, the surface area on which the 2-2 electrode ELT2-2 can be deposited can be increased. The contact area with the lower layer on which the 2-2 electrode ELT2-2 is deposited can be increased, and accordingly, the adhesive force with the surface on which the 2-2 electrode ELT2-2 is deposited can be increased. Therefore, the warping phenomenon with respect to the 2-2 electrode ELT2-2 can be prevented.

[0153] The above description is made with reference to the preferred embodiments of the present disclosure, but any skilled technician in the technical field to which the present disclosure belongs or a technician with ordinary knowledge in the technical field to which the present disclosure belongs can understand that various modifications and changes can be made to the present disclosure without departing from the scope of the idea and technical field of the present disclosure recorded in the claims.

[0154] Therefore, the technical scope of the present disclosure is not limited to the contents described in the detailed description of the specification but should be determined by the claims.

Claims

1. A display device, include: A display area and a non-display area, wherein pixels are arranged in the display area, and the non-display area is an area outside the display area; A pixel circuit layer, including a pixel circuit; as well as a partition wall arranged on the pixel circuit layer of the display area and the non-display area, and comprising a pixel defining layer and a partition arranged on the pixel defining layer, Wherein, in the non-display area, one end of the pixel defining layer and one end of the spacer do not overlap when viewed from a plane.

2. The display device according to claim 1, in, The pixel defining layer comprises: a first pixel defining layer, arranged on the pixel circuit layer and having a first defining layer width; and a second pixel defining layer, arranged on the first pixel defining layer and having a second defining layer width, Wherein, the separator comprises: a first spacer disposed on the pixel defining layer and having a first spacer width; and The second separator is arranged on the first separator and has a second separator width.

3. The display device according to claim 2, in, The width of the first limiting layer is greater than the width of the second limiting layer, The pixel defining layer includes an uneven side surface.

4. The display device according to claim 2, in, The first spacer width is smaller than the second limiting layer width, The second divider width is smaller than the first divider width.

5. The display device according to claim 4, in, The separator comprises a curved surface, Compared with the first spacer, the second spacer is more recessed toward the inside along a direction in which a plane on which the pixel circuit layer is arranged extends.

6. The display device according to claim 2, in, The pixel defining layer further comprises: a third pixel defining layer, arranged on the second pixel defining layer and having a third defining layer width, Wherein, the separator also includes: The third separator is arranged on the second separator and has a third separator width.

7. The display device according to claim 6, in, An end portion of the first pixel defining layer, an end portion of the second pixel defining layer, and an end portion of the third pixel defining layer do not overlap when viewed from a plane.

8. The display device according to claim 6, in, An end portion of the first pixel defining layer, an end portion of the second pixel defining layer, and an end portion of the third pixel defining layer overlap when viewed from a plane.

9. The display device according to claim 7, in, An end portion of the first spacer and an end portion of the third pixel defining layer do not overlap each other when viewed from a plane. The second separator width is smaller than the first separator width and the third separator width.

10. The display device according to claim 7, in, An end portion of the first spacer and an end portion of the third pixel defining layer do not overlap each other when viewed from a plane. The first spacer width, the second spacer width, and the third spacer width are the same as each other.

11. The display device according to claim 8, in, An end portion of the first spacer and an end portion of the third pixel defining layer do not overlap each other when viewed from a plane. The second separator width is smaller than the first separator width and the third separator width.

12. The display device according to claim 9, further comprising: include: The first electrode and the second electrode are arranged on the pixel circuit layer, The second electrode includes a 2-1 electrode arranged in the display area and a 2-2 electrode arranged in the non-display area. The 2-2 electrode is arranged on the partition wall.

13. The display device according to claim 12, in, The 2-2 electrode covers the pixel defining layer and side surfaces of the partition.

14. A method for manufacturing a display device, the display device comprising a display area where pixels are arranged and a non-display area which is an area outside the display area, the manufacturing method comprising the following steps: Depositing a basic pixel defining layer on the pixel circuit layers of the display area and the non-display area, and depositing a basic spacer on the basic pixel defining layer; and etching the base separator, in, The step of etching the base separator comprises the following steps: The base spacer is etched in such a manner that the base spacer disposed at the non-display area exposes at least a portion of the basic pixel defining layer.

15. The method for manufacturing a display device according to claim 14, in, The step of depositing the basic pixel defining layer comprises the following steps: depositing a first basic pixel defining layer on the pixel circuit layer, and depositing a second basic pixel defining layer on the first basic pixel defining layer, The step of depositing the base separator comprises the following steps: A first base spacer is deposited on the base pixel defining layer, and a second base spacer is deposited on the first base spacer.

16. The method for manufacturing a display device according to claim 15, in, The step of etching the base separator comprises the following steps: The etching is performed such that the first base spacer and the second base spacer have the same width as each other.

17. The method for manufacturing a display device according to claim 16, in, The step of etching the base separator also includes the following steps: The second base spacer is etched deeper than the first base spacer, Wherein, in the step of etching the base spacers, the first base spacers are formed to have a first spacer width, and the second base spacers are formed to have a second spacer width, and the second spacer width has a width smaller than the first spacer width.

18. The method for manufacturing a display device according to claim 16, further comprising the following steps: etching the base pixel defining layer, in, In the step of etching the basic pixel defining layer, a first pixel defining layer is formed by etching the first basic pixel defining layer in a manner having a first defining layer width, and a second pixel defining layer is formed by etching the second basic pixel defining layer in a manner having a second defining layer width smaller than the first defining layer width.

19. A method for manufacturing a display device, the display device comprising a display area where pixels are arranged and a non-display area which is an area outside the display area, the manufacturing method comprising the following steps: Depositing a basic pixel defining layer on the pixel circuit layers of the display area and the non-display area, and depositing a basic spacer on the basic pixel defining layer; etching the base spacer; and etching the base pixel defining layer, in, The step of depositing the basic pixel defining layer comprises the following steps: depositing a first basic pixel defining layer on the pixel circuit layer, and depositing a second basic pixel defining layer on the first basic pixel defining layer, The step of depositing the basic separator comprises the following steps: depositing a first base spacer on the base pixel defining layer, and depositing a second base spacer on the first base spacer, In which, in the step of etching the basic pixel defining layer, the first basic pixel defining layer is etched to form a first pixel defining layer having a first defining layer width, and the second basic pixel defining layer is etched to form a second pixel defining layer having a second defining layer width smaller than the first defining layer width, and an end portion of the first pixel defining layer and an end portion of the second pixel defining layer do not overlap each other when viewed from a plane.

20. The method for manufacturing a display device according to claim 19, In the step of etching the base separator, the first base separator is etched to form a first separator having a first separator width, and the second base separator is etched to form a second separator having a second separator width, wherein the second separator width is smaller than the first separator width. Each of the base spacer and the base pixel defining layer includes an inorganic material, The inorganic material includes one or more of the group consisting of silicon nitride and silicon oxide.

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