Display panel and display device

Abstract

The invention relates to a display panel and a display device. The display panel comprises a substrate; the driving circuit layer is located on one side of the substrate, the driving circuit layer comprises a first scanning signal line and a pixel circuit, and the first scanning signal line is used for outputting a first scanning signal to the pixel circuit; a first orthographic projection and a second orthographic projection of the first scanning signal line on the substrate are overlapped to form a parasitic capacitor in the pixel circuit; wherein the second orthographic projection comprises an orthographic projection of a target metal layer on the substrate, the target metal layer is connected with a gate part of a driving transistor in the pixel circuit, or the second orthographic projection comprises an orthographic projection of a target active layer on the substrate, and the target active layer is connected with a gate part of a driving transistor in the pixel circuit. And the target active layer is connected with a gate part of a driving transistor in the pixel circuit. The display panel provided by the invention has relatively good display performance.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a display panel and a display device. Background Art

[0002] As an important part of the information industry, display technology has played an important role in the development of information technology. With the development of display technology, organic light emitting diode display panels and other types of display panels have been widely used.

[0003] However, the display performance of the display panel in the related art is insufficient. Summary of the invention

[0004] Based on this, it is necessary to provide a display panel and a display device, aiming to improve the display performance of the display panel.

[0005] In a first aspect, the present application provides a display panel, the display panel comprising:

[0006] substrate;

[0007] A driving circuit layer, located on one side of the substrate, the driving circuit layer comprising a first scanning signal line and a pixel circuit, the first scanning signal line being used to output a first scanning signal to the pixel circuit; a first orthographic projection and a second orthographic projection of the first scanning signal line on the substrate overlap to form a parasitic capacitance in the pixel circuit;

[0008] The second orthographic projection includes an orthographic projection of a target metal layer on the substrate, and the target metal layer is connected to the gate portion of the driving transistor in the pixel circuit; or the second orthographic projection includes an orthographic projection of a target active layer on the substrate, and the target active layer is connected to the gate portion of the driving transistor in the pixel circuit.

[0009] In a second aspect, an embodiment of the present application further provides a display device, which includes the display panel provided in the first aspect.

[0010] The display panel and display device provided by the embodiments of the present application include a substrate, a driving circuit layer located on one side of the substrate, the driving circuit layer includes a first scanning signal line and a pixel circuit, the first scanning signal line is used to output a first scanning signal to the pixel circuit; a first orthographic projection of the first scanning signal line on the substrate overlaps with a second orthographic projection to form a parasitic capacitor in the pixel circuit, the second orthographic projection includes an orthographic projection of a target metal layer on the substrate, the target metal layer is connected to a gate portion of a driving transistor in the pixel circuit, or the second orthographic projection includes an orthographic projection of a target active layer on the substrate, the target active layer is connected to a gate portion of a driving transistor in the pixel circuit, by forming a parasitic capacitor between the first scanning signal line and the gate portion of the driving transistor, when the first scanning signal line controls the data writing process of the pixel circuit, the parasitic capacitor can pull up the potential of the gate of the driving transistor at the end of the data writing process, thereby reducing the driving current generated by the driving transistor in the light-emitting stage and reducing the brightness of the corresponding light-emitting element, so that the dark state requirement can be met at a smaller dark state voltage, so that the dark state voltage is reduced, and the display performance of the display panel is improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1 A schematic cross-sectional view of a display panel provided in an embodiment of the present application;

[0012] FIG2 is a schematic diagram of a layout structure of a pixel circuit provided in an embodiment of the present application;

[0013] Figure 3 A schematic diagram of the layout structure of another pixel circuit provided in an embodiment of the present application;

[0014] FIG4 is a schematic diagram of a layout structure of another pixel circuit provided in an embodiment of the present application;

[0015] FIG5 is a schematic diagram of a layout structure of another pixel circuit provided in an embodiment of the present application;

[0016] FIG6 is a schematic diagram of a layout structure of an active layer provided in an embodiment of the present application;

[0017] FIG7 is a schematic diagram of a layout structure of a first metal layer provided in an embodiment of the present application;

[0018] FIG8 is a schematic diagram of a layout structure of an interlayer insulation layer provided in an embodiment of the present application;

[0019] FIG9 is a schematic diagram of a layout structure of a second metal layer provided in an embodiment of the present application;

[0020] FIG10 is a schematic diagram of a layout structure of a third metal layer provided in an embodiment of the present application;

[0021] FIG11 is a schematic diagram of a layout structure of another interlayer insulation layer provided in an embodiment of the present application;

[0022] FIG12 is a schematic diagram of another layout structure of a second metal layer provided in an embodiment of the present application;

[0023] FIG13 is a schematic diagram of another layout structure of a third metal layer provided in an embodiment of the present application;

[0024] FIG14 is a schematic diagram of a layout structure of an organic planar layer provided in an embodiment of the present application;

[0025] FIG15 is a schematic diagram of a layout structure of a fourth metal layer provided in an embodiment of the present application;

[0026] FIG16 is a schematic diagram of another layout structure of an active layer provided in an embodiment of the present application;

[0027] FIG17 is a schematic diagram of the structure of a pixel circuit provided in an embodiment of the present application;

[0028] FIG18 is a schematic diagram of the structure of another pixel circuit provided in an embodiment of the present application;

[0029] FIG19 is a schematic diagram of the structure of another pixel circuit provided in an embodiment of the present application;

[0030] FIG20 is a schematic diagram of the structure of another pixel circuit provided in an embodiment of the present application;

[0031] FIG. 21 is a schematic diagram of the structure of a display device provided in an embodiment of the present application.

[0032] Explanation of the figure marks: 10-substrate, 20-driving circuit layer, 201-active layer, 202 first metal layer, 203-third metal layer, 204-second metal layer, 205-interlayer insulating layer, 206-organic flat layer, 207-fourth metal layer, 21-first scanning signal line, 22-gate part, 23-second scanning signal line, 24-third scanning signal line, 25-light-emitting control signal line, 31-first connecting part, 311-first sub-connecting part, 32-second connecting part, 321-second sub-connecting part. DETAILED DESCRIPTION

[0033] In order to facilitate the understanding of the present application, the present application will be described more fully below with reference to the relevant drawings. The preferred embodiments of the present application are provided in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the understanding of the disclosure of the present application more thorough and comprehensive.

[0034] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application. The term "and / or" used herein includes any and all combinations of one or more of the related listed items.

[0035] When describing positional relationships, unless otherwise specified, when an element such as a layer, film, or substrate is referred to as being "on" another element, it can be directly on the other element or there may be intervening elements. Further, when a layer is referred to as being "under" another layer, it can be directly under or there may be one or more intervening elements. It is also understood that when a layer is referred to as being "between" two layers, it can be the only layer between the two layers or there may be one or more intervening elements.

[0036] In the case of using “including”, “having”, and “comprising” described herein, another component may be added unless a clear limiting term such as “only”, “consisting of”, etc. is used. Unless mentioned otherwise, a term in the singular form may include a plural form and should not be understood as being one in number.

[0037] It should be understood that although the terms "first", "second", etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. For example, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element without departing from the scope of the present application.

[0038] It should also be understood that when interpreting an element, even if not explicitly described, the element is interpreted as including a range of error, which should be within the acceptable deviation range of the specific value determined by those skilled in the art. For example, "approximately", "approximately" or "substantially" can mean within one or more standard deviations, which are not limited here.

[0039] Furthermore, in the specification, the phrase “planar distribution schematic diagram” refers to a drawing when a target portion is viewed from above, and the phrase “cross-sectional schematic diagram” refers to a drawing when a section taken by vertically cutting the target portion is viewed from the side.

[0040] In addition, the drawings are not drawn to a 1:1 scale, and the relative sizes of the elements in the drawings are drawn only as examples and not necessarily according to the true scale.

[0041] As described in the background technology section, the pixel circuit in the related art will use the initialization signal to initialize the gate of the driving transistor in the initialization stage, and in the threshold compensation stage, the initial potential of the gate of the driving transistor is the potential of the initialization signal. The potential of the initialization signal is greatly different from the potential of the gate of the driving transistor when the threshold compensation is completed, resulting in a long time to complete the threshold compensation in the threshold compensation stage. For some high-resolution display panels, the number of pixel circuits in the display panel is large and the row cycle is short, resulting in a short charging time in the threshold compensation stage. For some low-frequency display panels, the storage capacitor in its pixel circuit has a large capacity and requires a long charging time. In summary, the display panel in the related art may have a short threshold compensation time and a low gate potential of the driving transistor. In the subsequent light-emitting stage, the low gate potential of the driving transistor will cause the driving current to be too large, and the large driving current will cause the light-emitting element to emit high brightness, so the dark state voltage of the light-emitting element will increase, thereby increasing the driving power consumption.

[0042] Based on the above technical problems, the inventors have found that by adding a parasitic capacitor in the pixel circuit that can pull up the gate potential of the driving transistor at the end of the threshold compensation process, the situation where the threshold compensation time is short and the gate potential of the driving transistor is low can be improved. Based on this, the inventors have further studied the technical solution of the embodiment of the present application. Specifically, the display panel provided in the embodiment of the present application includes a substrate, a driving circuit layer located on one side of the substrate, the driving circuit layer includes a first scanning signal line and a pixel circuit, the first scanning signal line is used to output a first scanning signal to the pixel circuit; the first orthographic projection of the first scanning signal line on the substrate overlaps with the second orthographic projection to form a parasitic capacitor in the pixel circuit; wherein the second orthographic projection includes an orthographic projection of the target metal layer on the substrate, and the target metal layer is connected to the gate portion of the driving transistor in the pixel circuit, or the second orthographic projection includes an orthographic projection of the target active layer on the substrate, and the target active layer is connected to the gate portion of the driving transistor in the pixel circuit. By adopting the above technical solution, a parasitic capacitor is formed between the first scanning signal line and the gate portion of the driving transistor. When the first scanning signal line controls the threshold compensation process of the pixel circuit, the parasitic capacitor can pull up the potential of the gate of the driving transistor at the end of the threshold compensation process, thereby reducing the driving current generated by the driving transistor in the light-emitting stage and reducing the brightness of the corresponding light-emitting element, thereby meeting the dark state requirements under a smaller dark state voltage, thereby reducing the dark state voltage and improving the display performance of the display panel.

[0043] The above is the core idea of ​​this application. The technical solutions in the embodiments of this application will be described clearly and completely below in conjunction with the drawings in the embodiments of this application. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0044] In an exemplary embodiment, see Figure 1 As shown in FIG. 5 , the present application provides a display panel, which includes a substrate 10 and a driving circuit layer 20 located on one side of the substrate 10, wherein the driving circuit layer 20 includes a first scanning signal line 21 and a pixel circuit, wherein the first scanning signal line 21 is used to output a first scanning signal to the pixel circuit. A first orthographic projection of the first scanning signal line 21 on the substrate 10 overlaps with a second orthographic projection to form a parasitic capacitance in the pixel circuit 30.

[0045] In an example, see Figures 1 to 3 The second orthographic projection may be an orthographic projection of the target active layer on the substrate 10 , and the target active layer is connected to the gate portion 23 of the driving transistor in the pixel circuit 30 .

[0046] In application, the driving circuit layer 20 may include an active layer 201, a first metal layer 202 and other film layers, wherein the active layer 201 is located on one side of the substrate 10, the first metal layer 202 is located on the side of the target active layer 201 away from the substrate 10, the second metal layer 203 is located on the side of the first metal layer 202 away from the substrate 10, and the target active layer may be the active layer 201. Figure 3 2 is a schematic diagram of the layout structure of the display panel when the first orthographic projection of the first scanning signal line 21 on the substrate 10 overlaps with the orthographic projection of the active layer 201 on the substrate 10. Specifically, FIG. 2 is a schematic diagram of the layout structure of the display panel when the active layer 201 and the first metal layer 202 are stacked. Figure 3 2 shows a schematic diagram of the layout structure of the display panel when the active layer 201, the first metal layer 202 and other film layers are stacked.

[0047] In FIG2 , the narrow-pitch diagonal pattern is a structure on the first metal layer 202, and the dot pattern is a structure on the active layer 201. It can be seen from FIG2 that the first scanning signal line 21 and the gate portion 22 of the driving transistor are respectively located in the first metal layer 202, and the first orthographic projection of the first scanning signal line 21 on the substrate 10 overlaps with the orthographic projection of the target active layer 201 on the substrate 10, thereby forming a parasitic capacitor C1 in the pixel circuit. The first electrode plate of the parasitic capacitor C1 is the structure in the active layer 201, and the second electrode plate of the parasitic capacitor C1 is the first scanning signal line 21. Please refer to Figure 3, the first plate of the parasitic capacitor C1 can be connected to the gate portion 22 of the driving transistor through other film layers. In applications, the first scanning signal line can be used to control the data writing process and / or the threshold compensation process of the pixel circuit. When the data writing process and / or the threshold compensation process is completed, the first scanning signal jumps from low to high, thereby raising the gate potential of the driving transistor, so that the driving current generated by the driving transistor in the light-emitting stage becomes smaller, and the brightness of the corresponding light-emitting element is reduced, so that the dark state requirement can be met at a smaller dark state voltage, so that the dark state voltage is reduced, and the display performance of the display panel is improved.

[0048] In another example, see Figure 1 4 and 5 , the second orthographic projection includes an orthographic projection of the target metal layer on the substrate 10 , and the gate portion 23 of the driving transistor in the pixel circuit of the target metal layer is connected.

[0049] It can be understood that the driving circuit layer 20 also includes a third metal layer 203, and the third metal layer 203 is located on the side of the first metal layer 201 away from the substrate 10, and the target metal layer can be the third metal layer 203. Figures 4 and 5 are schematic diagrams of the layout structure of the display panel when the first orthographic projection of the first scanning signal line 21 on the substrate 10 overlaps with the orthographic projection of the third metal layer 203 on the substrate 10. Specifically, Figure 4 is a schematic diagram of the layout structure of the display panel when the active layer 201, the first metal layer 202 and the third metal layer 203 are stacked, and Figure 5 shows a schematic diagram of the layout structure of the display panel when the active layer 201, the first metal layer 202, the third metal layer 203 and other film layers are stacked.

[0050] The wide-spaced twill pattern in FIG4 is a structure on the third metal layer 203. It can be seen that the orthographic projection of the third metal layer 203 on the substrate 10 overlaps with the first orthographic projection of the first scanning signal line 21 on the substrate 10, thereby forming a parasitic capacitor C1 in the pixel circuit. The first plate of the parasitic capacitor C1 is the structure in the third metal layer 203, and the second plate of the parasitic capacitor C1 is the first scanning signal line 21. Please refer to FIG5. The first plate of the parasitic capacitor C1 can be connected to the gate portion 22 of the driving transistor through other film layers. In application, the first scanning signal line can be used to control the data writing process and / or the threshold compensation process of the pixel circuit. When the data writing process and / or the threshold compensation process are completed, the first scanning signal jumps from low to high to increase the gate potential of the driving transistor, so that the driving current generated by the driving transistor in the light-emitting stage becomes smaller and the brightness of the corresponding light-emitting element is reduced, so that the dark state requirement can be met at a smaller dark state voltage, so that the dark state voltage is reduced, and the display performance of the display panel is improved.

[0051] A display panel provided by an embodiment of the present application includes a substrate, a driving circuit layer located on one side of the substrate, the driving circuit layer includes a first scanning signal line and a pixel circuit, the first scanning signal line is used to output a first scanning signal to the pixel circuit, the first scanning signal is used to control the data writing process of the pixel circuit; a first orthographic projection of the first scanning signal line on the substrate overlaps with a second orthographic projection to form a parasitic capacitor in the pixel circuit, the second orthographic projection includes an orthographic projection of a target metal layer on the substrate, the target metal layer is connected to the gate portion of the driving transistor in the pixel circuit, or the second orthographic projection includes an orthographic projection of a target active layer on the substrate, the target active layer is connected to the gate portion of the driving transistor in the pixel circuit, by forming a parasitic capacitor between the first scanning signal line and the gate portion of the driving transistor, when the first scanning signal line controls the data writing process of the pixel circuit, the parasitic capacitor can pull up the potential of the gate of the driving transistor at the end of the data writing process, so that the driving current generated by the driving transistor in the light-emitting stage becomes smaller and the brightness of the corresponding light-emitting element is reduced, so that the dark state requirement can be met at a smaller dark state voltage, so that the dark state voltage is reduced, and the display performance of the display panel is improved.

[0052] In an exemplary embodiment, please refer to Figures 1 to 3 The driving circuit layer 20 includes an active layer 201 , a first metal layer 202 and a first connecting portion 31 . The first metal layer 202 is located on a side of the active layer 201 away from the substrate 10 . The target active layer is the active layer 201 .

[0053] Among them, the first electrode of the parasitic capacitor C1 is located in the active layer 201, the first scanning signal line 21 and the gate portion 22 of the driving transistor in the pixel circuit are respectively located in the first metal layer 202, the first scanning signal line 21 is reused as the second electrode of the parasitic capacitor C1, and the first electrode of the parasitic capacitor C1 is connected to the gate portion 22 of the driving transistor through the first connecting portion 31.

[0054] It can be understood that the first scanning signal line 21 and the gate portion 22 of the driving transistor in the pixel circuit are both located in the first metal layer 202. In order to form a parasitic capacitor between the first scanning signal line 21 and the gate portion 22 of the driving transistor, a first plate of the parasitic capacitor C1 can be firstly added to the active layer 201, and the first scanning signal line 21 can be reused as the second plate of the parasitic capacitor C1 to form a parasitic capacitor C1. Then, the first plate of the parasitic capacitor C1 is connected to the gate portion 22 of the driving transistor through the first connecting portion 31, so that a parasitic capacitor C1 can be formed between the first scanning signal line 21 and the gate portion 22 of the driving transistor.

[0055] In an exemplary embodiment, see Figure 36 to 9, FIG. 6 is a schematic diagram of the layout structure of the active layer 201 in an example, FIG. 7 is a schematic diagram of the layout structure of the first metal layer 202 in an example, FIG. 8 is a schematic diagram of the layout structure of the interlayer insulating layer 205 in an example, and FIG. 9 is a schematic diagram of the layout structure of the second metal layer 204 in an example. The driving circuit layer 20 further includes a second metal layer 204 and an interlayer insulating layer 205, wherein the second metal layer 204 is located on a side of the first metal layer 202 away from the substrate, and the interlayer insulating layer 205 is located between the first metal layer 202 and the second metal layer 204.

[0056] The first connection portion 31 includes a first via h1, a second via h2, a fourth via h3, a fifth via h6 and a first sub-connection portion 311. The first sub-connection portion 313 is located in the second metal layer 204. The first via h1 is located in the active layer 201. The second via h2 is located in the first metal layer 202. The fourth via h3 and the fifth via h4 are respectively located in the interlayer insulating layer 205. The first sub-connection portion 313 further includes a sixth via h5, a seventh via h6 and a connection structure k1. The sixth via h5 and the seventh via h6 are respectively located at two ends of the connection structure k1. The orthographic projections of the first via h1, the fourth via h3 and the sixth via h5 on the substrate 10 at least partially overlap, and the orthographic projections of the second via h2, the fifth via h6 and the seventh via h6 on the substrate 10 at least partially overlap.

[0057] It can be seen from Figure 6 that the first electrode plate of the parasitic capacitor C1 is connected to the first via h1, and since the first via h1, the fourth via h3 and the sixth via h5 are connected, and the second via h2, the fifth via h6 and the seventh via h6 are connected, the first electrode plate of the parasitic capacitor C1 can be connected to the connecting structure k1 through the first via h1, the fourth via h3 and the sixth via h5, and the gate portion 22 of the driving transistor can be connected to the connecting structure k1 through the second via h2, the fifth via h6 and the seventh via h6, and then the first electrode plate of the parasitic capacitor C1 can be connected to the gate portion 22 of the driving transistor.

[0058] In an exemplary embodiment, referring to FIG. 2, FIG. 6 and FIG. 7, the first scanning signal line 21 at least includes a first sub-signal line 211 extending along a first direction, and the first electrode plate C11 of the parasitic capacitor C1 extends along the first direction. The length of the first electrode plate C11 in the first direction is less than the length of the first sub-signal line 211 in the first direction, and the width of the first electrode plate C11 in the second direction is greater than or equal to the width of the first sub-signal line 211 in the second direction. The first direction is the X-axis direction shown in the figure, and the second direction is the Y-axis direction shown in the figure, and the first direction and the second direction intersect.

[0059] It can be understood that the capacitance of a capacitor is proportional to the facing area between the two capacitor plates. In the present application, by controlling the length of the first plate C11 in the first direction to be smaller than the length of the first sub-signal line 211 in the first direction, it is possible to avoid the first plate C11 from exceeding the area of ​​the original layout structure. By controlling the width of the first plate C11 in the second direction to be greater than or equal to the width of the first sub-signal line 211 in the second direction, the capacitance of the parasitic capacitor C1 can be increased as much as possible, thereby improving the effect of reducing the dark state voltage.

[0060] In an exemplary embodiment, see Figure 1 4 and 5 , the driving circuit layer 20 includes a first metal layer 202 , a third metal layer 203 and a second connection portion 32 , the third metal layer 203 is located on a side of the first metal layer 202 away from the substrate 10 , and the target metal layer includes the third metal layer 203 .

[0061] Among them, the first plate of the parasitic capacitor C1 is located in the third metal layer 203, the first scanning signal line 21 and the gate portion 22 of the driving transistor in the pixel circuit are respectively located in the first metal layer, the first scanning signal line 21 is reused as the second plate of the parasitic capacitor, and the first plate of the parasitic capacitor C1 is connected to the gate portion of the driving transistor in the pixel circuit through the second connecting portion.

[0062] In this embodiment, the first scanning signal line 21 and the gate portion 22 of the driving transistor in the pixel circuit are both located in the first metal layer 202. In order to form a parasitic capacitor between the first scanning signal line 21 and the gate portion 22 of the driving transistor, a first plate of the parasitic capacitor C1 can be firstly provided in the third metal layer 203, and the first scanning signal line 21 can be reused as the second plate of the parasitic capacitor C1 to form a parasitic capacitor C1. Then, the first plate of the parasitic capacitor C1 is connected to the gate portion 22 of the driving transistor through the second connecting portion 32, so that a parasitic capacitor C1 can be formed between the first scanning signal line 21 and the gate portion 22 of the driving transistor.

[0063] In an exemplary embodiment, see Figure 1 4, 5, 7, 10 to 12, FIG. 10 is a schematic diagram of the layout structure of the third metal layer 203 in an example, FIG. 11 is a schematic diagram of the layout structure of the interlayer insulating layer 205 in an example, and FIG. 12 is a schematic diagram of the layout structure of the second metal layer 204 in an example. The driving circuit layer 20 also includes a second metal layer 204 and an interlayer insulating layer 205, the second metal layer 204 is located on the side of the third metal layer 203 away from the substrate, and the interlayer insulating layer 205 is located between the first metal layer 202 and the second metal layer 204, and is located on the side of the third metal layer 203 away from the substrate.

[0064] In this embodiment, the second connection portion 32 includes a second via h2, a third via h7, a fifth via h6, an eighth via h8, and a second sub-connection portion 321, the third via h7 is located in the third metal layer 203 and connected to the first plate of the parasitic capacitor, the second via h2 is located in the first metal layer 202 and connected to the gate portion 22 of the driving transistor, the fourth via h3, the fifth via h4, and the eighth via h8 are located in the interlayer insulating layer 205, the second sub-connection portion 321 is located in the second metal layer 204, and the second sub-connection portion 321 includes a sixth via h5, a seventh via h6, a ninth via h9, and a connection structure k1, the sixth via h5 and the seventh via h6 are located at two ends of the connection structure k1, respectively, and the ninth via h9 is located between the sixth via h5 and the seventh via h6. The orthographic projections of the third via h7, the eighth via h8, and the ninth via h9 on the substrate 10 at least partially overlap.

[0065] Please refer to FIG. 10. In order to form a parasitic capacitor C1 in the pixel circuit, a first plate C12 of the parasitic capacitor can be added in the third metal layer 203, and a third via h7 is provided to connect with the first plate C12 so that the first plate C12 can be connected to the structure in other film layers. In order to save layout space, the third via h7 and the first plate C12 at least partially overlap. For example, the octagonal structure in FIG. 10 is the third via h7, and the square structure is the first plate C12 of the parasitic capacitor. Since the third via h7, the eighth via h8 and the ninth via h9 are connected, the second via h2, the fifth via h6 and the seventh via h6 are connected. Therefore, the first plate of the parasitic capacitor C1 can be connected to the connection structure k1 through the third via h7, the eighth via h8 and the ninth via h9, and the gate portion 22 of the driving transistor can be connected to the connection structure k1 through the second via h2, the fifth via h6 and the seventh via h6, and then the first plate of the parasitic capacitor C1 can be connected to the gate portion 22 of the driving transistor.

[0066] In an exemplary embodiment, please continue to refer to Figures 4, 7 and 10, the first scanning signal line 21 at least includes a first sub-signal line 211 extending along the first direction, and the first electrode plate C12 of the parasitic capacitor extends along the first direction. The length of the first electrode plate C12 in the first direction is less than the length of the first sub-signal line 211 in the first direction, and the width of the first electrode plate C12 in the second direction is greater than or equal to the width of the first sub-signal line 211 in the second direction.

[0067] It can be understood that in the present application, by controlling the length of the first electrode plate C12 in the first direction to be smaller than the length of the first sub-signal line 211 in the first direction, it is possible to avoid the first electrode plate C12 exceeding the area of ​​the original layout structure, and by controlling the width of the first electrode plate C12 in the second direction to be greater than or equal to the width of the first sub-signal line 211 in the second direction, the capacitance of the parasitic capacitor C1 can be increased as much as possible, thereby improving the effect of reducing the dark state voltage.

[0068] In a detailed embodiment, please refer to Figures 1 to 3 6 to 9, and 13 to 15. The driving circuit layer 20 includes an active layer 201, a first metal layer 202, a third metal layer 203, an interlayer insulating layer 205, a second metal layer 204, an organic planar layer 206, and a fourth metal layer 207. The active layer 201 is located on one side of the substrate 10, the first metal layer 202 is located on a side of the active layer 201 away from the substrate 10, the third metal layer 203 is located on a side of the first metal layer 202 away from the substrate 10, the interlayer insulating layer 205 is located on a side of the first metal layer 202 and the third metal layer 203 away from the substrate 10, the second metal layer 204 is located on a side of the interlayer insulating layer 205 away from the substrate 10, the organic planar layer 206 is located on a side of the interlayer insulating layer 205 and the second metal layer 204 away from the substrate 10, and the fourth metal layer 207 is located on a side of the second metal layer 204 and the organic planar layer 206 away from the substrate 10.

[0069] FIG6 is a schematic diagram of the layout structure of the active layer 201 in this embodiment, FIG7 is a schematic diagram of the layout structure of the first metal layer 202 in this embodiment, FIG13 is a schematic diagram of the layout structure of the third metal layer 203 in this embodiment, FIG8 is a schematic diagram of the layout structure of the interlayer insulating layer 205 in this embodiment, FIG9 is a schematic diagram of the layout structure of the second metal layer 204 in this embodiment, FIG14 is a schematic diagram of the layout structure of the organic planar layer 206 in this embodiment, and FIG15 is a schematic diagram of the layout structure of the fourth metal layer 207 in this embodiment. By stacking the film layer structures in FIGS. 6 to 9 and 13 to 15, a Figure 3 The layout structure of the driving circuit layer is shown.

[0070] In this embodiment, by adding a capacitor plate C11 in the active layer 201, the first scanning signal line is multiplexed as another capacitor plate, thereby forming a parasitic capacitor C1 in the driving circuit layer. As can be seen from Figures 6 to 9, the active layer 201 has a first via hole h1, the first metal layer 202 has a second via hole h2, the interlayer insulating layer 205 has a fourth via hole h3 and a fifth via hole h4, the second metal layer 204 has a sixth via hole h5, a seventh via hole h6 and a connecting structure k1, the sixth via hole h5 and the seventh via hole h6 are respectively located at both ends of the connecting structure k1, the first via hole h1, the fourth via hole h3 and the sixth via hole h5 are connected, and the second via hole h2, the fifth via hole h6 and the seventh via hole h6 are connected. Therefore, the first plate C11 can be connected to the gate portion 22 of the driving transistor through the first via hole h1, the fourth via hole h3, the sixth via hole h5, the connecting structure k1, the second via hole h2, the fifth via hole h6 and the seventh via hole h6. Since the first scanning signal line is multiplexed as the second plate of the parasitic capacitor C1, one end of the parasitic capacitor C1 is used to receive the first scanning signal, and the first scanning signal is used to control the data writing or threshold compensation process of the pixel circuit. When the data writing or threshold compensation process is completed, the first scanning signal jumps from low to high, and since the potential at both ends of the capacitor remains relatively stable, when the first scanning signal jumps from low to high, the potential of the gate of the driving transistor will be pulled up, thereby reducing the driving current in the subsequent light-emitting stage, reducing the dark state voltage of the light-emitting element, reducing the driving power consumption, and improving the display performance.

[0071] In another detailed embodiment, please refer to Figure 1 4 and 5, Figures 10 to 12, and Figures 14 to 16. The driving circuit layer 20 includes an active layer 201, a first metal layer 202, a third metal layer 203, an interlayer insulating layer 205, a second metal layer 204, an organic planar layer 206, and a fourth metal layer 207. The active layer 201 is located on one side of the substrate 10, the first metal layer 202 is located on a side of the active layer 201 away from the substrate 10, the third metal layer 203 is located on a side of the first metal layer 202 away from the substrate 10, the interlayer insulating layer 205 is located on a side of the first metal layer 202 and the third metal layer 203 away from the substrate 10, the second metal layer 204 is located on a side of the interlayer insulating layer 205 away from the substrate 10, the organic planar layer 206 is located on a side of the interlayer insulating layer 205 and the second metal layer 204 away from the substrate 10, and the fourth metal layer 207 is located on a side of the second metal layer 204 and the organic planar layer 206 away from the substrate 10.

[0072] FIG. 16 is a schematic diagram of the layout structure of the active layer 201 in this embodiment, FIG. 7 is a schematic diagram of the layout structure of the first metal layer 202 in this embodiment, FIG. 10 is a schematic diagram of the layout structure of the third metal layer 203 in this embodiment, FIG. 11 is a schematic diagram of the layout structure of the interlayer insulating layer 205 in this embodiment, FIG. 12 is a schematic diagram of the layout structure of the second metal layer 204 in this embodiment, FIG. 14 is a schematic diagram of the layout structure of the organic planar layer 206 in this embodiment, and FIG. 15 is a schematic diagram of the layout structure of the fourth metal layer 207 in this embodiment. The layout structure of the driving circuit layer shown in FIG. 5 can be formed by stacking the film layer structures in FIG. 10 to FIG. 12 and FIG. 14 to FIG. 16.

[0073] In this embodiment, a capacitor plate C12 is added to the third metal layer 203, and the first scanning signal line is reused as another capacitor plate, thereby forming a parasitic capacitor C1 in the driving circuit layer. It can be seen from Figures 10 to 12 that the third metal layer 203 has a third via h7, the first metal layer 202 has a second via h2, the interlayer insulating layer 205 has a fourth via h3, a fifth via h4 and an eighth via h8, the second metal layer 204 has a sixth via h5, a seventh via h6, a ninth via h9 and a connecting structure k1, the sixth via h5 and the seventh via h6 are respectively located at the two ends of the connecting structure k1, the ninth via h9 is located between the sixth via h5 and the seventh via h6, the third via h7, the eighth via h8 and the ninth via h9 are connected, the second via h2, the fifth via h6 and the seventh via h6 are connected, therefore, the first electrode C12 can be connected to the gate portion 22 of the driving transistor through the third via h7, the eighth via h8, the ninth via h9, the connecting structure k1, the seventh via h6, the fifth via h6 and the second via h2. Since the first scanning signal line is multiplexed as the second plate of the parasitic capacitor C1, one end of the parasitic capacitor C1 is used to receive the first scanning signal, and the first scanning signal is used to control the data writing or threshold compensation process of the pixel circuit. When the data writing or threshold compensation process is completed, the first scanning signal jumps from low to high, and since the potential at both ends of the capacitor remains relatively stable, when the first scanning signal jumps from low to high, the potential of the gate of the driving transistor will be pulled up, thereby reducing the driving current in the subsequent light-emitting stage, reducing the dark state voltage of the light-emitting element, reducing the driving power consumption, and improving the display performance.

[0074] In an exemplary embodiment, referring to FIG. 17 , the pixel circuit includes a threshold compensation module 41 and a data writing module 42 .

[0075] The first end of the threshold compensation module 41 is connected to the second electrode of the driving transistor T0, the second end of the threshold compensation module 41 is respectively connected to the gate of the driving transistor T0 and the second end of the parasitic capacitor C1, and the control end of the threshold compensation module 41 is connected to the first scanning signal line 21 and the first end of the parasitic capacitor C1, for receiving the first scanning signal S1. The first end of the data writing module 42 is used to receive the data signal Vdata, the second end of the data writing module 42 is connected to the first electrode of the driving transistor T0, and the control end of the data writing module 42 is respectively connected to the first scanning signal line 21 and the first end of the parasitic capacitor C1, for receiving the first scanning signal S1.

[0076] The threshold compensation module 41 may include a first threshold compensation transistor T1-1 and a second threshold compensation transistor T1-2, and the data writing module 42 may include a data writing transistor T2, wherein the first electrode of the data writing transistor T2 is used to receive the data signal Vdata, the second electrode of the data writing transistor T2 is connected to the first electrode of the driving transistor T0, and the gate of the data writing transistor T2 is used to receive the first scanning signal. The first electrode of the first threshold compensation transistor T1-1 is connected to the second electrode of the driving transistor T0, the second electrode of the first threshold compensation transistor T1-1 is connected to the first electrode of the second threshold compensation transistor T1-2, the second electrode of the second threshold compensation transistor T1-2 is connected to the gate of the driving transistor T0, and the gates of the first threshold compensation transistor T1-1 and the second threshold compensation transistor T1-2 are used to receive the first scanning signal. The first electrode of the parasitic capacitor C1 is connected to the gate of the driving transistor T0, and the second electrode of the parasitic capacitor C1 is connected to the gate of the first threshold compensation transistor T1-1 and the gate of the second threshold compensation transistor T1-2.

[0077] The pixel circuit includes a data writing stage. In the data writing stage, the first scanning signal S1 is in a low level state, and the data writing transistor T2, the first threshold compensation transistor T1-1 and the second threshold compensation transistor T1-2 are turned on in response to the first scanning signal S1, so that the data signal Vdata is written into the gate of the driving transistor through the data writing transistor T2, the first threshold compensation transistor T1-1 and the second threshold compensation transistor T1-2; at the end of the data writing stage, the first scanning signal S1 jumps from low to high, thereby coupling the gate potential of the driving transistor to a high level, so that the driving current in the subsequent light-emitting stage is small, the dark state voltage of the light-emitting element D is reduced, the driving power consumption is reduced, and the display performance is improved.

[0078] In an exemplary embodiment, referring to Figures 7 and 18, the driving circuit layer 20 also includes a second scanning signal line 23, which is located on the first metal layer 202. The second scanning signal line 23 is used to output a second scanning signal S2 to the corresponding pixel circuit, and the second scanning signal S2 is used to control the initialization process of the gate of the driving transistor in the corresponding pixel circuit. The second scanning signal line 23 is located on the side of the first scanning signal line 21 away from the gate portion 22 of the driving transistor.

[0079] The pixel circuit includes a first initialization module 43, a first end of the first initialization module 43 is connected to the second end of the threshold compensation module 41 and the gate of the driving transistor T0, a second end of the first initialization module 43 is used to receive a first initialization signal Vref1, and a control end of the first initialization module 43 is connected to the second scanning signal line 23 for receiving a second scanning signal S2.

[0080] Among them, the first initialization module 43 may include a first initialization transistor T3-1 and a second initialization transistor T3-2, the first electrode of the first initialization transistor T3-1 is respectively connected to the gate of the driving transistor T0 and the second electrode of the second threshold compensation transistor T1-2, the second electrode of the first initialization transistor T3-1 is connected to the first electrode of the second initialization transistor T3-2, the second electrode of the second initialization transistor T3-2 is used to receive the first initialization signal Vref1, and the gates of the first initialization transistor T3-1 and the second initialization transistor T3-2 are used to receive the second scanning signal S2.

[0081] The pixel circuit also includes a first initialization stage, which is located before the data writing stage. In the first initialization stage, the second scanning signal S2 is in a low level state, the first scanning signal S1 is in a high level state, the first initialization transistor T3-1 and the second initialization transistor T3-2 are turned on in response to the second scanning signal S1, the data writing transistor T2, the first threshold compensation transistor T1-1 and the second threshold compensation transistor T1-2 are turned off in response to the first scanning signal S1, and the first initialization signal Vref1 is written into the gate of the driving transistor via the first initialization transistor T3-1 and the second initialization transistor T3-2 to initialize the gate of the driving transistor.

[0082] In other embodiments, the threshold compensation module 41 may include only one threshold compensation transistor, and the first initialization module 43 may include only one first initialization transistor.

[0083] In an exemplary embodiment, referring to Figures 7 and 19, the driving circuit layer also includes a third scanning signal line 24, which is used to output a third scanning signal S3. The third scanning signal is used to control the initialization process of the corresponding pixel circuit for the first electrode of the light-emitting element D. The third scanning signal line is located on the side of the gate portion of the driving transistor away from the first scanning signal line.

[0084] The pixel circuit further includes a second initialization module 44 , a bias adjustment module 45 and a storage module 46 .

[0085] The control end of the second initialization module 44 is used to receive the third scanning signal S3, the first end of the second initialization module 44 is used to receive the second initialization signal, and the second end of the second initialization module 44 is connected to the first electrode of the light-emitting element. The first end of the bias adjustment module 45 is used to receive the bias adjustment signal, the second end of the bias adjustment module 45 is respectively connected to the second end of the data writing module and the first electrode of the driving transistor, and the control end of the bias adjustment module 45 is used to receive the third scanning signal S3. The first end of the storage module 46 is used to receive the first power supply signal PVDD, and the second end of the storage module 46 is connected to the gate of the driving transistor.

[0086] The second initialization module 44 includes an initialization transistor T4, the gate of the initialization transistor T4 is used to receive the third scanning signal S3, the first electrode of the initialization transistor T4 is used to receive the second initialization signal, and the second electrode of the initialization transistor T4 is connected to the first electrode of the light-emitting element D. The first electrode of the bias adjustment transistor T5 is used to receive the bias adjustment signal, the second electrode of the bias adjustment transistor T5 is respectively connected to the second electrode of the data writing transistor T2 and the first electrode of the driving transistor T0, and the gate of the bias adjustment transistor T5 is used to receive the third scanning signal S3. The storage module 46 includes a storage capacitor Cst, the first electrode of the storage capacitor Cst is used to receive the first power supply signal PVDD, and the second electrode of the storage capacitor Cst is connected to the gate of the driving transistor.

[0087] The pixel circuit also includes a second initialization stage. In the second initialization stage, the initialization transistor T4 and the bias adjustment transistor T5 are turned on to initialize the first electrode of the light emitting element D and to bias the first electrode of the driving transistor respectively.

[0088] In an exemplary embodiment, referring to FIG. 7 and FIG. 20 , the driving circuit layer further includes a light-emitting control signal line 25, which is used to output a light-emitting control signal, and the light-emitting control signal is used to control the light-emitting of the corresponding light-emitting element, and the light-emitting control signal line is located between the third scanning signal line and the first scanning signal line.

[0089] The pixel circuit includes a light emitting control module 47, which includes a first light emitting control transistor T6 and a second light emitting control transistor T7. The first electrode of the first light emitting control transistor T6 is used to receive the first power supply signal PVDD, the second electrode of the first light emitting control transistor T6 is connected to the first electrode of the driving transistor T0, and the gate of the first light emitting control transistor T6 is used to receive the light emitting control signal EM. The first electrode of the second light emitting control transistor T7 is connected to the second electrode of the driving transistor T0, the second electrode of the second light emitting control transistor T7 is connected to the first electrode of the light emitting element D, and the gate of the second light emitting control transistor T7 is used to receive the light emitting control signal EM.

[0090] The pixel circuit includes a light-emitting stage, and the light-emitting control signal EM can be used to control the light-emitting element D to emit light. In the light-emitting stage, the first light-emitting control transistor T6 and the second light-emitting control transistor T7 are both turned on in response to the light-emitting control signal EM, and the driving transistor generates a driving current under the control of the gate voltage, and provides the driving current to the light-emitting element D in this stage. When the first light-emitting control transistor T6 and the second light-emitting control transistor T7 are both turned off in response to the light-emitting control signal EM, the driving transistor stops providing the driving current to the light-emitting element D.

[0091] Based on the same application concept, the embodiment of the present application also provides a display device. FIG21 is a schematic diagram of the structure of a display device 200 provided in an embodiment of the present application. As shown in FIG21 , the display device 20 includes a display panel 100 in any of the above embodiments. Exemplarily, as shown in FIG21 , the display device 200 includes a display panel 100. Therefore, the display device 200 also has the beneficial effects of the display panel 100 in the above embodiments. The similarities can be understood by referring to the above explanation of the display panel 100, which will not be repeated below.

[0092] The display device 200 provided in the embodiment of the present application can be the mobile phone shown in Figure 21, or it can be any electronic product with a display function, including but not limited to the following categories: televisions, laptops, desktop displays, tablet computers, digital cameras, smart bracelets, smart glasses, car displays, industrial control equipment, medical display screens, touch interactive terminals, etc. The embodiment of the present application does not make any special limitations on this.

[0093] The technical features of the above-described embodiments may be arbitrarily combined. To make the description concise, not all possible combinations of the technical features in the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0094] The above-mentioned embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the invention patent. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent of the present application shall be subject to the attached claims.

Claims

1. A display panel, characterized in that: The display panel comprises: substrate; A driving circuit layer, located on one side of the substrate, the driving circuit layer comprising a first scanning signal line and a pixel circuit, the first scanning signal line being used to output a first scanning signal to the pixel circuit; a first orthographic projection and a second orthographic projection of the first scanning signal line on the substrate overlap to form a parasitic capacitance in the pixel circuit; The second orthographic projection includes an orthographic projection of a target metal layer on the substrate, and the target metal layer is connected to the gate portion of the driving transistor in the pixel circuit; or the second orthographic projection includes an orthographic projection of a target active layer on the substrate, and the target active layer is connected to the gate portion of the driving transistor in the pixel circuit.

2. The display panel according to claim 1, characterized in that: The driving circuit layer includes an active layer, a first metal layer and a first connection portion, the first metal layer is located on a side of the active layer away from the substrate, and the target active layer includes the active layer; Among them, the first plate of the parasitic capacitor is located in the active layer, the first scanning signal line and the gate portion of the driving transistor in the pixel circuit are respectively located in the first metal layer, the first scanning signal line is multiplexed as the second plate of the parasitic capacitor, and the first plate of the parasitic capacitor is connected to the gate portion of the driving transistor through the first connecting portion.

3. The display panel according to claim 2, characterized in that: The driving circuit layer further comprises a second metal layer, and the second metal layer is located on a side of the first metal layer away from the substrate; The first connection portion includes a first via, a second via and a first sub-connection portion, the first sub-connection portion is located in the second metal layer, the first plate of the parasitic capacitor is connected to the first sub-connection portion through the first via, and the gate portion of the driving transistor in the pixel circuit is connected to the first sub-connection portion through the second via.

4. The display panel according to claim 2, characterized in that: The first scanning signal line at least includes a first sub-signal line extending along a first direction, and the first electrode plate of the parasitic capacitor extends along the first direction; Among them, the length of the first electrode in the first direction is smaller than the length of the first sub-signal line in the first direction, the width of the first electrode in the second direction is greater than or equal to the width of the first sub-signal line in the second direction; the first direction and the second direction intersect.

5. The display panel according to claim 1, characterized in that: The driving circuit layer includes a first metal layer, a third metal layer and a second connection portion, the third metal layer is located on a side of the first metal layer away from the substrate, and the target metal layer includes the third metal layer; Among them, the first plate of the parasitic capacitor is located in the third metal layer, the first scanning signal line and the gate part of the driving transistor in the pixel circuit are respectively located in the first metal layer, the first scanning signal line is multiplexed as the second plate of the parasitic capacitor, and the first plate of the parasitic capacitor is connected to the gate part of the driving transistor in the pixel circuit through the second connecting part.

6. The display panel according to claim 5, characterized in that: The driving circuit layer further comprises a second metal layer, and the second metal layer is located on a side of the third metal layer away from the substrate; The second connection portion includes a second via, a third via and a second sub-connection portion, the second sub-connection portion is located in the second metal layer, the first plate of the parasitic capacitor is connected to the second sub-connection portion through the third via, and the gate portion of the driving transistor in the pixel circuit is connected to the second sub-connection portion through the second via.

7. The display panel according to claim 5, characterized in that: The first scanning signal line at least includes a first sub-signal line extending along a first direction, and the first electrode plate of the parasitic capacitor extends along the first direction; Among them, the length of the first electrode in the first direction is smaller than the length of the first sub-signal line in the first direction, the width of the first electrode in the second direction is greater than or equal to the width of the first sub-signal line in the second direction; the first direction and the second direction intersect.

8. The display panel according to claim 1, characterized in that: The driving circuit layer also includes a second scanning signal line, which is used to output a second scanning signal to the corresponding pixel circuit, and the second scanning signal is used to control the initialization process of the gate of the driving transistor in the corresponding pixel circuit. The second scanning signal line is located on the side of the first scanning signal line away from the gate portion of the driving transistor.

9. The display panel according to claim 1, characterized in that: The driving circuit layer also includes a third scanning signal line, which is used to output a third scanning signal. The third scanning signal is used to control the initialization process of the first pole of the light-emitting element corresponding to the pixel circuit. The third scanning signal line is located on the side of the gate portion of the driving transistor away from the first scanning signal line.

10. The display panel according to claim 9, characterized in that: The driving circuit layer also includes a light-emitting control signal line, which is used to output a light-emitting control signal, and the light-emitting control signal is used to control the light emission of the corresponding light-emitting element. The light-emitting control signal line is located between the third scanning signal line and the first scanning signal line.

11. The display panel according to claim 1, characterized in that: The pixel circuit comprises: a threshold compensation module, wherein a first end of the threshold compensation module is connected to the second electrode of the driving transistor, a second end of the threshold compensation module is respectively connected to the gate of the driving transistor and the second end of the parasitic capacitor, and a control end of the threshold compensation module is connected to the first scanning signal line and the first end of the parasitic capacitor; A data writing module, wherein the first end of the data writing module is used to receive a data signal, the second end of the data writing module is connected to the first electrode of the driving transistor, and the control end of the data writing module is respectively connected to the first scanning signal line and the first end of the parasitic capacitor.

12. A display device, characterized in that: The invention comprises the display panel as claimed in any one of claims 1 to 11.

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