A gallium nitride device with enhanced heat dissipation through thermoelectric cooling and its fabrication method

Abstract

This invention discloses a GaN device with thermoelectric cooling for enhanced heat dissipation, primarily addressing the problem of drastic deterioration in output power density caused by self-heating and heat accumulation effects in existing GaN devices at high power. From bottom to top, it comprises a heat sink layer, a heat transfer interface layer, a substrate, a nucleation layer, a buffer layer, a channel layer, a barrier layer, and metal electrodes. Multiple thermoelectric cooling modules are arranged sequentially between the heat transfer interface layer and the substrate. Each thermoelectric cooling module includes a corresponding N-type thermoelectric material layer and a P-type thermoelectric material layer, with a series-patterned upper and lower metal electrode layer on its upper and lower surfaces, respectively, and is surrounded by an insulating support material. A substrate insulating layer is provided on the lower surface of the substrate to achieve electrical isolation between the substrate and the thermoelectric cooling modules. This invention reduces the device's thermal resistance, enhances heat conduction from the device substrate to the heat sink, and improves the device's heat dissipation capacity, making it applicable to GaN microwave power devices and power electronic devices.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor device technology, specifically relating to a GaN device and its fabrication method, which can be used as a microwave power device and a power electronic device. Background Technology

[0002] With the rapid advancement of microelectronics technology, GaN devices are finding increasingly widespread applications across various industries. Thanks to the high electron saturation velocity and mobility of GaN materials, its devices excel in power conversion and current handling, particularly in applications requiring high power and high frequency, such as power amplifiers and RF power devices, where they provide near-ideal solutions. Furthermore, GaN's wide bandgap and high breakdown voltage enable it to remain stable in high-temperature environments, making it ideal for extreme operating conditions and thus finding significant applications in critical sectors such as communications, energy, and defense. Looking ahead, with further technological advancements, GaN devices will continue to leverage their unique advantages, providing strong support for innovation in electronic technology and the expansion of its application areas.

[0003] Despite this, increasing market demand places higher demands on the performance and output power of GaN devices. The self-heating effect and extremely high power of GaN devices cause a rapid increase in internal heat flux within a short period, severely impacting their electrical performance and long-term stability. Simultaneously, the high thermal resistance and insufficient thermal conductivity of GaN materials limit the output power density and overall efficiency of GaN devices. Therefore, effective thermal management technologies are urgently needed to improve the electrical performance and reliability of these devices. Currently, there are four main technologies for optimizing the heat dissipation performance of GaN devices. First, using high thermal conductivity materials such as silicon carbide and diamond as GaN device substrates improves heat dissipation performance. However, the significant lattice mismatch between GaN and diamond affects the electrical performance of the device. Second, using substrate thinning technology reduces the heat transfer path, thereby improving device performance. However, excessively thin substrates increase the difficulty of subsequent processes, reducing the device yield. Third, high thermal conductivity materials such as nanocrystalline diamond and boron nitride are deposited on the surface of GaN devices as passivation layers. Simultaneously, flip-chip packaging technology is used to increase thermal conductivity while reducing heat transfer paths, thus improving the device's heat dissipation performance. However, directly growing high thermal conductivity materials on the device surface introduces additional stress, thereby reducing the device's electrical performance and potentially lowering reliability. Fourth, layout optimization is performed, adjusting the spacing between hotspots to reduce thermal crosstalk and mitigate self-heating effects. However, this increases the overall chip area and doesn't provide optimal heat dissipation. Fifth, microfluidic channels are integrated inside or on the device substrate to achieve active cooling with a coolant, improving heat dissipation efficiency. However, the coolant requires additional energy to transport, increasing the device's energy consumption.

[0004] Patent document CN202211287046.7 discloses a method and device for bonding a GaN layer on a diamond substrate, the device structure of which is as follows: Figure 5 As shown, this method uses a transfer method to bond GaN material and a diamond substrate together to fabricate the device, allowing the GaN device to directly utilize the high thermal conductivity of diamond for heat dissipation. However, this method is difficult to operate, has a low success rate, and is difficult to mass-produce. Furthermore, the significant lattice mismatch between GaN and materials such as diamond affects the electrical performance of the device.

[0005] Patent document with application number CN202010324599.X discloses a GaN semiconductor structure, device, and fabrication method with diamond microchannels. The device structure is as follows: Figure 6 As shown, a diamond film with a microfluidic structure is grown on the AlGaN back barrier layer. This improves the heat conduction of the substrate while allowing the coolant to directly contact the heat source of the device for heat dissipation, thus enhancing the device's heat dissipation performance. However, the growth temperature of diamond is extremely high, which can damage the grown GaN material at high temperatures, causing device failure. Furthermore, the coolant requires additional energy to transport, increasing the device's energy consumption. Summary of the Invention

[0006] The purpose of this invention is to address the shortcomings of the prior art by proposing a GaN device and its fabrication method that enhances heat dissipation through thermoelectric cooling. This avoids the additional stress and lattice mismatch caused by the contact between the GaN device surface and the high thermal conductivity material, reduces the additional power consumption of the device, and further optimizes the heat dissipation performance of the device.

[0007] The technical solutions for achieving the objectives of this invention include the following:

[0008] 1. A GaN device with thermoelectric cooling and enhanced heat dissipation, comprising, from bottom to top: a heat sink layer, a heat transfer interface layer, a substrate, a nucleation layer, a buffer layer, a channel layer, a barrier layer, and a metal electrode, characterized in that:

[0009] Multiple thermoelectric cooling modules are arranged sequentially between the heat transfer interface layer and the substrate. Each thermoelectric cooling module includes a corresponding N-type thermoelectric material layer and a P-type thermoelectric material layer. Its upper and lower surfaces are respectively provided with a series-patterned upper metal electrode layer and a lower metal electrode layer, which are used to connect the N-type thermoelectric material layer and the P-type thermoelectric material layer in series and apply voltage. Its periphery is wrapped with an insulating support material to support the deposition and patterning of the lower metal electrode layer and to achieve electrical isolation between adjacent thermoelectric cooling modules.

[0010] The lower surface of the substrate is provided with a substrate insulating layer to achieve electrical isolation between the substrate and the thermoelectric cooling module.

[0011] Furthermore, the N-type thermoelectric material layer in the thermoelectric cooling module is any one of Bi2Te3, Bi2(TeSe)3, PbTe, or other N-type materials with thermoelectric effect, with a thickness of 0.03 to 3000 μm and a side length of 60 to 200 μm;

[0012] The P-type thermoelectric material layer in the thermoelectric cooling module is any one of Sb2Te3, (BiSb)2Te3, Bi2Te3 or other P-type materials with thermoelectric effect, with a thickness of 0.03 to 3000 μm and a side length of 60 to 200 μm;

[0013] The spacing between the N-type thermoelectric material layer and the P-type thermoelectric material layer in a single thermoelectric refrigeration module is 10–20 μm, and the spacing between two adjacent thermoelectric refrigeration modules is 10–30 μm.

[0014] Furthermore, the patterned upper and lower metal electrode layers are made of Ni / Au, Au / Cu, Ni / Cu, or other metals that match the thermoelectric material, with a thickness of 40-100 / 200-2000 nm. They are used to apply voltage to the thermoelectric cooling module to form a current, thereby creating a temperature difference between the upper and lower surfaces of the thermoelectric cooling module and improving the heat dissipation capacity of the device.

[0015] The substrate insulating layer is made of SiO2 or Si3N4, and its thickness is 0.1 to 1 μm;

[0016] The insulating support material is any one of SiO2, Si3N4 or photoresist, and its thickness is the sum of the thickness of the upper metal electrode layer and the thermoelectric cooling module.

[0017] Furthermore, the heat transfer interface layer is made of any one of silicone, silicone grease, epoxy resin or phase change material, and its thickness is 1 to 500 μm, wherein the phase change material includes polyolefin resin and acrylic resin.

[0018] The heat sink layer is made of any one of copper alloy, aluminum alloy, high thermal conductivity metal or high thermal conductivity ceramic material, and its thickness is 0.1 to 10 mm. The copper alloy includes copper-tungsten alloy and copper-molybdenum alloy, the aluminum alloy includes aluminum-magnesium-silicon alloy and aluminum-silicon-carbon alloy, the high thermal conductivity metal includes W, Mo, Cu and Al, and the high thermal conductivity ceramic material includes SiC ceramic and AlN ceramic.

[0019] Furthermore, the substrate is made of Si or SiC with a thickness of 50–500 μm; the nucleation layer is made of AlN with a thickness of 20–200 nm; the buffer layer is made of any one of GaN, AlN, or AlGaN with a thickness of 0.1–5 μm; the channel layer is made of GaN with a thickness of 20–1000 nm; and the barrier layer is made of AlGaN with a thickness of 10–30 nm.

[0020] 2. A method for fabricating a GaN device with enhanced heat dissipation through electrothermal cooling, characterized by comprising the following steps:

[0021] S1: On the upper surface of the substrate, a nucleation layer, a buffer layer, a channel layer, and a barrier layer are sequentially epitaxially deposited by metal-organic chemical vapor deposition (MOCVD).

[0022] S2: Electrode metal is first deposited on the barrier layer by electron beam evaporation of E-Beam, and then ion implantation is performed to achieve device isolation;

[0023] S3: The surface of the barrier layer is connected to the external carrier wafer through a bonding process, and the lower surface of the substrate is pretreated by grinding and thinning and surface polishing.

[0024] S4: An insulating layer is deposited on the lower surface of the pretreated substrate by plasma-enhanced chemical vapor deposition (PECVD).

[0025] S5: Deposit a metal electrode layer on the substrate insulating layer by electron beam evaporation of E-Beam;

[0026] S6: An N-type thermoelectric material layer and a P-type thermoelectric material layer are deposited on the upper metal electrode layer by photolithography and metal-organic chemical vapor deposition (MOCVD) to form a thermoelectric cooling module.

[0027] S7: Insulating support material is deposited or spin-coated around the thermoelectric cooling module by plasma-enhanced chemical vapor deposition (PECVD).

[0028] S8: Deposit metal electrode layers on thermoelectric cooling modules and insulating support materials by electron beam evaporation of E-Beam;

[0029] S9: The heat sink material is bonded to the surface of the lower metal electrode layer using a heat transfer interface material, and the carrier wafer is removed to complete the device fabrication.

[0030] This invention has the following advantages over existing inventions:

[0031] 1) The present invention provides multiple thermoelectric cooling modules arranged in sequence between the substrate and the heat transfer interface layer, and applies voltage to the upper and lower metal electrode layers connecting the multiple thermoelectric cooling modules to generate current in the thermoelectric cooling modules, thereby generating a thermoelectric effect on the upper and lower surfaces of the thermoelectric cooling modules, reducing the temperature of the upper surface of the thermoelectric cooling modules, and improving the heat dissipation capacity of the device.

[0032] 2) By providing a substrate insulating layer between the upper metal electrode layer and the substrate, the present invention can achieve electrical isolation between the thermoelectric cooling module and the conductive channel, reduce substrate current leakage of the device, and improve the heat dissipation performance of the device while optimizing the electrical performance of the device.

[0033] 3) This invention achieves continuous low temperature on the device substrate side through the thermoelectric effect of the thermoelectric cooling module. Compared with passive cooling technologies such as high thermal conductivity substrate or passivation layer cooling, it can further increase the thermal conductivity of the device, while avoiding the additional stress and lattice mismatch caused by the direct contact of high thermal conductivity substrate or passivation layer with GaN device surface. It can achieve better heat dissipation and electrical performance of the device. At the same time, since the thermoelectric cooling technology used only requires applying voltage to the thermoelectric module, compared with existing active cooling technologies such as microchannel cooling technology, it greatly reduces the additional power consumption of the device.

[0034] 4) By directly integrating the thermoelectric cooling module heterogeneously on the back side of the substrate, this invention significantly shortens the heat conduction distance and reduces the thermal resistance of the device, which is beneficial for reducing the size and weight of the device. At the same time, by integrating the thermoelectric cooling module on the substrate, the thermal design of the subsequent device packaging can be simplified, reducing the complexity of device fabrication. While ensuring the stability and reliability of the device, it further improves its flexibility and overall performance. Attached Figure Description

[0035] Figure 1 This is a schematic diagram of the GaN HEMT structure for enhanced heat dissipation through thermoelectric cooling according to the present invention;

[0036] Figure 2 This is a schematic diagram of the process flow for fabricating GaN devices with enhanced thermoelectric cooling and heat dissipation according to the present invention.

[0037] Figure 3 This is a partial top view of the thermoelectric cooling module fabrication process at different steps in this invention.

[0038] Figure 4 This is a schematic diagram of the GaN SBD structure with enhanced heat dissipation and thermoelectric cooling fabricated according to Embodiment 3 of the present invention;

[0039] Figure 5 This is a schematic diagram of a device with a GaN layer bonded on a diamond substrate, as shown in patent document CN202211287046.7.

[0040] Figure 6 This is a schematic diagram of the structure of a GaN semiconductor device with diamond microchannels from the patent document with application number CN202010324599.X. Detailed Implementation

[0041] The present invention will be further described in detail below with reference to the accompanying drawings and embodiments.

[0042] Reference Figure 1 The GaN high electron mobility transistor (HEMT) with thermoelectric cooling enhanced heat dissipation of the present invention includes a heat sink layer 1, a heat transfer interface layer 2, a thermoelectric cooling module 3, a substrate insulating layer 41, a substrate 4, a nucleation layer 5, a buffer layer 6, a channel layer 7, a barrier layer 8, and a source electrode (S), a drain electrode (D), and a gate electrode (G). Wherein:

[0043] The substrate 4 is made of Si or SiC and has a thickness of 50 to 500 μm.

[0044] The nucleation layer 5 is made of AlN and has a thickness of 20-200 nm, and it is located on the substrate 4.

[0045] The buffer layer 6 is made of any one of GaN, AlN or AlGaN, with a thickness of 0.1 to 5 μm, and is located above the nucleation layer 5.

[0046] The channel layer 7 is made of GaN and has a thickness of 20–1000 nm, and it is located above the buffer layer 6.

[0047] The barrier layer 8 is made of AlGaN and has a thickness of 10-30 nm. It is located above the channel layer 7.

[0048] The source S and drain D are made of Ti / Au with a thickness of 10-80 / 70-200nm, and are located above the barrier layer 8; the gate G is made of Ni / Au with a thickness of 20-80 / 60-300nm, and is located between the source S and drain D, above the barrier layer 8.

[0049] The substrate insulating layer 41 is made of SiO2 or Si3N4 and has a thickness of 0.1 to 1 μm. It is located on the back side of the substrate 4.

[0050] The thermoelectric cooling modules 3 are multiple in number and arranged sequentially between the heat transfer interface layer and the substrate at a spacing of 10–30 μm. Each thermoelectric cooling module consists of a corresponding N-type thermoelectric material layer and a P-type thermoelectric material layer. The spacing between the N-type and P-type thermoelectric material layers is 10–20 μm. Each pair of N-type and P-type thermoelectric material layers has a series-patterned upper metal electrode layer 31 and a lower metal electrode layer 32 on its upper and lower surfaces, respectively, for connecting the N-type and P-type thermoelectric material layers in series and applying voltage. Each pair of N-type and P-type thermoelectric material layers is surrounded by an insulating support material 33 to support the deposition and patterning of the lower metal electrode layer 32, achieving electrical isolation between adjacent thermoelectric cooling modules 3.

[0051] The N-type thermoelectric material layer is made of any one of Bi2Te3, Bi2(TeSe)3, PbTe or other N-type materials with thermoelectric effect, with a thickness of 0.03 to 3000 μm and a side length of 60 to 200 μm, and is located on the upper surface of the heat transfer interface layer 2.

[0052] The P-type thermoelectric material layer is made of any one of Sb2Te3, (BiSb)2Te3, Bi2Te3 or other P-type materials with thermoelectric effect, with a thickness of 0.03 to 3000 μm and a side length of 60 to 200 μm; it is located on the lower surface of the substrate insulating layer 41.

[0053] The upper metal electrode layer 31 and the lower metal electrode layer 32 are both 240-2100 nm thick and are deposited using Ni / Au, Au / Cu, Ni / Cu or other metals that match the thermoelectric material.

[0054] The insulating support material 33 can be any one of SiO2, Si3N4 or photoresist, and its thickness is the sum of the thicknesses of the upper metal electrode layer 31 and the thermoelectric cooling module 3.

[0055] The heat transfer interface layer 2 is made of any one of silicone, silicone grease, epoxy resin or phase change material, with a thickness of 1 to 500 μm, and is located on the lower surface of the lower metal electrode layer.

[0056] The heat sink layer 1 is made of any one of copper alloy, aluminum alloy, high thermal conductivity metal or high thermal conductivity ceramic material, with a thickness of 0.1 to 10 mm, and is located on the lower surface of the heat transfer interface layer.

[0057] Reference Figure 2 The present invention provides the following three embodiments, but the implementation of the present invention is not limited thereto. Unless otherwise specified, the experimental methods described in the following embodiments are conventional methods; the reagents and materials described are commercially available unless otherwise specified.

[0058] Example 1: A GaN high electron mobility transistor (HEMT) with a thickness of 30 nm is fabricated, in which the N-type thermoelectric material layer is Bi2Te3, the P-type thermoelectric material layer is Sb2Te3, the buffer layer is GaN, and the thickness is 100 nm.

[0059] Step 1: Epitaxially deposit a group III nitride material on the front side of the Si substrate 4, such as... Figure 2 (a).

[0060] 1.1) Deposited AlN nucleation layer 5:

[0061] A 6-inch Si substrate with a thickness of 600 μm and a crystal orientation of

[111] was selected;

[0062] Using metal-organic chemical vapor deposition (MOCVD) technology, an AlN nucleation layer 5 with a thickness of 20 nm was epitaxially grown on the front side of Si substrate 4 under the process conditions of NH3 to TMAl flow rate ratio of 1000, temperature of 450℃, and growth pressure of 50 mbar.

[0063] 1.2) Deposition of GaN buffer layer 6:

[0064] Metal-organic chemical vapor deposition (MOCVD) was used to epitaxially grow a 100 nm thick layer of Fe doping at a doping concentration of 1 × 10⁻⁶ on an AlN nucleation layer 5 under the following process conditions: an NH₃ to TMGa flow rate ratio of 1500, a temperature of 900 °C, and a growth pressure of 50 mbar. 18 cm -3 GaN buffer layer 6;

[0065] 1.3) Deposited GaN channel layer 7:

[0066] Using metal-organic chemical vapor deposition (MOCVD) technology, under the process conditions of NH3 to TMGa flow rate ratio of 2000, temperature of 1000℃, and growth pressure of 150mbar, an unintentionally doped GaN channel layer 7 with a thickness of 20nm was epitaxially grown on GaN buffer layer 6.

[0067] 1.4) Deposition of AlGaN barrier layer 8:

[0068] Using metal-organic chemical vapor deposition (MOCVD) technology, an AlGaN barrier layer 8 with an Al composition of 0.25 and a thickness of 10 nm was epitaxially grown on the GaN channel layer 7 under the following process conditions: a flow rate ratio of NH3 to TMGa of 1000, a flow rate ratio of TMGa to TMAl of 4, a temperature of 800℃, and a growth pressure of 50 mbar.

[0069] Step 2: Deposit source (S), drain (D), and gate (G) metal electrodes on the surface of barrier layer 8, and perform ion implantation to achieve device isolation, such as... Figure 2 (b)

[0070] 2.1) Photolithography is performed on the surface of the barrier layer 8. That is, a layer of photoresist is first coated on the barrier layer, and then alignment, exposure, development and pattern detection are performed in sequence to form the source and drain regions of the device. Then, oxygen plasma is used to bombard the source and drain regions for 3 minutes to reduce the ohmic contact resistance of the source and drain regions.

[0071] 2.2) E-Beam was evaporated by electron beam, and the working chamber was evacuated to 2.0 × 10⁻⁶. -4 Under the process conditions of Pa, electron gun accelerating voltage of 6KV, electron gun beam current of 1A, and evaporation time of 80s, Ti / Au with a thickness of 10 / 70nm is deposited in the source and drain regions as source (S) and drain (D), and then the wafer is placed in photoresist stripping solution to remove photoresist.

[0072] 2.3) Place the wafer with the source and drain metals deposited above into an annealing furnace and anneal it rapidly for 50 seconds in a N2 atmosphere at a temperature of 800°C to form a high-quality ohmic contact at the interface between the source and drain metals and the barrier layer 8.

[0073] 2.4) The surface of the barrier layer 8 is photolithographically etched again to form the gate region, and the E-Beam is evaporated by electron beam evaporation. The vacuum level in the working chamber is then reduced to 2.0 × 10⁻⁶. -4 Under the process conditions of Pa, electron gun accelerating voltage of 6KV, electron gun beam current of 1A, and evaporation time of 80s, Ni / Au with a thickness of 20 / 60nm is deposited in the gate region as gate G to form a Schottky contact at the interface between the gate metal and the barrier layer 8. Then the wafer is placed in the photoresist stripping solution to remove the photoresist.

[0074] 2.5) Ion implantation technology was used, with an implantation energy of 200 keV and an ion concentration of 2 × 10⁻⁶. 14 cm -2 Under the specified process conditions, high-energy ion implantation is performed on the surface of the barrier layer 8 outside the active region of the wafer to complete device isolation.

[0075] Step 3: The surface of barrier layer 8 is bonded to the external carrier wafer using a bonding process, and the lower surface of substrate 4 is pretreated by grinding, thinning, and surface polishing, such as... Figure 2 (c)

[0076] 3.1) The surface of the barrier layer 8 of the device having a substrate 4, nucleation layer 5, buffer layer 6, channel layer 7, barrier layer 8 and source S, drain D and gate G is bonded to the sapphire wafer using bonding adhesive, and pressure is applied to the lower surface of the substrate 4 for temporary bonding.

[0077] 3.2) The lower surface of the Si substrate 4 of the device with temporary bonded sapphire carrier wafer is thinned by grinding to reduce its thickness to 50 μm;

[0078] 3.3) Polishing technology is used to polish the lower surface of the thinned Si substrate 4 to improve the surface smoothness and flatness of the wafer.

[0079] Step 4: Plasma-enhanced chemical vapor deposition (PECVD) was used, with SiH4 and N2O flow rates of 50 cm⁻¹. 3 / min, 160cm 3 Under the process conditions of 100 nm thick SiO2 substrate insulating layer 41, with a growth rate of 250 °C, a growth pressure of 80 Pa, and an RF power of 60 W, a SiO2 substrate insulating layer 41 was deposited on the back side of Si substrate 4. Figure 2 (d)

[0080] Step 5: Deposit a metal electrode layer 31 on the substrate insulating layer 41, such as... Figure 2 (e).

[0081] 5.1) Photolithography is performed on the surface of the substrate insulating layer 41, that is, a layer of photoresist is first coated on the substrate insulating layer 41, and then alignment, exposure, development, and pattern detection are performed in sequence to form the area where the metal electrode is deposited.

[0082] 5.2) E-Beam was evaporated by electron beam, and the working chamber was evacuated to 2.5 × 10⁻⁶. -4 Under the process conditions of Pa, electron gun accelerating voltage of 8KV, electron gun beam current of 1A, and evaporation time of 240s, Au / Ni with a thickness of 200 / 40nm is deposited as the upper metal electrode layer 31 in the region where the upper metal electrode is deposited. Then the wafer is placed in the photoresist stripping solution to remove the photoresist. Its top view is as shown in 3(a).

[0083] Step 6: Deposit the thermoelectric cooling module 3 on the upper metal electrode layer 31, such as... Figure 2 (f).

[0084] 6.1) Photolithography is performed on the surface of the upper metal electrode layer 31. That is, a layer of photoresist is first coated on the upper metal electrode layer 31, and then alignment, exposure, development and pattern detection are performed in sequence to form multiple regions for depositing N-type thermoelectric material. The side length of each region is 60μm and the spacing is 80μm.

[0085] 6.2) Using metal-organic chemical vapor deposition (MOCVD) technology, under the process conditions of a flow rate ratio of DipTe to TMBi of 2, a temperature of 200℃, and a growth pressure of 300mbar, a 30nm thick N-type Bi2Te3 layer was deposited in the region where N-type thermoelectric material was deposited as an N-type thermoelectric material layer. The wafer was then placed in a photoresist stripping solution to remove the photoresist.

[0086] 6.3) The surface of the upper metal electrode layer 31 is photolithographically etched again to form multiple regions for depositing P-type thermoelectric material. Each region has a side length of 60 μm and is 10 μm away from the adjacent N-type thermoelectric material layer.

[0087] 6.4) Using metal-organic chemical vapor deposition (MOCVD) technology, under the process conditions of a flow rate ratio of DipTe to TDSb of 1, a temperature of 250℃, and a growth pressure of 200mbar, a 30nm thick P-type Sb2Te3 layer is deposited in the region where P-type thermoelectric material is deposited as a P-type thermoelectric material layer. The wafer is then placed in a photoresist stripping solution to remove the photoresist, thus completing the fabrication of the thermoelectric cooling module 3, the top view of which is shown in 3(b).

[0088] Step 7: Deposit insulating support material 33 around the thermoelectric cooling module 3, such as... Figure 2 (g)

[0089] 7.1) Photolithography is performed again on the surface of the substrate insulating layer 41. That is, a layer of photoresist is first coated on the substrate insulating layer 41, and then alignment, exposure, development, and pattern detection are performed in sequence to form the area where the insulating support material is deposited.

[0090] 7.2) Plasma-enhanced chemical vapor deposition (PECVD) was used, with SiH4 and N2O flow rates of 80 cm⁻¹. 3 / min, 200cm 3 Under the process conditions of 100W / min, 300℃ temperature, 100Pa growth pressure, and 100W RF power, SiO2 is deposited in the area where the insulating support material is deposited until its height is flush with the thermoelectric cooling module as the insulating support material 33. Then the wafer is placed in the photoresist stripping solution to remove the photoresist. Its top view is as shown in 3(c).

[0091] Step 8: Deposit a metal electrode layer 32 on the thermoelectric cooling module 3 and the insulating support material 33, such as... Figure 2 (h).

[0092] 8.1) Photolithography is performed on the surfaces of the thermoelectric cooling module 3 and the insulating support material 33. That is, a layer of photoresist is first coated on the thermoelectric cooling module 3 and the insulating support material 33, and then alignment, exposure, development and pattern detection are performed in sequence to form the area of ​​the deposited metal electrode layer.

[0093] 8.2) E-Beam was evaporated by electron beam, with the working chamber evacuated to 2.5 × 10⁻⁶. -4 Under the process conditions of Pa, electron gun accelerating voltage of 8KV, electron gun beam current of 1A, and evaporation time of 240s, a Ni / Au layer with a thickness of 40 / 200nm is deposited as the lower metal electrode layer 32 in the region where the lower metal electrode is deposited. Then the wafer is placed in the photoresist stripping solution to remove the photoresist. Its top view is shaped as 3(d).

[0094] Step 9: Bond the heat sink layer 1 to the surface of the lower metal electrode layer 32 through the heat transfer interface layer 2, and remove the carrier wafer, as shown. Figure 2 (i).

[0095] 9.1) Using a spin coating process, silicone is dropped onto a copper-tungsten alloy heat sink 1 with a thickness of 0.1 mm, and then rotated at a speed of 4500 r / s for 40 s to obtain a silicone film with a thickness of 1 μm as the heat transfer interface layer 2. The surface of the lower metal electrode layer 32 is bonded to the silicone film, and then it is placed in an oven to cure the silicone film at 100℃ for 15 min to complete the heat sink connection.

[0096] 9.2) The sapphire substrate temporarily bonded to the surface of barrier layer 8 was removed using a debonding adhesive to complete the fabrication of the device.

[0097] Example 2: A GaN high electron mobility transistor (HEMT) with a back barrier structure is fabricated, in which the N-type thermoelectric material layer is Bi2(TeSe)3, the P-type thermoelectric material layer is (BiSb)2Te3 with a thickness of 30 μm, and the buffer layer is AlGaN with an Al composition of 0.05 and a thickness of 2 μm.

[0098] Step 1: Epitaxially deposit a group III nitride material on the front side of SiC substrate 4, such as... Figure 2 (a).

[0099] A 6-inch SiC substrate with a thickness of 600μm was selected.

[0100] With the process conditions set at a flow rate ratio of NH3 to TMAl of 1500, a temperature of 600℃, and a growth pressure of 150mbar, an AlN nucleation layer 5 with a thickness of 100nm was epitaxially grown on the front side of a SiC substrate 4 using metal-organic chemical vapor deposition (MOCVD).

[0101] With the process conditions set as follows: the flow rate ratio of NH3 to TMGa is 2500, the flow rate ratio of TMGa to TMAl is 20, the temperature is 950℃, and the growth pressure is 100mbar, an AlGaN buffer layer 6 is epitaxially grown on the AlN nucleation layer 5 using metal-organic chemical vapor deposition (MOCVD) technology. The Al composition is 0.05 and the thickness is 2μm.

[0102] With the process conditions set at a flow rate ratio of NH3 to TMGa of 2000, a temperature of 1000℃, and a growth pressure of 120mbar, an unintentionally doped GaN channel layer 7 with a thickness of 500nm was epitaxially grown on the AlGaN buffer layer 6 using metal-organic chemical vapor deposition (MOCVD).

[0103] With process conditions set at NH3 to TMGa flow rate ratio of 2000, TMGa to TMAl flow rate ratio of 4, temperature of 1100℃, and growth pressure of 150mbar, an AlGaN barrier layer 8 was epitaxially grown on the GaN channel layer 7 using metal-organic chemical vapor deposition (MOCVD) technology. The Al composition of the layer was 0.25, and the thickness was 20nm.

[0104] Step 2: Deposit source (S), drain (D), and gate (G) metal electrodes on the surface of barrier layer 8, and perform ion implantation to achieve device isolation, such as... Figure 2 (b)

[0105] Photolithography is performed on the surface of barrier layer 8. That is, a layer of photoresist is first coated on barrier layer 8, and then alignment, exposure, development, and pattern detection are performed in sequence to form the source and drain regions of the device. Then, oxygen plasma is used to bombard the source and drain regions for 4 minutes to reduce the ohmic contact resistance of the source and drain regions.

[0106] Set the vacuum level of the working chamber to 2.0 × 10⁻⁶. -4 Under the process conditions of Pa, electron gun accelerating voltage of 8KV, electron gun beam current of 0.5A, and evaporation time of 180s, Ti / Au with a thickness of 40 / 140nm was deposited in the source and drain regions as source (S) and drain (D) by electron beam evaporation of E-Beam. Then, the photoresist was removed by placing it in the photoresist stripping solution.

[0107] The wafer with the source and drain metals deposited above is placed in an annealing furnace, the furnace temperature is set to 830°C, and it is rapidly annealed in a N2 atmosphere for 40 seconds to form a high-quality ohmic contact at the interface between the source and drain metals and the barrier layer 8.

[0108] The gate region was formed again by photolithography on the surface of barrier layer 8, with the working chamber vacuum level set to 2.0 × 10⁻⁶. -4Under the process conditions of Pa, electron gun accelerating voltage of 8KV, electron gun beam current of 0.5A, and evaporation time of 240s, Ni / Au with a thickness of 60 / 180nm is deposited in the gate region as gate G by electron beam evaporation of E-Beam, so as to form Schottky contact at the interface between gate G and barrier layer 8, and then the photoresist is removed by immersing it in photoresist stripping solution.

[0109] The injection energy was set to 260 keV and the ion concentration to 5 × 10⁻⁶. 14 cm -2 Under the specified process conditions, ion implantation technology was used to perform high-energy ion implantation on the surface of the barrier layer 8 outside the active region of the wafer to complete device isolation.

[0110] Step 3: The surface of barrier layer 8 is bonded to the external carrier wafer using a bonding process, and the lower surface of substrate 4 undergoes pretreatment such as wafer thinning and surface polishing, as follows: Figure 2 (c)

[0111] The surface of the barrier layer 8 of the device, which has a substrate 4, a nucleation layer 5, a buffer layer 6, a channel layer 7, a barrier layer 8, and a source S, a drain D, and a gate G, is bonded to the sapphire wafer using bonding adhesive, and pressure is applied to the lower surface of the substrate 4 for temporary bonding.

[0112] The SiC substrate 4 of the device with temporary bonded sapphire carrier wafer is thinned by grinding to reduce its thickness to 250 μm;

[0113] The lower surface of the thinned SiC substrate 4 is polished to improve the surface smoothness and flatness of the wafer.

[0114] Step 4: Set the flow rates of SiH4 and NH3 to 20 cm⁻¹. 3 / min, 15cm 3 Under the process conditions of 300℃, 120Pa growth pressure, and 300W RF power, a 500nm thick Si3N4 substrate insulating layer 41 was deposited on the back side of SiC substrate 4 via plasma-enhanced chemical vapor deposition (PECVD). Figure 2 (d)

[0115] Step 5: Deposit a metal electrode layer 31 on the substrate insulating layer 41, such as... Figure 2 (e).

[0116] Photolithography is performed on the surface of the substrate insulating layer 41, that is, a layer of photoresist is first coated on the substrate insulating layer 41, and then alignment, exposure, development, and pattern detection are performed in sequence to form the area where the metal electrode is deposited.

[0117] Set the vacuum level of the working chamber to 2.5 × 10⁻⁶. -4Under the process conditions of Pa, electron gun accelerating voltage of 9KV, electron gun beam current of 0.7A, and evaporation time of 1200s, Cu / Au with a thickness of 1000 / 80nm was deposited as the upper metal electrode layer 31 in the region where the upper metal electrode was deposited by electron beam evaporation of E-Beam. Then the wafer was placed in the photoresist stripping solution to remove the photoresist, and its top view is as shown in 3(a).

[0118] Step Six: Deposit the thermoelectric cooling module 3 on the upper metal electrode layer 31, such as... Figure 2 (f).

[0119] Photolithography is performed on the surface of the upper metal electrode layer 31. That is, a layer of photoresist is first coated on the upper metal electrode layer 31, and then alignment, exposure, development and pattern detection are performed in sequence to form multiple regions for depositing N-type thermoelectric material. Each region has a side length of 120μm and a spacing of 155μm.

[0120] The process conditions were set as follows: the flow rate ratio of DipTe to TMBi was 5, the flow rate ratio of DipTe to DESe was 2, the temperature was 420℃, and the growth pressure was 400mbar. Using metal-organic chemical vapor deposition (MOCVD), a 30μm thick N-type Bi2(TeSe)3 layer was deposited as the N-type thermoelectric material layer in the region where N-type thermoelectric material was deposited. The wafer was then placed in a photoresist stripping solution to remove the photoresist.

[0121] The surface of the upper metal electrode layer 31 is photolithographically etched again to form multiple regions for depositing P-type thermoelectric material. Each region has a side length of 120 μm and is 15 μm away from the nearest adjacent N-type thermoelectric material layer and 20 μm away from the farthest adjacent N-type thermoelectric material layer.

[0122] The process conditions were set as follows: the flow rate ratio of DipTe to TMBi was 4, the flow rate ratio of TMBi to TDSb was 2, the temperature was 350℃, and the growth pressure was 400mbar. Using metal-organic chemical vapor deposition (MOCVD), a 30μm thick layer of P-type (BiSb)2Te3 was deposited as the P-type thermoelectric material layer in the region where P-type thermoelectric material was deposited. The wafer was then placed in a photoresist stripping solution to remove the photoresist, thus completing the fabrication of the thermoelectric cooling module 3, whose top view is shown in 3(b).

[0123] Step 7: Deposit insulating support material 33 around the thermoelectric cooling module 3, such as... Figure 2 (g)

[0124] The surface of the substrate insulating layer 41 is photolithographically ...

[0125] The flow rates of SiH4 and NH3 were set to 30 cm⁻¹. 3 / min, 20cm 3 Under the process conditions of 400℃, 150Pa growth pressure, and 500W RF power, Si3N4 was deposited in the area where the insulating support material was deposited until its height was flush with that of the thermoelectric cooling module 3, using plasma enhanced chemical vapor deposition (PECVD) technology. The wafer was then placed in a photoresist stripping solution to remove the photoresist, and its top view is shown in 3(c).

[0126] Step 8: Deposit a metal electrode layer 32 on the thermoelectric cooling module 3 and the insulating support material 33, such as... Figure 2 (h).

[0127] Photolithography is performed on the surfaces of the thermoelectric cooling module 3 and the insulating support material 33. That is, a layer of photoresist is first coated on the thermoelectric cooling module 3 and the insulating support material 33, and then alignment, exposure, development and pattern detection are performed in sequence to form the area of ​​the deposited metal electrode layer.

[0128] Set the vacuum level of the working chamber to 2.5 × 10⁻⁶. -4 Under the process conditions of Pa, electron gun accelerating voltage of 9 kV, electron gun beam current of 0.7 A, and evaporation time of 1200 s, E-Beam is evaporated by electron beam to deposit Au / Cu with a thickness of 80 / 1000 nm as the lower metal electrode layer 32 in the region where the lower metal electrode is deposited. Then the wafer is placed in the photoresist stripping solution to remove the photoresist. Its top view is shaped as 3(d).

[0129] Step 9: Bond the heat sink layer 1 to the surface of the lower metal electrode layer 32 through the heat transfer interface layer 2, and remove the carrier wafer, as follows. Figure 2 (i).

[0130] Using a spin coating process, epoxy resin is dropped onto an aluminum-silicon-carbon alloy heat sink 1 with a thickness of 1 mm, and then rotated at a speed of 4000 r / s for 40 s to obtain an epoxy resin film with a thickness of 20 μm as the heat transfer interface layer 2. The surface of the lower metal electrode layer 32 is bonded to the epoxy resin film, and then it is placed in an oven to cure the epoxy resin film at 150℃ for 20 min to complete the heat sink connection.

[0131] The sapphire substrate temporarily bonded to the surface of the barrier layer was removed using a debonding adhesive to complete the device fabrication.

[0132] Example 3: A GaN Schottky diode (SBD) with an N-type thermoelectric material layer of PbTe, a P-type thermoelectric material layer of Bi2Te3, a thickness of 300 μm, a buffer layer of AlN, and a thickness of 5 μm was fabricated in the thermoelectric cooling module.

[0133] Step A: Epitaxially deposit a group III nitride material on the front side of SiC substrate 4.

[0134] A 6-inch SiC substrate with a thickness of 600μm was selected.

[0135] A1) An AlN nucleation layer 5 with a thickness of 200 nm was epitaxially grown on the front side of a SiC substrate 4 using metal-organic chemical vapor deposition (MOCVD) technology. The MOCVD process conditions are as follows:

[0136] The flow rate ratio of NH3 to TMAl is 2500.

[0137] The temperature is 600℃.

[0138] The growth pressure is 100 mbar;

[0139] A2) An AlN buffer layer 6 with a thickness of 5 μm was epitaxially grown on the AlN nucleation layer 5 using metal-organic chemical vapor deposition (MOCVD) technology. The MOCVD process conditions are as follows:

[0140] The flow rate ratio of NH3 to TMAl is 3000.

[0141] The temperature is 750℃.

[0142] The growth pressure is 250 mbar;

[0143] A3) Using metal-organic chemical vapor deposition (MOCVD), a 1000 nm thick, unintentionally doped GaN channel layer 7 was epitaxially grown on the AlN buffer layer 6. The MOCVD process conditions are as follows:

[0144] The flow rate ratio of NH3 to TMGa is 2500.

[0145] The temperature is 1100℃.

[0146] The growth pressure is 200 mbar;

[0147] A4) An AlGaN barrier layer 8 with an Al composition of 0.25 and a thickness of 30 nm was epitaxially grown on the GaN channel layer 7 using metal-organic chemical vapor deposition (MOCVD) technology. The MOCVD process conditions are as follows:

[0148] The flow rate ratio of NH3 to TMGa is 2000.

[0149] The flow rate ratio of TMGa to TMAl is 4.

[0150] The temperature is 1100℃.

[0151] The growth pressure is 150 mbar.

[0152] Step B: Deposit cathode and anode metal electrodes on the surface of barrier layer 8 and perform ion implantation to achieve device isolation.

[0153] B1) Photolithography is performed on the surface of the barrier layer 8. That is, a layer of photoresist is first coated on the barrier layer 8, and then alignment, exposure, development, and pattern detection are performed in sequence to form the cathode region of the device. Then, oxygen plasma is used to bombard the cathode region for 5 minutes to reduce the ohmic contact resistance of the cathode region.

[0154] B2) E-Beam is evaporated by electron beam to deposit a Ti / Au layer with a thickness of 80 / 200 nm as the cathode in the cathode region. The wafer is then placed in a photoresist stripping solution to remove the photoresist. The process conditions for electron beam evaporation of E-Beam are as follows:

[0155] The vacuum level of the work chamber is 2.0 × 10⁻⁶. -4 Pa,

[0156] The electron gun accelerating voltage is 10 kV.

[0157] The electron gun beam current is 0.2A.

[0158] The evaporation time is 280 seconds;

[0159] B3) Place the cathode metal deposition wafer into an annealing furnace and anneal it rapidly for 35 seconds in a N2 environment at a furnace temperature of 860°C to form an ohmic contact at the contact surface between the cathode and the barrier layer 8.

[0160] B4) The surface of the barrier layer 8 is photolithographically etched again to form the anode region. E-Beam is evaporated by electron beam to deposit Ni / Au with a thickness of 80 / 300nm as the anode, so as to form a Schottky contact at the interface between the anode and the barrier layer 8. The wafer is then placed in the photoresist stripping solution to remove the photoresist. The process conditions for electron beam evaporation of E-Beam are as follows:

[0161] The vacuum level of the work chamber is 2.0 × 10⁻⁶. -4 Pa,

[0162] The electron gun accelerating voltage is 10 kV.

[0163] The electron gun beam current is 0.2A.

[0164] The evaporation time is 380 seconds.

[0165] B5) Ion implantation technology is used to perform high-energy ion implantation on the surface of the barrier layer 8 outside the active region of the wafer to complete device isolation. The ion implantation process conditions are as follows:

[0166] The injected energy is 320 keV.

[0167] The ion concentration is 8×10 14 cm -2 .

[0168] Step C: Connect the surface of the barrier layer 8 to the external carrier wafer through a bonding process, and perform pretreatment of the lower surface of the substrate 4 by grinding and thinning and surface polishing.

[0169] C1) The surface of the barrier layer 8 of the device, which has a substrate 4, a nucleation layer 5, a buffer layer 6, a channel layer 7, a barrier layer 8, and a cathode and an anode, is bonded to the sapphire wafer using bonding adhesive, and pressure is applied to the lower surface of the substrate 4 for temporary bonding.

[0170] C2) The SiC substrate 4 of the device with temporary bonded sapphire carrier wafer is thinned by grinding to reduce its thickness to 350 μm;

[0171] C3) Polishing technology is used on the lower surface of the thinned SiC substrate to improve the smoothness and flatness of the wafer surface.

[0172] Step D: A 1 μm thick Si3N4 substrate insulating layer 41 is deposited on the back side of the SiC substrate 4 by plasma-enhanced chemical vapor deposition (PECVD). The PECVD process conditions are as follows:

[0173] The flow rates of SiH4 and NH3 were 30 cm⁻¹. 3 / min, 20cm 3 / min,

[0174] The temperature is 400℃.

[0175] The growth pressure is 150 Pa.

[0176] The radio frequency power is 500W.

[0177] Step E: Deposit a metal electrode layer 31 on the substrate insulating layer 41.

[0178] E1) Photolithography is performed on the surface of the substrate insulating layer 41, that is, a layer of photoresist is first coated on the substrate insulating layer 41, and then alignment, exposure, development, and pattern detection are performed in sequence to form the area where the metal electrode is deposited.

[0179] E2) By electron beam evaporation of E-Beam, a Cu / Ni layer with a thickness of 2000 / 100 nm is deposited as the upper metal electrode layer 31 in the region where the upper metal electrode is deposited. The wafer is then immersed in a photoresist stripping solution to remove the photoresist. The process conditions for electron beam evaporation of E-Beam are as follows:

[0180] The vacuum level of the working chamber is 2.5 × 10⁻⁶. -4 Pa,

[0181] The electron gun accelerating voltage is 10 kV.

[0182] The electron gun beam current is 0.5A.

[0183] The evaporation time is 2100s.

[0184] Step F: Deposit the thermoelectric cooling module 3 on the upper metal electrode layer 31.

[0185] F1) Photolithography is performed on the surface of the upper metal electrode layer 31. That is, a layer of photoresist is first coated on the upper metal electrode layer 31, and then alignment, exposure, development and pattern detection are performed in sequence to form multiple regions for depositing N-type thermoelectric material. The side length of each region is 200μm and the spacing is 250μm.

[0186] F2) Using metal-organic chemical vapor deposition (MOCVD), a 300 μm thick N-type PbTe layer is deposited as the N-type thermoelectric material layer in the region where N-type thermoelectric material is deposited. The wafer is then immersed in a photoresist stripping solution to remove the photoresist. The MOCVD process conditions are as follows:

[0187] The flow rate ratio of DipTe to TEL is 2.

[0188] The temperature is 400℃.

[0189] The growth pressure is 450 mbar;

[0190] F3) The surface of the upper metal electrode layer 31 is photolithographically etched again to form multiple regions for depositing P-type thermoelectric material. Each region has a side length of 200 μm and is 20 μm away from the nearest adjacent N-type thermoelectric material layer and 30 μm away from the farthest adjacent N-type thermoelectric material layer.

[0191] F4) Using metal-organic chemical vapor deposition (MOCVD), a 300 μm thick P-type Bi₂Te₃ layer is deposited as the P-type thermoelectric material layer in the region where N-type thermoelectric material is deposited. The wafer is then immersed in a photoresist stripping solution to remove the photoresist, thus completing the fabrication of thermoelectric cooling module 3. The MOCVD process conditions are as follows:

[0192] When the flow rate ratio of DipTe to TMBi is 6,

[0193] The temperature is 500℃.

[0194] The growth pressure is 600 mbar.

[0195] Step G: Deposit insulating support material 33 around the thermoelectric cooling module 3.

[0196] G1) Photolithography is performed on the surface of the substrate insulating layer 41. A layer of photoresist is first coated on the substrate insulating layer 41 using spin coating technology. Then, alignment, exposure, development, and pattern detection are performed sequentially. In the area where the insulating support material needs to be deposited, the photoresist with a height flush with the thermoelectric cooling module is retained as the insulating support material. The spin coating process conditions are as follows:

[0197] The rotational speed is 2000 r / s.

[0198] Spin coating time is 35 seconds;

[0199] G2) The wafer with the completed insulating support material 33 deposition is subjected to hard baking to prevent the photoresist from dissolving in the photoresist stripping solution or other etching solvents used subsequently. The hard baking process conditions are as follows:

[0200] The baking temperature is 240℃.

[0201] Baking time is 10 minutes.

[0202] Step H: Deposit a metal electrode layer on the thermoelectric cooling module 3 and the insulating support material 33.

[0203] H1) Photolithography is performed on the surfaces of the thermoelectric cooling module 3 and the insulating support material 33. That is, a layer of photoresist is first coated on the thermoelectric cooling module 3 and the insulating support material 33, and then alignment, exposure, development and pattern detection are performed in sequence to form the area of ​​the deposited metal electrode layer 32.

[0204] H2) By electron beam evaporation of E-Beam, a Ni / Cu layer with a thickness of 100 / 2000 nm is deposited as the lower metal electrode layer 32 in the region where the lower metal electrode is deposited. The wafer is then placed in a photoresist stripping solution to remove the photoresist. The process conditions for electron beam evaporation of E-Beam are as follows:

[0205] The vacuum level of the working chamber is 2.5 × 10⁻⁶. -4 Pa,

[0206] The electron gun accelerating voltage is 10 kV.

[0207] The electron gun beam current is 0.5A.

[0208] The evaporation time is 2100s.

[0209] Step I: The heat sink layer 1 is bonded to the surface of the lower metal electrode layer 32 through the heat transfer interface layer 2, and the carrier wafer is removed.

[0210] I1) Using a spin coating process, polyolefin resin is dropped onto a 5mm thick AlN ceramic heat sink 1 and then rotated at 3000r / s for 30s to obtain a 100μm thick polyolefin resin film as the heat transfer interface layer 2. The surface 32 of the lower metal electrode layer and the polyolefin resin film are bonded together. Then, the polyolefin resin film is placed in an oven and cured at 250℃ for 25min to complete the heat sink connection.

[0211] I2) The sapphire substrate temporarily bonded to the surface of the barrier layer is removed using a debonding adhesive to obtain a GaN Schottky diode (SBD), such as... Figure 4 As shown.

[0212] The above descriptions are merely three specific examples of the present invention and do not constitute any limitation on the present invention. Obviously, those skilled in the art, after understanding the content and principles of the present invention, may make various modifications and changes in form and detail without departing from the principles and results of the present invention. For example, in addition to copper-tungsten alloys, aluminum-silicon-carbon alloys, aluminum-silicon-carbon alloys, and AlN ceramics, the heat sink layer can also use copper-molybdenum alloys, aluminum-magnesium-silicon alloys, SiC ceramics, and metals with high thermal conductivity; in addition to Bi2Te3 / Sb2Te3, Bi2(TeSe)3 / (BiSb)2Te3, and PbTe / Bi2Te3, other materials with thermoelectric effects can also be used in the thermoelectric cooling module; in addition to Au / Cu, Ni / Cu, and Ni / Au, other metals that match the thermoelectric materials can also be used in the upper and lower metal electrode layers. However, these modifications and changes based on the ideas of the present invention are still within the scope of protection of the claims of the present invention.

Claims

1. A GaN device with thermoelectric cooling and enhanced heat dissipation, comprising, from bottom to top: a heat sink layer (1), a heat transfer interface layer (2), a substrate (4), a nucleation layer (5), a buffer layer (6), a channel layer (7), a barrier layer (8), and a metal electrode, characterized in that: The heat transfer interface layer (2) and the substrate (4) are provided with a plurality of thermoelectric cooling modules (3) arranged in sequence. Each thermoelectric cooling module includes an N-type thermoelectric material layer and a P-type thermoelectric material layer corresponding to each other. The upper and lower surfaces of each module are respectively provided with a series-patterned upper metal electrode layer (31) and a lower metal electrode layer (32) for connecting the N-type thermoelectric material layer and the P-type thermoelectric material layer in series and applying voltage. The outer periphery is wrapped with an insulating support material (33) to support the deposition and patterning of the lower metal electrode layer (32) and to achieve electrical isolation between adjacent thermoelectric cooling modules (3). The substrate (4) has a substrate insulating layer (41) on its lower surface to achieve electrical isolation between the substrate (4) and the thermoelectric cooling module (3).

2. The device according to claim 1, characterized in that: The N-type thermoelectric material layer in the thermoelectric cooling module (3) is any one of Bi2Te3, Bi2(TeSe)3, PbTe or other N-type materials with thermoelectric effect, with a thickness of 0.03 to 3000 μm and a side length of 60 to 200 μm; The P-type thermoelectric material layer in the thermoelectric cooling module (3) is any one of Sb2Te3, (BiSb)2Te3, Bi2Te3 or other P-type materials with thermoelectric effect, with a thickness of 0.03 to 3000 μm and a side length of 60 to 200 μm; The spacing between the N-type thermoelectric material layer and the P-type thermoelectric material layer in a single thermoelectric refrigeration module is 10-20 μm, and the spacing between two adjacent thermoelectric refrigeration modules is 10-30 μm.

3. The device according to claim 1, characterized in that: The patterned upper metal electrode layer (31) and lower metal electrode layer (32) are made of Ni / Au, Au / Cu, Ni / Cu or other metals that match the thermoelectric material, with a thickness of 40-100 / 200-2000nm. They are used to apply voltage to the thermoelectric cooling module to form current, so that a temperature difference is formed between the upper and lower surfaces of the thermoelectric cooling module, thereby improving the heat dissipation capacity of the device. The substrate insulating layer (41) is made of SiO2 or Si3N4 and has a thickness of 0.1 to 1 μm; The insulating support material (33) is any one of SiO2, Si3N4 or photoresist, and its thickness is the sum of the thickness of the upper metal electrode layer (31) and the thermoelectric cooling module (3).

4. The device according to claim 1, characterized in that: The heat transfer interface layer (2) is made of any one of silicone, silicone grease, epoxy resin or phase change material, and its thickness is 20 to 500 μm. The phase change material includes polyolefin resin and acrylic resin. The heat sink layer (1) is made of any one of copper alloy, aluminum alloy, high thermal conductivity metal or high thermal conductivity ceramic material, and its thickness is 0.1 to 10 mm. The copper alloy includes copper-tungsten alloy and copper-molybdenum alloy, the aluminum alloy includes aluminum-magnesium-silicon alloy and aluminum-silicon-carbon alloy, the high thermal conductivity metal includes W, Mo, Cu and Al, and the high thermal conductivity ceramic material includes SiC ceramic and AlN ceramic.

5. The device according to claim 1, characterized in that: The substrate (4) is made of Si or SiC and has a thickness of 50 to 500 μm; The nucleation layer (5) is made of AlN and has a thickness of 20-200 nm. The buffer layer (6) is made of any one of GaN, AlN or AlGaN, and its thickness is 0.1 to 5 μm. The channel layer (7) is made of GaN and has a thickness of 20-1000 nm; The barrier layer (8) is made of AlGaN and has a thickness of 10-30 nm.

6. A method for fabricating a GaN device with enhanced heat dissipation through electrothermal cooling, characterized in that, Includes the following steps: S1: On the upper surface of the substrate, a nucleation layer, a buffer layer, a channel layer, and a barrier layer are sequentially epitaxially deposited by metal-organic chemical vapor deposition (MOCVD). S2: Electrode metal is first deposited on the barrier layer by electron beam evaporation of E-Beam, and then ion implantation is performed to achieve device isolation; S3: The surface of the barrier layer is connected to the external carrier wafer through a bonding process, and the lower surface of the substrate is pretreated by grinding and thinning and surface polishing. S4: An insulating layer is deposited on the lower surface of the pretreated substrate by plasma-enhanced chemical vapor deposition (PECVD). S5: Deposit a metal electrode layer on the substrate insulating layer by electron beam evaporation of E-Beam; S6: An N-type thermoelectric material layer and a P-type thermoelectric material layer are deposited on the upper metal electrode layer by photolithography and metal-organic chemical vapor deposition (MOCVD) to form a thermoelectric cooling module. S7: Insulating support material is deposited or spin-coated around the thermoelectric cooling module by plasma-enhanced chemical vapor deposition (PECVD). S8: Deposit metal electrode layers on thermoelectric cooling modules and insulating support materials by electron beam evaporation of E-Beam; S9: The heat sink material is bonded to the surface of the lower metal electrode layer using a heat transfer interface material, and the carrier wafer is removed to complete the device fabrication.

7. The method according to claim 6, characterized in that: The metal-organic chemical vapor deposition (MOCVD) process in step S1 is as follows: TMGa was used as a precursor for Ga, TMAl as a precursor for Al, NH3 as a nitrogen source, and a mixture of H2 and N2 as a carrier gas. The flow rate ratio of NH3 to TMAl for AlN deposition was 1000–3000, the temperature was maintained at 450–750℃, and the growth pressure was maintained at 50–250 mbar. The flow rate ratio of NH3 to TMGa for GaN deposition was 1500–2500, the temperature was maintained at 900–1100℃, and the growth pressure was maintained at 50–200 mbar. The flow rate ratio of NH3 to TMGa for AlGaN deposition is 1000–2000, the flow rate ratio of TMGa to TMAl is 4–20, the temperature is maintained at 800–1100℃, and the growth pressure is maintained at 50–150 mbar.

8. The method according to claim 6, characterized in that: The metal-organic chemical vapor deposition (MOCVD) process in step S6 is as follows: TMBi was used as the precursor of Bi, TDSb as the precursor of Sb, DipTe as the precursor of Te, TEL as the precursor of Pb, DESe as the precursor of Se, and high-purity H2 as the carrier gas. The flow rate ratio of DipTe to TMBi for Bi2Te3 deposition was 2–10, the temperature was maintained at 200–500℃, and the growth pressure was maintained at 300–600 mbar. The flow rate ratio of DipTe to TDSb for depositing Sb2Te3 was 1–6, the temperature was maintained at 250–450℃, and the growth pressure was maintained at 200–500 mbar. The flow rate ratio of DipTe to TEL for PbTe deposition was 1–3, the temperature was maintained at 300–500℃, and the growth pressure was maintained at 200–450 mbar. The flow rate ratio of DipTe to TMBi for depositing Bi2(TeSe)3 was 1–8, the flow rate ratio of DipTe to DESe was 1–3, the temperature was maintained at 220–600℃, and the growth pressure was maintained at 200–600 mbar. The flow rate ratio of DipTe to TMBi for (BiSb)2Te3 deposition was 1–5, the flow rate ratio of TMBi to TDSb was 2–4, the temperature was maintained at 200–550℃, and the growth pressure was maintained at 300–500 mbar.

9. The method according to claim 6, characterized in that, In steps S4 and S7, the plasma-enhanced chemical vapor deposition (PECVD) process conditions are as follows: SiO2 deposition uses SiH4 and N2O as precursor gases, with the flow rate maintained at 50–80 cm⁻¹. 3 / min, 160~200cm 3 The growth rate was maintained at 250–300℃, the growth pressure at 80–100Pa, and the RF power at 60–100W. Si3N4 was deposited using SiH4 and NH3 as precursor gases, with the flow rate maintained at 10–30 cm⁻¹. 3 / min, 5~20cm 3 The growth rate was maintained at 100-150 Pa, the temperature was kept at 200-400℃, the growth pressure was kept at 100-150 Pa, and the RF power was set to 50-500 W.

10. The method according to claim 6, characterized in that: The electron beam evaporation of E-Beam in step S2 is performed under the following process conditions: The studio was vacuumed to 2.0×10. -4 Pa, electron gun accelerating voltage is 6-10 kV, electron gun beam current is 0.1-1 A, and evaporation time is 80-380 s; The electron beam evaporation of E-Beam in steps S5 and S8 is performed under the following process conditions: The studio was evacuated to a vacuum level of 2.5 x 10. -4 Pa, electron gun accelerating voltage of 8-10 kV, electron gun beam current of 0.4-1 A, and evaporation time of 240-2100 s.

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