Floating high voltage level converter with adaptive bypass circuit

Abstract

Techniques for enhancing the capability of a floating level converter (100) are described herein. For example, the increased margin is achieved by adaptively bypassing a protection element (309, 310) of the voltage level converter (100). In an example, a floating level converter (100) may transform an input signal from a low voltage domain to a high voltage domain. A bypass circuit (414) is coupled across the protection element (309, 310). The bypass circuit (414) selectively engages during low voltage operation (e.g., thereby providing a lower loss path relative to loss caused by a high voltage protection element (309, 310) and thus increasing a margin swing) and, in response to a high voltage reference rail of the high voltage domain exceeding a threshold or otherwise sufficiently high (e.g., a low voltage reference rail of the high voltage domain exceeding a threshold). The electrical potential of the low voltage domain power rail is greater than the electrical potential of the low voltage domain power rail. The bypass circuit (414) may be implemented in a relatively low complexity manner (e.g., back-to-back high voltage FETs) without additional signal control of low voltage capabilities.

Description

Technical Field

[0001] The present description relates to voltage level shifters, and more particularly, to floating high voltage level shifters. Background Art

[0002] A voltage level translator, also known as a voltage level shifter, is a circuit that translates a given signal from one voltage domain to another, which is useful for applications that utilize multiple voltage domains. The voltage domains between which the translation is performed may be different, but may include, for example, a first logic domain and a second logic domain (e.g., where the level translator shifts a TTL signal to an ECL signal or a CMOS signal or vice versa, where TTL refers to transistor-to-transistor logic, ECL refers to emitter-coupled logic, and CMOS refers to complementary metal oxide semiconductor), or a low voltage domain and a high voltage domain (e.g., where the level translator shifts a relatively low voltage signal to a relatively high voltage signal or vice versa).

[0003] The floating high voltage level translator is used to shift the high and low levels of the input control signal received from the low voltage circuit to the high and low levels of the high voltage circuit having a floating power rail and a reference (ground) rail. The potential difference between the floating power rail and the reference rail can be relatively low (e.g., less than 5 volts, such as 2 volts or 3 volts), but the respective absolute values ​​of the floating power rail and the floating reference rail can vary depending on the application and can be relatively high voltages (e.g., 2 volts to 700 volts).

[0004] Many level shifter designs are available, each offering certain benefits that may be desired for a given application, but there may be tradeoffs between performance parameters such as propagation speed, common mode transient immunity (CMTI), and power dissipation. Thus, many important issues remain with level shifters. Summary of the invention

[0005] Techniques for enhancing low voltage operation of floating high voltage level shifters are described herein.

[0006] One example is a voltage level translator circuit. The voltage level translator circuit includes a first field effect transistor (FET) and a second FET, the first FET and the second FET each having a respective source coupled to a first (e.g., low voltage) supply reference terminal, a gate of the first FET configured to receive an input signal, and a gate of the second FET configured to receive an inverted version of the input signal. The voltage level translator circuit further includes a third FET and a fourth FET, the third FET and the fourth FET each having a respective gate coupled to a floating second (e.g., high voltage) supply reference terminal, a drain of the third FET coupled to a drain of the first FET, a drain of the fourth FET coupled to a drain of the second FET, a source of the third FET coupled to a first output terminal, and a source of the fourth FET coupled to a second output terminal. The voltage level translator circuit further includes a fifth FET and a sixth FET, each having a respective source coupled to a floating (e.g., high voltage) supply terminal, a drain of the fifth FET coupled to the first output terminal, a drain of the sixth FET coupled to the second output terminal, a gate of the fifth FET coupled to the second output terminal, and a gate of the sixth FET coupled to the first output terminal. The voltage level translator circuit further includes a first bypass circuit coupled from the first output terminal to the gate of the third FET, and a second bypass circuit coupled from the second output terminal to the gate of the fourth FET.

[0007] Another example is an adaptive bypass circuit for a floating level converter. The floating level converter can convert a voltage level from a first voltage domain (e.g., a low voltage domain) to a second voltage domain (e.g., a high voltage domain). The adaptive bypass circuit includes a switching circuit and a comparator circuit. The switching circuit is coupled across a protection element of the floating level converter. The comparator circuit is configured to activate the switching circuit to bypass the protection element in response to a reference rail of the second voltage domain being less than a threshold value (e.g., thus indicating low voltage operation), and deactivate the switching circuit in response to the reference rail of the second voltage domain being not less than the threshold value (e.g., thus not indicating low voltage operation) so as not to bypass the protection element. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 A voltage level translator configured for enhanced low voltage operation is described in an example.

[0009] Figure 2 A voltage level converter application is described in an example.

[0010] Figure 3is a schematic diagram of an example voltage level translator that is susceptible to limited supply voltage operating range at lower voltages.

[0011] Figure 4 is a schematic diagram of a voltage level translator configured to adaptively bypass a high voltage protection element during low voltage operation in an example.

[0012] Figure 5 is a schematic diagram of a voltage level shifter configured to adaptively bypass a high voltage protection element during low voltage operation in another example.

[0013] Figure 6 is a schematic diagram of a voltage level translator configured to adaptively bypass a high voltage protection element during low voltage operation in another example.

[0014] Figure 7 is a schematic diagram of a voltage level shifter configured to adaptively bypass a high voltage protection element during low voltage operation in another example.

[0015] Figure 8 is a schematic diagram of a voltage level shifter configured to adaptively bypass a high voltage protection element during low voltage operation in another example.

[0016] Fig. 9 Various plots are shown illustrating enhanced low voltage operation of a voltage level translator configured in an example to adaptively bypass high voltage protection elements during low voltage operation.

[0017] Fig.10 In another example, a voltage level translator application is described. DETAILED DESCRIPTION

[0018] The technology for enhancing the low voltage capability of the voltage level converter by increasing the margin swing is described herein. The increased margin is realized by adaptively bypassing the high voltage protection element of the voltage level converter. In an example, a floating high voltage level converter can transform an input signal from a low voltage domain to a high voltage domain. The level converter includes a bypass circuit, which is coupled across the source-gate junction of the high voltage protection element. The bypass circuit selectively engages during low voltage operation, thereby bypassing the source-gate voltage of the high voltage protection element and thus increasing the margin swing, and disengages in response to the high voltage reference rail of the high voltage domain exceeding a threshold or otherwise being high enough (e.g., greater than the potential of the low voltage domain power rail). The bypass circuit can be implemented in a relatively low complexity manner (e.g., back-to-back high voltage FET) without additional signal control of low voltage capability and without affecting propagation speed, quiescent current or CMTI. The high voltage protection element can be optimally sized for propagation speed, and does not need to be too large to improve low voltage performance, thereby saving area.

[0019] Overall Overview

[0020] Level shifters or converters are used in a wide range of applications that may require a wider operating voltage range (e.g., 2-700 volts). However, and as described above, there are still many important problems associated with level converters. For example, high voltage level converter applications are often limited to the power supply voltage operating range at lower voltages, and cannot maintain the correct state, propagation speed, and / or common mode transient immunity (CMTI) at low quiescent currents. The root cause of such limitations is that, at lower voltages, the level converter may lose margin. This margin loss actually reduces the potential difference between the high level and the low level, making the converter more susceptible to noise and errors (e.g., noise may cause the high level to appear as a low level, and vice versa). In order to solve such margin problems, different solutions have been proposed, but the solutions often cause one or more additional problems.

[0021] In more detail, consider Figure 3 . As shown, the level converter 50 includes cross-coupled low voltage p-type field effect transistors (PFETs) 305 and 306, pull-up resistors 307 and 308, high voltage PFETs 309 and 310, high voltage n-type field effect transistors (NFETs) 311 and 312, and low voltage logic inverter 313. The sources of PFETs 305 and 306 are connected to the floating high voltage power rail HVDD and act as pull-up devices. The drains of PFETs 305 and 306 are connected to nodes V through corresponding pull-up resistors 307 and 308, respectively. out_b and V out_a Other embodiments may not include pull-up resistors 307 and 308 or different pull-up elements or circuits. The gate of PFET 305 is connected to node V out_a , and the gate of PFET 306 is connected to node V out_b PFETs 309 and 310 act as high voltage protection elements. The source of PFET 309 is connected to node V out_b , and the source of PFET 310 is connected to node V out_a The gates of PFETs 309 and 310 are connected to a floating high voltage reference rail HVSS. The drain of PFET 309 is connected to the drain of NFET 311, and the drain of PFET 310 is connected to the drain of NFET 312. The sources of NFETs 311 and 312 are connected to a low voltage reference rail LVSS, which is ground in this example. The gate of NFET 311 receives an input signal IN, and the gate of NFET 312 receives an inverted version of the input signal IN, which is provided by inverter 313.

[0022] In operation, the level converter 50 converts the high and low levels of the input signal IN from a low voltage domain (LVDD referenced to LVSS) to a high voltage domain (HVDD referenced to HVSS). The input signal IN may be, for example, a pulse width modulation (PWM) driver signal. In more detail, the PFETs 309 and 310 are always turned on, but their respective source-gate voltages (Vsg) vary depending on the states of the NFETs 311 and 312. Specifically, for the PFET 309, in response to the NFET 311 being turned on, Vsg is approximately equal to the PFET 309 threshold voltage, or in response to the NFET 311 being turned off, Vsg is approximately equal to HVDD-HVSS. Similarly, for the PFET 310, in response to the NFET 312 being turned on, Vsg is approximately equal to the PFET 310 threshold voltage, or in response to the NFET 312 being turned off, Vsg is approximately equal to HVDD-HVSS. Therefore, in response to the input signal IN being high, NFET 311 is turned on and thus the node V is pulled high through PFET 309. out_b connected to LVSS, which in turn turns on PFET 306, thereby turning node V out_a Therefore, the high level of the input signal IN is converted from the low voltage domain to the high level of the high voltage domain and is provided as OUT_a. In addition, the node V out_b is clamped to the high voltage reference level (HVSS) minus the PFET 309 threshold voltage and is provided at OUT_b. In addition, in response to the input signal IN being low, NFET 312 is turned on and thus the node V is pulled higher through PFET 310. out_a connected to LVSS, which in turn turns on PFET 305, thereby turning node V out_b Pull up to HVDD. In addition, the node V out_a is clamped to HVSS minus the PFET 310 threshold voltage and provided at OUT_a. Therefore, the low level of the input signal IN is converted from the low voltage domain to the low level of the high voltage domain and provided as OUT_a. OUT_b is complementary to OUT_a.

[0023] The quiescent current of the level converter 50 is zero or very low. This means that the level converter 50 consumes almost no current when the signal is not level shifted. Unfortunately, under low voltage operation (e.g., when HVDD-LVSS is in the range of 2 or 3 volts or otherwise below a given threshold indicating low voltage operation for a given application), the source-gate voltage of PFETs 309 and 310 limits the performance of the level converter 50. Therefore, the margin may be calculated as (HVDD-LVSS) minus the source-gate voltage of the corresponding PFET 309 or 310. Many solutions are possible to solve this margin problem, but each solution will cause another problem to appear.

[0024] In more detail, one such possible solution uses a first diode-connected PFET and a second diode-connected PFET in parallel with the corresponding PFET in PFET 305 or 306 to provide appropriate headroom swing, but at the expense of quiescent current (increased power dissipation). Another possible related solution adds a dynamic gate biasing scheme that helps reduce power dissipation to restore low quiescent current, but in turn results in an increase in propagation speed. Another possible solution employs a pulse-triggered level shifter topology that includes a pulse generator circuit and pull-up and pull-down current mirrors to eliminate (or otherwise reduce) injected common-mode current, thereby providing good low voltage capability and CMTI, but at the expense of complexity and increased quiescent current. Therefore, as described above, there is generally a trade-off between headroom swing, propagation speed, CMTI, power dissipation (quiescent current), and complexity (especially at low voltage operation).

[0025] Therefore, the present invention describes a technique for enhancing the low voltage capability of a floating high voltage level converter by increasing the margin swing without significantly affecting the propagation speed, quiescent current, CMTI or circuit complexity. In an example, a bypass circuit can be coupled across the source-gate junction of a high voltage protection element (e.g., PFET 309 and 310). The bypass circuit can be adaptively engaged (and disengaged), and can be implemented without an additional signal to control the low voltage capability. The bypass circuit can be controlled by an input PWM driver control signal, and adaptively engaged during low voltage operation, thereby bypassing the source-gate voltage of the high voltage protection element, and thus increasing the margin swing. In addition, the bypass circuit is adaptively disengaged in response to a high voltage reference rail (e.g., HVSS) exceeding a threshold or otherwise being sufficiently high. The bypass circuit can be implemented in a relatively low complexity manner (e.g., back-to-back high voltage FET) and without affecting the propagation speed, quiescent current or CMTI. According to some such examples, high voltage protection elements (e.g., PFETs 309 and 310) may be optimally sized for propagation speed and need not be oversized to improve low voltage performance, thereby saving area and reducing complexity, speeding up signal paths, having zero quiescent current impact, and enhancing CMTI performance at low voltages without compromising CMTI performance at high voltages.

[0026] Circuit Architecture

[0027] Figure 1 A voltage level converter 100 configured for enhanced low voltage operation is described in an example. As shown, the level converter 100 is a floating high voltage level converter that receives an input signal IN corresponding to a first (low) voltage domain and generates an output signal OUT corresponding to a second (high) voltage domain. The first voltage domain includes a fixed low voltage power rail LVDD and a fixed low voltage reference rail LVSS, and the second voltage domain includes a floating high voltage power rail HVDD and a floating high voltage reference rail HVSS. The input signal IN is a PWM signal that is typically converted from LVSS to LVDD (or some smaller value, considering junction losses and any parasitic effects), and the output signal OUT is a PWM signal that is typically converted from HVSS to HVDD (or some smaller value, considering junction losses and any parasitic effects).

[0028] In operation, the voltage level converter 100 operates to shift the high and low levels of the low voltage domain input signal IN to the high and low levels of the high voltage domain output signal OUT. In an example, LVDD is a low voltage supply (e.g., 2 volts or 3 volts) referenced to ground. The potential difference between the floating high voltage power rail and the reference rail (HVDD-HVSS) can be relatively low (e.g., less than 5 volts, such as 2 volts or 3 volts), but the respective absolute values ​​of HVDD and HVSS can vary depending on the application and can be relatively high voltages (e.g., 2 volts to 700 volts).

[0029] In addition to referring to an actual supply voltage or reference level, a "rail" as used herein may also refer to, for example, a physical terminal of a power supply (a supply terminal, or a return or reference terminal) or a circuit node adapted to be coupled to a terminal of a power supply. Thus, a rail as used herein may refer to a voltage supply signal, a voltage supply reference signal, a voltage supply node within a circuit, a voltage supply reference node within a circuit, a supply terminal of a voltage supply, or a reference terminal of a voltage supply. For example, a power supply may be a fixed voltage supply with a fixed voltage output referenced to ground, or a floating voltage supply with a voltage output (further including both power level and reference level) that may vary (or float) within a given output range to meet the specific requirements of a given application.

[0030] Figure 2 The application of the voltage level converter 100 is described in an example. In this example, the voltage level converter 100 is part of an integrated circuit 200 including an input buffer 201 and an output buffer 202. The input / output (I / O) pins or pads of the integrated circuit include IN, LVDD, LVSS, HVDD, HVSS and OUT. As shown, the input buffer 201 is coupled to the power rail (LVDD) and ground rail (LVSS) of the low voltage domain, and drives the input signal IN from the input of the integrated circuit to the input of the voltage level converter 100. The output buffer 202 is coupled to the power rail (HVDD) and ground rail (HVSS) of the high voltage domain, and drives the output signal OUT of the voltage level converter 100 to the output of the integrated circuit 200. Each of the input buffer 201 and the output buffer 202 can be implemented with a standard buffer or driver circuit system. The integrated circuit 200 may also include other circuit systems and / or I / O pins or pads. As shown, output signal OUT is used to drive the gate of high voltage NFET 203, which in turn switches the high voltage supply to load 204. NFET 203 may be implemented with any suitable switching technology. Similarly, load 204 may be any load, such as a servo motor.

[0031] Figure 4is a schematic diagram of a voltage level translator 100a configured in an example to adaptively bypass a high voltage protection element during low voltage operation. As shown, the voltage level translator 100a is similar to the level translator 50, except that the voltage level translator 100a further includes an adaptive bypass circuit 414 connected across the source-gate junction of the high voltage PFETs 309 and 310. Figure 3 The above related descriptions of are equally applicable here, except that in some such instances, the margin issues under low voltage operation are alleviated through the operation of the adaptive bypass circuit 414 and without affecting the low quiescent current, state, propagation speed or CMTI.

[0032] During low voltage operation, the adaptive bypass circuit 414 is configured to bypass or short the high voltage protection element (FET 309 or 310). Such bypassing eliminates or otherwise reduces the headroom loss attributable to the source-gate voltage of the FET 309 or 310. As shown, the adaptive bypass circuit 414 generally includes a comparator circuit or function (C1, C2) and a switching circuit or function (S1, S2) for each high voltage protection element (309, 310). In more detail, the comparator functions C1 and C2 effectively sense when the output voltage is high (HVDD>HVSS>LVDD) and disable switches S1 and S2, respectively, regardless of the input signal IN. In this case, the enable (en) input of the corresponding switching circuit is low (e.g., the switch driver is disabled), so the switch remains open regardless of the input signal IN. In addition, comparator functions C1 and C2 sense low voltage operation, such as when HVSS is less than LVDD (minus any threshold voltage of the comparator function), thereby allowing switches S1 and S2 to be controlled by input signal IN, respectively. In this case, the enable (en) input of the switching circuit is high (e.g., the switch driver is enabled), so the switch opens and closes in response to the input signal IN. Therefore, during the sensed low voltage operation, switch S1 is closed in response to the input signal IN being high (logic 1), and switch S1 is opened in response to the input signal IN being low (logic 0). Due to inverter 313, switch S2 is complementary to switch S1. In this way, comparator functions C1 and C2 enable switches S1 and S2 to be adaptively engaged in response to input signal IN under low voltage operation, and to be adaptively disengaged in response to HVSS being sufficiently high.

[0033] Figure 5 1 is a schematic diagram of a voltage level translator 100b configured to adaptively bypass a high voltage protection element during low voltage operation in another example. As shown, the voltage level translator 100b is similar to the level translator 100a, except that the adaptive bypass circuit 414 is implemented with a back-to-back NFET configuration, which effectively provides the above-mentioned Figure 4The comparator and switching functions (C1, C2, S1 and S2) are described.

[0034] In more detail, a first pair of back-to-back NFETs (515 and 516) are connected across the source-gate junction of PFET 309, and a second pair of back-to-back NFETs (517 and 518) are connected across the source-gate junction of PFET 310. The gates and sources of NFETs 515 and 516 are connected together; similarly, the gates and sources of NFETs 517 and 518 are connected together. In addition, the drain of NFET 515 is connected to node V out_b , and the drain of NFET 516 is connected to the high voltage reference rail HVSS; similarly, the drain of NFET 517 is connected to the node V out_a , and the drain of NFET 518 is connected to the high voltage reference rail HVSS. The gates of NFETs 515 and 516 are driven by the input signal IN, and the gates of NFETs 517 and 518 are driven by the complementary signal of the input signal IN, which is provided by inverter 313.

[0035] In operation, at high voltage, HVDD>HVSS>LVDD, back-to-back NFETs 515 and 516 are naturally disabled / turned off regardless of input signal IN. As HVDD decreases to a point where HVSS is less than LVDD (minus any threshold voltages of NFETs 515 and 516), back-to-back NFETs 515 and 516 are naturally turned on and are now controlled by input signal IN. For example, NFETs 515 and 516 are enabled / turned on in response to input signal IN being high (logic 1), and disabled / turned off in response to input signal IN being low (logic 0). When turned on or otherwise enabled, back-to-back NFETs 515 and 516 effectively turn V out_b The short connection to HVSS thus bypasses the source-gate voltage of PFET 309 and thus adds additional margin to the cross-coupled PFET 305 .

[0036] Due to inverter 313, the polarity of back-to-back NFETs 517 and 518 are complementary. Therefore, at high voltages, HVDD>HVSS>LVDD, back-to-back NFETs 517 and 518 are naturally disabled / turned off regardless of input signal IN. As HVDD decreases to a point where HVSS is less than LVDD (minus any threshold voltages of NFETs 517 and 518), back-to-back NFETs 517 and 518 are naturally turned on and are now controlled by input signal IN. For example, NFETs 515 and 516 are enabled / turned on in response to input signal IN being low (logic 0), and disabled / turned off in response to input signal IN being high (logic 1). When turned on or otherwise enabled, back-to-back NFETs 517 and 518 effectively turn Vout_a The short connection to HVSS thus bypasses the source-gate voltage of PFET 310 and thus adds additional margin to the cross-coupled PFET 306 .

[0037] The amount of increase in margin may be approximately equal to the source-gate voltage of the bypassed PFET 309 or 310, and may vary from example to example depending on the CMOS process employed. In some examples, the source-gate voltage of the bypassed PFET 309 or 310 is in the range of approximately 0.7 volts to 1.0 volts. Fig. 9 Describing a specific example, this figure shows how a voltage converter configured with the bypass circuits variously described herein can begin operation (level shifting) earlier in a high voltage power rail ramp-up relative to a voltage converter not so configured.

[0038] Depending on a given application and CMOS process, the values ​​of the high voltage and low voltage power rails and reference rails and various transistor parameters (e.g., threshold voltage, gate oxide rating, source-gate voltage) may vary from instance to instance, but in one example case, the HVDD-HVSS differential supply is a relatively low voltage, such as a voltage below the maximum gate oxide rating of the NFETs 515-518. In one such case, for example, the HVDD-HVSS differential supply is in the range of about 2 or 3 volts. The absolute value of each of the HVDD and HVSS rails may float over a relatively large range, such as 2 volts to 30 volts or more, depending on the application. LVDD is a low voltage supply referenced to ground, such as in the range of about 1 to 2 volts. The input signal IN may be, for example, a PWM signal or other control signal that transitions between a high state and a low state of a given low voltage domain. In any such case, the techniques provided herein, whether or not through the use of back-to-back FETs controlled by input signal IN (or other comparable comparator / switching functions), produce an adaptive enhancement that automatically engages during low voltage operation and automatically disengages after HVSS is sufficiently high (e.g., in response to HVSS being greater than LVDD).

[0039] The comparator and switching functions are effectively integrated into the back-to-back FETs. For example, in response to HVSS being above node V out_b, the intrinsic diode of NFET 515 is forward biased, and thus FET 515 can be turned on. In contrast, the intrinsic diode of NFET 516 is reverse biased, and thus FET 516 can be turned off by applying the low level of input signal IN to the gate of FET 516. Applying the high level of input signal IN to the gate of FET 516 also applies the high level to the gate of FET 515, thereby increasing the channel conductivity of FET 515 relative to its conductivity achieved by simply forward biasing its intrinsic diode, and both FETs 515 and 516 are turned on. If V out_b Above HVSS, NFETs 515 and 516 reverse these effects. NFETs 515 and 516 turn on (source to drain) in response to LVDD being sufficiently greater than HVSS (sensing low voltage operation), thus providing both comparator-like functionality and switching functionality. This description is equally applicable to back-to-back FETs 517 and 518.

[0040] Figure 6 6 is a schematic diagram of a voltage level translator 100c configured to adaptively bypass high voltage protection elements during low voltage operation in another example. As shown, voltage level translator 100c is similar to voltage level translator 100b, except that voltage level translator 100c additionally includes a differential output latch formed by PFETs 619 and 620 and cross-coupled NFETs 621 and 622. The sources of FETs 619 and 620 are connected to a high voltage power rail HVDD. The gate of FET 619 is connected to node V out_a The drain of FET 619 provides the output signal OUT_b and is connected to the drain of FET 621 and the gate of FET 622. The gate of FET 620 is connected to node V out_b The drain of FET 620 provides the output signal OUT_a and is connected to the drain of FET 622 and the gate of FET 621. The sources of FETs 621 and 622 are connected to a high voltage reference rail HVSS.

[0041] In operation, in response to V out_a Greater than V out_b , FET 619 produces less drain current than FET 620, which in turn causes FETs 621 and 622 to latch OUT_a to HVDD and OUT_b to HVSS. In contrast, in response to V out_a Less than V out_b , FET 619 generates more drain current than FET 620, which in turn causes FETs 621 and 622 to latch OUT_a to HVSS and OUT_b to HVDD.

[0042] Figure 7 1 is a schematic diagram of a voltage level converter 100d configured to adaptively bypass a high voltage protection element during low voltage operation in another example. As shown, the voltage level converter 100d is similar to the voltage level converter 100c, except that the voltage level converter 100d further includes a latch 723 and a driver or buffer 724. The latch 723 receives OUT_a and OUT_b as inputs, and latches OUT_a to the input of the driver 724. The driver 724 provides an output signal OUT, which is a high voltage version (or a transformed version) of the input signal IN. The output signal OUT can be, for example, a PWM signal. The latch 723 can be any number of latch circuits (e.g., a NAND-based latch, a NOR-based latch), and the driver 724 can be any number of buffer / driver circuits (e.g., a high voltage driver, such as a gate for driving a high voltage FET).

[0043] Figure 8 Schematic diagram of voltage level converter 100e configured to adaptively bypass high voltage protection element during low voltage operation in another example. As shown, voltage level converter 100e is similar to voltage level converter 100d, except that latch 723 is implemented with a NAND-based latch including NAND gates 825 and 826. In this example, if OUT_a is high and OUT_b is low, gate 826 outputs a high level signal. In contrast, if OUT_a is low and OUT_b is high, gate 826 outputs a low level signal. If NAND gates 825 and 826 are changed to NOR gates arranged in the same manner, the opposite situation will apply. Specifically, if OUT_a is high and OUT_b is low, gate 826 outputs a low level signal. In contrast, if OUT_a is low and OUT_b is high, gate 826 outputs a high level signal.

[0044] Enhanced Low Voltage Operation

[0045] Fig. 9 Various plots are shown illustrating enhanced low voltage operation of a voltage level converter configured in an example to adaptively bypass high voltage protection elements during low voltage operation. As shown in this example case, the input signal IN is a PWM signal (PWM In ), output signal OUT(PWM Out ) is also a PWM signal, further comprising an output generated by a level shifter including bypass circuit 414 and another output generated by a level shifter not including bypass circuit 414. In this example case, PWM In and PWM OutBoth switch between approximately ground (0 volts) and approximately 3.6 volts. As shown, under low voltage operation, when HVDD-LVSS is relatively low (e.g., in the 3 volt range, or some other threshold suitable for a given application), the source-gate voltage of PMOS transistors 309 and 310 limits the performance of the level shifter.

[0046] For example, the plot shows that as the supply HVDD ramps up, when OUT follows PWM In , the margin is improved by about 0.75 volts. Specifically, when the adaptive bypass circuit 414 is in place, the output voltage signal OUT of the voltage converter becomes active in response to the supply HVDD of about 2.764 volts. In contrast, when the adaptive bypass circuit 414 is not in place, the output voltage signal OUT does not become active until the supply HVDD is about 3.512 volts. This 0.748 volt margin improvement is largely because the adaptive bypass circuit 414 provides a parallel path to bypass the PMOS transistors 309 and 310. In some examples of such cases, this parallel path provided by the bypass circuit 414 is a zero-loss (or otherwise low-loss) path relative to the path through the PMOS transistors 309 and 310. In this way, according to one such example, the increase in margin is equal to the source-gate voltage (Vsg) of the transistor 309 or 310, and the source-gate voltage is approximately equal to the threshold voltage of the transistor 309 or 310, respectively. Another example may have a margin increase amount approximately equal to the Vsg of transistor 309 or 310 minus any threshold voltage of the parallel path provided by the bypass circuit (eg, FETs 515 and 516 or FETs 517 and 518).

[0047] Power Converter Applications

[0048] Fig.10 A voltage level converter application is described in another example. As shown, this example application includes a high-side low-side driver 1028 coupled between a PWM controller 1027 and power PFETs 1029 and 1030 of an isolated switching power converter, which additionally includes a transformer 1031 and a secondary-side circuit 1032. A feedback signal from the secondary-side circuit 1032 is provided to the PWM controller 1027 through an isolation and feedback circuit 1033. In an example, each of the PWM controller 1027, the high-side low-side driver 1028, the isolated switching power converter, and the secondary-side circuit 1032 can be implemented with standard or proprietary technology, except that the driver 1028 is configured with a level shifter 100.

[0049] In operation, the PWM controller 1027 generates high (HI) and low (LI) PWM signals in response to feedback signals provided from the secondary side circuit 1032 through the isolation and feedback circuit 1033. The driver 1028 receives each of the HI and LO PWM control signals and generates a corresponding output drive signal OUT H and OUT L , which in turn drives the gates of power FETs 1029 and 1030, respectively. Switching of FETs 1029 and 1030 allows the desired power level to be supplied to the secondary side circuit 1032. The PWM controller 1027 is connected to a low voltage domain including a low voltage power rail LVDD and a reference rail LVSS, the switching power converter is connected to a high voltage domain including a floating high voltage power rail HVDD and a floating high voltage reference rail HVSS, and the driver 1028 transforms the PWM control signal from the low voltage domain to the high voltage domain. Filter capacitors may be connected between ground and each power rail to attenuate high frequency noise.

[0050] In an example, driver 1028 is implemented with a high-side low-side driver (e.g., UCC27210 or UCC27211 of Texas Instruments Incorporated), except that a high-side drive circuit (driving high block) is implemented with a voltage level converter 100 (further including any one of voltage level converters 100a-e) configured with an adaptive bypass circuit. More generally, any number of circuits that need to interface a voltage domain with another voltage domain, whether in a high-side low-side power converter application or a single drive application (e.g., only a high-side application or an amplifier application) or other floating high voltage level converter applications, can also benefit from using a voltage level converter configured with an adaptive bypass circuit described differently herein. As shown, the PWM control signal HI is processed (e.g., buffered) by the control block of driver 1028 and applied to the input of the driving high block. As shown, the driving high block generates a high-side PWM control output signal OUT H , and connected to a low voltage power rail LVDD and a low voltage reference rail LVSS, and a floating high voltage power rail HVDD and a floating high voltage reference rail HVSS. In one such example, the low voltage power rail LVDD is about 12 volts, the low voltage reference rail LVSS is ground, the floating high voltage power rail HVSS is in the range of -0.3 volts to 120 volts, the floating high voltage reference rail HVSS is in the range of -1 volt to 115 volts, and the potential difference between HVSS and HVDD is about 12 volts. More generally, each of LVDD, LVSS, HVDD, and HVSS can be set as needed for a given application.

[0051] In any such case, the PWM input signal to the drive high block may correspond to Figure 1-8 The input signal IN from the drive high block; similarly, the output signal OUT from the drive high block H (High-side PWM Out ) corresponds to Figure 1-8 The output signal OUT or OUT_a (or OUT_b, as the case may be) of the driver 1028 is used to drive the gate of the power FET 1029. The above description of the level converter 100 (further including any of 100a-e) is also applicable here. In addition, the drive low block of the driver 1028 generates the output signal OUT L (Low-side PWM Out ), the output signal is used to drive the gate of power FET 1030.

[0052] Additional Example Embodiments

[0053] Example 1 is a voltage level converter circuit. The voltage level converter circuit includes a first field effect transistor (FET) and a second FET, the first FET and the second FET each having a respective source coupled to a first (e.g., low voltage) supply reference terminal, a gate of the first FET configured to receive an input signal, and a gate of the second FET configured to receive an inverted version of the input signal. The voltage level converter circuit further includes a third FET and a fourth FET, the third FET and the fourth FET each having a respective gate coupled to a floating second (e.g., high voltage) supply reference terminal, a drain of the third FET coupled to a drain of the first FET, a drain of the fourth FET coupled to a drain of the second FET, a source of the third FET coupled to a first output terminal, and a source of the fourth FET coupled to a second output terminal. The voltage level translator circuit further includes a fifth FET and a sixth FET, each having a respective source coupled to a floating (e.g., high voltage) supply terminal, a drain of the fifth FET coupled to the first output terminal, a drain of the sixth FET coupled to the second output terminal, a gate of the fifth FET coupled to the second output terminal, and a gate of the sixth FET coupled to the first output terminal. The voltage level translator circuit further includes a first bypass circuit coupled from the first output terminal to the gate of the third FET, and a second bypass circuit coupled from the second output terminal to the gate of the fourth FET.

[0054] Example 2 includes a voltage level converter circuit according to Example 1, wherein the floating supply terminal is a first supply terminal and the voltage level converter circuit further includes an inverter configured to generate an inverted version of the input signal, the inverter being coupled to a second (e.g., low voltage) supply terminal.

[0055] Example 3 includes the voltage level translator circuit of Example 1 or 2, wherein the drain of the fifth FET is coupled to the first output terminal through a first resistor, and the drain of the sixth FET is coupled to the second output terminal through a second resistor.

[0056] Example 4 includes the voltage level translator circuit of any of Examples 1-3, wherein the input signal is a pulse width modulated signal.

[0057] Example 5 includes the voltage level translator circuit of any of Examples 1 to 4, wherein the first and second FETs are each an n-type FET (NFET), and the third and fourth FETs are each a p-type FET (PFET). In some examples, the first, second, third, and fourth FETs are high voltage FETs.

[0058] Example 6 includes a voltage level converter circuit according to any one of Examples 1 to 5, which further includes a differential output latch circuit, wherein the differential output latch circuit has a first input coupled to the first output terminal, a second input coupled to the second output terminal, a first latch output, and a second latch output.

[0059] Example 7 includes a voltage level converter circuit according to Example 6, and further includes a logic latch circuit having a first input coupled to the first latch output of the differential output latch, a second input coupled to the second latch output of the differential output latch, and a third latch output.

[0060] Example 8 includes the voltage level translator circuit of Example 7 and additionally includes a buffer or driver circuit configured to receive the third latch output and provide an output signal.

[0061] Example 9 includes a voltage level converter circuit according to any one of Examples 1 to 8, wherein: the first bypass circuit includes a seventh FET and an eighth FET, the drain of the seventh FET is coupled to the first output terminal, the source of the seventh FET is coupled to the source of the eighth FET, the drain of the eighth FET is coupled to the gate of the third FET, and the gates of the seventh and eighth FETs are configured to receive the input signal; and the second bypass circuit includes a ninth FET and a tenth FET, the drain of the ninth FET is coupled to the second output terminal, the source of the ninth FET is coupled to the source of the tenth FET, the drain of the tenth FET is coupled to the gate of the fourth FET, and the gates of the ninth and tenth FETs are configured to receive the inverted version of the input signal.

[0062] Example 10 includes the voltage level translator circuit of Example 9, wherein each of the seventh, eighth, ninth, and tenth FETs is an n-type FET (NMOS) FET. In some examples, the seventh, eighth, ninth, and tenth FETs are high voltage FETs.

[0063] Example 11 is an integrated circuit comprising the voltage level converter circuit according to any one of Examples 1 to 10.

[0064] Example 12 includes the integrated circuit of Example 11, further comprising a power converter driver including the voltage level translator circuit.

[0065] Example 13 includes the integrated circuit of Example 12, the power converter driver being a high-side low-side driver, and the voltage level shifter circuit being part of a high-side driver circuit of the high-side low-side driver. In a specific example, the integrated circuit includes a high-side low-side driver, the high-side low-side driver including the voltage level shifter circuit of any one of Examples 1 to 10, the voltage level shifter circuit being part of a high-side driver circuit of the high-side low-side driver.

[0066] Example 14 is a system further comprising the integrated circuit according to any one of Examples 11 to 13.

[0067] Example 15 includes the system of example 14, wherein the system is a power converter.

[0068] Example 16 includes a system according to Example 14, wherein the system is a power supply.

[0069] Example 17 includes the system of Example 14, wherein the system is an amplifier.

[0070] Example 18 is an adaptive bypass circuit for a floating level converter. The circuit can convert a voltage level from a first voltage domain (e.g., a low voltage domain) to a second voltage domain (e.g., a high voltage domain). The adaptive bypass circuit includes a switching circuit and a comparator circuit. The switching circuit is coupled across a protection element (e.g., a high voltage protection element) of the floating level converter. The comparator circuit is configured to activate the switching circuit to bypass the protection element in response to a reference rail of the second voltage domain being less than a threshold (e.g., where HVSS is less than LVDD and thus indicates a low voltage operation), and deactivate the switching circuit in response to the reference rail of the second voltage domain being not less than the threshold (e.g., where HVSS is not less than LVDD and thus does not indicate a low voltage operation), so as not to bypass the protection element.

[0071] Example 19 includes the adaptive bypass circuit of Example 18, wherein the switching circuit and the comparator circuit are implemented by a pair of field effect transistors (FETs) arranged in a back-to-back configuration.

[0072] Example 20 includes the adaptive bypass circuit of Example 19, wherein the pair of FETs includes a first n-type FET (NFET) and a second NFET, and the protection element includes a p-type FET (PFET).

[0073] Example 21 includes an adaptive bypass circuit according to Example 20, wherein the drain of the first NFET is coupled to the source of the protection element, the source of the first NFET is coupled to the source of the second NFET, the drain of the second NFET is coupled to the gate of the protection element, and the gates of the first and second NFETs are configured to receive an input signal of the floating level converter.

[0074] Example 22 includes an adaptive bypass circuit according to Example 21, wherein the drain of a third NFET is coupled to the source of an additional protection element of the floating level converter, the source of the third NFET is coupled to the source of a fourth NFET, the drain of the fourth NFET is coupled to the gate of the additional protection element, and the gates of the third and fourth NFETs are configured to receive an inverted version of the input signal of the floating level converter.

[0075] Example 23 is an integrated circuit, which also includes the adaptive bypass circuit according to Example 18.

[0076] Example 24 includes the integrated circuit of Example 23, further comprising a power converter driver including the adaptive bypass circuit.

[0077] Example 25 includes the integrated circuit of Example 24, the power converter driver being a high-side low-side driver, and the adaptive bypass circuit being part of a high-side driver circuit of the high-side low-side driver.

[0078] Example 26 is a system further comprising the integrated circuit according to any one of Examples 23 to 25.

[0079] Example 27 includes the system of Example 27, wherein the system is a power converter.

[0080] Example 28 includes the system of Example 27, wherein the system is a power supply.

[0081] Example 29 includes the system of Example 27, wherein the system is an amplifier.

[0082] Example 30 is a voltage level converter circuit. The voltage level converter circuit includes a first n-type field effect transistor (NFET) and a second NFET, the first NFET and the second NFET each having a respective source coupled to a ground terminal, a gate of the first NFET configured to receive a pulse width modulated (PWM) input signal, and a gate of the second NFET configured to receive an inverted version of the PWM input signal. The voltage level converter circuit further includes a first p-type field effect transistor (PFET) and a second PFET, the first PFET and the second PFET each having a respective gate coupled to a floating (e.g., high voltage) supply reference terminal, a drain of the first PFET coupled to a drain of the first NFET, a drain of the second PFET coupled to a drain of the second NFET, a source of the first PFET coupled to a first output terminal, and a source of the second PFET coupled to a second output terminal. The voltage level translator circuit further includes a third PFET and a fourth PFET, each having a respective source coupled to a floating (e.g., high voltage) supply terminal, a drain of the third PFET coupled to the first output terminal, a drain of the fourth PFET coupled to the second output terminal, a gate of the third PFET coupled to the second output terminal, and a gate of the fourth PFET coupled to the first output terminal. The voltage level translator circuit further includes a first bypass circuit coupled from the first output terminal to the gate of the first PFET, and a second bypass circuit coupled from the second output terminal to the gate of the second PFET.

[0083] Example 31 includes a voltage level converter circuit according to Example 30, wherein the floating supply terminal is a first supply terminal and the example further includes an inverter configured to generate an inverted version of the PWM input signal, the inverter being coupled to a second (e.g., low voltage) supply terminal.

[0084] Example 32 includes the voltage level translator circuit of Example 30 or 31, wherein the drain of the third PFET is coupled to the first output terminal through a first resistor, and the drain of the fourth PFET is coupled to the second output terminal through a second resistor.

[0085] Example 33 includes the voltage level translator circuit of any of Examples 30-32, wherein the first and second NFETs are each a high voltage NFET and the first and second PFETs are each a high voltage PFET.

[0086] Example 34 includes a voltage level converter circuit according to any one of Examples 30 to 33, and further includes a differential output latch circuit having a first input coupled to the first output terminal, a second input coupled to the second output terminal, a first latch output, and a second latch output.

[0087] Example 35 includes a voltage level converter circuit according to Example 34, and further includes a logic latch circuit having a first input coupled to the first latch output of the differential output latch, a second input coupled to the second latch output of the differential output latch, and a third latch output.

[0088] Example 36 includes the voltage level translator circuit of Example 35 and additionally includes a buffer or driver circuit configured to receive the third latch output and provide a PWM output signal.

[0089] Example 37 includes a voltage level translator circuit according to any of Examples 30 to 36, wherein the first bypass circuit includes a third NFET and a fourth NFET, the drain of the third NFET being coupled to the first output terminal, the source of the third NFET being coupled to the source of the fourth NFET, the drain of the fourth NFET being coupled to the gate of the first PFET, and the gates of the third and fourth NFETs being configured to receive the PWM input signal. Additionally, the second bypass circuit includes a fifth NFET and a sixth NFET, the drain of the fifth NFET being coupled to the second output terminal, the source of the fifth NFET being coupled to the source of the sixth NFET, the drain of the sixth NFET being coupled to the gate of the second PFET, and the gates of the fifth and sixth NFETs being configured to receive the inverted version of the PWM input signal.

[0090] Example 38 includes the voltage level translator circuit of Example 37, wherein each of the third, fourth, fifth, and sixth NFETs is a high voltage NFET.

[0091] Example 39 is an integrated circuit further comprising the voltage level translator circuit according to any one of Examples 30 to 38.

[0092] Example 40 includes the integrated circuit of Example 39, further comprising a power converter driver including the voltage level translator circuit.

[0093] Example 41 includes the integrated circuit of Example 40, the power converter driver being a high-side low-side driver, and the adaptive bypass circuit being part of a high-side driver circuit of the high-side low-side driver.

[0094] Example 42 is a system further comprising an integrated circuit according to any one of Examples 39 to 41.

[0095] Example 43 includes the system of Example 42, wherein the system is a power converter.

[0096] Example 44 includes a system according to Example 42, wherein the system is a power supply.

[0097] Example 45 includes a system according to Example 42, wherein the system is an amplifier.

[0098] Modifications of the described embodiments are possible, and other embodiments are possible, within the scope of the claims.

[0099] In this description, the term "coupled" may encompass connections, communications, or signal paths that enable a functional relationship consistent with this description. For example, if device A generates a signal to control device B to perform an action, then: (a) in a first instance, device A is coupled to device B through a direct connection; or (b) in a second instance, device A is coupled to device B through an intermediate component C, provided that the intermediate component C does not change the functional relationship between device A and device B, so that device B is controlled by device A through the control signal generated by device A.

[0100] A device "configured to" perform a task or function may be configured (e.g., programmed and / or hardwired) to perform the function when manufactured by a manufacturer, and / or may be configurable (or reconfigurable) by a user after manufacture to perform the function and / or other additional or alternative functions. The configuration may be performed through firmware and / or software programming of the device, through the construction and / or layout of hardware components and interconnection of the device, or a combination thereof.

[0101] As used herein, the terms "terminal", "node", "interconnect", "pin" and "lead" are used interchangeably. Unless specifically stated to the contrary, these terms are generally used to refer to the interconnections between device elements, circuit elements, integrated circuits, devices or other electronic or semiconductor components or their ends.

[0102] A circuit or device described herein as including certain components may actually be adapted to be coupled to those components to form the described circuit system or device. For example, a structure described as including one or more semiconductor elements (e.g., transistors), one or more passive elements (e.g., resistors, capacitors, and / or inductors), and / or one or more sources (e.g., voltage and / or current sources) may actually include only semiconductor elements within a single physical device (e.g., a semiconductor die and / or integrated circuit (IC) package), and may be adapted to be coupled to at least some of the passive elements and / or sources to form the described structure, e.g., during or after manufacture, by an end user and / or a third party.

[0103] Although the use of specific transistors is described herein, other transistors (or equivalent devices) may be used instead. For example, a p-channel field effect transistor (PFET) may be used in place of an n-channel field effect transistor (NFET) with little or no change to the circuit. Furthermore, other types of transistors (e.g., bipolar junction transistors (BJTs)) may be used. Furthermore, the device may be implemented in / on any number of substrates, such as a silicon substrate (Si), a silicon carbide substrate (SiC), a gallium nitride substrate (GaN), or a gallium arsenide substrate (GaAs).

[0104] Reference herein to a field effect transistor (FET) being "on" means that there is a conduction channel of the FET and drain current can flow through the FET. Reference herein to a FET being "off" means that there is no conduction channel, and therefore drain current does not flow through the FET. However, an off FET can have current flowing through the body diode of the transistor.

[0105] The circuits described herein may be reconfigured to include additional components or different components to provide functionality at least partially similar to functionality available prior to component replacement. Unless otherwise specified, components shown as resistors generally represent any one or more elements coupled in series and / or in parallel to provide the amount of impedance represented by the resistor shown. For example, a resistor or capacitor shown and described herein as a single component may alternatively be a plurality of resistors or capacitors coupled in parallel between the same nodes, respectively. For example, a resistor or capacitor shown and described herein as a single component may actually be a plurality of resistors or capacitors coupled in series between the same two nodes as a single resistor or capacitor, respectively.

[0106] The use of the phrase "ground" in the foregoing description includes chassis ground, ground wire ground, floating ground, virtual ground, digital ground, universal ground, and / or any other form of ground connection that is applicable or suitable for the teachings of this specification. In this specification, unless otherwise specified, "about", "substantially" or "substantially" before a parameter means within + / -10% of the parameter.

Claims

1. A voltage level converter circuit, comprising: a first field effect transistor (FET) and a second FET, the first FET and the second FET each having a respective source coupled to a first supply reference terminal, a gate of the first FET configured to receive an input signal, and a gate of the second FET configured to receive an inverted version of the input signal; a third FET and a fourth FET, each having a respective gate coupled to a floating second supply reference terminal, a drain of the third FET coupled to the drain of the first FET, a drain of the fourth FET coupled to the drain of the second FET, a source of the third FET coupled to the first output terminal, and a source of the fourth FET coupled to the second output terminal; a fifth FET and a sixth FET, each having a respective source coupled to a floating supply terminal, a drain of the fifth FET coupled to the first output terminal, a drain of the sixth FET coupled to the second output terminal, a gate of the fifth FET coupled to the second output terminal, and a gate of the sixth FET coupled to the first output terminal; as well as A first bypass circuit is coupled from the first output terminal to the gate of the third FET, and a second bypass circuit is coupled from the second output terminal to the gate of the fourth FET.

2. The voltage level translator circuit of claim 1, wherein the floating supply terminal is a first supply terminal, the voltage level translator circuit further comprising an inverter configured to generate the inverted version of the input signal, the inverter coupled to a second supply terminal. 3 . The voltage level converter circuit of claim 1 , wherein the drain of the fifth FET is coupled to the first output terminal through a first resistor, and the drain of the sixth FET is coupled to the second output terminal through a second resistor.

4. The voltage level converter circuit according to claim 1, wherein the input signal is a pulse width modulated signal. 5 . The voltage level translator circuit of claim 1 , wherein the first and second FETs are each an n-type FET (NFET), and the third and fourth FETs are each a p-type FET (PFET).

6. The voltage level translator circuit of claim 1, further comprising a differential output latch circuit having a first input coupled to the first output terminal, a second input coupled to the second output terminal, a first latch output, and a second latch output.

7. The voltage level converter circuit of claim 6 , further comprising a logic latch circuit having a first input coupled to the first latch output of the differential output latch, a second input coupled to the second latch output of the differential output latch, and a third latch output.

8. The voltage level translator circuit of claim 7, further comprising a buffer or driver circuit configured to receive the third latch output and provide an output signal.

9. The voltage level converter circuit according to claim 1, wherein: the first bypass circuit comprising a seventh FET and an eighth FET, the drain of the seventh FET being coupled to the first output terminal, the source of the seventh FET being coupled to the source of the eighth FET, the drain of the eighth FET being coupled to the gate of the third FET, and the gates of the seventh and eighth FETs being configured to receive the input signal; and The second bypass circuit includes a ninth FET and a tenth FET, the drain of the ninth FET being coupled to the second output terminal, the source of the ninth FET being coupled to the source of the tenth FET, the drain of the tenth FET being coupled to the gate of the fourth FET, and the gates of the ninth and tenth FETs being configured to receive the inverted version of the input signal.

10. The voltage level translator circuit of claim 9, wherein each of the seventh, eighth, ninth, and tenth FETs is an n-type FET (NMOS) FET.

11. An integrated circuit comprising a high-side low-side driver, the high-side low-side driver including the voltage level shifter circuit according to claim 1, the voltage level shifter circuit being part of a high-side driver circuit of the high-side low-side driver.

12. An adaptive bypass circuit for a floating level converter, the floating level converter configured to convert a voltage level from a first voltage domain to a second voltage domain, the adaptive bypass circuit comprising: a switching circuit coupled across a protection element of the floating level converter; as well as A comparator circuit is configured to activate the switching circuit to bypass the protection element in response to a reference rail of the second voltage domain being less than a threshold, and to deactivate the switching circuit so as not to bypass the protection element in response to the reference rail of the second voltage domain being not less than the threshold.

13. The adaptive bypass circuit of claim 12, wherein the switching circuit and the comparator circuit are implemented by a pair of field effect transistors (FETs) arranged in a back-to-back configuration.

14. The adaptive bypass circuit of claim 13, wherein the pair of FETs comprises a first n-type FET (NFET) and a second NFET, and the protection element comprises a p-type FET (PFET).

15. The adaptive bypass circuit of claim 14, wherein the drain of the first NFET is coupled to the source of the protection element, the source of the first NFET is coupled to the source of the second NFET, the drain of the second NFET is coupled to the gate of the protection element, and the gates of the first and second NFETs are configured to receive an input signal of the floating level converter.

16. The adaptive bypass circuit of claim 15 , wherein a drain of a third NFET is coupled to a source of an additional protection element of the floating level converter, a source of the third NFET is coupled to a source of a fourth NFET, a drain of the fourth NFET is coupled to a gate of the additional protection element, and gates of the third and fourth NFETs are configured to receive an inverted version of the input signal of the floating level converter.

17. A voltage level converter circuit, comprising: a first n-type field effect transistor (NFET) and a second NFET, the first NFET and the second NFET each having a respective source coupled to a ground terminal, the first NFET having a gate configured to receive a pulse width modulated (PWM) input signal, and the second NFET having a gate configured to receive an inverted version of the PWM input signal; a first p-type field effect transistor (PFET) and a second PFET, the first PFET and the second PFET each having a respective gate coupled to a floating supply reference terminal, a drain of the first PFET coupled to a drain of the first NFET, a drain of the second PFET coupled to a drain of the second NFET, a source of the first PFET coupled to a first output terminal, and a source of the second PFET coupled to a second output terminal; a third PFET and a fourth PFET, each having a respective source coupled to the floating first supply terminal, a drain of the third PFET coupled to the first output terminal, a drain of the fourth PFET coupled to the second output terminal, a gate of the third PFET coupled to the second output terminal, and a gate of the fourth PFET coupled to the first output terminal; a first bypass circuit coupled from the first output terminal to the gate of the first PFET, and a second bypass circuit coupled from the second output terminal to the gate of the second PFET; as well as An inverter configured to generate the inverted version of the PWM input signal, the inverter being coupled to a second supply terminal.

18. The voltage level translator circuit of claim 17, wherein the drain of the third PFET is coupled to the first output terminal through a first resistor, and the drain of the fourth PFET is coupled to the second output terminal through a second resistor.

19. The voltage level translator circuit of claim 17, wherein the first and second NFETs are each NFETs and the first and second PFETs are each PFETs.

20. The voltage level translator circuit of claim 17, wherein: the first bypass circuit comprising a third NFET and a fourth NFET, the drain of the third NFET being coupled to the first output terminal, the source of the third NFET being coupled to the source of the fourth NFET, the drain of the fourth NFET being coupled to the gate of the first PFET, and the gates of the third and fourth NFETs being configured to receive the PWM input signal; the second bypass circuit includes a fifth NFET and a sixth NFET, the drain of the fifth NFET being coupled to the second output terminal, the source of the fifth NFET being coupled to the source of the sixth NFET, the drain of the sixth NFET being coupled to the gate of the second PFET, and the gates of the fifth and sixth NFETs being configured to receive the inverted version of the PWM input signal; and Each of the third, fourth, fifth and sixth NFETs is a NFET.

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