Receiver, RF transceiver and terminal

Abstract

This application provides a receiver, an RF transceiver, and a terminal, relating to the field of integrated circuit technology. It allows the use of existing components in the receiver to replace a vector synthesis phase shifter for adjusting the phase of the RF signal. The RF signal received by the receiver is amplified by a first adjustable RF amplifier to output a first RF amplified signal, and then amplified by a second adjustable RF amplifier to output a second RF amplified signal. The first RF amplified signal is mixed by a first in-phase mixer to output a first in-phase intermediate frequency (IF) signal, and then mixed by a first quadrature mixer to output a first quadrature IF signal. The second RF amplified signal is mixed by a second quadrature mixer to output a second quadrature IF signal, and then mixed by a second in-phase mixer to output a second in-phase IF signal. The first in-phase IF signal and the second quadrature IF signal are selectively added to or subtracted by a first adder / subtractor; the first quadrature IF signal and the second in-phase IF signal are selectively added to or subtracted by a second adder / subtractor.

Description

Technical Field

[0001] This application relates to the field of integrated circuit technology, and more particularly to a receiver, radio frequency transceiver, and terminal. Background Technology

[0002] To meet the demands of high-speed modern wireless communication, such as the millimeter-wave band of 5G communication and terahertz (THz) imaging, the operating frequency of wireless communication systems is becoming increasingly higher.

[0003] To overcome the high path loss in high-frequency wireless transmission, phased-array technology is widely used in wireless communication systems such as radar and communications, for example, in phased-array receivers. A traditional phased-array receiver includes a vector synthesizer phase shifter, a variable gain amplifier (VGA), and a mixer. The vector synthesizer phase shifter adjusts signals received from different antennas to the same phase and superimposes them to enhance the signal-to-noise ratio of the received signal. The variable gain amplifier is used to control the amplitude and phase of the signal on each receiving path. The mixer down-mixes the RF signal to baseband for signal demodulation.

[0004] However, the independent operation of the vector synthesis phase shifter and the variable gain amplifier leads to increased power consumption in the receiver circuitry. Summary of the Invention

[0005] To address the aforementioned technical problems, this application provides a receiver, an RF transceiver, and a terminal that can utilize existing components in the receiver to replace traditional vector synthesis phase shifters in order to adjust the phase of the received RF signal.

[0006] In a first aspect, this application provides a receiver comprising a first adjustable RF amplifier, a second adjustable RF amplifier, a first in-phase mixer, a first quadrature mixer, a second quadrature mixer, a second in-phase mixer, a first adder / subtractor, and a second adder / subtractor. The receiver is used to receive RF signals. The RF signal is amplified by the first adjustable RF amplifier to output a first RF amplified signal, and the RF signal is amplified by the second adjustable RF amplifier to output a second RF amplified signal. The first RF amplified signal is mixed by the first in-phase mixer to output a first in-phase intermediate frequency (IF) signal, and then mixed by the first quadrature mixer to output a first quadrature IF signal; the second RF amplified signal is mixed by the second quadrature mixer to output a second quadrature IF signal, and then mixed by the second in-phase mixer to output a second in-phase IF signal. The first in-phase IF signal and the second quadrature IF signal are selectively added or subtracted by the first adder / subtractor to output a first composite signal; the first quadrature IF signal and the second in-phase IF signal are selectively added or subtracted by the second adder / subtractor to output a second composite signal.

[0007] Those skilled in the art will know that the working principle of the vector synthesis phase shifter 1012 is to achieve the phase shifting function by changing the ratio of two orthogonal signals.

[0008] The first adder / subtractor receives a first in-phase intermediate frequency (IF) signal and a second quadrature IF signal. Furthermore, since the radio frequency (RF) signal forming the first in-phase IF signal is amplified by a first adjustable RF amplifier, and the RF signal forming the second quadrature IF signal is amplified by a second adjustable RF amplifier, the ratio of the first in-phase IF signal to the second quadrature IF signal can be adjusted by regulating the gains of the first and second adjustable RF amplifiers, thereby replacing the existing vector synthesis phase shifter and achieving phase shifting functionality.

[0009] The second adder / subtractor receives a first quadrature intermediate frequency (IF) signal and a second in-phase IF signal. Furthermore, since the radio frequency (RF) signal forming the first quadrature IF signal is amplified by a first adjustable RF amplifier, and the RF signal forming the second in-phase IF signal is amplified by a second adjustable RF amplifier, the ratio of the first quadrature IF signal to the second in-phase IF signal can be adjusted by regulating the gains of the first and second adjustable RF amplifiers, thereby replacing the existing vector synthesis phase shifter and achieving phase shifting functionality.

[0010] In summary, this application can utilize existing first adjustable RF amplifiers, second adjustable RF amplifiers, first in-phase mixers, first quadrature mixers, second quadrature mixers, second in-phase mixers, first adders / subtractors, and second adders / subtractors to replace traditional vector synthesis phase shifters to adjust the phase of the received RF signal, thus saving receiver layout area and power consumption. Furthermore, since this application integrates the first adjustable RF amplifier, second adjustable RF amplifier, first in-phase mixer, first quadrature mixer, second quadrature mixer, second in-phase mixer, first adder / subtractor, and second adder / subtractor—which implement amplification, phase shifting, and mixing functions—into a single unit, the integration density of the receiver is significantly improved, thereby reducing parasitic capacitance and inductance in the receiver.

[0011] Furthermore, the first and second adjustable RF amplifiers can also adjust the amplitude of the RF signal. Moreover, since the first adder / subtractor selectively adds or subtracts the first in-phase IF signal and the second quadrature IF signal through vector synthesis, and the second adder / subtractor selectively adds or subtracts the first quadrature IF signal and the second in-phase IF signal through vector synthesis, the first in-phase IF signal and the first quadrature IF signal are amplified by the first adjustable RF amplifier, and the second quadrature IF signal and the second in-phase IF signal are amplified by the second adjustable RF amplifier. Therefore, even if the gain of the first and / or second adjustable RF amplifiers is changed, the amplitude of the vector synthesis result of the first in-phase IF signal and the second quadrature IF signal remains the same as that of the vector synthesis result of the first quadrature IF signal and the second in-phase IF signal.

[0012] In some possible implementations, a first adjustable RF amplifier amplifies the RF signal with an adjustable first gain; a second adjustable RF amplifier amplifies the RF signal with an adjustable second gain. The number of bits for the first and second gains can be designed according to the actual required amplitude and phase. Since the number of bits for the first and second gains themselves contains multiple states, adjusting the phase of the RF signal by adjusting the magnitudes of the first and second gains does not require increasing the number of bits in the control circuit.

[0013] For example, the first gain has 3 bits, including 8 states: 000, 001, 010, 011, 100, 101, 110, and 111. The second gain has 3 bits, including 8 states: 000, 001, 010, 011, 100, 101, 110, and 111.

[0014] In some possible implementations, the first RF amplified signal and the first local oscillator signal can be mixed by a first in-phase mixer to output a first in-phase intermediate frequency (IF) signal. The first RF amplified signal and the second local oscillator signal can be mixed by a first quadrature mixer to output a first quadrature IF signal. The second RF amplified signal and the second local oscillator signal can be mixed by a second quadrature mixer to output a second quadrature IF signal. The second RF amplified signal and the first local oscillator signal can be mixed by a second in-phase mixer to output a second in-phase IF signal. Furthermore, the first local oscillator signal and the second local oscillator signal are orthogonal, such that the first in-phase IF signal is orthogonal to the second quadrature IF signal, and the first quadrature IF signal is orthogonal to the second in-phase IF signal; the phase of the first in-phase IF signal is the same as the phase of the second in-phase IF signal, and the phase of the first quadrature IF signal is the same as the phase of the second quadrature IF signal.

[0015] In some possible implementations, the receiver also includes control circuitry, which includes a control code generator for inputting a first gain to a first adjustable RF amplifier and a second gain to a second adjustable RF amplifier. On one hand, the control circuitry can enable the first and second adjustable RF amplifiers to have variable gain functionality by outputting the first and second gains, thereby adjusting the amplitude and phase of the RF signal.

[0016] In some possible implementations, the control circuit further includes a symbol code generator, which inputs a first digital signal and a third digital signal to the first adder / subtractor, and a second digital signal and a fourth digital signal to the second adder / subtractor. The first digital signal is used to determine whether the phase of the first in-phase intermediate frequency signal is positive or negative; the second digital signal is used to determine whether the phase of the first quadrature intermediate frequency signal is positive or negative; the third digital signal is used to determine whether the phase of the second quadrature intermediate frequency signal is positive or negative; and the fourth digital signal is used to determine whether the phase of the second in-phase intermediate frequency signal is positive or negative.

[0017] For example, if the first digital signal is 1, the phase of the first in-phase intermediate frequency signal is positive; if the first digital signal is 0, the phase of the first in-phase intermediate frequency signal is negative; if the second digital signal is 1, the phase of the first quadrature intermediate frequency signal is positive; if the second digital signal is 0, the phase of the first quadrature intermediate frequency signal is negative; if the third digital signal is 1, the phase of the second quadrature intermediate frequency signal is positive; if the third digital signal is 0, the phase of the second quadrature intermediate frequency signal is negative; if the fourth digital signal is 1, the phase of the second in-phase intermediate frequency signal is positive; if the fourth digital signal is 0, the phase of the second in-phase intermediate frequency signal is negative.

[0018] In some possible implementations, based on the first digital signal and the third digital signal, the first adder / subtractor performs vector synthesis on the first in-phase intermediate frequency signal with positive / negative phase and the second quadrature intermediate frequency signal with positive / negative phase to obtain the first synthesized signal. Alternatively, the first adder / subtractor adds or subtracts the first in-phase intermediate frequency signal with positive phase and the second quadrature intermediate frequency signal with positive phase, or adds or subtracts the first in-phase intermediate frequency signal with negative phase and the second quadrature intermediate frequency signal with positive phase, to obtain the first synthesized signal.

[0019] Based on the second and fourth digital signals, the second adder / subtractor performs vector synthesis on the first quadrature intermediate frequency (IF) signal with positive / negative phase and the second in-phase IF signal with positive / negative phase, to obtain the second synthesized signal. Alternatively, the second adder / subtractor adds or subtracts the first quadrature IF signal with positive phase and the second in-phase IF signal with positive phase, or adds or subtracts the first quadrature IF signal with negative phase and the second in-phase IF signal with positive phase, to obtain the second synthesized signal.

[0020] Furthermore, since both the first and second synthesized signals include intermediate frequency signals amplified by the first and second gains, they have the same amplitude. Based on the first, second, third, and fourth digital signals, the first and second synthesized signals can be controlled to have orthogonal phases. Therefore, the receiver also includes a differential circuit and a phase shifter. The phase shifter is coupled between the first adder / subtractor and the differential circuit to perform a 90° phase shift on the first synthesized signal; or, the phase shifter is coupled between the second adder / subtractor and the differential circuit to perform a 90° phase shift on the second synthesized signal. The differential circuit is used to add the second synthesized signal and the phase-shifted first synthesized signal, or the first synthesized signal and the phase-shifted second synthesized signal, to filter out image interference signals in the first and second synthesized signals.

[0021] In some possible implementations, the phase shifter can be coupled to the positive input of the differential circuit; alternatively, the phase shifter can also be coupled to the negative input of the differential circuit. If the phase shifter is coupled to the first adder / subtractor for phase shifting the first synthesized signal, and the negative input of the differential circuit is coupled to the phase shifter and the positive input is coupled to the second adder / subtractor, a truth table can be determined based on quadrant control codes and image suppression modes. If the phase shifter is coupled to the first adder / subtractor for phase shifting the first synthesized signal, and the positive input of the differential circuit is coupled to the phase shifter and the negative input is coupled to the second adder / subtractor, another truth table can be determined based on quadrant control codes and image suppression modes. If the phase shifter is coupled to the second adder / subtractor for phase shifting the second synthesized signal, and the negative input of the differential circuit is coupled to the phase shifter and the positive input is coupled to the first adder / subtractor, yet another truth table can be determined based on quadrant control codes and image suppression modes. If the phase shifter is coupled to the second adder / subtractor to phase-shift the second synthesized signal, and the positive input of the differential circuit is coupled to the phase shifter, while the negative input is coupled to the first adder / subtractor, then another truth table can be determined based on the quadrant control code and the image suppression mode. Then, based on the data in the truth table, the first, second, third, and fourth digital signals are determined to be either 0 or 1.

[0022] In some possible implementations, the radio frequency (RF) signal includes a first RF signal and a second RF signal, which are mirror-symmetric about either the first or second local oscillator signal; both the first and second synthesized signals include the first and second signals; the first signal is obtained by amplifying and mixing the first RF signal, and the second signal is obtained by amplifying and mixing the second RF signal. The first signal is the useful signal, and the second signal is the mirror interference signal; or, the first signal is the mirror interference signal, and the second signal is the useful signal.

[0023] In this application, by pre-selecting the aforementioned truth table, a first digital signal, a second digital signal, a third digital signal, and a fourth digital signal are determined. Based on these signals, either the first signal or the second signal is filtered out to resolve the image interference problem. Furthermore, based on the first, second, third, and fourth digital signals, the quadrants containing the retained second signal and the first signal can be selected; in other words, the phases of the retained second signal and the first signal can be selected.

[0024] In some possible implementations, the control code generator is coupled to the symbol code generator. The symbol code generator is also used to receive the image suppression control code and the quadrant control code sent by the control code generator, and, based on the quadrant control code, the image suppression control code, the coupling relationship between the phase shifter and the first and second adders / subtractors, and the coupling relationship between the phase shifter and the input of the differential circuit, inputs a first digital signal and a third digital signal to the first adder / subtractor, and inputs a second digital signal and a fourth digital signal to the second adder / subtractor (or, determines the truth table mentioned above). The quadrant control code is used to characterize the quadrant in which the useful signal resides; the image suppression mode is used to characterize whether the first signal or the second signal is a useful signal.

[0025] Specifically, the symbol code generator, based on the quadrant control code, the image suppression control code, the coupling relationship between the phase shifter and the first and second adders / subtractors, and the coupling relationship between the phase shifter and the input terminal of the differential circuit, inputs a first digital signal and a third digital signal to the first adder / subtractor, and inputs a second digital signal and a fourth digital signal to the second adder / subtractor in the following two ways:

[0026] The first type includes a symbol code generator comprising a first switch, a second switch, a third switch, a fourth switch, a first inverter, and a second inverter; a first adder / subtractor comprises a first differential circuit and a second differential circuit. The symbol code generator generates a first initial digital signal; the first and second switches are connected in parallel; the first switch receives a first in-phase intermediate frequency (IF) signal and the first initial digital signal; the second switch is coupled to the first inverter and receives the first in-phase IF signal and the inverted first initial digital signal. The symbol code generator also generates a third initial digital signal; the third and fourth switches are connected in parallel; the third switch receives a second quadrature IF signal and the third initial digital signal; the fourth switch is coupled to the second inverter and receives the second quadrature IF signal and the inverted third initial digital signal. The outputs of the first and second switches are coupled to the input of the first differential circuit, the outputs of the third and fourth switches are coupled to the input of the second differential circuit, and the outputs of both the first and second differential circuits are coupled to the input of the differential circuit.

[0027] The symbol code generator also includes a fifth switch, a sixth switch, a seventh switch, an eighth switch, a third inverter, and a fourth inverter; the second adder / subtractor includes a third differential circuit and a fourth differential circuit. The symbol code generator is used to generate a second initial digital signal; the fifth and sixth switches are connected in parallel; the fifth switch is used to receive the first quadrature intermediate frequency (IF) signal and the second initial digital signal; the sixth switch is coupled to the third inverter and is used to receive the first quadrature IF signal and the inverted second initial digital signal. The symbol code generator is also used to generate a fourth initial digital signal; the seventh and eighth switches are connected in parallel; the seventh switch is used to receive the second in-phase IF signal and the fourth initial digital signal; the eighth switch is coupled to the fourth inverter and is used to receive the second in-phase IF signal and the inverted fourth initial digital signal. The outputs of the fifth and sixth switches are coupled to the input of the third differential circuit, the outputs of the seventh and eighth switches are coupled to the input of the fourth differential circuit, and the outputs of both the third and fourth differential circuits are coupled to the input of the differential circuit.

[0028] Based on this circuit, the specific processes of the symbol code generator and the first and second adders / subtractors can include the following, so as to enable the first in-phase intermediate frequency signal and the second quadrature intermediate frequency signal to be selectively added or subtracted through the first adder / subtractor, and the first quadrature intermediate frequency signal and the second in-phase intermediate frequency signal to be selectively added or subtracted through the second adder / subtractor:

[0029] If the first switch is coupled to the positive input terminal of the first differential circuit, and the second switch is coupled to the negative input terminal of the first differential circuit, then the first initial digital signal input to the first and second switches is 1. If the required first digital signal is 1, the first switch can be turned on and the second switch can be turned off, and the first in-phase intermediate frequency signal is input to the positive input terminal of the first differential circuit through the first switch and output from the first differential circuit; if the required first digital signal is 0, the first switch can be turned off and the second switch can be turned on, and the first in-phase intermediate frequency signal is input to the negative input terminal of the first differential circuit through the second switch, and the first differential circuit inverts the first in-phase intermediate frequency signal and outputs it.

[0030] Alternatively, if the first switch is coupled to the negative input terminal of the first differential circuit and the second switch is coupled to the positive input terminal of the first differential circuit, then the first initial digital signal input to the first and second switches is 0. If the required first digital signal is 1, the first switch can be controlled to open and the second switch to open, and the first in-phase intermediate frequency signal is input to the positive input terminal of the first differential circuit through the second switch and output from the first differential circuit; if the required first digital signal is 0, the first switch can be controlled to open and the second switch to open, and the first in-phase intermediate frequency signal is input to the negative input terminal of the first differential circuit through the first switch, and the first differential circuit inverts the first in-phase intermediate frequency signal and outputs it.

[0031] If the third switch is coupled to the positive input terminal of the second differential circuit, and the fourth switch is coupled to the negative input terminal of the second differential circuit, then the third initial digital signal input to the third and fourth switches is 1. If the required third digital signal is 1, the third switch can be turned on and the fourth switch can be turned off. The second quadrature intermediate frequency signal is input to the positive input terminal of the second differential circuit through the third switch and output from the second differential circuit. If the required third digital signal is 0, the third switch can be turned off and the fourth switch can be turned on. The second quadrature intermediate frequency signal is input to the negative input terminal of the second differential circuit through the fourth switch. The second differential circuit inverts the second quadrature intermediate frequency signal and outputs it.

[0032] Alternatively, if the third switch is coupled to the negative input of the second differential circuit and the fourth switch is coupled to the positive input of the second differential circuit, then the third initial digital signal input to the third and fourth switches is 0. If the required third digital signal is 1, the third switch can be controlled to open and the fourth switch to open, and the second quadrature intermediate frequency signal is input to the positive input of the second differential circuit through the fourth switch and output from the second differential circuit; if the required third digital signal is 0, the third switch can be controlled to open and the fourth switch to open, and the second quadrature intermediate frequency signal is input to the negative input of the second differential circuit through the third switch, and the second differential circuit inverts the second quadrature intermediate frequency signal and outputs it.

[0033] Furthermore, the first synthesized signal is obtained by vector summation of the signals output from the first differential circuit and the second differential circuit.

[0034] If the fifth switch is coupled to the positive input terminal of the third differential circuit, and the sixth switch is coupled to the negative input terminal of the third differential circuit, then the second initial digital signal received by the fifth and sixth switches is 1. If the required second digital signal is 1, the fifth switch can be turned on and the sixth switch can be turned off. The first quadrature intermediate frequency signal is input to the positive input terminal of the third differential circuit through the fifth switch and output from the third differential circuit. If the required second digital signal is 0, the fifth switch can be turned off and the sixth switch can be turned on. The first quadrature intermediate frequency signal is input to the negative input terminal of the third differential circuit through the sixth switch. The third differential circuit inverts the first quadrature intermediate frequency signal and outputs it.

[0035] Alternatively, if the fifth switch is coupled to the negative input of the third differential circuit and the sixth switch is coupled to the positive input of the third differential circuit, then the second initial digital signal received by the fifth and sixth switches is 0. If the required second digital signal is 1, the fifth switch can be turned off and the sixth switch turned on, and the first quadrature intermediate frequency signal is input to the positive input of the third differential circuit through the sixth switch and output from the third differential circuit; if the required second digital signal is 0, the fifth switch can be turned on and the sixth switch turned off, and the first quadrature intermediate frequency signal is input to the negative input of the third differential circuit through the fifth switch, and the third differential circuit inverts the first quadrature intermediate frequency signal and outputs it.

[0036] If the seventh switch is coupled to the positive input of the fourth differential circuit, and the eighth switch is coupled to the negative input of the fourth differential circuit, then the fourth initial digital signal received by the seventh and eighth switches is 1. If the required fourth digital signal is 1, the seventh switch can be turned on and the eighth switch can be turned off. The second in-phase intermediate frequency signal is input to the positive input of the fourth differential circuit through the seventh switch and output from the fourth differential circuit. If the required fourth digital signal is 0, the seventh switch can be turned off and the eighth switch can be turned on. The second in-phase intermediate frequency signal is input to the negative input of the fourth differential circuit through the eighth switch. The fourth differential circuit inverts the second in-phase intermediate frequency signal and outputs it.

[0037] Alternatively, if the seventh switch is coupled to the negative input of the fourth differential circuit and the eighth switch is coupled to the positive input of the fourth differential circuit, then the fourth initial digital signal received by the seventh and eighth switches will be 0. If the desired fourth digital signal is 1, the seventh switch can be turned off and the eighth switch turned on, allowing the second in-phase intermediate frequency (IF) signal to be input to the positive input of the fourth differential circuit through the eighth switch and output from the fourth differential circuit. If the desired fourth digital signal is 0, the seventh switch can be turned on and the eighth switch turned off, allowing the second in-phase IF signal to be input to the negative input of the fourth differential circuit through the seventh switch, and the fourth differential circuit will invert the second in-phase IF signal before outputting it.

[0038] Furthermore, the second synthesized signal is obtained by vector summation of the signals output from the third and fourth differential circuits.

[0039] The second type of receiver also includes a third, fourth, fifth, and sixth adjustable RF amplifiers. The first in-phase IF signal, amplified by the third adjustable RF amplifier with a third gain, and the second quadrature IF signal, amplified by the fifth adjustable RF amplifier with a fourth gain, are selectively added or subtracted by a first adder / subtractor to output a first composite signal. The first quadrature IF signal, amplified by the fourth adjustable RF amplifier with a third gain, and the second in-phase IF signal, amplified by the sixth adjustable RF amplifier with a fourth gain, are selectively added or subtracted by a second adder / subtractor to output a second composite signal. Compared to receivers that only include a first and second adjustable RF amplifier, this type includes a third, fourth, fifth, and sixth adjustable RF amplifier, enabling a high variable gain range.

[0040] The third adjustable RF amplifier includes a first sub-amplifier and a second sub-amplifier; the fourth adjustable RF amplifier includes a third sub-amplifier and a fourth sub-amplifier; the fifth adjustable RF amplifier includes a fifth sub-amplifier and a sixth sub-amplifier; and the sixth adjustable RF amplifier includes a seventh sub-amplifier and an eighth sub-amplifier. The symbol code generator includes a first AND gate, a second AND gate, a third AND gate, a fourth AND gate, a fifth inverter, and a sixth inverter; the first adder / subtractor includes a fifth differential circuit and a sixth differential circuit. The first AND gate receives a third gain and a first initial digital signal; the output of the first AND gate is coupled to the first sub-amplifier; the input of the first sub-amplifier receives a first in-phase intermediate frequency signal, and its output is coupled to the fifth differential circuit. The second AND gate receives a fourth gain and a third initial digital signal; the output of the second AND gate is coupled to the fifth sub-amplifier; the input of the fifth sub-amplifier receives a second quadrature intermediate frequency signal, and its output is coupled to the sixth differential circuit. The third AND gate receives the third initial digital signal after the fourth gain and its inversion by the fifth inverter; the output of the third AND gate is coupled to the sixth sub-amplifier; the input of the sixth sub-amplifier receives the second quadrature intermediate frequency signal, and its output is coupled to the fifth differential circuit. The fourth AND gate receives the first initial digital signal after the third gain and its inversion by the sixth inverter; the output of the fourth AND gate is coupled to the second sub-amplifier; the input of the second sub-amplifier receives the first in-phase intermediate frequency signal, and its output is coupled to the sixth differential circuit. The outputs of both the fifth and sixth differential circuits are coupled to the inputs of the differential circuits.

[0041] The symbol code generator also includes a fifth AND gate, a sixth AND gate, a seventh AND gate, an eighth AND gate, a seventh inverter, and an eighth inverter; the second adder / subtractor includes a seventh differential circuit and an eighth differential circuit. The fifth AND gate receives the third gain and the second initial digital signal; its output is coupled to the third sub-amplifier; the input of the third sub-amplifier receives the first quadrature intermediate frequency (IF) signal, and its output is coupled to the seventh differential circuit. The sixth AND gate receives the fourth gain and the fourth initial digital signal; its output is coupled to the seventh sub-amplifier; the input of the seventh sub-amplifier receives the second in-phase IF signal, and its output is coupled to the eighth differential circuit. The seventh AND gate receives the second gain and the fourth initial digital signal inverted by the seventh inverter; its output is coupled to the eighth sub-amplifier; the input of the eighth sub-amplifier receives the second in-phase IF signal, and its output is coupled to the seventh differential circuit. The eighth AND gate receives the first gain and the second initial digital signal inverted by the eighth inverter; the output of the eighth AND gate is coupled to the fourth sub-amplifier; the input of the fourth sub-amplifier receives the first quadrature intermediate frequency signal, and its output is coupled to the eighth differential circuit. The outputs of both the seventh and eighth differential circuits are coupled to the inputs of the differential circuits.

[0042] Based on this circuit, the specific processes of the symbol code generator and the first and second adders / subtractors can include the following, so as to enable the first in-phase intermediate frequency signal and the second quadrature intermediate frequency signal to be selectively added or subtracted through the first adder / subtractor, and the first quadrature intermediate frequency signal and the second in-phase intermediate frequency signal to be selectively added or subtracted through the second adder / subtractor:

[0043] If the output of the first sub-amplifier is coupled to the positive input of the fifth differential circuit, and the output of the second sub-amplifier is coupled to the negative input of the sixth differential circuit, then the first initial digital signal received by the first AND gate and the fourth AND gate is 1. If the desired first digital signal is 1, an enable signal can be input to the first sub-amplifier, but not to the second sub-amplifier, so that the first sub-amplifier operates normally and the second sub-amplifier does not operate. The first initial digital signal (or the first digital signal) with a third gain sum of 1 is input to the first sub-amplifier through the first AND gate, and the first in-phase intermediate frequency signal is input to the positive input of the fifth differential circuit through the first sub-amplifier and output from the fifth differential circuit. If the desired first digital signal is 0, an enable signal can be input to the second sub-amplifier, but not to the first sub-amplifier, so that the first sub-amplifier does not operate and the second sub-amplifier operates normally. The first initial digital signal with a sum of 1 and the first digital signal with a sum of 0 after inversion are obtained. The first digital signal with a sum of 0 and a third gain is obtained is input to the second sub-amplifier through the fourth AND gate. The first in-phase intermediate frequency signal is input to the negative input terminal of the sixth differential circuit through the second sub-amplifier. After being inverted in the sixth differential circuit, it is output from the sixth differential circuit.

[0044] Alternatively, if the output of the first sub-amplifier is coupled to the negative input of the fifth differential circuit, and the output of the second sub-amplifier is coupled to the positive input of the sixth differential circuit, then the first initial digital signal received by the first AND gate and the fourth AND gate will be 0. If the desired first digital signal is 1, an enable signal can be input to the second sub-amplifier without inputting an enable signal to the first sub-amplifier, thus disabling the first sub-amplifier and allowing the second sub-amplifier to operate normally. The first initial digital signal, which is 0, is inverted to obtain a first digital signal of 1. This first digital signal, with a third gain sum of 1, is input to the second sub-amplifier through the fourth AND gate. The first in-phase intermediate frequency signal is input to the positive input of the sixth differential circuit through the second sub-amplifier and output from the sixth differential circuit. If the desired first digital signal is 0, an enable signal can be input to the first sub-amplifier without inputting an enable signal to the second sub-amplifier, thus disabling the first sub-amplifier and allowing the second sub-amplifier to operate normally. The first initial digital signal (or the first digital signal) with a third gain sum of 0 is input to the first sub-amplifier through the first AND gate. The first in-phase intermediate frequency signal is input to the negative input terminal of the fifth differential circuit through the first sub-amplifier. After being inverted in the fifth differential circuit, it is output from the fifth differential circuit.

[0045] If the output of the fifth sub-amplifier is coupled to the positive input of the sixth differential circuit, and the output of the sixth sub-amplifier is coupled to the negative input of the fifth differential circuit, then the third initial digital signal received by the second and third AND gates will be 1. If the desired third digital signal is 1, then an enable signal can be input to the fifth sub-amplifier, but not to the sixth sub-amplifier, allowing the fifth sub-amplifier to operate normally and the sixth sub-amplifier to operate normally. The third initial digital signal (or the third digital signal) with a fourth gain sum of 1 is input to the fifth sub-amplifier through the second AND gate. The second quadrature intermediate frequency signal is input to the positive input of the sixth differential circuit through the fifth sub-amplifier and output from the sixth differential circuit. If the desired third digital signal is 0, then an enable signal can be input to the sixth sub-amplifier, but not to the fifth sub-amplifier, allowing the fifth sub-amplifier to operate normally and the sixth sub-amplifier to operate normally. The third initial digital signal, which is 1, is inverted to obtain a third digital signal that is 0. The third digital signal with a fourth gain of 0 is input to the sixth sub-amplifier through the third AND gate. The second quadrature intermediate frequency signal is input to the negative input terminal of the fifth differential circuit through the sixth sub-amplifier. After being inverted in the fifth differential circuit, it is output from the fifth differential circuit.

[0046] Alternatively, if the output of the fifth sub-amplifier is coupled to the negative input of the sixth differential circuit, and the output of the sixth sub-amplifier is coupled to the positive input of the fifth differential circuit, then the third initial digital signal received by the second and third AND gates will be 0. If the required third digital signal is 1, then an enable signal can be input to the sixth sub-amplifier without inputting an enable signal to the fifth sub-amplifier, causing the fifth sub-amplifier to be inactive and the sixth sub-amplifier to operate normally. The third initial digital signal, which is 0, is inverted to obtain a third digital signal of 1. The third digital signal with a fourth gain sum of 1 is input to the sixth sub-amplifier through the third AND gate. The second quadrature intermediate frequency signal is input to the positive input of the fifth differential circuit through the sixth sub-amplifier and output from the fifth differential circuit. If the required third digital signal is 0, then an enable signal can be input to the fifth sub-amplifier without inputting an enable signal to the sixth sub-amplifier, causing the fifth sub-amplifier to operate normally and the sixth sub-amplifier to be inactive. The third initial digital signal (or third digital signal) with a fourth gain sum of 0 is input to the fifth sub-amplifier through the second AND gate. The second quadrature intermediate frequency signal is input to the negative input terminal of the sixth differential circuit through the fifth sub-amplifier. After being inverted in the sixth differential circuit, it is output from the sixth differential circuit.

[0047] Furthermore, the first synthesized signal is obtained by vector summation of the signals output from the fifth and sixth differential circuits.

[0048] If the output of the third sub-amplifier is coupled to the positive input of the seventh differential circuit, and the output of the fourth sub-amplifier is coupled to the negative input of the eighth differential circuit, then the second initial digital signal received by the fifth and eighth AND gates will be 1. If the desired second digital signal is 1, then an enable signal can be input to the third sub-amplifier without inputting an enable signal to the fourth sub-amplifier, allowing the third sub-amplifier to operate normally and the fourth sub-amplifier to operate normally. The second initial digital signal (or the second digital signal) with a third gain sum of 1 is input to the third sub-amplifier through the fifth AND gate. The first quadrature intermediate frequency signal is input to the positive input of the seventh differential circuit through the third sub-amplifier and output from the seventh differential circuit. If the desired second digital signal is 0, then an enable signal can be input to the fourth sub-amplifier without inputting an enable signal to the third sub-amplifier, allowing the third sub-amplifier to operate normally and the fourth sub-amplifier to operate normally. The second initial digital signal, which is 1, is inverted to obtain a second digital signal, which is 0. The second digital signal, which has a third gain and is 0, is input to the fourth sub-amplifier through the eighth AND gate. The first quadrature intermediate frequency signal is input to the negative input terminal of the eighth differential circuit through the fourth sub-amplifier. After being inverted in the eighth differential circuit, it is output from the eighth differential circuit.

[0049] Alternatively, if the output of the third sub-amplifier is coupled to the negative input of the seventh differential circuit, and the output of the fourth sub-amplifier is coupled to the positive input of the eighth differential circuit, then the second initial digital signal received by the fifth and eighth AND gates will be 0. If the desired second digital signal is 1, an enable signal can be input to the fourth sub-amplifier without inputting an enable signal to the third sub-amplifier, thus disabling the third sub-amplifier and allowing the fourth sub-amplifier to operate normally. The second initial digital signal, which is 0, is inverted to obtain a second digital signal of 1. This second digital signal, with a third gain sum of 1, is input to the fourth sub-amplifier through the eighth AND gate. The first quadrature intermediate frequency signal is input to the positive input of the eighth differential circuit through the fourth sub-amplifier and output from the eighth differential circuit. If the desired second digital signal is 0, an enable signal can be input to the third sub-amplifier without inputting an enable signal to the fourth sub-amplifier, thus disabling the third sub-amplifier and allowing the fourth sub-amplifier to operate normally. The second initial digital signal (or second digital signal) with a third gain sum of 0 is input to the third sub-amplifier through the fifth AND gate. The first quadrature intermediate frequency signal is input to the negative input terminal of the seventh differential circuit through the third sub-amplifier. After being inverted in the seventh differential circuit, it is output from the seventh differential circuit.

[0050] If the output of the seventh sub-amplifier is coupled to the positive input of the eighth differential circuit, and the output of the eighth sub-amplifier is coupled to the negative input of the seventh differential circuit, then the fourth initial digital signal received by the sixth and seventh AND gates will be 1. If the desired fourth digital signal is 1, then an enable signal can be input to the seventh sub-amplifier without inputting an enable signal to the eighth sub-amplifier, allowing the seventh sub-amplifier to operate normally and the eighth sub-amplifier to operate normally. The fourth initial digital signal (or the fourth digital signal) with a fourth gain sum of 1 is input to the seventh sub-amplifier through the sixth AND gate, and the second in-phase intermediate frequency signal is input to the positive input of the eighth differential circuit through the seventh sub-amplifier and output from the eighth differential circuit. If the desired fourth digital signal is 0, then an enable signal can be input to the eighth sub-amplifier without inputting an enable signal to the seventh sub-amplifier, allowing the seventh sub-amplifier to operate normally and the eighth sub-amplifier to operate normally. The fourth initial digital signal, which is 1, is inverted to obtain a fourth digital signal, which is 0. The fourth digital signal, which has a fourth gain of 0, is input to the eighth sub-amplifier through the seventh AND gate. The second in-phase intermediate frequency signal is input to the negative input terminal of the seventh differential circuit through the eighth sub-amplifier. After being inverted in the seventh differential circuit, it is output from the seventh differential circuit.

[0051] Alternatively, if the output of the seventh sub-amplifier is coupled to the negative input of the eighth differential circuit, and the output of the eighth sub-amplifier is coupled to the positive input of the seventh differential circuit, then the fourth initial digital signal received by the sixth and seventh AND gates will be 0. If the desired fourth digital signal is 1, then an enable signal can be input to the eighth sub-amplifier without inputting an enable signal to the seventh sub-amplifier, thus disabling the seventh sub-amplifier and allowing the eighth sub-amplifier to operate normally. The fourth initial digital signal, which is 0, is inverted to obtain a fourth digital signal of 1. This fourth digital signal, with a fourth gain sum of 1, is input to the eighth sub-amplifier through the seventh AND gate. The second in-phase intermediate frequency signal is input to the positive input of the seventh differential circuit through the eighth sub-amplifier and output from the seventh differential circuit. If the desired fourth digital signal is 0, then an enable signal can be input to the seventh sub-amplifier without inputting an enable signal to the eighth sub-amplifier, thus disabling the seventh sub-amplifier and allowing the eighth sub-amplifier to operate normally. The fourth initial digital signal (or fourth digital signal) with a gain sum of 0 is input to the seventh sub-amplifier through the sixth AND gate. The second in-phase intermediate frequency signal is input to the negative input terminal of the eighth differential circuit through the seventh sub-amplifier. After being inverted in the eighth differential circuit, it is output from the eighth differential circuit.

[0052] Furthermore, a second synthesized signal is obtained by vector summation of the signals output from the seventh and eighth differential circuits.

[0053] Secondly, this application provides a radio frequency transceiver, the receiver including a transmitter and the receiver described in the first aspect.

[0054] The implementation method of the second aspect corresponds to any implementation method of the first aspect. The technical effects corresponding to the implementation method of the second aspect can be found in the first aspect and the technical effects corresponding to any implementation method of the first aspect mentioned above, and will not be repeated here.

[0055] Thirdly, this application provides a terminal that includes an antenna and the radio frequency transceiver described in the second aspect.

[0056] The implementation method of the third aspect corresponds to any implementation method of the first aspect. The technical effects corresponding to the implementation method of the third aspect can be found in the first aspect and the technical effects corresponding to any implementation method of the first aspect mentioned above, and will not be repeated here. Attached Figure Description

[0057] Figure 1a A structural framework diagram of a terminal provided in an embodiment of this application;

[0058] Figure 1b A diagram showing the relationship between the first radio frequency signal, the second radio frequency signal, and the local oscillator signal provided in the embodiments of this application;

[0059] Figure 2 A circuit diagram of a receiver provided for related technologies;

[0060] Figure 3a A circuit diagram of a receiver provided in an embodiment of this application;

[0061] Figure 3b A circuit diagram of another receiver provided in an embodiment of this application;

[0062] Figure 3c A circuit diagram of another receiver provided in an embodiment of this application;

[0063] Figure 3d A circuit diagram of another receiver provided in an embodiment of this application;

[0064] Figure 3e A circuit diagram of another receiver provided in an embodiment of this application;

[0065] Figure 3f A circuit diagram of another receiver provided in an embodiment of this application;

[0066] Figure 4a A circuit structure diagram of a control circuit provided in an embodiment of this application;

[0067] Figure 4b A gain variation diagram provided for an embodiment of this application;

[0068] Figure 4c A phase change diagram provided in an embodiment of this application;

[0069] Figure 5a Phase diagrams of the first and second radio frequency signals provided in embodiments of this application;

[0070] Figure 5b The phase diagram of the first radio frequency signal and the second radio frequency signal amplified by the first gain is provided in the embodiments of this application;

[0071] Figure 5c A two-dimensional diagram of the first and second radio frequency signals amplified by a second gain, as provided in the embodiments of this application;

[0072] Figure 5d A phase diagram of the first in-phase intermediate frequency signal provided in the embodiments of this application;

[0073] Figure 5e A phase diagram of the first orthogonal intermediate frequency signal provided in the embodiments of this application;

[0074] Figure 5f Phase diagram of the second orthogonal intermediate frequency signal provided in the embodiments of this application;

[0075] Figure 5g A phase diagram of the second in-phase intermediate frequency signal provided in the embodiments of this application;

[0076] Figure 5h This application provides a mode for filtering out image interference signals in its embodiments.

[0077] Figure 5i A phase diagram of the first synthesized signal provided in the embodiments of this application;

[0078] Figure 5j A phase diagram of the second synthesized signal provided in the embodiments of this application;

[0079] Figure 5k The phase diagram of the first synthesized signal after a 90° phase shift is provided in an embodiment of this application;

[0080] Figure 5l This is a schematic diagram illustrating the process of adding the first synthesized signal and the second synthesized signal according to an embodiment of this application.

[0081] Figure 6a A circuit diagram of another receiver provided in an embodiment of this application;

[0082] Figure 6b A circuit diagram of another receiver provided in an embodiment of this application;

[0083] Figure 6c A circuit diagram of another receiver provided in an embodiment of this application;

[0084] Figure 7a Another mode for filtering out mirror interference signals provided in the embodiments of this application;

[0085] Figure 7b A circuit diagram of another receiver provided in an embodiment of this application;

[0086] Figure 7c A circuit diagram of another receiver provided in an embodiment of this application;

[0087] Figure 7d A circuit diagram of another receiver provided in an embodiment of this application;

[0088] Figure 7e A circuit diagram of another receiver provided in an embodiment of this application;

[0089] Figure 8a A circuit diagram of a control circuit and a first adder / subtractor provided in an embodiment of this application;

[0090] Figure 8bA circuit diagram of another control circuit and a first adder / subtractor provided in an embodiment of this application;

[0091] Figure 8c A circuit diagram of a control circuit and a second adder / subtractor provided in an embodiment of this application;

[0092] Figure 8d A circuit diagram of another control circuit and a second adder / subtractor provided in the embodiments of this application;

[0093] Figure 9a A circuit diagram of another receiver provided in an embodiment of this application;

[0094] Figure 9b The circuit diagram of the control circuit, amplifier, and first adder / subtractor provided in the embodiments of this application;

[0095] Figure 9c The circuit diagram of the control circuit, amplifier, and first adder / subtractor provided in the embodiments of this application;

[0096] Figure 9d The circuit diagram of the control circuit, amplifier, and second adder / subtractor provided in the embodiments of this application;

[0097] Figure 9e The circuit diagram of the control circuit, amplifier, and second adder / subtractor provided in the embodiments of this application is shown.

[0098] Figure label:

[0099] 101-Receiver; 102-Transmitter; 103-Antenna; 1011-Variable gain amplifier; 1012-Vector synthesis phase shifter; 11-First adder / subtractor; 12-Second adder / subtractor; 13-Phase shifter; 14-Differential circuit; 15-Control circuit. Detailed Implementation

[0100] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0101] In this article, the term "and / or" is merely a description of the relationship between related objects, indicating that there can be three relationships. For example, A and / or B can represent three situations: A exists alone, A and B exist simultaneously, and B exists alone.

[0102] The terms "first" and "second," etc., used in the specification and claims of this application are used to distinguish different objects, not to describe a specific order of objects. For example, "first target object" and "second target object," etc., are used to distinguish different target objects, not to describe a specific order of target objects.

[0103] In the embodiments of this application, the terms "exemplary" or "for example" are used to indicate that something is an example, illustration, or description. Any embodiment or design that is described as "exemplary" or "for example" in the embodiments of this application should not be construed as being more preferred or advantageous than other embodiments or design. Specifically, the use of the terms "exemplary" or "for example" is intended to present the relevant concepts in a specific manner.

[0104] In the description of the embodiments in this application, unless otherwise stated, "multiple" means two or more. For example, multiple processing units means two or more processing units; multiple systems means two or more systems.

[0105] This application provides a terminal, which can be a device including a radar, base station, server, mobile phone, or other device with a radio frequency transceiver. This application does not limit the specific device to this type. For ease of explanation, a mobile phone is used as an example below.

[0106] Figure 1a This illustration shows an application scenario of a mobile phone according to an embodiment of this application. The mobile phone includes a radio frequency transceiver and an antenna 103. The radio frequency transceiver may include a receiver 101 and a transmitter 102. The antenna 103 is coupled to both the receiver 101 and the transmitter 102, and is used to transmit radio frequency signals to the receiver 101 and receive radio frequency signals transmitted by the transmitter 102.

[0107] like Figure 1b As shown, assume the radio frequency signal includes a first radio frequency signal and a second radio frequency signal, the frequency of the first radio frequency signal is f1, the frequency of the second radio frequency signal is f2, and the frequency of the local oscillator signal is f. LO Where, f1+f IF =f LO f2-f LO =f IF That is, the frequency difference between the first radio frequency signal, the second radio frequency signal, and the local oscillator signal is f. IF The first and second radio frequency signals, after being mixed with the local oscillator signal respectively, can both output an intermediate frequency (IF) signal, thus causing image frequency interference.

[0108] Related technologies can utilize orthogonal mixer architectures for image suppression. Figure 2A typical receiver 101 with amplitude, phase control and image suppression functions is shown. The amplitude control of the radio frequency signal is achieved by a variable gain amplifier 1011, the phase control of the radio frequency signal is achieved by a vector synthesis phase shifter 1012, and the image suppression is achieved by a mixer 1013 with an orthogonal architecture.

[0109] However, Figure 2 In the receiver 101 shown, the amplitude and phase of the radio frequency (RF) signal are controlled separately. The amplitude control circuit independently controls the amplitude of the RF signal by controlling the variable gain amplifier 1011; the phase control circuit independently controls the phase of the RF signal by controlling the vector synthesizer phase shifter 1012. Achieving high-precision phase shifting would increase the size and losses of the circuitry in the receiver 101 for a passive vector synthesizer phase shifter 1012, and increase the power consumption of the circuitry in the receiver 101 for an active vector synthesizer phase shifter 1012.

[0110] Based on this, this application provides a receiver 101, which can use an amplifier, a mixer and a mirror rejection circuit to replace the traditional vector synthesis phase shifter 1012 to adjust the phase of the received radio frequency signal, thereby saving the layout area and power consumption of the receiver 101.

[0111] The circuit structure of receiver 101 will be described in detail below with reference to the accompanying drawings.

[0112] like Figure 3a and Figure 3b As shown, the receiver 101 includes a first adjustable radio frequency amplifier VGA1, a second adjustable radio frequency amplifier VGA2, a first in-phase mixer H1, a first quadrature mixer H2, a second quadrature mixer H3, a second in-phase mixer H4, a first adder / subtractor 11, and a second adder / subtractor 12.

[0113] Receiver 101 is used to receive radio frequency (RF) signals. The RF signal is amplified by a first adjustable RF amplifier VGA1 to output a first amplified RF signal RFr. The RF signal is then amplified by a second adjustable RF amplifier VGA2 to output a second amplified RF signal RFi. The first amplified RF signal RFr is mixed by a first in-phase mixer H1 to output a first in-phase intermediate frequency (IF) signal IFIr. This is then mixed by a first quadrature mixer H2 to output a first quadrature intermediate frequency (IFQ) signal IFQr. The second amplified RF signal RFi is mixed by a second quadrature mixer H3 to output a second quadrature intermediate frequency (IFQi). This is then mixed by a second in-phase mixer H4 to output a second in-phase intermediate frequency (IFi) signal IFIi.

[0114] The first in-phase intermediate frequency signal IFQr and the second quadrature intermediate frequency signal IFQi are selectively added or subtracted by the first adder / subtractor 11 to output the first synthesized signal IFI. The first quadrature intermediate frequency signal IFQr and the second in-phase intermediate frequency signal IFIi are selectively added or subtracted by the second adder / subtractor 12 to output the second synthesized signal IFQ.

[0115] In some possible implementations, the first adjustable RF amplifier VGA1 can amplify the RF signal RF with an adjustable first gain r1, and the second adjustable RF amplifier VGA2 can amplify the RF signal RF with an adjustable second gain i1.

[0116] In some possible implementations, the first RF amplified signal RFr can be mixed with the first local oscillator signal LOI through a first in-phase mixer H1 to output a first in-phase intermediate frequency signal IFIr. The first RF amplified signal RFr can be mixed with the second local oscillator signal LOQ through a first quadrature mixer M2 to output a first quadrature intermediate frequency signal IFQr. The second RF amplified signal RFi can be mixed with the second local oscillator signal LOQ through a second quadrature mixer H3 to output a second quadrature intermediate frequency signal IFQi. The second RF amplified signal RFi can be mixed with the first local oscillator signal LOI through a second in-phase mixer H4 to output a second in-phase intermediate frequency signal IFIi. Furthermore, the first local oscillator signal LOI and the second local oscillator signal LOQ are orthogonal, making the first in-phase intermediate frequency signal IFIr orthogonal to the second quadrature intermediate frequency signal IFQi, and the first quadrature intermediate frequency signal IFQr orthogonal to the second in-phase intermediate frequency signal IFIi; the phase of the first in-phase intermediate frequency signal IFIr is the same as the phase of the second in-phase intermediate frequency signal IFIi, and the phase of the first quadrature intermediate frequency signal IFQr is the same as the phase of the second quadrature intermediate frequency signal IFQi.

[0117] Those skilled in the art will know that the working principle of the vector synthesis phase shifter 1012 is to achieve the phase shifting function by changing the ratio of two orthogonal signals.

[0118] The first adder / subtractor 11 receives a first in-phase intermediate frequency (IF) signal IFIr and a second quadrature IF signal IFQi. Furthermore, since the radio frequency (RF) signal RF forming the first in-phase IF signal IFIr is amplified by a first adjustable RF amplifier VGA1 with an adjustable first gain r1, and the RF signal RF forming the second quadrature IF signal IFQi is amplified by a second adjustable RF amplifier VGA2 with an adjustable second gain i, the ratio of the first in-phase IF signal IFIr to the second quadrature IF signal IFQi can be adjusted by regulating the magnitudes of the first gain r1 and the second gain i1, thereby replacing the existing vector synthesis phase shifter 1012 and achieving phase shifting functionality.

[0119] The second adder / subtractor 12 receives a first quadrature intermediate frequency (IF) signal IFQr and a second in-phase IF signal IFIi. Furthermore, since the radio frequency (RF) signal RF forming the first quadrature IF signal IFQr is amplified by a first adjustable RF amplifier VGA1 with an adjustable first gain r1, and the RF signal RF forming the second in-phase IF signal IFIi is amplified by a second adjustable RF amplifier VGA2 with an adjustable second gain i1, the ratio of the first quadrature IF signal IFQr to the second in-phase IF signal IFIi can be adjusted by regulating the magnitudes of the first gain r1 and the second gain i1, thereby replacing the existing vector synthesis phase shifter 1012 and achieving phase shifting functionality.

[0120] In summary, this application can utilize existing first adjustable RF amplifier VGA1, second adjustable RF amplifier VGA2, first in-phase mixer H1, first quadrature mixer H2, second quadrature mixer H3, second in-phase mixer H4, first adder / subtractor 11, and second adder / subtractor 12 to replace the traditional vector synthesis phase shifter 1012 to adjust the phase of the received RF signal, saving the layout area and power consumption of the receiver 101. Furthermore, since this application integrates the first adjustable RF amplifier VGA1, second adjustable RF amplifier VGA2, first in-phase mixer H1, first quadrature mixer H2, second quadrature mixer H3, second in-phase mixer H4, first adder / subtractor 11, and second adder / subtractor 12, which implement amplification, phase shifting, and mixing functions, into a single unit, the integration density of the receiver 101 is significantly improved, thereby reducing parasitic capacitance and inductance in the receiver 101.

[0121] Furthermore, the first and second adjustable RF amplifiers can also adjust the amplitude of the RF signal. Moreover, since the first adder / subtractor 11 can selectively add or subtract the first in-phase IF signal IFQr and the second quadrature IF signal IFQi through vector synthesis, and the second adder / subtractor 12 can selectively add or subtract the first quadrature IF signal IFQr and the second in-phase IF signal IFQi through vector synthesis, the first in-phase IF signal IFQr and the first quadrature IF signal IFQr are amplified by the first gain r1, and the second quadrature IF signal IFQi and the second in-phase IF signal IFQi are amplified by the second gain i1. Therefore, even if the first gain r1 and / or the second gain i1 are changed, the amplitude of the vector synthesis result of the first in-phase IF signal IFQr and the second quadrature IF signal IFQi is always the same as that of the vector synthesis result of the first quadrature IF signal IFQr and the second in-phase IF signal IFQi.

[0122] In some possible implementations, after receiving the radio frequency (RF) signal, receiver 101 can input the same RF signal to the first adjustable RF amplifier VGA1 and the second adjustable RF amplifier VGA2. Specifically, the signal quantity, amplitude, and phase of the RF signal input to the first adjustable RF amplifier VGA1 and the second adjustable RF amplifier VGA2 can all be the same.

[0123] In some possible implementations, the first adjustable RF amplifier VGA1 amplifies the RF signal with a first gain r1, meaning that the first adjustable RF amplifier VGA1 amplifies the RF signal RF input to the first amplifier with a first gain r1, and the ratio of the first RF amplified signal RFr output from the first adjustable RF amplifier VGA1 to the RF signal RF input to the first adjustable RF amplifier VGA1 is the first gain r1; the second adjustable RF amplifier VGA2 amplifies the RF signal RF input to the second adjustable RF amplifier VGA2 with a second gain i1, and the ratio of the second RF amplified signal RFi output from the second adjustable RF amplifier VGA2 to the RF signal RF input to the second adjustable RF amplifier VGA2 is the second gain i1.

[0124] In some possible implementations, this application can utilize a single-stage amplifier to amplify the radio frequency (RF) signal. For example, as Figure 3a As shown in the embodiment of this application, a first adjustable RF amplifier VGA1 and a second adjustable RF amplifier VGA2 are coupled between the input terminal IN of the receiver 101 and the first in-phase mixer H1, the first quadrature mixer H2, the second quadrature mixer H3, and the second in-phase mixer H4. In this case, the RF signal received by the receiver 101 can be amplified by the first adjustable RF amplifier VGA1 and the second adjustable RF amplifier VGA2, and then mixed by the first in-phase mixer H1, the first quadrature mixer H2, the second quadrature mixer H3, and the second in-phase mixer H4.

[0125] Or, such as Figure 3b As shown, the first in-phase mixer H1, the first quadrature mixer H2, the second quadrature mixer H3, and the second in-phase mixer H4 can also be coupled between the input terminal IN of the receiver 101 and the first adjustable RF amplifier VGA1 and the second adjustable RF amplifier VGA2. In this case, the RF signal received by the receiver 101 can first be mixed by the first in-phase mixer H1, the first quadrature mixer H2, the second quadrature mixer H3, and the second in-phase mixer H4, and then amplified by the first adjustable RF amplifier VGA1 and the second adjustable RF amplifier VGA2.

[0126] In other possible implementations, this application can also utilize multi-stage amplifiers to amplify radio frequency (RF) signals. For example... Figure 3c As shown, the first adjustable RF amplifier VGA1 and the second adjustable RF amplifier VGA2 are coupled between the input terminal IN of the receiver 101 and the first in-phase mixer H1, the first quadrature mixer H2, the second quadrature mixer H3, and the second in-phase mixer H4. In addition, the receiver 101 may also include a third adjustable RF amplifier VGA2, a fourth adjustable RF amplifier VGA4, a fifth adjustable RF amplifier VGA5, and a sixth adjustable RF amplifier VGA6. The third adjustable RF amplifier VGA2, the fourth adjustable RF amplifier VGA4, the fifth adjustable RF amplifier VGA5, and the sixth adjustable RF amplifier VGA6 can be coupled between the first in-phase mixer H1, the first quadrature mixer H2, the second quadrature mixer H3, the second in-phase mixer H4 and the output terminal OUT of the receiver 101. The third adjustable RF amplifier VGA2 amplifies the first in-phase intermediate frequency signal IFQr with a third gain r2; the fourth adjustable RF amplifier VGA4 amplifies the second quadrature intermediate frequency signal IFQi with a third gain r2; the fifth adjustable RF amplifier VGA5 amplifies the first quadrature intermediate frequency signal IFQr with a fourth gain i2; and the sixth adjustable RF amplifier VGA6 amplifies the second in-phase intermediate frequency signal IFIi with a fourth gain i2.

[0127] Of course, the aforementioned Figures 3a-3c The situation shown is merely an example, and the number of amplifiers in receiver 101 can be other than that described in this embodiment.

[0128] Compared to single-stage amplifiers, multi-stage amplifiers can achieve a high variable gain range. Compared to multi-stage amplifiers, single-stage amplifiers can improve linearity and reduce the power consumption and layout area of ​​receiver 101. Regardless of whether a single-stage amplifier or a multi-stage amplifier is used, the traditional vector synthesis phase shifter 1012 can be eliminated, saving the layout area and power consumption of receiver 101.

[0129] In some embodiments, such as Figure 4aAs shown, receiver 101 may further include control circuit 15, which may include a control code generator. The output of the control code generator is coupled to the first adjustable RF amplifier VGA1 and the second adjustable RF amplifier VGA2. The control code generator can input a first gain r1 to the first adjustable RF amplifier VGA1 and a second gain i1 to the second adjustable RF amplifier VGA2 according to preset gain control codes and phase control codes. If receiver 101 also includes a third adjustable RF amplifier VGA3, a fourth adjustable RF amplifier VGA4, a fifth adjustable RF amplifier VGA5, and a sixth adjustable RF amplifier VGA6, the control code generator can input a third gain r2 to the third adjustable RF amplifier VGA3 and the fourth adjustable RF amplifier VGA4, and a fourth gain i2 to the fifth adjustable RF amplifier VGA5 and the sixth adjustable RF amplifier VGA6 according to preset gain control codes and phase control codes.

[0130] In some possible implementations, the embodiments of this application do not limit the number of bits for the first gain r1, the second gain i1, the third gain r2, and the fourth gain i2. The number of bits for these four gains can be designed according to the actual required amplitude and phase. Furthermore, since the number of bits for the first gain r1, the second gain i1, the third gain r2, and the fourth gain i2 themselves includes multiple states, adjusting the phase of the radio frequency signal by adjusting the magnitudes of the first gain r1, the second gain i1, the third gain r2, and the fourth gain i2 does not require increasing the number of bits in the control circuit 15.

[0131] For example, assuming the total number of bits for the first gain r1 and the third gain r2 is 3, denoted as r code <0:m>, then the first gain r1 and the third gain r2 have a total of 8 states: 000, 001, 010, 011, 100, 101, 110, and 111. Similarly, assuming the total number of bits for the second gain i1 and the fourth gain i2 is 3, denoted as i code <0:m>, then the second gain i1 and the fourth gain i2 have a total of 8 states: 000, 001, 010, 011, 100, 101, 110, and 111. Here, m is a positive integer.

[0132] The first gain r1 of the first adjustable RF amplifier VGA1 can have n-1 bits, denoted as r1code<0:n-1>. The third gain r2 of the third adjustable RF amplifier VGA3 and the fourth adjustable RF amplifier VGA4 can have m-n+1 bits. The total number of bits for the first gain r1 and the third gain r2 is n-1+m-n+1=m. The second gain i1 of the second adjustable RF amplifier VGA2 can have n-1 bits, denoted as i1code<0:n-1>. The fourth gain i2 of the fifth adjustable RF amplifier VGA5 and the sixth adjustable RF amplifier VGA6 can have m-n+1 bits. The total number of bits for the second gain i1 and the fourth gain i2 is n-1+m-n+1=m. Here, n is a positive integer less than m.

[0133] Furthermore, if the receiver 101 includes a first adjustable RF amplifier VGA1 and a second adjustable RF amplifier VGA2, but does not include a third adjustable RF amplifier VGA3, a fourth adjustable RF amplifier VGA4, a fifth adjustable RF amplifier VGA5, and a sixth adjustable RF amplifier VGA6, then the first gain r1 includes eight states: 000, 001, 010, 011, 100, 101, 110, and 111. The second gain i1 includes eight states: 000, 001, 010, 011, 100, 101, 110, and 111.

[0134] The foregoing example illustrates that the total number of bits of the first gain r1 and the third gain r2 is the same as the total number of bits of the second gain i1 and the fourth gain i2. In some possible implementations, the total number of bits of the first gain r1 and the third gain r2 may not be the same as the total number of bits of the second gain i1 and the fourth gain i2. This application does not limit this.

[0135] In some embodiments, the control circuit 15 may further include a symbol code generator. The symbol code generator is used to input a first digital signal S1r and a third digital signal S1i to the first adder / subtractor 11, and a second digital signal S2r and a fourth digital signal S2i to the second adder / subtractor 12. The first digital signal S1r is used to determine whether the phase of the first in-phase intermediate frequency signal IFIr is positive or negative; the second digital signal S2r is used to determine whether the phase of the first quadrature intermediate frequency signal IFQr is positive or negative; the third digital signal S1i is used to determine whether the phase of the second quadrature intermediate frequency signal IFQi is positive or negative; and the fourth digital signal S2i is used to determine whether the phase of the second in-phase intermediate frequency signal IFIi is positive or negative.

[0136] For example, when the first digital signal S1r is 1, the phase of the first in-phase intermediate frequency signal IF1r is negative; when the first digital signal S1r is 0, the phase of the first in-phase intermediate frequency signal IF1r is positive. When the second digital signal S2r is 1, the phase of the first quadrature intermediate frequency signal IFQr is negative; when the second digital signal S2r is 0, the phase of the first quadrature intermediate frequency signal IFQr is positive. When the third digital signal S1i is 1, the phase of the second quadrature intermediate frequency signal IFQi is negative; when the third digital signal S1i is 0, the phase of the second quadrature intermediate frequency signal IFQi is positive. When the fourth digital signal S2i is 1, the phase of the second in-phase intermediate frequency signal IF1i is negative; when the fourth digital signal S2i is 0, the phase of the second in-phase intermediate frequency signal IF1i is positive.

[0137] Alternatively, if the first digital signal S1r is 1, the phase of the first in-phase intermediate frequency signal IF1r is positive; if the first digital signal S1r is 0, the phase of the first in-phase intermediate frequency signal IF1r is negative. If the second digital signal S2r is 1, the phase of the first quadrature intermediate frequency signal IFQr is positive; if the second digital signal S2r is 0, the phase of the first quadrature intermediate frequency signal IFQr is negative. If the third digital signal S1i is 1, the phase of the second quadrature intermediate frequency signal IFQi is positive; if the third digital signal S1i is 0, the phase of the second quadrature intermediate frequency signal IFQi is negative. If the fourth digital signal S2i is 1, the phase of the second in-phase intermediate frequency signal IF1i is positive; if the fourth digital signal S2i is 0, the phase of the second in-phase intermediate frequency signal IF1i is negative. For ease of description, the following text will use this example.

[0138] In some embodiments, based on the first digital signal S1r and the third digital signal S1i, the first adder / subtractor 11 performs vector synthesis on the first in-phase intermediate frequency signal IFIr (or the first in-phase intermediate frequency signal IFIr with a positive phase) and the second quadrature intermediate frequency signal IFQi (or the second quadrature intermediate frequency signal IFQi with a negative phase) to obtain the first synthesized signal IFI. Based on the second digital signal S2r and the fourth digital signal S2i, the second adder / subtractor 12 performs vector synthesis on the first quadrature intermediate frequency signal IFQr (or the first quadrature intermediate frequency signal IFQr with a negative phase) and the second in-phase intermediate frequency signal IFIi (or the second in-phase intermediate frequency signal IFIi with a negative phase) to obtain the second synthesized signal IFQ.

[0139] Based on the above, the receiver 101 may further include a differential circuit 14 and an existing phase shifter 13. By further processing the first synthesized signal IFI and the second synthesized signal IFQ, image interference signals in the first synthesized signal IFI and the second synthesized signal IFQ are filtered out.

[0140] Specifically, phase shifter 13 is used to perform a 90° phase shift on either the first synthesized signal IFI or the second synthesized signal IFQ. Differential circuit 14 is used to add the second synthesized signal IFQ to the phase-shifted first synthesized signal IFI, or to the first synthesized signal IFI to the phase-shifted second synthesized signal IFQ, to filter out mirror interference signals in the first and second synthesized signals IFI and IFQ. Phase shifter 13 can be a multiphase filter or a quadrature coupler, etc.

[0141] The preceding text described the origin of the image frequency interference problem. Both the first in-phase intermediate frequency (IF) signal IF1r and the second in-phase IF signal IF1i are obtained by mixing a first radio frequency (RF) signal and a second radio frequency (RF) signal, which are mirrored by the first local oscillator (LOI) signal and have the same frequency difference but different frequencies, with the first RF signal LOI after amplification. Similarly, both the first quadrature intermediate frequency (IF) signal IFQr and the second quadrature intermediate frequency (IFQi) signal are obtained by mixing a first RF signal and a second RF signal, which are mirrored by the second local oscillator (LOQ) signal and have the same frequency difference but different frequencies, with the second RF signal LOQ after amplification.

[0142] Alternatively, the first in-phase intermediate frequency (IF) signal IFIr, the first quadrature intermediate frequency (IFQr), the second quadrature intermediate frequency (IFQi), and the second in-phase IF signal IFIi include both the first signal obtained by mixing the amplified first radio frequency (RF) signal with the first local oscillator (LOI) or the second local oscillator (LOQ) signal, and the second signal obtained by mixing the amplified second RF signal with the first local oscillator (LOI) or the second local oscillator (LOQ) signal. One of the first and second signals is the useful signal, and the other is a mirror interference signal. It is necessary to filter out the mirror interference signal from the first in-phase IF signal IFIr, the first quadrature intermediate frequency (IFQr), the second quadrature intermediate frequency (IFQi), and the second in-phase IF signal IFIi, retaining the useful signal to solve the mirror interference problem.

[0143] This application embodiment does not limit the digital logic of the first digital signal S1r, the second digital signal S2r, the third digital signal S1i, and the fourth digital signal S2i when filtering out mirror interference signals. The mirror suppression circuit 14 can select the first signal as a useful signal to filter out the second signal based on the first digital signal S1r, the second digital signal S2r, the third digital signal S1i, and the fourth digital signal S2i input to the mirror suppression circuit 14 by the symbol code generator; or, select the second signal as a useful signal to filter out the first signal.

[0144] Specifically, such as Figure 4aAs shown, the symbol code generator can be coupled with the control code generator to receive the image suppression control code and the quadrant control code input by the control code generator. Based on the quadrant control code, the image suppression control code, the coupling relationship between the phase shifter 13 and the first adder / subtractor 11 and the second adder / subtractor 12, and the coupling relationship between the phase shifter 13 and the input terminal of the differential circuit 14, it determines that the first digital signal S1r and the third digital signal S1i input to the first adder / subtractor 11, and the second digital signal S2r and the fourth digital signal S2i input to the second adder / subtractor 12 are 0 or 1.

[0145] Quadrant control codes are used to characterize the quadrant in which the useful signal resides. Image suppression mode is used to characterize that the first signal is the useful signal and the second signal is an image interference signal; or, image suppression mode is used to characterize that the first signal is an image interference signal and the second signal is the useful signal. Based on the phase of the input RF signal, 360° can be divided into four quadrants. Specifically, 0°-90° is the first quadrant, 90°-180° is the second quadrant, 180°-270° is the third quadrant, and 270°-360° is the fourth quadrant. If the quadrant control code is 0°-90°, the useful signal is located in the first quadrant; if the quadrant control code is 90°-180°, the useful signal is located in the second quadrant; if the quadrant control code is 180°-270°, the useful signal is located in the third quadrant; and if the quadrant control code is 270°-360°, the useful signal is located in the fourth quadrant.

[0146] When the image suppression mode MC is 0, it indicates that the first signal is a useful signal and the second signal is an image interference signal; when the image suppression mode MC is 1, it indicates that the first signal is an image interference signal and the second signal is a useful signal.

[0147] In some possible implementations, four sets of truth tables can be pre-set based on quadrant control codes, mirror suppression modes, the coupling relationship between phase shifter 13 and the first adder / subtractor 11 or the second adder / subtractor 12, and the coupling relationship between the input side of differential circuit 14 and phase shifter 13. The first digital signal S1r, the second digital signal S2r, the third digital signal S1i, and the fourth digital signal S2i are determined to be 0 or 1 based on the data in the truth tables.

[0148] like Figure 3a As shown, if phase shifter 13 is coupled to the first adder / subtractor 11 to phase shift the first synthesized signal IFI, and the negative input terminal of differential circuit 14 is coupled to phase shifter 13 and the positive input terminal is coupled to the second adder / subtractor 12, then the first set of truth tables can be determined according to the quadrant control code and the image suppression mode, as shown in Tables 1 and 2. For ease of description, the following description will use the first set of truth tables, i.e., Tables 1 and 2, as examples.

[0149] Table 1

[0150] Quadrant control codes MC S1r S2r S1i S2i First Quadrant 0 1 0 1 1 Second Quadrant 0 0 1 1 1 Third Quadrant 0 0 1 0 0 Fourth Quadrant 0 1 0 0 0

[0151] Table 2

[0152] Quadrant control codes MC S1r S2r S1i S2i First Quadrant 1 1 1 0 1 Second Quadrant 1 0 0 0 1 Third Quadrant 1 0 0 1 0 Fourth Quadrant 1 1 1 1 0

[0153] like Figure 3d As shown, if the phase shifter 13 is coupled to the first adder / subtractor 11 to phase shift the first synthesized signal IFI, and the positive input terminal of the differential circuit 14 is coupled to the phase shifter 13 and the negative input terminal is coupled to the second adder / subtractor 12, then the second set of truth tables can be determined according to the quadrant control code and the image suppression mode.

[0154] like Figure 3e As shown, if the phase shifter 13 is coupled to the second adder / subtractor 12 to phase shift the second synthesized signal IFQ, and the negative input terminal of the differential circuit 14 is coupled to the phase shifter 13 and the positive input terminal is coupled to the first adder / subtractor 11, then the third set of truth tables can be determined according to the quadrant control code and the image suppression mode.

[0155] like Figure 3f As shown, if the phase shifter 13 is coupled to the second adder / subtractor 12 to phase shift the second synthesized signal IFQ, and the positive input terminal of the differential circuit 14 is coupled to the phase shifter 13 and the negative input terminal is coupled to the first adder / subtractor 11, then the fourth set of truth tables can be determined according to the quadrant control code and the image suppression mode.

[0156] Furthermore, as mentioned above, this application can not only utilize the first adjustable RF amplifier VGA1 and the second adjustable RF amplifier VGA2 (or, the first adjustable RF amplifier VGA1, the second adjustable RF amplifier VGA2, the third adjustable RF amplifier VGA3, the fourth adjustable RF amplifier VGA4, the fifth adjustable RF amplifier VGA5, and the sixth adjustable RF amplifier VGA6) to amplify the RF signal to different degrees based on the variable first gain r1 and the second gain i1 (or, the first gain r1, the second gain i1, the third gain r2, and the fourth gain i2), but also utilize the first adjustable RF amplifier VGA1 and the second... The adjustable RF amplifier VGA2 (or the first adjustable RF amplifier VGA1, the second adjustable RF amplifier VGA2, the third adjustable RF amplifier VGA3, the fourth adjustable RF amplifier VGA4, the fifth adjustable RF amplifier VGA5, and the sixth adjustable RF amplifier VGA6) adjusts the phase of the RF signal RF according to the variable first gain r1 and second gain i1 (or the first gain r1, the second gain i1, the third gain r2, and the fourth gain i2), in conjunction with the first in-phase mixer H1, the first quadrature mixer H2, the second quadrature mixer H3, the second in-phase mixer H4, the first adder / subtractor 11, and the second adder / subtractor 12.

[0157] like Figure 4b As shown, for the function of amplifying the radio frequency signal RF according to the variable first gain r1 and second gain i1, regardless of whether the useful signal after filtering out the image interference signal is located in the first quadrant Q1, the second quadrant Q2, the third quadrant Q3, or the fourth quadrant Q4, the larger the first gain r1 and the second gain i1 (or, the first gain r1, the second gain i1, the third gain r2, and the fourth gain i2), the larger the amplified useful signal; the smaller the first gain r1 and the second gain i1 (or, the first gain r1, the second gain i1, the third gain r2, and the fourth gain i2), the smaller the amplified useful signal.

[0158] like Figure 4c As shown, for adjusting the phase of the RF signal according to the variable first gain r1 and second gain i1, if the useful signal after filtering out the image interference signal is located in the first quadrant Q1 or the third quadrant Q3, then the larger the second gain i1 (or, the second gain i and the fourth gain i2), the larger the phase of the useful signal; the smaller the second gain i1 (or, the second gain i and the fourth gain i2), the smaller the phase of the useful signal. If the useful signal after filtering out the image interference signal is located in the second quadrant Q2 or the fourth quadrant Q4, then the larger the second gain i1 (or, the second gain i1 and the fourth gain i2), the smaller the phase of the useful signal; the smaller the second gain i1 (or, the second gain i1 and the fourth gain i2), the larger the phase of the useful signal.

[0159] Of course, the relationship between phase change and gain change described above is based on the first set of truth tables mentioned above. If based on other truth tables, the relationship between phase change and gain change can be different.

[0160] The process of the receiver 101 filtering out image interference signals will be described in detail below, referring to the circuit diagram of the receiver 101 and Tables 1 and 2 above.

[0161] like Figure 3a and Figure 5a As shown, the first radio frequency signal A1 and the second radio frequency signal A2 are input to the first adjustable radio frequency amplifier VGA1 and the second adjustable radio frequency amplifier VGA2 with the same phase. It is assumed that the phase of the first radio frequency signal A1 and the second radio frequency signal A2 is 0°.

[0162] like Figure 3a and Figure 5bAs shown, after receiving the first radio frequency signal A1 and the second radio frequency signal A2, the first adjustable radio frequency amplifier VGA1 amplifies the first radio frequency signal A1 and the second radio frequency signal A2 with a first gain r1 and outputs the first radio frequency amplified signal RFr. The first radio frequency amplified signal RFr includes the first amplified signal A1Ar1 and the second amplified signal A2Ar1, and the phase of the first amplified signal A1Ar1 and the second amplified signal A2Ar1 does not change and remains at 0°.

[0163] like Figure 3a and Figure 5c As shown, after receiving the first RF signal A1 and the second RF signal A2, the second adjustable RF amplifier VGA2 amplifies the first RF signal A1 and the second RF signal A2 with the second gain i1, and outputs the second RF amplified signal RFi. The second RF amplified signal RFi includes the third amplified signal A1Ai1 and the fourth amplified signal A2Ai1, and the phase of the third amplified signal A1Ai1 and the fourth amplified signal A2Ai1 does not change and remains at 0°.

[0164] like Figure 3a and Figure 5d As shown, the first amplified signal A1Ar1 and the second amplified signal A2Ar1 are mixed with the first local oscillator signal LOI by the first in-phase mixer H1 to output the first in-phase intermediate frequency signal IFIr. The first in-phase intermediate frequency signal IFIr includes the first in-phase intermediate frequency signal jA1Ar1 obtained by mixing the first amplified signal A1Ar1 with the first local oscillator signal LOI, and the first in-phase intermediate frequency signal jA2Ar1 obtained by mixing the second amplified signal A2Ar1 with the first local oscillator signal LOI. Assume the first local oscillator signal LOI is sin(ω... LO t), take the first in-phase intermediate frequency signal IFIr from the mixing product, that is, ω IF =ω2-ω LO =ω LO -ω1, according to the mixing formula IF=(A1A r1 sinω1t+A2A r1 sinω2t)sinω LO As can be seen from t, the product of the first in-phase intermediate frequency signal IFIr is This includes the first in-phase intermediate frequency signal jA1Ar1 and the first in-phase intermediate frequency signal jA2Ar1. Assume ω IF When t is 0°, then cosω IF t is 90°, and the phases of the first in-phase intermediate frequency signal jA1Ar1 and the first in-phase intermediate frequency signal jA2Ar1 are both 90°. Where ω... IF This represents the angular frequency of the intermediate frequency signal, where ω... IFIt can be the angular frequency of the first in-phase intermediate frequency signal IFIr; ω1 represents the angular frequency of the first radio frequency signal A1; ω2 is the angular frequency of the second radio frequency signal A2; ω LO The first local oscillator signal LOI is represented by its angular frequency; sinω1t is the expression for the first radio frequency signal A1, and sinω2t is the expression for the second radio frequency signal A2.

[0165] like Figure 3a and Figure 5e As shown, the first amplified signal A1Ar1 and the second amplified signal A2Ar1 are mixed with the second local oscillator signal LOQ by the first quadrature mixer H2 to output the first quadrature intermediate frequency signal IFQr. The first quadrature intermediate frequency signal IFQr includes the first quadrature intermediate frequency signal -A1Ar1 obtained by mixing the first amplified signal A1Ar1 with the second local oscillator signal LOQ, and the first quadrature intermediate frequency signal A2Ar1 obtained by mixing the second amplified signal A2Ar1 with the second local oscillator signal LOQ. It is assumed that the second local oscillator signal LOQ is orthogonal to the first local oscillator signal LOQ by cos(ω). LO t). Take the first orthogonal intermediate frequency signal IFQr from the mixing product, i.e., ω IF =ω2-ω LO =ω LO -ω1, according to the mixing formula IF=(A1A r1 sinω1t+A2A r1 sinω2t)cosω LO As can be seen from t, the product of the first orthogonal intermediate frequency signal IFQr is This includes the first orthogonal intermediate frequency signal -A1Ar1 and the first orthogonal intermediate frequency signal A2Ar1. Assume ω IF When t is 0°, then sinω IF When t is 0°, the phase of the first orthogonal intermediate frequency signal -A1Ar1 becomes 180°, while the phase of the first orthogonal intermediate frequency signal A2Ar1 remains unchanged at 0°.

[0166] like Figure 3a and Figure 5f As shown, the third amplified signal A1Ai1 and the fourth amplified signal A2Ai1 are mixed with the second local oscillator signal LOQ by the second quadrature mixer H3 to output the second quadrature intermediate frequency signal IFQi. The second quadrature intermediate frequency signal IFQi includes the second quadrature intermediate frequency signal -A1Ai1 obtained by mixing the third amplified signal A1Ai1 with the second local oscillator signal LOQ, and the second quadrature intermediate frequency signal A2Ai1 obtained by mixing the fourth amplified signal A2Ai1 with the second local oscillator signal LOQ. It is assumed that the second local oscillator signal LOQ is orthogonal to the first local oscillator signal LOI, cos(ω...) LO t). Take the second orthogonal intermediate frequency signal IFQi from the mixing product, that is, ω IF =ω2-ωLO =ω LO -ω1, according to the mixing formula IF=(A1A i1 sinω1t+A2A i1 sinω2t)cosω LO As can be seen from t, the product of the second orthogonal intermediate frequency signal IFQi is It can be seen that this includes the second orthogonal intermediate frequency signal -A1Ai1 and the second orthogonal intermediate frequency signal A2Ai1. Assume ω IF When t is 0°, then sinω IF When t is 0°, the phase of the second orthogonal intermediate frequency signal -A1Ai1 becomes 180°, while the phase of the second orthogonal intermediate frequency signal A2Ai1 remains unchanged at 0°.

[0167] like Figure 3a and Figure 5g As shown, the third amplified signal A1Ai1 and the fourth amplified signal A2Ai1 are mixed with the second local oscillator signal LOQ by the second in-phase mixer H4 to output the second in-phase intermediate frequency signal IFIi. The second in-phase intermediate frequency signal IFIi includes the second in-phase intermediate frequency signal jA1Ai1 obtained by mixing the third amplified signal A1Ai1 with the first local oscillator signal LOI, and the second in-phase intermediate frequency signal jA2Ai1 obtained by mixing the fourth amplified signal A2Ai1 with the first local oscillator signal LOI. Assume the first local oscillator signal LOI is sin(ω... LO t), take the second in-phase intermediate frequency signal IFIi from the mixing product, that is, ω IF =ω2-ω LO =ω LO -ω1, according to the mixing formula IF=(A1A i1 sinω1t+A2A i1 sinω2t)sinω LO As can be seen from t, the product of the second in-phase intermediate frequency signal IFIi is This includes the second in-phase intermediate frequency (IF) signal jA1Ai1 and the second in-phase IF signal jA2Ai1. Assume ω IF When t is 0°, then cosω IF When t is 90°, the phases of the second in-phase intermediate frequency signal jA1Ai1 and the second in-phase intermediate frequency signal jA2Ai1 both become 90°.

[0168] Next, combining the first digital signal S1r and the third digital signal S1i, the first adder / subtractor 11 performs vector addition on the first in-phase intermediate frequency signal IFIr and the second quadrature intermediate frequency signal IFQi to obtain the first composite signal IFI, IFI = S1r * Ar1(jA1 + jA2) + S1i * Ai1(-A1 + A2); combining the second digital signal S2r and the fourth digital signal S2i, the second adder / subtractor 12 performs vector addition on the first quadrature intermediate frequency signal IFQr and the second in-phase intermediate frequency signal IFIi to obtain the second composite signal IFQ, IFQ = S2r * Ar1(-A1 + A2) + S2i * Ai1(jA1 + jA2).

[0169] Since both the first synthesized signal IFI and the second synthesized signal IFQ include parameters Ar1 and Ai1, they have the same amplitude. Based on the first, second, third, and fourth digital signals in Tables 1 and 2, the first synthesized signal IFI and the second synthesized signal IFQ can be controlled to have orthogonal phases.

[0170] Therefore, by coupling the phase shifter 13 between the first adder / subtractor 11 and the differential circuit 14, the first synthesized signal IFI can be phase-shifted by 90° using the phase shifter 13. In other words, the phase shifter 13 adds 90° to the phase of S1r*Ar1(jA1+jA2)+S1i*Ai1(-A1+A2) in the first synthesized signal IFI. Thus, IFI+90°=j*(S1r*Ar1(jA1+jA2)+S1i*Ai1(-A1+A2))=jS1i*Ai1(-A1+A2)-S1r*Ar1(A1+A2).

[0171] Then, the differential circuit 14 can be used to add the second synthesized signal IFQ and the first synthesized signal IFI after a 90° phase shift to filter out the image interference signal and output the useful signal IF. OUT Since phase shifter 13 is coupled to the negative input of differential circuit 14, and second adder / subtractor 12 is coupled to the positive input of differential circuit 14, differential circuit 14 can be used to subtract the second synthesized signal IFQ from the first synthesized signal IFI after a 90° phase shift. OUT =S2r*Ar1(-A1+A2)+S2i*Ai1(jA1+jA2)-(jS1i*Ai1(-A1+A2)-S1r*Ar1(A1+A2)) =A1(jAi1*(S2i+S1i)+Ar1*(S1r-S2r))+A2(-jAi1*(S1i-S2i)+Ar1(S1r+S2r)).

[0172] When S1i = S2i and S1r = -S2r (i.e., the sign of the third digital signal S1i is the same as the sign of the fourth digital signal S2i, and the sign of the first digital signal S1r is opposite to the sign of the second digital signal S2r), the first signal is retained as the useful signal, and the second signal is filtered out. When S1i = -S2i and S1r = S2r (i.e., the sign of the third digital signal S1i is opposite to the sign of the fourth digital signal S2i, and the sign of the first digital signal S1r is the same as the sign of the second digital signal S2r), the second signal is retained as the useful signal, and the first signal is filtered out.

[0173] According to Tables 1 and 2 above, regardless of whether the first signal or the second signal is retained, the quadrant in which the first signal is located can be adjusted by setting the first digital signal S1r, the second digital signal S2r, the third digital signal S1i, and the fourth digital signal S2r to 1 or 0. Specifically, this can include the following eight cases:

[0174] The first case, such as Figure 3a and Figure 5h As shown, taking the first signal as the useful signal and the second signal as the image interference signal, with the useful signal located in the first quadrant as an example, referring to Table 1 above, the first and third digital signals input by the symbol code generator to the first adder / subtractor 11 are both 1, and the phases of the first in-phase intermediate frequency signal IF1r and the second quadrature intermediate frequency signal IFQi are both positive. The second digital signal input by the symbol code generator to the second adder / subtractor 12 is 0, the fourth digital signal is 1, the phase of the first quadrature intermediate frequency signal IFQr is negative, and the phase of the second in-phase intermediate frequency signal IF1i is positive.

[0175] In this way, the first adder / subtractor 11 can control the vector addition of the first in-phase intermediate frequency signal IFIr (with positive phase) and the second quadrature intermediate frequency signal IFQi (with positive phase) to obtain the first synthesized signal IFI. Wherein, as... Figure 5i As shown, when the first in-phase intermediate frequency signal jA1Ar1 with a phase of 90° is vector-added to the second orthogonal intermediate frequency signal -A1Ai1 with a phase of 180°, the vector sum of the two signals, the first synthesized signal IFI, is jA1Ar1-A1Ai1, and the phase of jA1Ar1-A1Ai1 is located in the second quadrant. Similarly, when the first in-phase intermediate frequency signal jA2Ar1 with a phase of 90° is vector-added to the second orthogonal intermediate frequency signal A2Ai1 with a phase of 0°, the vector sum of the two signals, the first synthesized signal IFI, is jA2Ar1+A2Ai1, and the phase of jA2Ar1+A2Ai1 is located in the first quadrant.

[0176] Similarly, the second adder / subtractor 12 can control the vector addition of the first quadrature intermediate frequency signal IFQr (negative phase) and the second in-phase intermediate frequency signal IFIi (positive phase) to obtain the second synthesized signal IFQ. Wherein, as... Figure 5jAs shown, the first orthogonal intermediate frequency signal -A1Ar1 with a phase of 180° is inverted, resulting in a phase of 0°. When vectorially added to the second in-phase intermediate frequency signal jA1Ai1 with a phase of 90°, the resulting vector and the combined signal IFQ are -(-A1Ar1) + jA1Ai1 = jA1Ai1 + A1Ar1, with the phase of jA1Ai1 + A1Ar1 located in the first quadrant. Similarly, the first orthogonal intermediate frequency signal A2Ar1 with a phase of 0° is inverted, resulting in a phase of 180°. When vectorially added to the second in-phase intermediate frequency signal jA2Ai1 with a phase of 90°, the resulting vector and the combined signal IFQ are jA2Ai1 - A2Ar1, with the phase of jA2Ai1 - A2Ar1 located in the second quadrant.

[0177] like Figure 5i and Figure 5j As shown, since both the first synthesized signal IFI and the second synthesized signal IFQ include parameters Ar1 and Ai1, they have the same amplitude. Based on the first digital signal S1r, the second digital signal S2r, the third digital signal S1i, and the fourth digital signal S2r in Tables 1 and 2, the first synthesized signal IFI and the second synthesized signal IFQ can be controlled to have orthogonal phases.

[0178] Based on this, such as Figure 5k As shown, phase shifter 13 can be used to shift the phase of jA1Ar1-A1Ai1 and jA2Ar1+A2Ai1 in the first synthesized signal IFI by 90°. Alternatively, phase shifter 13 can be used to add 90° to the phase of jA1Ar1-A1Ai1 and jA2Ar1+A2Ai1 in the first synthesized signal IFI. Please refer to... Figure 5i and Figure 5k After rotating the first synthesized signal jA1Ar1-A1Ai1 and the first synthesized signal jA2Ar1+A2Ai1 clockwise by 90°, jA1Ar1-A1Ai1 becomes j(jA1Ar1-A1Ai1)=-A1Ar1-jA1Ai1, and jA2Ar1+A2Ai1 becomes j(jA2Ar1+A2Ai1)=jA2Ai1-A2Ar1.

[0179] like Figure 3a and Figure 5lAs shown, since the phase shifter 13 is coupled to the negative input of the differential circuit 14, and the second adder / subtractor 12 is coupled to the positive input of the differential circuit, the differential circuit 14 can be used to subtract the second synthesized signal IFQ from the first synthesized signal IFI after a 90° phase shift. That is, jA1Ai1+A1Ar1-(-A1Ar1-jA1Ai1)=2(jA1Ai1+A1Ar1), jA2Ai1-A2Ar1-(jA2Ai1-A2Ar1)=0. In this way, the second signal obtained by mixing the second RF signal A2 with the first local oscillator signal LOI and the second local oscillator signal LOQ can be filtered out, and the first signal can be retained as the useful signal. Furthermore, the retained first signal has the same phase as jA1Ai1+A1Ar1 in the second synthesized signal IFQ and is located in the first quadrant.

[0180] The second scenario, such as Figure 5h and Figure 6a As shown, taking the first signal as the useful signal, the second signal as the image interference signal, and the quadrant where the useful signal is located as the second quadrant as an example, referring to Table 1 above, the first digital signal input by the symbol code generator to the first adder / subtractor 11 is 0, the third digital signal is 1, the phase of the first in-phase intermediate frequency signal IFIr is negative, and the phase of the second quadrature intermediate frequency signal IFQi is positive. The second and fourth digital signals input by the symbol code generator to the second adder / subtractor 12 are both 1, and the phases of the first quadrature intermediate frequency signal IFQr and the second in-phase intermediate frequency signal IFIi are both positive.

[0181] In this way, the first adder / subtractor 11 can control the vector addition of the first in-phase intermediate frequency signal IFIr (negative phase) and the second quadrature intermediate frequency signal IFQi (positive phase) to obtain the first composite signal IFI. Specifically, the first in-phase intermediate frequency signal jA1Ar1 (90° phase) is inverted to have a phase of 270°. When this is vector-added to the second quadrature intermediate frequency signal -A1Ai1 (180° phase), the vector sum of these two signals, the first composite signal IFI, is -jA1Ar1-A1Ai1, with the phase of -jA1Ar1-A1Ai1 located in the third quadrant. Similarly, the first in-phase intermediate frequency signal jA2Ar1 (90° phase) is inverted to have a phase of 270°. When this is vector-added to the second quadrature intermediate frequency signal A2Ai1 (0° phase), the vector sum of these two signals, the first composite signal IFI, is -jA2Ar1+A2Ai1, with the phase of -jA2Ar1+A2Ai1 located in the fourth quadrant.

[0182] Similarly, the second adder / subtractor 12 can control the vector addition of the first orthogonal intermediate frequency signal IFQr with positive phase and the second in-phase intermediate frequency signal IFIi with positive phase to obtain the second composite signal IFQ. Specifically, after the vector addition of the first orthogonal intermediate frequency signal -A1Ar1 with a phase of 180° and the second in-phase intermediate frequency signal jA1Ai1 with a phase of 90°, the vectors of the two signals and the second composite signal IFQ are jA1Ai1-A1Ar1, and the phase of jA1Ai1-A1Ar1 is located in the second quadrant. After the vector addition of the first orthogonal intermediate frequency signal A2Ar1 with a phase of 0° and the second in-phase intermediate frequency signal jA2Ai1 with a phase of 90°, the vectors of the two signals and the second composite signal IFQ are jA2Ai1+A2Ar1, and the phase of jA2Ai1+A2Ar1 is located in the first quadrant.

[0183] Since both the first synthesized signal IFI and the second synthesized signal IFQ include parameters Ar1 and Ai1, they have the same amplitude. Based on the first digital signal S1r, the second digital signal S2r, the third digital signal S1i, and the fourth digital signal S2r in Tables 1 and 2, the first synthesized signal IFI and the second synthesized signal IFQ can be controlled to have orthogonal phases.

[0184] Based on this, the phase shifter 13 can be used to shift the phase of -jA1Ar1-A1Ai1 and -jA2Ar1+A2Ai1 in the first synthesized signal IFI by 90°. In other words, the phase shifter 13 can be used to add 90° to the phase of -jA1Ar1-A1Ai1 and -jA2Ar1+A2Ai1 in the first synthesized signal IFI. After rotating the first synthesized signal -jA1Ar1-A1Ai1 and the first synthesized signal -jA2Ar1+A2Ai1 clockwise by 90°, -jA1Ar1-A1Ai1 becomes j(-jA1Ar1-A1Ai1)=A1Ar1-jA1Ai1, and -jA2Ar1+A2Ai1 becomes j(-jA2Ar1+A2Ai1)=A2Ar1+jA2Ai1.

[0185] like Figure 6aAs shown, since phase shifter 13 is coupled to the negative input of differential circuit 14, and second adder / subtractor 12 is coupled to the positive input of differential circuit, differential circuit 14 can be used to subtract the second synthesized signal IFQ from the first synthesized signal IFI after a 90° phase shift: jA1Ai1-A1Ar1-(A1Ar1-jA1Ai1)=2(jA1Ai1-A1Ar1), jA2Ai1+A2Ar1-(A2Ar1+jA2Ai1)=0. In this way, the second signal obtained by mixing the second RF signal A2 with the first local oscillator signal LOI and the second local oscillator signal LOQ can be filtered out, retaining the first signal as the useful signal. Furthermore, the retained first signal has the same phase as jA1Ai1-A1Ar1 in the second synthesized signal IFQ, and is located in the second quadrant.

[0186] The third scenario, such as Figure 5h and Figure 6b As shown, taking the first signal as the useful signal, the second signal as the image interference signal, and the useful signal located in the third quadrant as an example, referring to Table 1 above, the first and third digital signals input by the symbol code generator to the first adder / subtractor 11 are both 0, and the phases of the first in-phase intermediate frequency signal IFIr and the second quadrature intermediate frequency signal IFQi are both negative. The second digital signal input by the symbol code generator to the second adder / subtractor 12 is 1, the fourth digital signal is 0, the phase of the first quadrature intermediate frequency signal IFQr is positive, and the phase of the second in-phase intermediate frequency signal IFIi is negative.

[0187] In this way, the first adder / subtractor 11 can control the vector addition of the first in-phase intermediate frequency signal IFIr (negative phase) and the second quadrature intermediate frequency signal IFQi (negative phase) to obtain the first composite signal IFI. Specifically, the first in-phase intermediate frequency signal jA1Ar1 (90° phase) becomes 270° after being inverted; the second quadrature intermediate frequency signal -A1Ai1 (180° phase) becomes 0° after being inverted. The vector sum of the inverted first in-phase intermediate frequency signal jA1Ar1 and the inverted second quadrature intermediate frequency signal -A1Ai1, resulting in the first composite signal IFI, is -jA1Ar1 - (-A1Ai1) = A1Ai1 - jA1Ar1, where A1Ai1 - jA1Ar1 is located in the fourth quadrant. Inverting the first in-phase intermediate frequency signal jA2Ar1 (90° phase) results in a phase of 270°; inverting the second quadrature intermediate frequency signal A2Ai1 (0° phase) results in a phase of 180°. Vector-wise addition of the inverted first in-phase intermediate frequency signal jA2Ar1 and the inverted second quadrature intermediate frequency signal A2Ai1 yields a vector sum, the first synthesized signal IFI, which is -jA2Ar1-A2Ai1. The phase of -jA2Ar1-A2Ai1 lies in the third quadrant.

[0188] Similarly, the second adder / subtractor 12 can control the vector addition of the first orthogonal intermediate frequency signal IFQr with positive phase and the second in-phase intermediate frequency signal IFIi with negative phase to obtain the second composite signal IFQ. Specifically, the second in-phase intermediate frequency signal jA1Ai1 with a 90° phase, after being inverted, has a phase of 270°. When this is added to the vector of the first orthogonal intermediate frequency signal -A1Ar1 with a 180° phase, the vectors of these two signals and the second composite signal IFQ are -jA1Ai1 + (-A1Ar1) = -jA1Ai1 - A1Ar1, with the phase of -jA1Ai1 - A1Ar1 located in the third quadrant. After the second in-phase intermediate frequency signal jA2Ai1 with a phase of 90° is inverted, its phase is 270°. After vector addition with the first orthogonal intermediate frequency signal A2Ar1 with a phase of 0°, the vectors of the two signals and the second synthesized signal IFQ are A2Ar1-jA2Ai1, and the phase of A2Ar1-jA2Ai1 is located in the fourth quadrant.

[0189] Since both the first synthesized signal IFI and the second synthesized signal IFQ include parameters Ar1 and Ai1, they have the same amplitude. Based on the first digital signal S1r, the second digital signal S2r, the third digital signal S1i, and the fourth digital signal S2r in Tables 1 and 2, the first synthesized signal IFI and the second synthesized signal IFQ can be controlled to have orthogonal phases.

[0190] Based on this, the phase shifter 13 can be used to shift the phase of A1Ai1-jA1Ar1 and -jA2Ar1-A2Ai1 in the first synthesized signal IFI by 90°. In other words, the phase shifter 13 can be used to add 90° to the phase of A1Ai1-jA1Ar1 and -jA2Ar1-A2Ai1 in the first synthesized signal IFI. After rotating the first synthesized signal A1Ai1-jA1Ar1 and the first synthesized signal -jA2Ar1-A2Ai1 clockwise by 90°, A1Ai1-jA1Ar1 becomes j(A1Ai1-jA1Ar1)=jA1Ai1+A1Ar1, and -jA2Ar1-A2Ai1 becomes j(-jA2Ar1-A2Ai1)=A2Ar1-jA2Ai1.

[0191] like Figure 6bAs shown, since phase shifter 13 is coupled to the negative input of differential circuit 14, and second adder / subtractor 12 is coupled to the positive input of differential circuit, differential circuit 14 can be used to subtract the second synthesized signal IFQ from the first synthesized signal IFI after a 90° phase shift. That is, -jA1Ai1-A1Ar1-(jA1Ai1+A1Ar1)=2(-jA1Ai1-A1Ar1), A2Ar1-jA2Ai1-(A2Ar1-jA2Ai1)=0. In this way, the second signal obtained by mixing the second RF signal A2 with the first local oscillator signal LOI and the second local oscillator signal LOQ can be filtered out, and the first signal can be retained as the useful signal. Furthermore, the retained first signal has the same phase as -jA1Ai1-A1Ar1 in the second synthesized signal IFQ and is located in the third quadrant.

[0192] The fourth case, such as Figure 5h and Figure 6c As shown, taking the first signal as the useful signal, the second signal as the image interference signal, and the useful signal located in the fourth quadrant as an example, referring to Table 1 above, the first digital signal input by the symbol code generator to the first adder / subtractor 11 is 1, the third digital signal is 0, the phase of the first in-phase intermediate frequency signal IFIr is positive, and the phase of the second quadrature intermediate frequency signal IFQi is negative. The second and fourth digital signals input by the symbol code generator to the second adder / subtractor 12 are both 0, and the phases of the first quadrature intermediate frequency signal IFQr and the second in-phase intermediate frequency signal IFIi are both negative.

[0193] In this way, the first adder / subtractor 11 can control the vector addition of the first in-phase intermediate frequency signal IFIr (positive phase) and the second quadrature intermediate frequency signal IFQi (negative phase) to obtain the first composite signal IFI. Specifically, the second quadrature intermediate frequency signal -A1Ai1 (180° phase) is inverted to have a phase of 0°. When this is vector-added to the first in-phase intermediate frequency signal jA1Ar1 (90° phase), the vector sum of these two signals, the first composite signal IFI, is jA1Ar1 - (-A1Ai1) = jA1Ar1 + A1Ai1, with the phase of jA1Ar1 + A1Ai1 located in the first quadrant. Similarly, the second quadrature intermediate frequency signal A2Ai1 (0° phase) is inverted to have a phase of 180°. When this is vector-added to the first in-phase intermediate frequency signal jA2Ar1 (90° phase), the vector sum of these two signals, the first composite signal IFI, is jA2Ar1 - A2Ai1, with the phase of jA2Ar1 - A2Ai1 located in the second quadrant.

[0194] Similarly, the second adder / subtractor 12 can control the vector addition of the first quadrature intermediate frequency signal IFQr (negative phase) and the second in-phase intermediate frequency signal IFIi (negative phase) to obtain the second composite signal IFQ. Specifically, the first quadrature intermediate frequency signal -A1Ar1 (180° phase) becomes 0° after inversion; the second in-phase intermediate frequency signal jA1Ai1 (90° phase) becomes 270° after inversion. After adding the inverted first quadrature intermediate frequency signal -A1Ar1 and the inverted second in-phase intermediate frequency signal jA1Ai1, their vectors and the second composite signal IFQ are -(-A1Ar1)-jA1Ai1=-jA1Ai1+A1Ar1, with the phase of -jA1Ai1+A1Ar1 located in the fourth quadrant. The first quadrature intermediate frequency (IF) signal A2Ar1, with a phase of 0°, is inverted to have a phase of 180°; the second in-phase IF signal jA2Ai1, with a phase of 90°, is inverted to have a phase of 270°. After vectorially adding the inverted first quadrature IF signal A2Ar1 and the inverted second in-phase IF signal jA2Ai1, the vector sum of the two signals and the resulting composite signal IFQ is -jA2Ai1-A2Ar1, and the phase of -jA2Ai1-A2Ar1 lies in the third quadrant.

[0195] Since both the first synthesized signal IFI and the second synthesized signal IFQ include parameters Ar1 and Ai1, they have the same amplitude. Based on the first digital signal S1r, the second digital signal S2r, the third digital signal S1i, and the fourth digital signal S2r in Tables 1 and 2, the first synthesized signal IFI and the second synthesized signal IFQ can be controlled to have orthogonal phases.

[0196] Based on this, the phase shifter 13 can be used to shift the phases of jA1Ar1+A1Ai1 and jA2Ar1-A2Ai1 in the first synthesized signal IFI by 90°. Alternatively, the phase shifter 13 can be used to add 90° to the phases of jA1Ar1+A1Ai1 and jA2Ar1-A2Ai1 in the first synthesized signal IFI. After rotating the first synthesized signals jA1Ar1+A1Ai1 and jA2Ar1-A2Ai1 clockwise by 90°, jA1Ar1+A1Ai1 becomes j(jA1Ar1+A1Ai1)=jA1Ai1-A1Ar1, and jA2Ar1+A2Ai1 becomes j(jA2Ar1-A2Ai1)=-A2Ar1-jA2Ai1.

[0197] like Figure 6cAs shown, since the phase shifter 13 is coupled to the negative input of the differential circuit 14, and the second adder / subtractor 12 is coupled to the positive input of the differential circuit, the differential circuit 14 can be used to subtract the second synthesized signal IFQ from the first synthesized signal IFI after a 90° phase shift. That is, -jA1Ai1+A1Ar1-(jA1Ai1-A1Ar1)=2(A1Ar1-jA1Ai1), -jA2Ai1-A2Ar1-(-A2Ar1-jA2Ai1)=0. In this way, the second signal obtained by mixing the second RF signal A2 with the first local oscillator signal LOI and the second local oscillator signal LOQ can be filtered out, and the first signal can be retained as the useful signal. Furthermore, the retained first signal has the same phase as -jA1Ai1+A1Ar1 in the second synthesized signal IFQ and is located in the fourth quadrant.

[0198] The fifth situation, such as Figure 7a and Figure 7b As shown, taking the first signal as the mirror interference signal and the second signal as the useful signal, with the useful signal located in the first quadrant as an example, referring to Table 2 above, the first digital signal input by the symbol code generator to the first adder / subtractor 11 is 1, the third digital signal is 0, the phase of the first in-phase intermediate frequency signal IFIr is positive, and the phase of the second quadrature intermediate frequency signal IFQi is negative. The second and fourth digital signals input by the symbol code generator to the second adder / subtractor 12 are both 1, and the phases of the first quadrature intermediate frequency signal IFQr and the second in-phase intermediate frequency signal IFIi are both positive.

[0199] In this way, the first adder / subtractor 11 can control the vector addition of the first in-phase intermediate frequency signal IFIr (positive phase) and the second quadrature intermediate frequency signal IFQi (negative phase) to obtain the first composite signal IFI. Specifically, the second quadrature intermediate frequency signal -A1Ai1 (180° phase) is inverted to have a phase of 0°. When this is vector-added to the first in-phase intermediate frequency signal jA1Ar1 (90° phase), the vector sum of these two signals, the first composite signal IFI, is jA1Ar1 - (-A1Ai1) = jA1Ar1 + A1Ai1, with the phase of jA1Ar1 + A1Ai1 located in the first quadrant. Similarly, the second quadrature intermediate frequency signal A2Ai1 (0° phase) is inverted to have a phase of 180°. When this is vector-added to the first in-phase intermediate frequency signal jA2Ar1 (90° phase), the vector sum of these two signals, the first composite signal IFI, is jA2Ar1 - A2Ai1, with the phase of jA2Ar1 - A2Ai1 located in the second quadrant.

[0200] Similarly, the second adder / subtractor 12 can control the vector addition of the first orthogonal intermediate frequency signal IFQr with positive phase and the second in-phase intermediate frequency signal IFIi with positive phase to obtain the second composite signal IFQ. Specifically, after the vector addition of the first orthogonal intermediate frequency signal -A1Ar1 with a phase of 180° and the second in-phase intermediate frequency signal jA1Ai1 with a phase of 90°, the vectors of the two signals and the second composite signal IFQ are jA1Ai1-A1Ar1, and the phase of jA1Ai1-A1Ar1 is located in the second quadrant. After the vector addition of the first orthogonal intermediate frequency signal A2Ar1 with a phase of 0° and the second in-phase intermediate frequency signal jA2Ai1 with a phase of 90°, the vectors of the two signals and the second composite signal IFQ are jA2Ai1+A2Ar1, and the phase of jA2Ai1+A2Ar1 is located in the first quadrant.

[0201] Since both the first synthesized signal IFI and the second synthesized signal IFQ include parameters Ar1 and Ai1, they have the same amplitude. Based on the first digital signal S1r, the second digital signal S2r, the third digital signal S1i, and the fourth digital signal S2r in Tables 1 and 2, the first synthesized signal IFI and the second synthesized signal IFQ can be controlled to have orthogonal phases.

[0202] Based on this, phase shifter 13 can be used to shift the phases of jA1Ar1+A1Ai1 and jA2Ar1-A2Ai1 in the second synthesized signal IFQ by 90°. Alternatively, phase shifter 13 can be used to add 90° to the phases of jA1Ar1+A1Ai1 and jA2Ar1-A2Ai1 in the second synthesized signal IFQ. After rotating the second synthesized signal jA1Ar1+A1Ai1 and the second synthesized signal jA2Ar1-A2Ai1 clockwise by 90°, jA1Ar1+A1Ai1 becomes j(jA1Ar1+A1Ai1)=jA1Ai1-A1Ar1, and jA2Ar1-A2Ai1 becomes j(jA2Ar1-A2Ai1)=-A2Ar1-jA2Ai1.

[0203] like Figure 7bAs shown, since the phase shifter 13 is coupled to the negative input terminal of the differential circuit 14, and the second adder / subtractor 12 is coupled to the positive input terminal of the differential circuit, the differential circuit 14 can be used to subtract the second synthesized signal IFQ from the first synthesized signal IFI after a 90° phase shift. That is, jA1Ai1-A1Ar1-(jA1Ai1-A1Ar1)=0, jA2Ai1+A2Ar1-(-A2Ar1-jA2Ai1)=2(jA2Ai1+A2Ar1). In this way, the first signal obtained by mixing the first RF signal A1 with the first local oscillator signal LOI and the second local oscillator signal LOQ can be filtered out, and the second signal can be retained as the useful signal. Furthermore, the retained second signal has the same phase as jA2Ai1+A2Ar1 in the second synthesized signal IFQ and is located in the first quadrant.

[0204] The sixth case, such as Figure 7a and Figure 7c As shown, taking the first signal as the mirror interference signal and the second signal as the useful signal, with the useful signal located in the fourth quadrant as an example, referring to Table 2 above, the first and third digital signals input by the symbol code generator to the first adder / subtractor 11 are both 0, and the first in-phase intermediate frequency signal IFIr and the second quadrature intermediate frequency signal IFQi are both negative. The second digital signal input by the symbol code generator to the second adder / subtractor 12 is 0, the fourth digital signal is 1, the phase of the first quadrature intermediate frequency signal IFQr is negative, and the phase of the second in-phase intermediate frequency signal IFIi is positive.

[0205] In this way, the first adder / subtractor 11 can control the vector addition of the first in-phase intermediate frequency signal IFIr (negative phase) and the second quadrature intermediate frequency signal IFQi (negative phase) to obtain the first composite signal IFI. Specifically, the first in-phase intermediate frequency signal jA1Ar1 (90° phase) becomes 270° after being inverted; the second quadrature intermediate frequency signal -A1Ai1 (180° phase) becomes 0° after being inverted. The vector sum of the inverted first in-phase intermediate frequency signal jA1Ar1 and the inverted second quadrature intermediate frequency signal -A1Ai1, resulting in the first composite signal IFI, is -jA1Ar1 - (-A1Ai1) = A1Ai1 - jA1Ar1, where A1Ai1 - jA1Ar1 is located in the fourth quadrant. After inverting the first in-phase intermediate frequency signal jA2Ar1 with a phase of 90°, its phase becomes 270°; after inverting the second quadrature intermediate frequency signal A2Ai1 with a phase of 0°, its phase becomes 180°. The vector sum of the inverted first in-phase intermediate frequency signal jA2Ar1 and the inverted second quadrature intermediate frequency signal A2Ai1 is -jA2Ar1-A2Ai1, and the phase of -jA2Ar1-A2Ai1 lies in the third quadrant.

[0206] Similarly, the second adder / subtractor 12 can control the vector addition of the first quadrature intermediate frequency signal IFQr (negative phase) and the second in-phase intermediate frequency signal IFIi (positive phase) to obtain the second synthesized signal IFQ. Wherein, as... Figure 5j As shown, the first orthogonal intermediate frequency signal -A1Ar1 with a phase of 180° is inverted, resulting in a phase of 0°. When vectorially added to the second in-phase intermediate frequency signal jA1Ai1 with a phase of 90°, the resulting vector and the combined signal IFQ are -(-A1Ar1) + jA1Ai1 = jA1Ai1 + A1Ar1, with the phase of jA1Ai1 + A1Ar1 located in the first quadrant. Similarly, the first orthogonal intermediate frequency signal A2Ar1 with a phase of 0° is inverted, resulting in a phase of 180°. When vectorially added to the second in-phase intermediate frequency signal jA2Ai1 with a phase of 90°, the resulting vector and the combined signal IFQ are jA2Ai1 - A2Ar1, with the phase of jA2Ai1 - A2Ar1 located in the second quadrant.

[0207] Since both the first synthesized signal IFI and the second synthesized signal IFQ include parameters Ar1 and Ai1, they have the same amplitude. Based on the first digital signal S1r, the second digital signal S2r, the third digital signal S1i, and the fourth digital signal S2r in Tables 1 and 2, the first synthesized signal IFI and the second synthesized signal IFQ can be controlled to have orthogonal phases.

[0208] Based on this, the phase shifter 13 can be used to shift the phase of A1Ai1-jA1Ar1 and -jA2Ar1-A2Ai1 in the first synthesized signal IFI by 90°. In other words, the phase shifter 13 can be used to add 90° to the phase of A1Ai1-jA1Ar1 and -jA2Ar1-A2Ai1 in the first synthesized signal IFI. After rotating the first synthesized signal A1Ai1-jA1Ar1 and the first synthesized signal -jA2Ar1-A2Ai1 clockwise by 90°, A1Ai1-jA1Ar1 becomes j(A1Ai1-jA1Ar1)=jA1Ai1+A1Ar1, and -jA2Ar1-A2Ai1 becomes j(-jA2Ar1-A2Ai1)=A2Ar1-jA2Ai1.

[0209] like Figure 7cAs shown, since the phase shifter 13 is coupled to the negative input of the differential circuit 14, and the second adder / subtractor 12 is coupled to the positive input of the differential circuit, the differential circuit 14 can be used to subtract the second synthesized signal IFQ from the first synthesized signal IFI after a 90° phase shift. That is, jA1Ai1+A1Ar1-(jA1Ai1+A1Ar1)=0, jA2Ai1-A2Ar1-(A2Ar1-jA2Ai1)=2(jA2Ai1-A2Ar1). In this way, the first signal obtained by mixing the first RF signal A1 with the first local oscillator signal LOI and the second local oscillator signal LOQ can be filtered out, and the second signal can be retained as the useful signal. Furthermore, the retained second signal has the same phase as jA2Ai1-A2Ar1 in the second synthesized signal IFQ and is located in the second quadrant.

[0210] The seventh case, such as Figure 7a and Figure 7d As shown, taking the first signal as the mirror interference signal, the second signal as the useful signal, and the useful signal located in the third quadrant as an example, referring to Table 2 above, the first digital signal input by the symbol code generator to the first adder / subtractor 11 is 0, the third digital signal is 1, the phase of the first in-phase intermediate frequency signal IFIr is negative, and the phase of the second quadrature intermediate frequency signal IFQi is positive. The second and fourth digital signals input by the symbol code generator to the second adder / subtractor 12 are both 0, and the phases of the first quadrature intermediate frequency signal IFQr and the second in-phase intermediate frequency signal IFIi are both negative.

[0211] In this way, the first adder / subtractor 11 can control the vector addition of the first in-phase intermediate frequency signal IFIr (negative phase) and the second quadrature intermediate frequency signal IFQi (positive phase) to obtain the first composite signal IFI. Specifically, the first in-phase intermediate frequency signal jA1Ar1 (90° phase) is inverted to have a phase of 270°. When this is vector-added to the second quadrature intermediate frequency signal -A1Ai1 (180° phase), the vector sum of these two signals, the first composite signal IFI, is -jA1Ar1-A1Ai1, with the phase of -jA1Ar1-A1Ai1 located in the third quadrant. Similarly, the first in-phase intermediate frequency signal jA2Ar1 (90° phase) is inverted to have a phase of 270°. When this is vector-added to the second quadrature intermediate frequency signal A2Ai1 (0° phase), the vector sum of these two signals, the first composite signal IFI, is -jA2Ar1+A2Ai1, with the phase of -jA2Ar1+A2Ai1 located in the fourth quadrant.

[0212] Similarly, the second adder / subtractor 12 can control the vector addition of the negative first quadrature intermediate frequency signal IFQr and the negative second in-phase intermediate frequency signal IFIi to obtain the second synthesized signal IFQ. Specifically, the first quadrature intermediate frequency signal -A1Ar1, with a phase of 180°, is inverted to have a phase of 0°; the second in-phase intermediate frequency signal jA1Ai1, with a phase of 90°, is inverted to have a phase of 270°. After the vector addition of the inverted first quadrature intermediate frequency signal -A1Ar1 and the inverted second in-phase intermediate frequency signal jA1Ai1, their vectors and the second synthesized signal IFQ are -(-A1Ar1)-jA1Ai1=-jA1Ai1+A1Ar1, with the phase of -jA1Ai1+A1Ar1 located in the fourth quadrant. The first quadrature intermediate frequency (IF) signal A2Ar1, with a phase of 0°, is inverted to have a phase of 180°; the second in-phase IF signal jA2Ai1, with a phase of 90°, is inverted to have a phase of 270°. After vectorially adding the inverted first quadrature IF signal A2Ar1 and the inverted second in-phase IF signal jA2Ai1, the vector sum of the two signals and the resulting composite signal IFQ is -jA2Ai1-A2Ar1, and the phase of -jA2Ai1-A2Ar1 lies in the third quadrant.

[0213] Since both the first synthesized signal IFI and the second synthesized signal IFQ include parameters Ar1 and Ai1, they have the same amplitude. Based on the first digital signal S1r, the second digital signal S2r, the third digital signal S1i, and the fourth digital signal S2r in Tables 1 and 2, the first synthesized signal IFI and the second synthesized signal IFQ can be controlled to have orthogonal phases.

[0214] Based on this, the phase shifter 13 can be used to shift the phase of -jA1Ar1-A1Ai1 and -jA2Ar1+A2Ai1 in the first synthesized signal IFI by 90°. In other words, the phase shifter 13 can be used to add 90° to the phase of -jA1Ar1-A1Ai1 and -jA2Ar1+A2Ai1 in the first synthesized signal IFI. After rotating the second synthesized signal -jA1Ar1-A1Ai1 and the second synthesized signal -jA2Ar1+A2Ai1 clockwise by 90°, -jA1Ar1-A1Ai1 becomes j(-jA1Ar1-A1Ai1)=A1Ar1-jA1Ai1, and -jA2Ar1+A2Ai1 becomes j(-jA2Ar1+A2Ai1)=A2Ar1+jA2Ai1.

[0215] like Figure 7dAs shown, since the phase shifter 13 is coupled to the negative input of the differential circuit 14, and the second adder / subtractor 12 is coupled to the positive input of the differential circuit, the differential circuit 14 can be used to subtract the second synthesized signal IFQ from the first synthesized signal IFI after a 90° phase shift. That is, A1Ar1-jA1Ai1-(A1Ar1-jA1Ai1)=0, -jA2Ai1-A2Ar1-(A2Ar1+jA2Ai1)=2(-jA2Ai1-A2Ar1). In this way, the first signal obtained by mixing the first RF signal A1 with the first local oscillator signal LOI and the second local oscillator signal LOQ can be filtered out, and the second signal can be retained as the useful signal. Furthermore, the retained second signal has the same phase as -jA2Ai1-A2Ar1 in the second synthesized signal IFQ and is located in the third quadrant.

[0216] The eighth case, such as Figure 7a and Figure 7e As shown, taking the first signal as the mirror interference signal and the second signal as the useful signal, with the useful signal located in the second quadrant as an example, referring to Table 2 above, the first and third digital signals input by the symbol code generator to the first adder / subtractor 11 are both 1, and the phases of the first in-phase intermediate frequency signal IF1r and the second quadrature intermediate frequency signal IFQi are both positive. The second digital signal input by the symbol code generator to the second adder / subtractor 12 is 1, the fourth digital signal is 0, the phase of the first quadrature intermediate frequency signal IFQr is positive, and the phase of the second in-phase intermediate frequency signal IF1i is negative.

[0217] In this way, the first adder / subtractor 11 can control the vector addition of the first in-phase intermediate frequency signal IFIr (with positive phase) and the second quadrature intermediate frequency signal IFQi (with positive phase) to obtain the first synthesized signal IFI. Wherein, as... Figure 5i As shown, when the first in-phase intermediate frequency signal jA1Ar1 with a phase of 90° is vector-added to the second orthogonal intermediate frequency signal -A1Ai1 with a phase of 180°, the vector sum of the two signals, the first synthesized signal IFI, is jA1Ar1-A1Ai1, and the phase of jA1Ar1-A1Ai1 is located in the second quadrant. Similarly, when the first in-phase intermediate frequency signal jA2Ar1 with a phase of 90° is vector-added to the second orthogonal intermediate frequency signal A2Ai1 with a phase of 0°, the vector sum of the two signals, the first synthesized signal IFI, is jA2Ar1+A2Ai1, and the phase of jA2Ar1+A2Ai1 is located in the first quadrant.

[0218] Similarly, the second adder / subtractor 12 can control the vector addition of the first orthogonal intermediate frequency signal IFQr with positive phase and the second in-phase intermediate frequency signal IFIi with negative phase to obtain the second composite signal IFQ. Specifically, the second in-phase intermediate frequency signal jA1Ai1 with a 90° phase, after being inverted, has a phase of 270°. When this is added to the vector of the first orthogonal intermediate frequency signal -A1Ar1 with a 180° phase, the vectors of these two signals and the second composite signal IFQ are -jA1Ai1 + (-A1Ar1) = -jA1Ai1 - A1Ar1, with the phase of -jA1Ai1 - A1Ar1 located in the third quadrant. After the second in-phase intermediate frequency signal jA2Ai1 with a phase of 90° is inverted, its phase is 270°. After vector addition with the first orthogonal intermediate frequency signal A2Ar1 with a phase of 0°, the vectors of the two signals and the second synthesized signal IFQ are A2Ar1-jA2Ai1, and the phase of A2Ar1-jA2Ai1 is located in the fourth quadrant.

[0219] Since both the first synthesized signal IFI and the second synthesized signal IFQ include parameters Ar1 and Ai1, they have the same amplitude. Based on the first digital signal S1r, the second digital signal S2r, the third digital signal S1i, and the fourth digital signal S2r in Tables 1 and 2, the first synthesized signal IFI and the second synthesized signal IFQ can be controlled to have orthogonal phases.

[0220] Based on this, the phase shifter 13 can be used to shift the phases of jA1Ar1-A1Ai1 and jA2Ar1+A2Ai1 in the first synthesized signal IFI by 90°. In other words, the phase shifter 13 adds 90° to the phases of jA1Ar1-A1Ai1 and jA2Ar1+A2Ai1 in the first synthesized signal IFI. After rotating the first synthesized signals jA1Ar1-A1Ai1 and jA2Ar1+A2Ai1 clockwise by 90°, jA1Ar1-A1Ai1 becomes j(jA1Ar1-A1Ai1)=-A1Ar1-jA1Ai1, and jA2Ar1+A2Ai1 becomes j(jA2Ar1+A2Ai1)=-A2Ar1+jA2Ai1.

[0221] like Figure 7eAs shown, since the phase shifter 13 is coupled to the negative input terminal of the differential circuit 14, and the second adder / subtractor 12 is coupled to the positive input terminal of the differential circuit, the differential circuit 14 can be used to subtract the second synthesized signal IFQ from the first synthesized signal IFI after a 90° phase shift. That is, -jA1Ai1-A1Ar1-(-A1Ar1-jA1Ai1)=0, A2Ar1-jA2Ai1-(-A2Ar1+jA2Ai1)=2(A2Ar1-jA2Ai1). In this way, the first signal obtained by mixing the first RF signal A1 with the first local oscillator signal LOI and the second local oscillator signal LOQ can be filtered out, and the second signal can be retained as the useful signal. Furthermore, the retained second signal has the same phase as A2Ar1-jA2Ai1 in the second synthesized signal IFQ and is located in the fourth quadrant.

[0222] The above example uses the first local oscillator signal LOI as sin(ω) LO t), the second local oscillator signal LOQ is cos(ω LO Taking t) as an example, various scenarios for filtering out image interference signals are listed. Of course, the first local oscillator signal LOI and the second local oscillator signal LOQ can also be other than those listed, as long as the first local oscillator signal LOI and the second local oscillator signal LOQ are orthogonal.

[0223] also, Figure 3d , Figure 3e and Figure 3f The calculation method of the three truth tables corresponding to the receiver 101 shown is the same as the calculation method of the first truth table in the aforementioned embodiment, and is also within the protection scope of this application embodiment.

[0224] The specific circuit structures of the first adder / subtractor 11, the second adder / subtractor 12, and the differential circuit 14 mentioned above are not limited in the embodiments of this application.

[0225] In one embodiment, such as Figure 8a As shown, the symbol code generator may include a first switch K1, a second switch K2, a third switch K3, a fourth switch K4, a first inverter D1, and a second inverter D2. The first adder / subtractor 11 may include a first differential circuit OP1 and a second differential circuit OP2. The first differential circuit OP1 and the second differential circuit OP2 may, for example, be operational amplifiers.

[0226] A symbol code generator is used to generate a first initial digital signal S1; a first switch K1 and a second switch K2 are connected in parallel. The first switch K1 is used to receive a first in-phase intermediate frequency signal IFIr and the first initial digital signal S1. The second switch K2 is coupled to a first inverter D1 and is used to receive the first in-phase intermediate frequency signal IFIr and the inverted first initial digital signal S1.

[0227] The symbol code generator is also used to generate the third initial digital signal S3; the third switch K3 is connected in parallel with the fourth switch K4, and the third switch K3 is used to receive the second quadrature intermediate frequency signal IFQi and the third initial digital signal S3. The fourth switch K4 is coupled to the second inverter D2 and is used to receive the second quadrature intermediate frequency signal IFQi and the inverted third initial digital signal S3.

[0228] The output sides of the first switch K1 and the second switch K2 are coupled to the input side of the first differential circuit OP1, the output sides of the third switch K3 and the fourth switch K4 are coupled to the input side of the second differential circuit OP2, and the output sides of both the first differential circuit OP1 and the second differential circuit OP2 are coupled to the input side of the differential circuit 14.

[0229] like Figure 8a As shown, if the first switch K1 is coupled to the positive input terminal of the first differential circuit OP1, and the second switch K2 is coupled to the negative input terminal of the first differential circuit OP1, then the first initial digital signal S1 input to the first switch K1 and the second switch K2 is 1. If the required first digital signal S1r is 1, the first switch K1 can be turned on and the second switch K2 can be turned off. The first in-phase intermediate frequency signal IFIr is input to the positive input terminal of the first differential circuit OP1 through the first switch K1 and output from the first differential circuit OP1. If the required first digital signal S1r is 0, the first switch K1 can be turned off and the second switch K2 can be turned on. The first in-phase intermediate frequency signal IFIr is input to the negative input terminal of the first differential circuit OP1 through the second switch K2. The first differential circuit OP1 inverts the first in-phase intermediate frequency signal IFIr and outputs it.

[0230] Or, such as Figure 8b As shown, if the first switch K1 is coupled to the negative input terminal of the first differential circuit OP1, and the second switch K2 is coupled to the positive input terminal of the first differential circuit OP1, then the first initial digital signal S1 input to the first switch K1 and the second switch K2 is 0. If the required first digital signal S1r is 1, then the first switch K1 can be controlled to open and the second switch K2 can be controlled to open. The first in-phase intermediate frequency signal IFIr is input to the positive input terminal of the first differential circuit OP1 through the second switch K2 and output from the first differential circuit OP1. If the required first digital signal S1r is 0, then the first switch K1 can be controlled to open and the second switch K2 can be controlled to open. The first in-phase intermediate frequency signal IFIr is input to the negative input terminal of the first differential circuit OP1 through the first switch K1. The first differential circuit OP1 inverts the first in-phase intermediate frequency signal IFIr and outputs it.

[0231] like Figure 8aAs shown, if the third switch K3 is coupled to the positive input terminal of the second differential circuit OP2, and the fourth switch K4 is coupled to the negative input terminal of the second differential circuit OP2, then the third initial digital signal S3 input to the third switch K3 and the fourth switch K4 is 1. If the required third digital signal S1i is 1, then the third switch K3 can be turned on and the fourth switch K4 can be turned off. The second quadrature intermediate frequency signal IFQi is input to the positive input terminal of the second differential circuit OP2 through the third switch K3 and output from the second differential circuit OP2. If the required third digital signal S1i is 0, then the third switch K3 can be turned off and the fourth switch K4 can be turned on. The second quadrature intermediate frequency signal IFQi is input to the negative input terminal of the second differential circuit OP2 through the fourth switch K4. The second differential circuit OP2 inverts the second quadrature intermediate frequency signal IFQi and outputs it.

[0232] Or, such as Figure 8b As shown, if the third switch K3 is coupled to the negative input terminal of the second differential circuit OP2, and the fourth switch K4 is coupled to the positive input terminal of the second differential circuit OP2, then the third initial digital signal S3 input to the third switch K3 and the fourth switch K4 is 0. If the required third digital signal S1i is 1, then the third switch K3 can be controlled to open and the fourth switch K4 can be controlled to open. The second quadrature intermediate frequency signal IFQi is input to the positive input terminal of the second differential circuit OP2 through the fourth switch K4 and output from the second differential circuit OP2. If the required third digital signal S1i is 0, then the third switch K3 can be controlled to open and the fourth switch K4 can be controlled to open. The second quadrature intermediate frequency signal IFQi is input to the negative input terminal of the second differential circuit OP2 through the third switch K3. The second differential circuit OP2 inverts the second quadrature intermediate frequency signal IFQi and outputs it.

[0233] Furthermore, the first synthesized signal IFI is obtained by vector summation of the signals output by the first differential circuit OP1 and the second differential circuit OP2.

[0234] like Figure 8c As shown, the symbol code generator may include a fifth switch K5, a sixth switch K6, a seventh switch K7, an eighth switch K8, a third inverter D3, and a fourth inverter D4. The second adder / subtractor 12 may include a third differential circuit OP3 and a fourth differential circuit OP4. The third differential circuit OP3 and the fourth differential circuit OP4 may, for example, be operational amplifiers.

[0235] A symbol code generator is used to generate the second initial digital signal S2; the fifth switch K5 and the sixth switch K6 are connected in parallel. The fifth switch K5 is used to receive the first quadrature intermediate frequency signal IFQr and the second initial digital signal S2. The sixth switch K6 is coupled to the third inverter D3 and is used to receive the first quadrature intermediate frequency signal IFQr and the inverted second initial digital signal S2.

[0236] The symbol code generator is also used to generate the fourth initial digital signal S4; the seventh switch K7 and the eighth switch K8 are connected in parallel. The seventh switch K7 is used to receive the second in-phase intermediate frequency signal IFIi and the fourth initial digital signal S4. The eighth switch K8 is coupled to the fourth inverter D4 and is used to receive the second in-phase intermediate frequency signal IFIi and the inverted fourth initial digital signal S4.

[0237] The output sides of the fifth switch K5 and the sixth switch K6 are coupled to the input side of the third differential circuit OP3, the output sides of the seventh switch K7 and the eighth switch K8 are coupled to the input side of the fourth differential circuit OP4, and the output sides of the third differential circuit OP3 and the fourth differential circuit OP4 are both coupled to the input side of the differential circuit 14.

[0238] like Figure 8c As shown, if the fifth switch K5 is coupled to the positive input terminal of the third differential circuit OP3, and the sixth switch K6 is coupled to the negative input terminal of the third differential circuit OP3, then the second initial digital signal S2 received by the fifth switch K5 and the sixth switch K6 is 1. If the required second digital signal S2r is 1, then the fifth switch K5 can be turned on and the sixth switch K6 can be turned off. The first quadrature intermediate frequency signal IFQr is input to the positive input terminal of the third differential circuit OP3 through the fifth switch K5 and output from the third differential circuit OP3. If the required second digital signal S2r is 0, then the fifth switch K5 can be turned off and the sixth switch K6 can be turned on. The first quadrature intermediate frequency signal IFQr is input to the negative input terminal of the third differential circuit OP3 through the sixth switch K6. The third differential circuit OP3 inverts the first quadrature intermediate frequency signal IFQr and outputs it.

[0239] Or, such as Figure 8d As shown, if the fifth switch K5 is coupled to the negative input terminal of the third differential circuit OP3, and the sixth switch K6 is coupled to the positive input terminal of the third differential circuit OP3, then the second initial digital signal S2 received by the fifth switch K5 and the sixth switch K6 is 0. If the required second digital signal S2r is 1, then the fifth switch K5 can be controlled to open and the sixth switch K6 can be controlled to open. The first quadrature intermediate frequency signal IFQr is input to the positive input terminal of the third differential circuit OP3 through the sixth switch K6 and output from the third differential circuit OP3. If the required second digital signal S2r is 0, then the fifth switch K5 can be controlled to open and the sixth switch K6 can be controlled to open. The first quadrature intermediate frequency signal IFQr is input to the negative input terminal of the third differential circuit OP3 through the fifth switch K5. The third differential circuit OP3 inverts the first quadrature intermediate frequency signal IFQr and outputs it.

[0240] like Figure 8cAs shown, if the seventh switch K7 is coupled to the positive input terminal of the fourth differential circuit OP4, and the eighth switch K8 is coupled to the negative input terminal of the fourth differential circuit OP4, then the fourth initial digital signal S4 received by the seventh switch K7 and the eighth switch K8 is 1. If the required fourth digital signal S2i is 1, then the seventh switch K7 can be turned on and the eighth switch K8 can be turned off. The second in-phase intermediate frequency signal IFIi is input to the positive input terminal of the fourth differential circuit OP4 through the seventh switch K7 and output from the fourth differential circuit OP4. If the required fourth digital signal S2i is 0, then the seventh switch K7 can be turned off and the eighth switch K8 can be turned on. The second in-phase intermediate frequency signal IFIi is input to the negative input terminal of the fourth differential circuit OP4 through the eighth switch K8. The fourth differential circuit OP4 inverts the second in-phase intermediate frequency signal IFIi and outputs it.

[0241] Or, such as Figure 8d As shown, if the seventh switch K7 is coupled to the negative input terminal of the fourth differential circuit OP4, and the eighth switch K8 is coupled to the positive input terminal of the fourth differential circuit OP4, then the fourth initial digital signal S4 received by the seventh switch K7 and the eighth switch K8 is 0. If the required fourth digital signal S2i is 1, then the seventh switch K7 can be controlled to open and the eighth switch K8 can be controlled to open. The second in-phase intermediate frequency signal IFIi is input to the positive input terminal of the fourth differential circuit OP4 through the eighth switch K8 and output from the fourth differential circuit OP4. If the required fourth digital signal S2i is 0, then the seventh switch K7 can be controlled to open and the eighth switch K8 can be controlled to open. The second in-phase intermediate frequency signal IFIi is input to the negative input terminal of the fourth differential circuit OP4 through the seventh switch K7. The fourth differential circuit OP4 inverts the second in-phase intermediate frequency signal IFIi and outputs it.

[0242] Furthermore, the second synthesized signal IFQ is obtained by vector summation of the signals output from the third differential circuit OP3 and the fourth differential circuit OP4.

[0243] In some possible implementations, embodiments of this application can determine that the first digital signal S1r, the second digital signal S2r, the third digital signal S1i, and the fourth digital signal S2r are 1 or 0 based on quadrant control codes and mirror suppression modes, so as to control the first switch K1, the second switch K2, the third switch K3, the fourth switch K4, the fifth switch K5, the sixth switch K6, the seventh switch K7, and the eighth switch K8 to be turned on or off, and execute one of the aforementioned four sets of truth tables.

[0244] In another embodiment, such as Figure 9aAs shown, the third adjustable RF amplifier VGA3, the fourth adjustable RF amplifier VGA4, the fifth adjustable RF amplifier VGA5, and the sixth adjustable RF amplifier VGA6 can be integrated with the symbol code generator. The third adjustable RF amplifier VGA3 includes a first sub-amplifier and a second sub-amplifier; the fourth adjustable RF amplifier VGA4 includes a third sub-amplifier and a fourth sub-amplifier; the fifth adjustable RF amplifier VGA5 includes a fifth sub-amplifier and a sixth sub-amplifier; and the sixth adjustable RF amplifier VGA6 includes a seventh sub-amplifier and an eighth sub-amplifier.

[0245] like Figure 9b As shown, the symbol code generator includes a first AND gate M1, a second AND gate M2, a third AND gate M3, a fourth AND gate M4, a fifth inverter, and a sixth inverter. The first adder / subtractor 11 includes a fifth differential circuit OP5 and a sixth differential circuit OP6.

[0246] The first AND gate M1 is used to receive the third gain r2 and the first initial digital signal S1; the output of the first AND gate M1 is coupled to the first sub-amplifier. The input of the first sub-amplifier receives the first in-phase intermediate frequency signal IFIr, and the output is coupled to the fifth differential circuit OP5.

[0247] The second AND gate M2 is used to receive the fourth gain i2 and the third initial digital signal S3; the output of the second AND gate M2 is coupled to the fifth sub-amplifier. The input of the fifth sub-amplifier receives the second quadrature intermediate frequency signal IFQi, and the output is coupled to the sixth differential circuit OP6.

[0248] The third AND gate M3 receives the fourth gain i2 and the third initial digital signal S3 after being inverted by the fifth inverter; the output of the third AND gate M3 is coupled to the sixth sub-amplifier. The input of the sixth sub-amplifier receives the second quadrature intermediate frequency signal IFQi, and the output is coupled to the fifth differential circuit OP5.

[0249] The fourth AND gate M4 is used to receive the third gain r2 and the first initial digital signal S1 after being inverted by the sixth inverter; the output of the fourth AND gate M4 is coupled to the second sub-amplifier. The input of the second sub-amplifier receives the first in-phase intermediate frequency signal IFIr, and the output is coupled to the sixth differential circuit OP6.

[0250] Based on the above, the output side of the fifth differential circuit OP5 and the output side of the sixth differential circuit OP6 are both coupled to the input side of the differential circuit 14.

[0251] like Figure 9bAs shown, if the output of the first sub-amplifier is coupled to the positive input of the fifth differential circuit OP5, and the output of the second sub-amplifier is coupled to the negative input of the sixth differential circuit OP6, then the first initial digital signal S1 received by the first AND gate M1 and the fourth AND gate M4 is 1. If the required first digital signal S1r is 1, then an enable signal can be input to the first sub-amplifier, but not to the second sub-amplifier, so that the first sub-amplifier works normally and the second sub-amplifier does not work. The first initial digital signal S1 (or the first digital signal S1r) with a third gain r2 of 1 is input to the first sub-amplifier through the first AND gate M1, and the first in-phase intermediate frequency signal IFIr is input to the positive input of the fifth differential circuit OP5 through the first sub-amplifier and output from the fifth differential circuit OP5. If the required first digital signal S1r is 0, then an enable signal can be input to the second sub-amplifier, but not to the first sub-amplifier, so that the first sub-amplifier does not work and the second sub-amplifier works normally. The first initial digital signal S1, which is 1, and the first digital signal S1r, which is 0 after being inverted, are input to the second sub-amplifier through the fourth AND gate M4. The first in-phase intermediate frequency signal IFIr is input to the negative input terminal of the sixth differential circuit OP6 through the second sub-amplifier. After being inverted in the sixth differential circuit OP6, it is output from the sixth differential circuit OP6.

[0252] Or, such as Figure 9c As shown, if the output of the first sub-amplifier is coupled to the negative input of the fifth differential circuit OP5, and the output of the second sub-amplifier is coupled to the positive input of the sixth differential circuit OP6, then the first initial digital signal S1 received by the first AND gate M1 and the fourth AND gate M4 is 0. If the required first digital signal S1r is 1, then an enable signal can be input to the second sub-amplifier without inputting an enable signal to the first sub-amplifier, so that the first sub-amplifier is not working and the second sub-amplifier is working normally. The first initial digital signal S1, which is 0, and the first digital signal S1r, which is 1 after being inverted, the third gain r2, and the first digital signal S1r, which is 1, are input to the second sub-amplifier through the fourth AND gate M4. The first in-phase intermediate frequency signal IFIr is input to the positive input of the sixth differential circuit OP6 through the second sub-amplifier and output from the sixth differential circuit OP6. If the required first digital signal S1r is 0, then an enable signal can be input to the first sub-amplifier without inputting an enable signal to the second sub-amplifier, so that the first sub-amplifier is working normally and the second sub-amplifier is not working. The first initial digital signal S1 (or the first digital signal S1r) with a third gain r2 of 0 is input to the first sub-amplifier through the first AND gate M1. The first in-phase intermediate frequency signal IFIr is input to the negative input terminal of the fifth differential circuit OP5 through the first sub-amplifier. After being inverted in the fifth differential circuit OP5, it is output from the fifth differential circuit OP5.

[0253] like Figure 9b As shown, if the output of the fifth sub-amplifier is coupled to the positive input of the sixth differential circuit OP6, and the output of the sixth sub-amplifier is coupled to the negative input of the fifth differential circuit OP5, then the third initial digital signal S3 received by the second AND gate M2 and the third AND gate M3 is 1. If the required third digital signal S1i is 1, then an enable signal can be input to the fifth sub-amplifier, but not to the sixth sub-amplifier, so that the fifth sub-amplifier works normally and the sixth sub-amplifier does not work. The third initial digital signal S3 (or the third digital signal S1i) with a fourth gain i2 of 1 is input to the fifth sub-amplifier through the second AND gate M2, and the second quadrature intermediate frequency signal IFQi is input to the positive input of the sixth differential circuit OP6 through the fifth sub-amplifier and output from the sixth differential circuit OP6. If the required third digital signal S1i is 0, then an enable signal can be input to the sixth sub-amplifier, but not to the fifth sub-amplifier, so that the fifth sub-amplifier does not work and the sixth sub-amplifier works normally. The third initial digital signal S3, which is 1, and the third digital signal S1i, which is 0 after being inverted, are input to the sixth sub-amplifier through the third AND gate M3. The second quadrature intermediate frequency signal IFQi is input to the negative input terminal of the fifth differential circuit OP5 through the sixth sub-amplifier. After being inverted in the fifth differential circuit OP5, it is output from the fifth differential circuit OP5.

[0254] Or, such as Figure 9c As shown, if the output of the fifth sub-amplifier is coupled to the negative input of the sixth differential circuit OP6, and the output of the sixth sub-amplifier is coupled to the positive input of the fifth differential circuit OP5, then the third initial digital signal S3 received by the second AND gate M2 and the third AND gate M3 is 0. If the required third digital signal S1i is 1, then an enable signal can be input to the sixth sub-amplifier without inputting an enable signal to the fifth sub-amplifier, so that the fifth sub-amplifier is not working and the sixth sub-amplifier is working normally. The third initial digital signal S3, which is 0, and the inverted third digital signal S1i, which is 1, are input to the sixth sub-amplifier through the third AND gate M3. The second quadrature intermediate frequency signal IFQi is input to the positive input of the fifth differential circuit OP5 through the sixth sub-amplifier and output from the fifth differential circuit OP5. If the required third digital signal S1i is 0, then an enable signal can be input to the fifth sub-amplifier without inputting an enable signal to the sixth sub-amplifier, so that the fifth sub-amplifier is working normally and the sixth sub-amplifier is not working. The third initial digital signal S3 (or the third digital signal S1i), with a fourth gain i2 and a sum of zero, is input to the fifth sub-amplifier through the second AND gate M2. The second quadrature intermediate frequency signal IFQi is input to the negative input terminal of the sixth differential circuit OP6 through the fifth sub-amplifier. After being inverted in the sixth differential circuit OP6, it is output from the sixth differential circuit OP6.

[0255] Furthermore, the first synthesized signal IFI is obtained by vector summation of the signals output from the fifth differential circuit OP5 and the sixth differential circuit OP6.

[0256] Furthermore, since the control circuit 15 will not enable the second sub-amplifier when the first sub-amplifier input is enabled, and will not enable the sixth sub-amplifier when the fifth sub-amplifier input is enabled, the power consumption of the receiver 101 will not increase further compared to the previous embodiment.

[0257] like Figure 9d As shown, the symbol code generator includes a fifth AND gate M5, a sixth AND gate M6, a seventh AND gate M7, an eighth AND gate M8, a seventh inverter, and an eighth inverter. The second adder / subtractor 12 includes a seventh differential circuit OP7 and an eighth differential circuit OP8.

[0258] The fifth AND gate M5 is used to receive the third gain r2 and the second initial digital signal S2; the output of the fifth AND gate M5 is coupled to the third sub-amplifier. The input of the third sub-amplifier receives the first quadrature intermediate frequency signal IFQr, and the output is coupled to the seventh differential circuit OP7.

[0259] The sixth AND gate M6 receives the fourth gain i2 and the fourth initial digital signal S4; the output of the sixth AND gate M6 is coupled to the seventh sub-amplifier. The input of the seventh sub-amplifier receives the second in-phase intermediate frequency signal IFIi, and the output is coupled to the eighth differential circuit OP8.

[0260] The seventh AND gate M7 receives the fourth gain i2 and the fourth initial digital signal S4 after being inverted by the seventh inverter; the output of the seventh AND gate M7 is coupled to the eighth sub-amplifier. The input of the eighth sub-amplifier receives the second in-phase intermediate frequency signal IFIi, and its output is coupled to the seventh differential circuit OP7.

[0261] The eighth AND gate M8 receives the third gain r2 and the second initial digital signal S2 after being inverted by the eighth inverter; the output of the eighth AND gate M8 is coupled to the fourth sub-amplifier. The input of the fourth sub-amplifier receives the first quadrature intermediate frequency signal IFQr, and its output is coupled to the eighth differential circuit OP8.

[0262] Based on the above, the output side of the seventh differential circuit OP7 and the output side of the eighth differential circuit OP8 are both coupled to the input side of the differential circuit 14.

[0263] like Figure 9dAs shown, if the output of the third sub-amplifier is coupled to the positive input of the seventh differential circuit OP7, and the output of the fourth sub-amplifier is coupled to the negative input of the eighth differential circuit OP8, then the second initial digital signal S2 received by the fifth AND gate M5 and the eighth AND gate M8 is 1. If the required second digital signal S2r is 1, then an enable signal can be input to the third sub-amplifier, but not to the fourth sub-amplifier, so that the third sub-amplifier works normally and the fourth sub-amplifier does not work. The second initial digital signal S2 (or the second digital signal S2r) with a third gain r2 of 1 is input to the third sub-amplifier through the fifth AND gate M5, and the first quadrature intermediate frequency signal IFQr is input to the positive input of the seventh differential circuit OP7 through the third sub-amplifier and output from the seventh differential circuit OP7. If the required second digital signal S2r is 0, then an enable signal can be input to the fourth sub-amplifier, but not to the third sub-amplifier, so that the third sub-amplifier does not work and the fourth sub-amplifier works normally. The second initial digital signal S2, which is 1, and the second digital signal S2r, which is 0 after being inverted, are input to the fourth sub-amplifier through the eighth AND gate M8. The first quadrature intermediate frequency signal IFQr is input to the negative input terminal of the eighth differential circuit OP8 through the fourth sub-amplifier. After being inverted in the eighth differential circuit OP8, it is output from the eighth differential circuit OP8.

[0264] Or, such as Figure 9e As shown, if the output of the third sub-amplifier is coupled to the negative input of the seventh differential circuit OP7, and the output of the fourth sub-amplifier is coupled to the positive input of the eighth differential circuit OP8, then the second initial digital signal S2 received by the fifth AND gate M5 and the eighth AND gate M8 is 0. If the required second digital signal S2r is 1, then an enable signal can be input to the fourth sub-amplifier without inputting an enable signal to the third sub-amplifier, so that the third sub-amplifier is not working and the fourth sub-amplifier is working normally. The second initial digital signal S2, which is 0, and the second digital signal S2r, which is 1 after inversion, are input to the fourth sub-amplifier through the eighth AND gate M8. The first quadrature intermediate frequency signal IFQr is input to the positive input of the eighth differential circuit OP8 through the fourth sub-amplifier and output from the eighth differential circuit OP8. If the required second digital signal S2r is 0, then an enable signal can be input to the third sub-amplifier without inputting an enable signal to the fourth sub-amplifier, so that the third sub-amplifier is working normally and the fourth sub-amplifier is not working. The second initial digital signal S2 (or the second digital signal S2r) with a third gain r2 of 0 is input to the third sub-amplifier through the fifth AND gate M5. The first quadrature intermediate frequency signal IFQr is input to the negative input terminal of the seventh differential circuit OP7 through the third sub-amplifier. After being inverted in the seventh differential circuit OP7, it is output from the seventh differential circuit OP7.

[0265] like Figure 9d As shown, if the output of the seventh sub-amplifier is coupled to the positive input of the eighth differential circuit OP8, and the output of the eighth sub-amplifier is coupled to the negative input of the seventh differential circuit OP7, then the fourth initial digital signal S4 received by the sixth AND gate M6 and the seventh AND gate M7 is 1. If the required fourth digital signal S2i is 1, then an enable signal can be input to the seventh sub-amplifier, but not to the eighth sub-amplifier, so that the seventh sub-amplifier works normally and the eighth sub-amplifier does not work. The fourth initial digital signal S4 (or the fourth digital signal S2i) with a fourth gain i2 of 1 is input to the seventh sub-amplifier through the sixth AND gate M6, and the second in-phase intermediate frequency signal IFIi is input to the positive input of the eighth differential circuit OP8 through the seventh sub-amplifier and output from the eighth differential circuit OP8. If the required fourth digital signal S2i is 0, then an enable signal can be input to the eighth sub-amplifier, but not to the seventh sub-amplifier, so that the seventh sub-amplifier does not work and the eighth sub-amplifier works normally. The fourth initial digital signal S4, which is 1, and the fourth digital signal S2i, which is 0 after being inverted, are input to the eighth sub-amplifier through the seventh AND gate M7. The second in-phase intermediate frequency signal IFIi is input to the negative input terminal of the seventh differential circuit OP7 through the eighth sub-amplifier. After being inverted in the seventh differential circuit OP7, it is output from the seventh differential circuit OP7.

[0266] Or, such as Figure 9e As shown, if the output of the seventh sub-amplifier is coupled to the negative input of the eighth differential circuit OP8, and the output of the eighth sub-amplifier is coupled to the positive input of the seventh differential circuit OP7, then the fourth initial digital signal S4 received by the sixth AND gate M6 and the seventh AND gate M7 is 0. If the required fourth digital signal S2i is 1, then an enable signal can be input to the eighth sub-amplifier without inputting an enable signal to the seventh sub-amplifier, so that the seventh sub-amplifier is not working and the eighth sub-amplifier is working normally. The fourth initial digital signal S4, which is 0, and the inverted fourth digital signal S2i, which is 1, are input to the eighth sub-amplifier through the seventh AND gate M7. The second in-phase intermediate frequency signal IFIi is input to the positive input of the seventh differential circuit OP7 through the eighth sub-amplifier and output from the seventh differential circuit OP7. If the required fourth digital signal S2i is 0, then an enable signal can be input to the seventh sub-amplifier without inputting an enable signal to the eighth sub-amplifier, so that the seventh sub-amplifier is working normally and the eighth sub-amplifier is not working. The fourth initial digital signal S4 (or the fourth digital signal S2i), with a gain of i2 equal to 0, is input to the seventh sub-amplifier through the sixth AND gate M6. The second in-phase intermediate frequency signal IFIi is input to the negative input terminal of the eighth differential circuit OP8 through the seventh sub-amplifier. After being inverted in the eighth differential circuit OP8, it is output from the eighth differential circuit OP8.

[0267] Furthermore, the second synthesized signal IFQ is obtained by vector summation of the signals output from the seventh differential circuit OP7 and the eighth differential circuit OP8.

[0268] Furthermore, since the control circuit 15 will not enable the fourth sub-amplifier when the third sub-amplifier input is enabled, and will not enable the eighth sub-amplifier when the seventh sub-amplifier input is enabled, the power consumption of the receiver 101 will not increase at the same time compared to the previous embodiment.

[0269] The two embodiments described above illustrate two cases where the symbol code controller inputs the first digital signal S1r, the second digital signal S2r, the third digital signal S1i, and the fourth digital signal S2i to the first adder / subtractor 11 and the second adder / subtractor 12. Of course, other circuit structures can also be used to input the first digital signal S1r, the second digital signal S2r, the third digital signal S1i, and the fourth digital signal S2i to the first adder / subtractor 11 and the second adder / subtractor 12. This application does not limit this, as long as the pattern of inputting the first digital signal S1r, the second digital signal S2r, the third digital signal S1i, and the fourth digital signal S2i to the first adder / subtractor 11 and the second adder / subtractor 12 conforms to the aforementioned four sets of truth tables, they all fall within the protection scope of this application.

[0270] The embodiments of this application have been described above with reference to the accompanying drawings. However, this application is not limited to the specific embodiments described above. The specific embodiments described above are merely illustrative and not restrictive. Those skilled in the art can make many other forms under the guidance of this application without departing from the spirit and scope of the claims, and all of these forms are within the protection scope of this application.

Claims

1. A receiver, characterized in that, It includes a first adjustable RF amplifier, a second adjustable RF amplifier, a first in-phase mixer, a first quadrature mixer, a second quadrature mixer, a second in-phase mixer, a first adder / subtractor, and a second adder / subtractor; The receiver is used to receive radio frequency signals; The radio frequency signal is amplified by the first adjustable radio frequency amplifier and then output as a first radio frequency amplified signal. The radio frequency signal is amplified by the second adjustable radio frequency amplifier and then output as a second radio frequency amplified signal. The first radio frequency amplified signal is mixed by the first in-phase mixer to output the first in-phase intermediate frequency signal, and is mixed by the first quadrature mixer to output the first quadrature intermediate frequency signal; The second RF amplified signal is mixed by the second quadrature mixer to output a second quadrature intermediate frequency signal, and then mixed by the second in-phase mixer to output a second in-phase intermediate frequency signal. The first in-phase intermediate frequency signal and the second quadrature intermediate frequency signal are selectively added or subtracted by the first adder / subtractor to output a first composite signal; the first quadrature intermediate frequency signal and the second in-phase intermediate frequency signal are selectively added or subtracted by the second adder / subtractor to output a second composite signal.

2. The receiver according to claim 1, characterized in that, The first adjustable RF amplifier amplifies the RF signal with an adjustable first gain; the second adjustable RF amplifier amplifies the RF signal with an adjustable second gain.

3. The receiver according to claim 2, characterized in that, After the first radio frequency amplified signal and the first local oscillator signal are mixed by the first in-phase mixer, the first in-phase intermediate frequency signal is output. After the first radio frequency amplified signal and the second local oscillator signal are mixed by the first quadrature mixer, the first quadrature intermediate frequency signal is output. After the second RF amplified signal and the second local oscillator signal are mixed by the second quadrature mixer, the second quadrature intermediate frequency signal is output. After the second RF amplified signal and the first local oscillator signal are mixed by the second in-phase mixer, the second in-phase intermediate frequency signal is output. The first local oscillator signal is orthogonal to the second local oscillator signal.

4. The receiver according to claim 3, characterized in that, The receiver further includes a control circuit, which includes a control code generator. The control code generator is used to input the first gain to the first adjustable RF amplifier and the second gain to the second adjustable RF amplifier.

5. The receiver according to claim 4, characterized in that, The control circuit further includes a symbol code generator, which is used to input a first digital signal and a third digital signal to the first adder / subtractor, and a second digital signal and a fourth digital signal to the second adder / subtractor. The first digital signal is used to determine whether the phase of the first in-phase intermediate frequency signal is positive or negative; the second digital signal is used to determine whether the phase of the first quadrature intermediate frequency signal is positive or negative; the third digital signal is used to determine whether the phase of the second quadrature intermediate frequency signal is positive or negative; and the fourth digital signal is used to determine whether the phase of the second in-phase intermediate frequency signal is positive or negative.

6. The receiver according to claim 5, characterized in that, When the first digital signal is 1, the phase of the first in-phase intermediate frequency signal is positive; when the first digital signal is 0, the phase of the first in-phase intermediate frequency signal is negative. When the second digital signal is 1, the phase of the first quadrature intermediate frequency signal is positive; when the second digital signal is 0, the phase of the first quadrature intermediate frequency signal is negative. When the third digital signal is 1, the phase of the second orthogonal intermediate frequency signal is positive; when the third digital signal is 0, the phase of the second orthogonal intermediate frequency signal is negative. When the fourth digital signal is 1, the phase of the second in-phase intermediate frequency signal is positive; when the fourth digital signal is 0, the phase of the second in-phase intermediate frequency signal is negative.

7. The receiver according to claim 5 or 6, characterized in that, Based on the first digital signal and the third digital signal, the first adder / subtractor performs vector synthesis on the first in-phase intermediate frequency signal with positive / negative phase and the second quadrature intermediate frequency signal with positive / negative phase to obtain the first synthesized signal; Based on the second digital signal and the fourth digital signal, the second adder / subtractor performs vector synthesis on the first quadrature intermediate frequency signal with positive / negative phase and the second in-phase intermediate frequency signal with positive / negative phase to obtain the second synthesized signal.

8. The receiver according to claim 7, characterized in that, The receiver also includes a differential circuit and a phase shifter; The phase shifter is coupled between the first adder / subtractor and the differential circuit to perform a 90° phase shift on the first synthesized signal; or, the phase shifter is coupled between the second adder / subtractor and the differential circuit to perform a 90° phase shift on the second synthesized signal. The differential circuit is used to add the second synthesized signal and the phase-shifted first synthesized signal, or the first synthesized signal and the phase-shifted second synthesized signal, to filter out the mirror interference signal in the first synthesized signal and the second synthesized signal.

9. The receiver according to claim 8, characterized in that, The phase shifter is coupled to the positive input terminal of the differential circuit; or, The phase shifter is coupled to the negative input terminal of the differential circuit.

10. The receiver according to claim 8 or 9, characterized in that, The radio frequency signal includes a first radio frequency signal and a second radio frequency signal, and the first radio frequency signal and the second radio frequency signal are mirror-symmetrical about the first local oscillator signal or the second local oscillator signal; both the first synthesized signal and the second synthesized signal include a first signal and a second signal; the first signal is obtained by amplifying and mixing the first radio frequency signal, and the second signal is obtained by amplifying and mixing the second radio frequency signal; The first signal is a useful signal, and the second signal is the image interference signal; or, The first signal is the mirror interference signal, and the second signal is the useful signal.

11. The receiver according to claim 10, characterized in that, The control code generator is coupled to the symbol code generator; The symbol code generator is also used to receive the image suppression control code and the quadrant control code sent by the control code generator, and input the first digital signal and the third digital signal to the first adder and subtractor, and input the second digital signal and the fourth digital signal to the second adder and subtractor according to the quadrant control code, the image suppression control code, the coupling relationship between the phase shifter and the first adder and subtractor and the second adder and subtractor, and the coupling relationship between the phase shifter and the input terminal of the differential circuit. The quadrant control code is used to characterize the quadrant in which the useful signal is located; The mirror suppression control code is used to characterize either the first signal as the useful signal or the second signal as the useful signal.

12. The receiver according to claim 10, characterized in that, The symbol code generator includes a first switch, a second switch, a third switch, a fourth switch, a first inverter, and a second inverter; the first adder / subtractor includes a first differential circuit and a second differential circuit. The symbol code generator is used to generate a first initial digital signal; the first switch and the second switch are connected in parallel; the first switch is used to receive the first in-phase intermediate frequency signal and the first initial digital signal; the second switch is coupled to the first inverter and is used to receive the first in-phase intermediate frequency signal and the inverted first initial digital signal. The symbol code generator is also used to generate a third initial digital signal; the third switch is connected in parallel with the fourth switch; the third switch is used to receive the second quadrature intermediate frequency signal and the third initial digital signal; the fourth switch is coupled to the second inverter and is used to receive the second quadrature intermediate frequency signal and the inverted third initial digital signal. The output sides of the first switch and the second switch are coupled to the input side of the first differential circuit, the output sides of the third switch and the fourth switch are coupled to the input side of the second differential circuit, and the output sides of both the first differential circuit and the second differential circuit are coupled to the input side of the differential circuit.

13. The receiver according to claim 12, characterized in that, The first switch is coupled to the positive input terminal of the first differential circuit, and the second switch is coupled to the negative input terminal of the first differential circuit. The first initial digital signal input to the first switch and the second switch is 1. or, The first switch is coupled to the negative input terminal of the first differential circuit, and the second switch is coupled to the positive input terminal of the first differential circuit. The first initial digital signal input to the first switch and the second switch is 0.

14. The receiver according to claim 12 or 13, characterized in that, The third switch is coupled to the positive input terminal of the second differential circuit, and the fourth switch is coupled to the negative input terminal of the second differential circuit. The third initial digital signal input to the third switch and the fourth switch is 1. or, The third switch is coupled to the negative input terminal of the second differential circuit, and the fourth switch is coupled to the positive input terminal of the second differential circuit. The third initial digital signal input to the third switch and the fourth switch is 0.

15. The receiver according to any one of claims 12-14, characterized in that, The symbol code generator includes a fifth switch, a sixth switch, a seventh switch, an eighth switch, a third inverter, and a fourth inverter; the second adder / subtractor includes a third differential circuit and a fourth differential circuit. The symbol code generator is used to generate a second initial digital signal; the fifth switch is connected in parallel with the sixth switch; The fifth switch is used to receive the first quadrature intermediate frequency signal and the second initial digital signal; the sixth switch is coupled to the third inverter and is used to receive the first quadrature intermediate frequency signal and the inverted second initial digital signal. The symbol code generator is also used to generate a fourth initial digital signal; the seventh switch is connected in parallel with the eighth switch; the seventh switch is used to receive the second in-phase intermediate frequency signal and the fourth initial digital signal; the eighth switch is coupled to the fourth inverter and is used to receive the second in-phase intermediate frequency signal and the inverted fourth initial digital signal. The output sides of the fifth and sixth switches are coupled to the input side of the third differential circuit, the output sides of the seventh and eighth switches are coupled to the input side of the fourth differential circuit, and the output sides of both the third and fourth differential circuits are coupled to the input side of the differential circuit.

16. The receiver according to claim 15, characterized in that, The fifth switch is coupled to the positive input terminal of the third differential circuit, and the sixth switch is coupled to the negative input terminal of the third differential circuit. The second initial digital signal input to the fifth switch and the sixth switch is 1. or, The fifth switch is coupled to the negative input terminal of the third differential circuit, and the sixth switch is coupled to the positive input terminal of the third differential circuit. The second initial digital signal input to the fifth switch and the sixth switch is 0.

17. The receiver according to claim 15 or 16, characterized in that, The seventh switch is coupled to the positive input terminal of the fourth differential circuit, and the eighth switch is coupled to the negative input terminal of the fourth differential circuit. The fourth initial digital signal input to the seventh switch and the eighth switch is 1. or, The seventh switch is coupled to the negative input terminal of the fourth differential circuit, and the eighth switch is coupled to the positive input terminal of the fourth differential circuit. The fourth initial digital signal input to the seventh switch and the eighth switch is 0.

18. The receiver according to claim 11, characterized in that, The receiver also includes a third adjustable radio frequency amplifier, a fourth adjustable radio frequency amplifier, a fifth adjustable radio frequency amplifier, and a sixth adjustable radio frequency amplifier; The first in-phase intermediate frequency signal, amplified by the third adjustable RF amplifier with the third gain, and the second quadrature intermediate frequency signal, amplified by the fifth adjustable RF amplifier with the fourth gain, are selectively added or subtracted by the first adder / subtractor to output the first synthesized signal. The first quadrature intermediate frequency signal, amplified by the fourth adjustable RF amplifier with the third gain, and the second in-phase intermediate frequency signal, amplified by the sixth adjustable RF amplifier with the fourth gain, are selectively added or subtracted by the second adder / subtractor to output the second synthesized signal.

19. The receiver according to claim 18, characterized in that, The third adjustable RF amplifier includes a first sub-amplifier and a second sub-amplifier; the fourth adjustable RF amplifier includes a third sub-amplifier and a fourth sub-amplifier; the fifth adjustable RF amplifier includes a fifth sub-amplifier and a sixth sub-amplifier; and the sixth adjustable RF amplifier includes a seventh sub-amplifier and an eighth sub-amplifier. The symbol code generator includes a first AND gate, a second AND gate, a third AND gate, a fourth AND gate, a fifth inverter, and a sixth inverter; the first adder / subtractor includes a fifth differential circuit and a sixth differential circuit. The first AND gate is used to receive the third gain and the first initial digital signal; the output side of the first AND gate is coupled to the first sub-amplifier; the input side of the first sub-amplifier receives the first in-phase intermediate frequency signal, and the output side is coupled to the fifth differential circuit. The second AND gate is used to receive the fourth gain and the third initial digital signal; the output side of the second AND gate is coupled to the fifth sub-amplifier; the input side of the fifth sub-amplifier receives the second quadrature intermediate frequency signal, and the output side is coupled to the sixth differential circuit. The third AND gate is used to receive the fourth gain and the third initial digital signal after being inverted by the fifth inverter; the output side of the third AND gate is coupled to the sixth sub-amplifier; the input side of the sixth sub-amplifier receives the second quadrature intermediate frequency signal, and the output side is coupled to the fifth differential circuit. The fourth AND gate is used to receive the third gain and the first initial digital signal after being inverted by the sixth inverter; the output side of the fourth AND gate is coupled to the second sub-amplifier; the input side of the second sub-amplifier receives the first in-phase intermediate frequency signal, and the output side is coupled to the sixth differential circuit. The output side of the fifth differential circuit and the output side of the sixth differential circuit are both coupled to the input side of the differential circuit.

20. The receiver according to claim 19, characterized in that, The output side of the first sub-amplifier is coupled to the positive input terminal of the fifth differential circuit, the output side of the second sub-amplifier is coupled to the negative input terminal of the sixth differential circuit, and the first initial digital signal received by the first AND gate and the fourth AND gate is 1; or, The output side of the first sub-amplifier is coupled to the negative input terminal of the fifth differential circuit, the output side of the second sub-amplifier is coupled to the positive input terminal of the sixth differential circuit, and the first initial digital signal received by the first AND gate and the fourth AND gate is 0.

21. The receiver according to claim 19 or 20, characterized in that, The output of the fifth sub-amplifier is coupled to the positive input of the sixth differential circuit, and the output of the sixth sub-amplifier is coupled to the negative input of the fifth differential circuit. The third initial digital signal received by the second AND gate and the third AND gate is 1; or, The output side of the fifth sub-amplifier is coupled to the negative input terminal of the sixth differential circuit, and the output side of the sixth sub-amplifier is coupled to the positive input terminal of the fifth differential circuit. The third initial digital signal received by the second AND gate and the third AND gate is 0.

22. The receiver according to any one of claims 19 or 20, characterized in that, The symbol code generator further includes a fifth AND gate, a sixth AND gate, a seventh AND gate, an eighth AND gate, a seventh inverter, and an eighth inverter; the second adder / subtractor includes a seventh differential circuit and an eighth differential circuit; The fifth AND gate is used to receive the third gain and the second initial digital signal; the output side of the fifth AND gate is coupled to the third sub-amplifier; the input side of the third sub-amplifier receives the first quadrature intermediate frequency signal, and the output side is coupled to the seventh differential circuit. The sixth AND gate is used to receive the fourth gain and the fourth initial digital signal; the output side of the sixth AND gate is coupled to the seventh sub-amplifier; the input side of the seventh sub-amplifier receives the second in-phase intermediate frequency signal, and the output side is coupled to the eighth differential circuit. The seventh AND gate is used to receive the second gain and the fourth initial digital signal after being inverted by the seventh inverter; the output side of the seventh AND gate is coupled to the eighth sub-amplifier; the input side of the eighth sub-amplifier receives the second in-phase intermediate frequency signal, and the output side is coupled to the seventh differential circuit. The eighth AND gate is used to receive the first gain and the second initial digital signal after being inverted by the eighth inverter; the output side of the eighth AND gate is coupled to the fourth sub-amplifier; the input side of the fourth sub-amplifier receives the first quadrature intermediate frequency signal, and the output side is coupled to the eighth differential circuit. The output side of the seventh differential circuit and the output side of the eighth differential circuit are both coupled to the input side of the differential circuit.

23. The receiver according to claim 22, characterized in that, The output of the third sub-amplifier is coupled to the positive input of the seventh differential circuit, and the output of the fourth sub-amplifier is coupled to the negative input of the eighth differential circuit. The second initial digital signal received by the fifth AND gate and the eighth AND gate is 1; or, The output side of the third sub-amplifier is coupled to the negative input terminal of the seventh differential circuit, the output side of the fourth sub-amplifier is coupled to the positive input terminal of the eighth differential circuit, and the second initial digital signal received by the fifth AND gate and the eighth AND gate is 0.

24. The receiver according to claim 22 or 23, characterized in that, The output of the seventh sub-amplifier is coupled to the positive input of the eighth differential circuit, and the output of the eighth sub-amplifier is coupled to the negative input of the seventh differential circuit. The fourth initial digital signal received by the sixth AND gate and the seventh AND gate is 1; or, The output side of the seventh sub-amplifier is coupled to the negative input terminal of the eighth differential circuit, and the output side of the eighth sub-amplifier is coupled to the positive input terminal of the seventh differential circuit. The fourth initial digital signal received by the sixth AND gate and the seventh AND gate is 0.

25. A radio frequency transceiver, characterized in that, Includes a transmitter and a receiver as described in any one of claims 1-24.

26. A terminal, characterized in that, Includes an antenna and the radio frequency transceiver as described in claim 25.

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