Memory expansion board card based on CXL technology, server and memory allocation method

Abstract

The invention relates to the technical field of storage equipment design, and discloses an expansion board card which aims at solving the problems that an expansion board card which uses a golden finger to plug and install a memory bank is large in size and small in capacity, and expansion management of a memory pool is inconvenient. The memory expansion board card based on the CXL technology comprises a CXL conversion module, at least one memory expansion control module, a plurality of memory pool modules and a main control module. The CXL conversion module is provided with an uplink port and a downlink port, and the uplink port is used for being connected with host equipment. One memory pool module is connected with a downlink port of the CXL conversion module through at least one memory expansion control module, and the memory pool module is provided with a plurality of memory particles in an integrated manner. And the main control module is connected with the downlink port. The memory expansion board card based on the CXL technology is used for expansion and shared connection of memory pools of one or more host devices.

Description

Technical Field

[0001] The present invention relates to the technical field of storage device design, and in particular to a memory expansion board, a server and a memory allocation method based on CXL technology. Background Art

[0002] CXL (Compute Express Link) is a new type of high-speed interconnect technology developed based on PCIE (Peripheral Component Interconnect Express) technology, designed to provide higher data throughput and lower latency. CXL technology provides an effective solution for data centers and high-performance computing environments. It not only improves memory performance and capacity, but also simplifies system integration and management through standardization and low latency features, ultimately helping users break through the limitations of the memory wall and achieve more efficient data processing and application performance.

[0003] At present, when using CXL technology for memory expansion, traditional gold finger memory sticks are usually used, that is, multiple memory sticks are installed on the substrate by plugging and unplugging gold fingers, so as to realize the integration and expansion of memory sticks. However, since the gold finger slots of the memory sticks have a large volume and occupy space, it is difficult to plug and install more memory sticks on the substrate for expansion, that is, the expansion substrate has the disadvantages of large volume and small capacity. In addition, the memory sticks installed by gold finger plugging are not convenient for the expansion management of the memory pool. Summary of the invention

[0004] In view of this, the present invention provides a memory expansion board, a server and a memory allocation method based on CXL technology, aiming to solve the problem that the expansion board using gold finger plug-in to install the memory stick has a large size and small capacity, and is not convenient for the expansion management of the memory pool.

[0005] In the first aspect, the present invention provides a memory expansion board based on CXL technology, including a CXL conversion module, at least one memory expansion control module, multiple memory pool modules and a main control module. The CXL conversion module has an upstream port and a downstream port, and the upstream port is used to connect to a host device. A memory pool module is connected to the downstream port of the CXL conversion module through at least one memory expansion control module, and the memory pool module is integrated with multiple memory particles. The main control module is connected to the downstream port.

[0006] Beneficial effects: One or more memory expansion control modules can be connected through the CXL conversion module, and up to 16 or 32 memory chips can be integrated in the memory pool module connected to the memory expansion control module. Since the area occupied by each memory chip is much smaller than that of a traditional memory stick, and it is possible to avoid setting up multiple gold finger slots with a large area for plugging in traditional memory sticks, more memory chips can be integrated and installed on a smaller expansion board, which has the advantages of small size and large capacity.

[0007] In addition, the gold finger plug-in installation scheme of the memory stick used in the related art is limited by the connection scheme of the gold finger, which will seriously limit the interconnection and topological performance between the memory particles. The present application integrates (encapsulates) multiple memory particles in the same memory pool module, and can flexibly set the connection between each memory particle, which is conducive to greatly improving the interconnection topological performance between the memory particles, such as reducing the delayed interconnection between the memory particles, and facilitating the expansion management of the memory pool. The main control module can monitor and regulate the real-time operating status of the memory pool module to balance the utilization rate of multiple memory pool modules and the memory occupancy rate of the host module.

[0008] Among them, the memory expansion board based on CXL technology provided in the embodiment of the present application can exist as an independent component, or the uplink port of the CXL conversion module can be connected to one or more host devices to serve as a memory pool of a host device, or as a shared memory pool of multiple host devices.

[0009] In some embodiments, there are multiple memory expansion control modules, one CXL conversion module has multiple downstream ports, and one downstream port is connected to one memory expansion control module. The number of memory pool modules is the same as the number of memory expansion control modules, and each memory pool module is connected to multiple memory expansion control modules. The main control module is at least used to balance the memory usage status of multiple memory pool modules.

[0010] Beneficial effect: Through the connection setting of the CXL conversion module, multiple memory expansion control modules and corresponding memory pool modules can be connected together to form a high-speed, scalable interconnected memory. By using the CXL conversion module, more efficient resource sharing and collaboration can be achieved, improving the overall performance of the system.

[0011] Since the main control module is connected to each memory pool module, the usage and actual usage rate of each memory pool module can be monitored through the setting of software or related programs for dynamic allocation of memory, so that the memory usage rate of all host devices is in a relatively balanced state, so that the server is in an overall stable and effective operation state.

[0012] In some embodiments, the memory pool module includes at least a first memory pool unit and a second memory pool unit. A first memory pool unit is connected to a memory expansion control module. In multiple memory pool modules connected to the same CXL conversion module, the first memory pool unit of each memory pool module is connected to multiple second memory pool units. The main control module is at least used to balance the memory usage status of multiple first memory pool units and multiple second memory pool units.

[0013] Beneficial effect: Since the overall memory of the first memory pool unit and the second memory pool unit is smaller than the overall memory of the memory pool module, the adaptive adjustment of the smaller memory pool is conducive to further improving the balanced adjustment effect of the memory occupancy rate of multiple host devices, such as making the up and down fluctuations of the memory load occupancy rate of multiple host devices smaller.

[0014] In some embodiments, the first memory pool unit is integrated with at least four memory particles, and the second memory pool unit is integrated with at least four memory particles.

[0015] The memory pool module also includes a third memory pool unit, a fourth memory pool unit and an ECC unit. The third memory pool unit is integrated with at least four memory particles. In multiple memory pool modules connected to the same CXL conversion module, the second memory pool unit of each memory pool module is connected to multiple third memory pool units. The fourth memory pool unit is integrated with at least four memory particles. In multiple memory pool modules connected to the same CXL conversion module, the third memory pool unit of each memory pool module is connected to multiple fourth memory pool units. The ECC unit is arranged between the memory expansion control module and the first memory pool unit, so that the memory expansion control module is connected to the first memory pool unit via the ECC unit.

[0016] Beneficial effect: Since the overall memory of the first memory pool unit, the second memory pool unit, the third memory pool unit and the fourth memory pool unit is smaller than the overall memory of the memory pool module, the adaptive adjustment of the smaller memory pool is conducive to further improving the balanced adjustment effect of the memory occupancy rate of multiple host devices. For example, the fluctuation of the memory load occupancy rate of multiple host devices is smaller.

[0017] Furthermore, through the check bits during data transmission, the ECC unit can detect and correct data errors in the transmitted data, thereby improving the host device (such as Figure 1 The stability of operation.

[0018] In some embodiments, the memory expansion board based on CXL technology also includes a main control substrate, a structural adapter board and a memory expansion board. The main control substrate is provided with at least a main control module and a first plug interface, and the first plug interface is connected to the main control module. The structural adapter board is provided with a first plug terminal, a plurality of second plug interfaces and a plurality of expansion high-speed connectors, and the plurality of second plug interfaces are connected to the first plug terminal, and one second plug interface is correspondingly connected to one expansion high-speed connector. The memory expansion board, the memory expansion board is provided with at least a CXL conversion module, a memory expansion control module, a memory pool module and a second plug terminal, and the second plug terminal is at least connected to the downstream port. The second plug terminal is plugged and adapted to the second plug interface so that the upstream port is connected to the host device via the expansion high-speed connector.

[0019] Beneficial effects: Through the configuration of the main control substrate, the structure adapter board and the memory expansion board, the CXL conversion modules and the memory pool modules on multiple memory expansion boards can be connected and managed through one main control module. In addition, through the configuration of the structure adapter board, one or more memory expansion boards can be expanded and plugged into one main control substrate as needed, thereby meeting different capacity requirements for the memory pool.

[0020] In some embodiments, the first plug end and the first plug interface are gold finger plug components, and the first plug end is plugged and installed with the first plug interface along the first straight line direction. The second plug end and the second plug interface are gold finger plug components, and the second plug end is plugged and installed with the second plug interface along the second straight line direction, and the first straight line direction is perpendicular to the second straight line direction. At the structural adapter plate, multiple second plug interfaces are spaced apart along the first straight line direction, and a vent is provided between two adjacent second plug interfaces.

[0021] Beneficial effect: multiple memory expansion boards that are connected to the second plug-in interface in sequence along the second straight line direction through the second plug-in end are arranged approximately parallel to the main control substrate, that is, multiple memory expansion boards can be installed in sequence along the vertical direction (first straight line direction), which is beneficial to improving the overall integration of the internal expansion board.

[0022] When the memory expansion board is plugged and installed with the structure adapter board along the second straight line direction, a ventilation hole is provided on one side of the structure adapter board between two adjacent memory expansion boards, so as to facilitate air circulation between the two adjacent memory expansion boards, so as to dissipate heat and cool down electronic components such as the CXL conversion module, the memory expansion control module and the memory pool module on the memory expansion board.

[0023] In some embodiments, a memory expansion board based on CXL technology includes a main control substrate, which is provided with at least a main control module, a CXL conversion module, a memory expansion control module, a memory pool module and a host high-speed connector. The CXL conversion module is used to connect to a host device via the host high-speed connector.

[0024] Beneficial effect: The main control substrate itself can be used as a memory pool for expanded applications.

[0025] In some embodiments, the memory pool module further includes an indicator light, which is used to display the operating status of the memory pool module and is configured as follows:

[0026] When the memory usage of the memory pool module is less than the first preset value, the indicator light is on and is green. When the memory usage of the memory pool module is greater than or equal to the first preset value and less than or equal to the second preset value, the indicator light is on and is yellow, and the second preset value is greater than the first preset value. When the memory usage of the memory pool module is greater than the second preset value, the indicator light is on and is red. When the memory pool module has a fault, the indicator light goes out.

[0027] Beneficial effect: By setting the indicator light, the operating status of the memory pool module can be quickly detected and judged.

[0028] In a second aspect, the present invention provides a server, comprising at least one host device and a memory expansion board based on the CXL technology in the previous aspect, wherein the host device is connected to an upstream port.

[0029] Beneficial effects: Since the server includes the memory expansion board based on the CXL technology in the above aspect, the server has all the beneficial effects of the memory expansion board based on the CXL technology, which will not be repeated here.

[0030] In a third aspect, the present invention provides a memory allocation method for a memory expansion board based on CXL technology, comprising:

[0031] The control main control module detects the memory usage status of multiple memory pool modules and the memory occupancy status of the host device, and allocates the memory pool module with a lower memory usage status to the host device with a higher memory occupancy rate.

[0032] Beneficial effect: By controlling the main control module to detect and monitor the memory usage status of the memory module and the memory occupancy status of the host device, and allocating memory modules with lower memory usage to host devices with higher memory usage, the usage rates of multiple memory pool modules and the memory occupancy rates of the host modules are balanced, so that the memory occupancy rate of the host device is in a more balanced state, so that the server is in an overall stable and efficient operating state. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] In order to more clearly illustrate the specific implementation methods of the present invention or the technical solutions in the prior art, the drawings required for use in the specific implementation methods or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some implementation methods of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0034] Figure 1 A schematic diagram of the structure of a server according to an embodiment of the present invention;

[0035] Figure 2 This is a schematic diagram of the structure of a first memory expansion board based on CXL technology according to an embodiment of the present invention;

[0036] Figure 3 This is a schematic diagram of the structure of a second memory expansion board based on CXL technology according to an embodiment of the present invention;

[0037] Figure 4 This is a schematic diagram of the structure of a third memory expansion board based on CXL technology according to an embodiment of the present invention;

[0038] Figure 5 A top view of a memory expansion board based on CXL technology according to an embodiment of the present invention;

[0039] Figure 6 for Figure 5 A front view of a memory expansion board based on CXL technology is shown in FIG;

[0040] Figure 7 A front view of a structural adapter card according to an embodiment of the present invention;

[0041] Figure 8 for Figure 7 A rear view of the structure adapter board shown;

[0042] Fig. 9 The present invention is a flowchart of a memory allocation method for a memory expansion card based on CXL technology according to an embodiment of the present invention.

[0043] Description of reference numerals:

[0044] 100. Server;

[0045] 10. Host equipment;

[0046] 20. Memory expansion board based on CXL technology;

[0047] 21. CXL conversion module; 211. Uplink port; 212. Downlink port;

[0048] 22. Memory expansion control module;

[0049] 23. Memory pool module; 231. First memory pool unit; 232. Second memory pool unit; 233. Third memory pool unit; 234. Fourth memory pool unit; 235. ECC unit; 236. Indicator light;

[0050] 24. Main control module;

[0051] 25. Main control substrate; 251. First plug interface; 252. Fan module;

[0052] 26. memory expansion board; 261. second plug-in terminal;

[0053] 27. Structural adapter plate; 271. First plug-in terminal; 272. Second plug-in interface; 273. Extended high-speed connector; 274. Ventilation port. DETAILED DESCRIPTION

[0054] In order to make the purpose, technical solution and advantages of the embodiments of the present invention clearer, the technical solution in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present invention.

[0055] In the description of the present invention, it should be noted that the terms "center", "up", "down", "left", "right", "vertical", "horizontal", "inside", "outside", etc. indicate directions or positional relationships based on the directions or positional relationships shown in the accompanying drawings. They are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific direction, be constructed and operated in a specific direction. Therefore, they cannot be understood as limitations on the present invention.

[0056] The terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features. In the description of the present invention, unless otherwise specified, "plurality" means two or more.

[0057] Among them, Compute Express Link, referred to as CXL, is the computing express connection.

[0058] Power management IC, referred to as PMIC, is a power management integrated circuit.

[0059] Inter-Integrated Circuit, referred to as I2C, is the bus between integrated circuits.

[0060] Central Processing Unit, referred to as CPU, is the central processing unit.

[0061] Error-Correcting Code, referred to as ECC, is error correction code.

[0062] Combine the following Figures 1 to 9 The present application describes a memory expansion board, a server and a memory allocation method based on CXL technology.

[0063] On the one hand, if Figure 1 As shown, the present application provides a server 100, which includes one or more host devices 10 and a memory expansion board 20 based on CXL technology. Among them, one or more host devices 10 can be connected to the memory expansion board 20 based on CXL technology through CXL technology, which is beneficial to improve the memory performance and capacity of the host device 10, so that the memory unit has higher data throughput and lower latency.

[0064] Based on this, Figure 2 As shown, the memory expansion board 20 based on CXL technology includes a CXL conversion module 21, at least one memory expansion control module 22 and a memory pool module 23. A memory pool module 23 is connected to the CXL conversion module 21 through at least one memory expansion control module 22, and a memory pool module 23 is integrated with multiple memory particles. The CXL conversion module 21 has an upstream port 211 and one or more downstream ports 212. The upstream port 211 is used to connect Figure 1 The host device 10 is shown in FIG.

[0065] Exemplarily, the memory expansion control module 22 is a memory controller based on CXL technology, which belongs to the third device type defined by the CXL protocol, and can greatly expand the memory capacity and bandwidth, so that the downstream port 212 of the CXL conversion module 21 can connect more memory particles through the memory expansion control module 22, and has high-speed data transmission capabilities. The memory expansion control module 22 can support the CXL2.0 protocol and support a transmission rate of 32GT / s.

[0066] Taking the bit width of a memory expansion control module 22 as X8 as an example, a downstream port 212 of the CXL conversion module 21 can connect 16 memory particles through a memory expansion control module 22, that is, a memory pool module 23 is integrated with at most 16 memory particles. Taking the bit width of a memory expansion control module 22 as X16 as an example, a downstream port 212 of the CXL conversion module 21 can connect 32 memory particles through a memory expansion control module 22, that is, a memory pool module 23 is integrated with at most 32 memory particles.

[0067] The memory chip can be of DDR4 standard. The capacity of a single memory chip can be 4Gb, 8Gb or 16Gb. Taking the capacity of a single memory chip of 16Gb as an example, its package size is 11mm*9.5mm, which is much smaller than the size of the memory stick. And the maximum transmission rate of DDR4 memory chip is 3200MT / s.

[0068] Alternatively, the memory chip can also be of DDR5 or DDR6 standard. Taking a single memory chip of 16Gb DDR5 as an example, its package size is 11mm*10mm, and the minimum transmission rate is 4800MT / s.

[0069] In this way, one or more memory expansion control modules 22 can be connected through the CXL conversion module 21, and up to 16 or 32 memory chips can be integrated in the memory pool module 23 connected to the memory expansion control module 22. Since each memory chip only occupies an area of ​​about one square centimeter, compared with the memory bar of more than 30 square centimeters and the corresponding gold finger slot setting scheme, more memory chips can be integrated and installed on a smaller expansion board, which has the advantages of small size and large capacity.

[0070] In addition, the gold finger plug-in installation scheme of the memory stick used in the related art is limited by the connection scheme of the gold finger, which will seriously limit the interconnection and topological performance between the memory particles, such as having a high delay. The present application integrates (encapsulates) multiple memory particles in the same memory pool module 23, and can flexibly set the connection between each memory particle, which is conducive to greatly improving the interconnection topological performance between the memory particles, such as reducing the delay interconnection between the memory particles, and facilitating the expansion management of the memory pool.

[0071] Among them, the memory expansion board 20 based on CXL technology provided in the embodiment of the present application can exist as an independent component, or the uplink port 211 of the CXL conversion module 21 can be connected to one or more host devices 10 to be set as a memory pool of a host device 10, or as a shared memory pool of multiple host devices 10.

[0072] In some embodiments, Figure 2and Figure 3 As shown, the memory expansion board 20 based on CXL technology also includes a main control module 24, which is connected to the downlink port 212 of the CXL conversion module 21 and is used to identify and adjust the real-time status of the memory expansion board 20 based on CXL technology.

[0073] Among them, Figure 2 and Figure 3 As shown, there are multiple memory expansion control modules 22, and one CXL conversion module 21 is connected to multiple memory expansion control modules 22, such as one memory expansion control module 22 is connected to one downstream port 212 of the CXL conversion module 21. The number of memory pool modules 23 is the same as the number of memory expansion control modules 22, and one memory pool module 23 is connected to one CXL conversion module 21 via one memory expansion control module 22.

[0074] That is, through the connection setting of the CXL conversion module 21, multiple memory expansion control modules 22 and corresponding memory pool modules 23 can be connected together to form a high-speed, scalable interconnected memory. By using the CXL conversion module 21, more efficient resource sharing and collaboration can be achieved, and the overall performance of the system can be improved.

[0075] On this basis, continue to refer to Figure 3 , each memory pool module 23 is connected to multiple memory expansion control modules 22. For example, if there are three memory expansion control modules 22 and memory pool modules 23 connected to the same CXL conversion module 21, each memory expansion control module 22 is connected to three memory pool modules 23. That is, on the expansion board, the memory pool module 23 is connected to all the memory expansion control modules 22 through physical lines. In this way, the main control module 24 can monitor and adjust the status of multiple memory pool modules 23 through the CXL conversion module 21 and the memory expansion control module 22, such as the main control module 24 is at least used to balance the memory usage status of multiple memory pool modules 23.

[0076] Exemplarily, since the main control module 24 is connected to each memory pool module 23, the usage and actual usage rate of each memory pool module 23 can be monitored through the setting of software or related programs for dynamic allocation of memory.

[0077] Taking multiple host devices 10 connected to the uplink port 211 of the CXL conversion module 21 as an example, the main control module 24 can synchronously monitor the memory occupancy rate of each uplink host device 10, and the main control module 24 can also synchronously monitor the usage rate of each downlink memory pool module 23. When the memory occupancy rate of one or part of the host devices 10 is higher than the first preset parameter (such as 10%) of the memory occupancy rate of other host devices 10, the main control module 24 controls and adjusts to allocate the idle or low-usage memory pool module 23 to the host device 10 with higher occupancy rate, so that the memory occupancy rate of all host devices 10 is in a relatively balanced state, so that the server 100 is in an overall stable and effective operation state.

[0078] In the process of balanced allocation of the above-mentioned memory pool modules 23, since each memory expansion control module 22 is connected to multiple memory pool modules 23, in the process of allocating one or more idle or low-utilization memory pool modules 23 to a host device 10 with a higher occupancy rate, the transmission adaptation of memory data can be performed through any memory expansion control module 22, which is beneficial to reduce the transmission delay between the memory pool module 23 and the host device 10, so that the server 100 is in an overall stable and efficient operating state.

[0079] It should be noted that, in the above embodiment, the memory pool module 23 is connected to one or more memory expansion control modules 22 as a whole memory pool.

[0080] In some embodiments, Figure 4 As shown, the memory pool module 23 includes at least a first memory pool unit 231 and a second memory pool unit 232. One first memory pool unit 231 is connected to one memory expansion control module 22. In the multiple memory pool modules 23 connected to the same CXL conversion module 21, the first memory pool unit 231 of each memory pool module is connected to multiple second memory pool units 232. At this time, the main control module 24 is at least used to balance the memory usage status of the multiple first memory pool units 231 and the multiple second memory pool units 232.

[0081] For example, each memory pool module 23 is provided with two smaller memory pools, namely, a first memory pool unit 231 and a second memory pool unit 232. The number of memory particles in the first memory pool unit 231 and the second memory pool unit 232 may be half of the total number of memory particles in the memory pool module 23. If the number of memory particles in the memory pool module 23 is 16, the number of memory particles in the first memory pool unit 231 and the second memory pool unit 232 is 8.

[0082] At this time, since the first memory pool unit 231 and the second memory pool unit 232 can be connected to the main control module 24 through a hardware line, the memory occupancy rate of multiple host devices 10 in the upstream can be synchronously monitored through the main control module 24, and the main control module 24 can also synchronously monitor the usage rate of each first memory pool unit 231 and each second memory pool unit 232 in the downstream.

[0083] When the memory occupancy rate of one or some of the host devices 10 is higher than the second preset parameter of the memory occupancy rate of other host devices 10 (such as 5%, the second preset parameter is less than the first preset parameter), the main control module 24 controls the adjustment to allocate the first memory pool unit 231 or the second memory pool unit 232 that is idle or has low usage to the host device 10 with higher occupancy rate, so that the memory occupancy rate of all the host devices 10 is in a more balanced state, so that the server 100 is in an overall stable and efficient operation state.

[0084] Since the overall memory of the first memory pool unit 231 and the second memory pool unit 232 is smaller than the overall memory of the memory pool module 23, the adaptive adjustment of the smaller memory pool is conducive to further improving the balanced adjustment effect of the memory occupancy rate of multiple host devices 10. For example, the fluctuation of the memory load occupancy rate of multiple host devices 10 is smaller.

[0085] For further information, please refer to Figure 4 For example, the number of memory particles integrated and packaged in each memory pool module 23 is between 16 and 32, such as 16, 20, 24, 28 or 32 memory particles integrated and packaged in the memory pool module 23. The first memory pool unit 231 is integrated with at least four memory particles, and the second memory pool unit 232 is integrated with at least four memory particles.

[0086] like Figure 4 As shown, the memory pool module 23 also includes a third memory pool unit 233 and a fourth memory pool unit 234. The third memory pool unit 233 is integrated with at least four memory particles, and the fourth memory pool unit 234 is integrated with at least four memory particles. In the multiple memory pool modules 23 connected to the same CXL conversion module 21, the second memory pool unit 232 of each memory pool module 23 is connected to multiple third memory pool units 233, and the third memory pool unit 233 of each memory pool module 23 is connected to multiple fourth memory pool units 234.

[0087] For example, the downstream port 212 of the same CXL conversion module 21 is connected to three memory pool modules 23. The three memory expansion control modules 22 are connected to the three first memory pool units 231 in a one-to-one correspondence. Each first memory pool unit 231 is connected to three second memory pool units 232, each second memory pool unit 232 is connected to three third memory pool units 233, and each third memory pool unit 233 is connected to three fourth memory pool units 234. The above connection settings all refer to connections made through physical lines on the board.

[0088] At this time, since the first memory pool unit 231, the second memory pool unit 232, the third memory pool unit 233 and the fourth memory pool unit 234 can be connected to the main control module 24 through the hardware line, the memory occupancy rate of the multiple host devices 10 in the upstream can be synchronously monitored through the main control module 24, and the main control module 24 can also synchronously monitor the usage rate of each first memory pool unit 231, each second memory pool unit 232, each third memory pool unit 233 and each fourth memory pool unit 234 in the downstream.

[0089] When the memory occupancy rate of one or some of the host devices 10 is higher than the third preset parameter of the memory occupancy rate of other host devices 10 (such as 1%, 2% or 3%, and the third preset parameter is less than the second preset parameter), the main control module 24 controls the adjustment to allocate the first memory pool unit 231, the second memory pool unit 232, the third memory pool unit 233 or the fourth memory pool unit 234 that are idle or have low usage to the host devices 10 with higher occupancy rate, so that the memory occupancy rate of all the host devices 10 is in a relatively balanced state, so that the server 100 is in an overall stable and efficient operation state.

[0090] Since the overall memory of each of the first memory pool unit 231, the second memory pool unit 232, the third memory pool unit 233 and the fourth memory pool unit 234 is smaller than the overall memory of the memory pool module 23, the adaptive adjustment of the smaller memory pool is conducive to further improving the balanced adjustment effect of the memory occupancy rate of multiple host devices 10. For example, the fluctuation of the memory load occupancy rate of multiple host devices 10 is smaller.

[0091] It should be noted that, in the embodiment of the present application, the smaller the memory capacity of a memory pool module 23 or a memory pool unit, the better the adjustment balance of the memory occupancy rate of the host device 10. However, if the overall memory capacity remains unchanged, the number of memory pool modules 23 or memory pool units will be increased, that is, the physical connection lines between multiple memory pool modules 23 or memory pool units will be more complicated.

[0092] For example, the memory pool module 23 may further include a fifth memory pool unit or a sixth memory pool unit. Alternatively, the number of memory pool units in each memory pool module 23 may be reduced. The number of memory pool units may be flexibly adjusted according to actual needs, and is not limited thereto.

[0093] In some embodiments, Figure 2 and Figure 3 As shown, the memory pool module 23 also includes an ECC unit 235, which is arranged between the memory particles and the memory expansion control module 22. Through the check bits in the data transmission process, the ECC unit 235 can detect and correct data errors in the transmitted data, thereby improving the host device 10 (such as Figure 1 The stability of operation.

[0094] Combination Figure 4 In the case where the memory pool module 23 includes at least a first memory pool unit 231 and a second memory pool unit 232, the ECC unit 235 is arranged between the memory expansion control module 22 and the first memory pool unit 231, so that the memory expansion control module 22 is connected to the first memory pool unit 231 via the ECC unit 235, thereby detecting and correcting the read and write data of the memory pool module 23.

[0095] In some embodiments, Figure 2 and Figure 3 As shown, the memory pool module 23 also includes an indicator light 236, which is used to display the operating status of the memory pool module 23. Exemplarily, the indicator light 236 can be an LED (Light-Emitting Diode), etc., which can emit different colors, such as red, yellow and blue, or red, yellow and green. Alternatively, the indicator light 236 can also be set to be two or more different ordinary light bulbs.

[0096] Take the indicator light 236 as an example, which is an LED light that can display red, yellow and green. The indicator light 236 is configured as follows: when the memory usage rate of the memory pool module 23 is less than a first preset value (such as 20%-40%, or 30%), the indicator light 236 is lit and is green. When the memory usage rate of the memory pool module 23 is greater than or equal to the first preset value and less than or equal to the second preset value (such as 70%-90%, or 80%), the indicator light 236 is lit and is yellow. When the memory usage rate of the memory pool module 23 is greater than the second preset value, the indicator light 236 is lit and is red. When the memory pool module 23 has a fault and cannot operate normally, the indicator light 236 is off.

[0097] In this way, by setting the indicator light 236, the operating status of the memory pool module 23 can be quickly detected and determined, which is very convenient.

[0098] It should be noted that when the memory pool module 23 includes a plurality of memory pool units such as the first memory pool unit 231 and the second memory pool unit 232, an indicator light 236 for displaying status information may be configured for each memory pool unit. Alternatively, an indicator light 236 for displaying status information may be configured for each memory pool module 23 as a whole. Flexible selection may be made according to needs, and this is not limited.

[0099] In some embodiments, Figures 2 to 4 As shown, the memory expansion board 20 based on CXL technology also includes a main control substrate 25 and a memory expansion board 26. Figure 5 The main control substrate 25 is provided with at least a main control module 24 and a first plug interface 251, and the first plug interface 251 is connected to the main control module 24. Figure 6 The memory expansion board 26 is provided with at least a CXL conversion module 21, a memory expansion control module 22, a memory pool module 22 and a second plug-in terminal 261. The second plug-in terminal 261 is at least connected to the downstream port 212 of the CXL conversion module 21. Figure 7 The memory expansion board 20 based on CXL technology also includes a structural adapter board 27, which is provided with a first plug-in terminal 271, a second plug-in interface 272 and a plurality of expansion high-speed connectors 273. The plurality of second plug-in interfaces 272 are connected to the first plug-in terminal 271, and one second plug-in interface is correspondingly connected to one expansion high-speed connector 273. The first plug-in terminal 271 is plug-fitted with the first plug-in interface 251. The second plug-in terminal 261 is plug-fitted with the second plug-in interface 272, so that the uplink port 211 of the CXL conversion module 21 is connected to the host device 10 via the expansion high-speed connector 273, so that the CPU in the host device 10 can quickly read and write data from the memory pool module 23.

[0100] Exemplarily, the expansion high-speed connector 273 can be connected to the CPU of the host device 10 at high speed through an MCIO protocol cable or a CDFP protocol cable. In the main control substrate 25, the memory expansion board 26 and the structure adapter board 27, the high-speed connection of the data channel is maintained through the built-in Retimer cable or channel.

[0101] In this way, the main control substrate 25 is integrated with components such as the main control module 24, and if an expansion connection of the memory pool is required, the structure adapter board 27 can be plugged into the first plug interface 251 of the main control substrate 25 via the first plug terminal 271. At this time, the first plug interface 251 can be expanded into multiple second plug interfaces 272 through the structure adapter board 27. Subsequently, the second plug terminals 261 of the memory expansion board 26 are sequentially plugged into the multiple second plug interfaces 272, so that the main control module 24 can be connected to a downstream port 212 of the CXL conversion module 21 through the built-in high-speed connector via the first plug interface 251, the first plug terminal 271, the second plug interface 272 and the second plug terminal 261.

[0102] In this way, through the configuration of the main control substrate 25, the structure adapter board 27 and the memory expansion board 26, the CXL conversion modules 21 and the memory pool modules 23 on multiple memory expansion boards 26 can be connected and managed through one main control module 24. In addition, through the configuration of the structure adapter board 27, one or more memory expansion boards 26 can be expanded and plugged on one main control substrate 25 as needed, thereby meeting different capacity requirements for the memory pool.

[0103] Exemplarily, three second plug interfaces 272 are provided on the structure adapter board 27, so that the same main control substrate 25 can be connected and managed and deployed with three memory expansion boards 26 through the plugged structure adapter board 27, which is very convenient.

[0104] It should be noted that the second plug-in terminal 261 of the memory expansion board 26 can also be directly plugged into the first plug-in interface 251 of the main control substrate 25, which can also enable the main control module 24 to connect, manage and coordinate the CXL conversion module 21 and the memory pool module 23 on the memory expansion board 26, with better adaptation flexibility.

[0105] In some embodiments, the first plug end 271 and the first plug interface 251 are gold finger plug components, and the second plug end 261 and the second plug interface 272 are also gold finger plug components. Exemplarily, the above-mentioned gold finger plug components can be PCI-E (Peripheral Component Interconnect Express, i.e., high-speed serial computer expansion bus standard) x16 or x8 interface components, and the interface standard can be PCI-E3.0, PCI-E 4.0 or PCI-E 5.0, which can be flexibly selected according to needs.

[0106] With the direction perpendicular to the main control substrate 25 as the first linear direction (such as the vertical direction, i.e., the Y direction), the first plug end 271 can be plugged and installed with the first plug interface 251 along the first linear direction, and the second plug end 261 can be plugged and installed with the second plug interface 272 along the second linear direction (perpendicular to the first linear direction, such as the horizontal direction or the X direction). Figure 7 and Figure 8 At the structural adapter plate 27, a plurality of second plug interfaces 272 are arranged at intervals along the first straight line direction.

[0107] Based on this, the multiple memory expansion boards 26 that are sequentially plugged into the second plug interface 272 along the second straight line direction through the second plug-in end 261 are approximately parallel to the main control substrate 25, that is, the multiple memory expansion boards 26 can be sequentially plugged in and installed along the vertical direction (first straight line direction), which is beneficial to improving the overall integration of the memory expansion board 20 based on CXL technology.

[0108] Furthermore, if Figure 7 and Figure 8 As shown, at the structure adapter plate 27, a vent 274 is provided between two adjacent second plug ports 272 spaced apart along a first straight line direction (such as a vertical direction).

[0109] Thus, when the memory expansion board 26 is plugged and installed with the structure adapter board 27 along the second straight line direction, a vent 274 is provided between two adjacent memory expansion boards 26 on one side close to the structure adapter board 27, so as to facilitate air circulation between the two adjacent memory expansion boards 26, so as to dissipate heat and cool down the electronic components such as the CXL conversion module 21, the memory expansion control module 22 and the memory pool module 23 on the memory expansion board 26.

[0110] In some embodiments, Figure 5 As shown, the main control substrate 25 is provided with a fan module 252. When the memory expansion board 26 (such as Figure 6 ) along the second straight line direction with the structural adapter plate 27 (as shown Figure 7 When the memory expansion board 26 is plugged in and installed (as shown in the figure), the fan module 252 located on the same side of the structural adapter plate 27 as the memory expansion board 26 draws external air into the gap between two adjacent memory expansion boards 26 for heat dissipation, and allows the air to flow out through the vents 274 for circulation, thereby dissipating heat and cooling the electronic components on the memory expansion board 26.

[0111] For example, as required, the CXL conversion module 21, the memory expansion control module 22, the memory pool module 23 and other components can be installed on one side of the memory expansion board 26. The memory expansion control module 22 and the memory pool module 23 and other components can also be set on opposite sides of the memory expansion board 26 at the same time to greatly increase the effective capacity of the memory pool of the same memory expansion board 26.

[0112] The number of CXL conversion modules 21 on the same memory expansion board 26 can be determined according to the number of its downstream ports 212 and the number of memory expansion control modules 22. Generally, only one CXL conversion module 21 is required.

[0113] In addition, the main control substrate 25 can also be used not only to plug in the memory expansion board 26 through the setting of the structural adapter board 27, so as to achieve connection management of multiple memory pool modules 23.

[0114] In some embodiments, when a memory expansion board 20 based on CXL technology includes a main control substrate 25, a main control module 24, a CXL conversion module 21, a memory expansion control module 22, a memory pool module 23 and a host high-speed connector can be integrated on the main control substrate 25, so that the CXL conversion module 21 is used to connect to the host device 10 via the host high-speed connector.

[0115] In this way, by integrating the CXL conversion module 21, the memory expansion control module 22, the memory pool module 23 and the host high-speed connector on the main control substrate 25, the main control substrate 25 itself can be used as a memory pool for expansion applications. In addition, on the main control substrate 25, one end of the host high-speed connector is connected to the uplink port 211 of the CXL conversion module 21, and the other end is connected to the CPU of the host device 10 through a cable via the MCIO protocol or the CDFP protocol, so that the CPU of the host device 10 can quickly write or read data in the expansion memory of the memory pool module 23 through the above line.

[0116] The main control module 24 disposed on the main control substrate 25 is an mCPU, which supports one or more M.2 hard disk interfaces and SATA / PCIE protocols, and the main control module 24 can also support a single PCIE-GEN4X4 output. The interfaces of the above main control module 24 can all be integrated on the main control substrate 25.

[0117] Continue to refer to Figures 2 to 4, the main control substrate 25 is also provided with a baseboard management control module, including a BMC (Baseboard Management Controller) integrated circuit, a DDR4 or DDR5 memory particle, two FLASH flash memory particles, an EEPROM (Electrically ErasableProgrammable Read-Only Memory) of corresponding capacity, a 25MHZ crystal oscillator, and a VR (Virtual Reality) module containing multiple power conversion integrated circuits. Among them, the baseboard management control module is the RunBMC module. Its network, I2C and GPIO (General-purpose input / output) and other integrated circuit modules are pointed out by the golden finger. The baseboard management control module is mainly used to realize system status management, power on and off management, fan control, abnormal status management and other functions. At the same time, a UART interface is provided to facilitate the integrated circuit module DEBUG, and the memory pool is externalized and shared through the CXL.io protocol and the CXL.mem protocol.

[0118] Among them, multiple level conversion integrated circuits (POWER) are provided on the main control substrate 25 and the memory expansion board 26. By setting PMIC, some or all of the level conversion integrated circuits can be replaced, that is, power supply output of multiple voltages can be achieved through one or a small number of PMICs, which has a simple structure and is conducive to reducing the number of components.

[0119] Exemplarily, the memory expansion control module 22 is an MCX integrated circuit based on CXL technology. An SPI-FLASH is connected to the memory expansion control module 22 to store the integrated circuit firmware information, so as to provide JTAG and UART interfaces for integrated circuit module Debug testing. The memory expansion control module 22 is connected to the CXL conversion module 21 to realize data exchange, and the main control module 24 is used to be responsible for data calculation, memory control, terminal processing and other functions.

[0120] Second, as Fig. 9 As shown, the present invention also provides a memory allocation method for a memory expansion board based on CXL technology, the allocation method comprising:

[0121] The control main control module detects the memory usage status of multiple memory pool modules and the memory occupancy status of the host device.

[0122] The memory pool module with lower memory usage rate is allocated to the host device with higher memory occupancy rate.

[0123] That is, by controlling the main control module to detect and monitor the memory usage status of the memory module and the memory occupancy status of the host device, and allocate memory modules with lower memory usage to host devices with higher memory usage, so as to balance the usage of multiple memory pool modules and the memory occupancy of the host module, so that the memory occupancy of the host device is in a more balanced state, so that the server is in an overall stable and efficient operation state.

[0124] It should be noted that, for the memory pool module, the usage status of multiple memory pool modules can be detected and monitored, and the usage status of each memory pool module can be allocated. Alternatively, each memory pool module can be further subdivided into multiple memory pool units, and the memory usage status of multiple memory pool units can be monitored and allocated. On the basis of reducing the monitoring and allocation capacity of a single memory module, it is beneficial to improve the allocation balance of memory usage and occupancy.

[0125] Although the embodiments of the present invention have been described in conjunction with the accompanying drawings, those skilled in the art may make various modifications and variations without departing from the spirit and scope of the present invention, and such modifications and variations are all within the scope defined by the appended claims.

Claims

1. A memory expansion board based on CXL technology, characterized in that: include: A CXL conversion module (21) having an upstream port (211) and a downstream port (212), wherein the upstream port (211) is used to connect to a host device (10); at least one memory expansion control module (22); A plurality of memory pool modules (23), one of the memory pool modules (23) being connected to the downstream port (212) of the CXL conversion module via at least one of the memory expansion control modules (22), and the memory pool module (23) being integrated with a plurality of memory particles; And a main control module (24), a CXL conversion module, wherein the main control module (24) is connected to the downlink port (212).

2. The memory expansion board based on CXL technology according to claim 1, characterized in that: The number of the memory expansion control modules (22) is multiple, one CXL conversion module (21) has multiple downstream ports (212), and one downstream port (212) is connected to one memory expansion control module (22); The number of the memory pool modules (23) is the same as the number of the memory expansion control modules (22), and each of the memory pool modules (23) is connected to a plurality of the memory expansion control modules (22); The main control module (24) is at least used to balance the memory usage status of the plurality of memory pool modules (23).

3. The memory expansion board based on CXL technology according to claim 1, characterized in that: The memory pool module (23) comprises at least a first memory pool unit (231) and a second memory pool unit (232); A first memory pool unit (231) is connected to a memory expansion control module (22); In a plurality of the memory pool modules (23) connected to the same CXL conversion module (21), the first memory pool unit (231) of each memory pool module (23) is connected to a plurality of the second memory pool units (232); The main control module (24) is at least used to balance the memory usage states of a plurality of the first memory pool units (231) and a plurality of the second memory pool units (232).

4. The memory expansion board based on CXL technology according to claim 3, characterized in that: The first memory pool unit (231) is integrated with at least four of the memory particles, and the second memory pool unit (232) is integrated with at least four of the memory particles; The memory pool module (23) further comprises: a third memory pool unit (233), wherein the third memory pool unit (233) is integrated with at least four memory particles; in a plurality of the memory pool modules (23) connected to the same CXL conversion module (21), the second memory pool unit (232) of each memory pool module (23) is connected to a plurality of the third memory pool units (233); a fourth memory pool unit (234), wherein the fourth memory pool unit (234) is integrated with at least four of the memory particles; in a plurality of the memory pool modules (23) connected to the same CXL conversion module (21), the third memory pool unit (233) of each of the memory pool modules (23) is connected to a plurality of the fourth memory pool units (234); and an ECC unit (235), wherein the ECC unit (235) is arranged between the memory expansion control module (22) and the first memory pool unit (231), so that the memory expansion control module (22) is connected to the first memory pool unit (231) via the ECC unit (235).

5. The memory expansion board based on CXL technology according to any one of claims 1 to 4, characterized in that: The memory expansion board based on CXL technology also includes: A main control substrate (25), the main control substrate (25) being provided with at least the main control module (24) and a first plug interface (251), the first plug interface (251) being connected to the main control module (24); A structural adapter plate (27), the structural adapter plate (27) being provided with a first plug end (271), a plurality of second plug interfaces (272) and a plurality of extended high-speed connectors (273), the plurality of second plug interfaces (272) being connected to the first plug end (271), and one second plug interface (272) being correspondingly connected to one extended high-speed connector (273); and a memory expansion board (26), wherein the memory expansion board (26) is provided with at least the CXL conversion module (21), the memory expansion control module (22), the memory pool module (23) and a second plug-in terminal (261), wherein the second plug-in terminal (261) is at least connected to the downlink port (212); the second plug-in terminal (261) is plug-fitted with the second plug interface (272) so that the uplink port (211) is connected to the host device (10) via the expansion high-speed connector (273).

6. The memory expansion board based on CXL technology according to claim 5, characterized in that: The first plug-in end (271) and the first plug-in interface (251) are gold finger plug-in components, and the first plug-in end (271) is plug-connected and installed with the first plug-in interface (251) along a first straight line direction; The second plug end (261) and the second plug interface (272) are gold finger plug components, the second plug end (261) is plugged and installed with the second plug interface (272) along a second straight line direction, and the first straight line direction is perpendicular to the second straight line direction; At the structural adapter plate (27), a plurality of the second plugging interfaces (272) are distributed at intervals along the first straight line direction, and a vent (274) is provided between two adjacent second plugging interfaces (272).

7. The memory expansion board based on CXL technology according to any one of claims 1 to 4, characterized in that: The memory expansion board based on CXL technology includes: A main control substrate (25), the main control substrate (25) being provided with at least the main control module (24), the CXL conversion module (21), the memory expansion control module (22), the memory pool module (23) and a host high-speed connector, the CXL conversion module (21) being used for connecting to a host device (10) via the host high-speed connector.

8. The memory expansion board based on CXL technology according to any one of claims 1 to 4, characterized in that: The memory pool module (23) further comprises: An indicator light (236), the indicator light (236) is used to display the operating status of the memory pool module (23), and is configured as follows: When the memory usage rate of the memory pool module (23) is less than a first preset value, the indicator light (236) lights up and is green; When the memory usage rate of the memory pool module (23) is greater than or equal to the first preset value and less than or equal to a second preset value, the indicator light (236) is lit and is yellow, and the second preset value is greater than the first preset value; When the memory usage rate of the memory pool module (23) is greater than a second preset value, the indicator light (236) lights up in red; When the memory pool module (23) has a fault, the indicator light (236) goes out.

9. A server, characterized in that: include: at least one host device (10); And according to any one of claims 1 to 8, the memory expansion board based on CXL technology, the host device (10) is connected to the uplink port (211).

10. A memory allocation method for a memory expansion board based on CXL technology, characterized in that: include: The control main control module detects the memory usage status of multiple memory pool modules and the memory occupancy status of the host device; The memory pool module with lower memory usage rate is allocated to the host device with higher memory occupancy rate.

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